forcedeth.c 70 KB

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  1. /*
  2. * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
  3. *
  4. * Note: This driver is a cleanroom reimplementation based on reverse
  5. * engineered documentation written by Carl-Daniel Hailfinger
  6. * and Andrew de Quincey. It's neither supported nor endorsed
  7. * by NVIDIA Corp. Use at your own risk.
  8. *
  9. * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10. * trademarks of NVIDIA Corporation in the United States and other
  11. * countries.
  12. *
  13. * Copyright (C) 2003,4 Manfred Spraul
  14. * Copyright (C) 2004 Andrew de Quincey (wol support)
  15. * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16. * IRQ rate fixes, bigendian fixes, cleanups, verification)
  17. * Copyright (c) 2004 NVIDIA Corporation
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License as published by
  21. * the Free Software Foundation; either version 2 of the License, or
  22. * (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  32. *
  33. * Changelog:
  34. * 0.01: 05 Oct 2003: First release that compiles without warnings.
  35. * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36. * Check all PCI BARs for the register window.
  37. * udelay added to mii_rw.
  38. * 0.03: 06 Oct 2003: Initialize dev->irq.
  39. * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40. * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41. * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42. * irq mask updated
  43. * 0.07: 14 Oct 2003: Further irq mask updates.
  44. * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45. * added into irq handler, NULL check for drain_ring.
  46. * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47. * requested interrupt sources.
  48. * 0.10: 20 Oct 2003: First cleanup for release.
  49. * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50. * MAC Address init fix, set_multicast cleanup.
  51. * 0.12: 23 Oct 2003: Cleanups for release.
  52. * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53. * Set link speed correctly. start rx before starting
  54. * tx (nv_start_rx sets the link speed).
  55. * 0.14: 25 Oct 2003: Nic dependant irq mask.
  56. * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57. * open.
  58. * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59. * increased to 1628 bytes.
  60. * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61. * the tx length.
  62. * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63. * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64. * addresses, really stop rx if already running
  65. * in nv_start_rx, clean up a bit.
  66. * 0.20: 07 Dec 2003: alloc fixes
  67. * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68. * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69. * on close.
  70. * 0.23: 26 Jan 2004: various small cleanups
  71. * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72. * 0.25: 09 Mar 2004: wol support
  73. * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74. * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75. * added CK804/MCP04 device IDs, code fixes
  76. * for registers, link status and other minor fixes.
  77. * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78. * 0.29: 31 Aug 2004: Add backup timer for link change notification.
  79. * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80. * into nv_close, otherwise reenabling for wol can
  81. * cause DMA to kfree'd memory.
  82. * 0.31: 14 Nov 2004: ethtool support for getting/setting link
  83. * capabilities.
  84. * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85. * 0.33: 16 May 2005: Support for MCP51 added.
  86. * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87. * 0.35: 26 Jun 2005: Support for MCP55 added.
  88. * 0.36: 28 Jun 2005: Add jumbo frame support.
  89. * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90. * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91. * per-packet flags.
  92. *
  93. * Known bugs:
  94. * We suspect that on some hardware no TX done interrupts are generated.
  95. * This means recovery from netif_stop_queue only happens if the hw timer
  96. * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  97. * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  98. * If your hardware reliably generates tx done interrupts, then you can remove
  99. * DEV_NEED_TIMERIRQ from the driver_data flags.
  100. * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  101. * superfluous timer interrupts from the nic.
  102. */
  103. #define FORCEDETH_VERSION "0.38"
  104. #define DRV_NAME "forcedeth"
  105. #include <linux/module.h>
  106. #include <linux/types.h>
  107. #include <linux/pci.h>
  108. #include <linux/interrupt.h>
  109. #include <linux/netdevice.h>
  110. #include <linux/etherdevice.h>
  111. #include <linux/delay.h>
  112. #include <linux/spinlock.h>
  113. #include <linux/ethtool.h>
  114. #include <linux/timer.h>
  115. #include <linux/skbuff.h>
  116. #include <linux/mii.h>
  117. #include <linux/random.h>
  118. #include <linux/init.h>
  119. #include <linux/if_vlan.h>
  120. #include <asm/irq.h>
  121. #include <asm/io.h>
  122. #include <asm/uaccess.h>
  123. #include <asm/system.h>
  124. #if 0
  125. #define dprintk printk
  126. #else
  127. #define dprintk(x...) do { } while (0)
  128. #endif
  129. /*
  130. * Hardware access:
  131. */
  132. #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
  133. #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
  134. #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
  135. enum {
  136. NvRegIrqStatus = 0x000,
  137. #define NVREG_IRQSTAT_MIIEVENT 0x040
  138. #define NVREG_IRQSTAT_MASK 0x1ff
  139. NvRegIrqMask = 0x004,
  140. #define NVREG_IRQ_RX_ERROR 0x0001
  141. #define NVREG_IRQ_RX 0x0002
  142. #define NVREG_IRQ_RX_NOBUF 0x0004
  143. #define NVREG_IRQ_TX_ERR 0x0008
  144. #define NVREG_IRQ_TX_OK 0x0010
  145. #define NVREG_IRQ_TIMER 0x0020
  146. #define NVREG_IRQ_LINK 0x0040
  147. #define NVREG_IRQ_TX_ERROR 0x0080
  148. #define NVREG_IRQ_TX1 0x0100
  149. #define NVREG_IRQMASK_WANTED 0x00df
  150. #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
  151. NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
  152. NVREG_IRQ_TX1))
  153. NvRegUnknownSetupReg6 = 0x008,
  154. #define NVREG_UNKSETUP6_VAL 3
  155. /*
  156. * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
  157. * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
  158. */
  159. NvRegPollingInterval = 0x00c,
  160. #define NVREG_POLL_DEFAULT 970
  161. NvRegMisc1 = 0x080,
  162. #define NVREG_MISC1_HD 0x02
  163. #define NVREG_MISC1_FORCE 0x3b0f3c
  164. NvRegTransmitterControl = 0x084,
  165. #define NVREG_XMITCTL_START 0x01
  166. NvRegTransmitterStatus = 0x088,
  167. #define NVREG_XMITSTAT_BUSY 0x01
  168. NvRegPacketFilterFlags = 0x8c,
  169. #define NVREG_PFF_ALWAYS 0x7F0008
  170. #define NVREG_PFF_PROMISC 0x80
  171. #define NVREG_PFF_MYADDR 0x20
  172. NvRegOffloadConfig = 0x90,
  173. #define NVREG_OFFLOAD_HOMEPHY 0x601
  174. #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
  175. NvRegReceiverControl = 0x094,
  176. #define NVREG_RCVCTL_START 0x01
  177. NvRegReceiverStatus = 0x98,
  178. #define NVREG_RCVSTAT_BUSY 0x01
  179. NvRegRandomSeed = 0x9c,
  180. #define NVREG_RNDSEED_MASK 0x00ff
  181. #define NVREG_RNDSEED_FORCE 0x7f00
  182. #define NVREG_RNDSEED_FORCE2 0x2d00
  183. #define NVREG_RNDSEED_FORCE3 0x7400
  184. NvRegUnknownSetupReg1 = 0xA0,
  185. #define NVREG_UNKSETUP1_VAL 0x16070f
  186. NvRegUnknownSetupReg2 = 0xA4,
  187. #define NVREG_UNKSETUP2_VAL 0x16
  188. NvRegMacAddrA = 0xA8,
  189. NvRegMacAddrB = 0xAC,
  190. NvRegMulticastAddrA = 0xB0,
  191. #define NVREG_MCASTADDRA_FORCE 0x01
  192. NvRegMulticastAddrB = 0xB4,
  193. NvRegMulticastMaskA = 0xB8,
  194. NvRegMulticastMaskB = 0xBC,
  195. NvRegPhyInterface = 0xC0,
  196. #define PHY_RGMII 0x10000000
  197. NvRegTxRingPhysAddr = 0x100,
  198. NvRegRxRingPhysAddr = 0x104,
  199. NvRegRingSizes = 0x108,
  200. #define NVREG_RINGSZ_TXSHIFT 0
  201. #define NVREG_RINGSZ_RXSHIFT 16
  202. NvRegUnknownTransmitterReg = 0x10c,
  203. NvRegLinkSpeed = 0x110,
  204. #define NVREG_LINKSPEED_FORCE 0x10000
  205. #define NVREG_LINKSPEED_10 1000
  206. #define NVREG_LINKSPEED_100 100
  207. #define NVREG_LINKSPEED_1000 50
  208. #define NVREG_LINKSPEED_MASK (0xFFF)
  209. NvRegUnknownSetupReg5 = 0x130,
  210. #define NVREG_UNKSETUP5_BIT31 (1<<31)
  211. NvRegUnknownSetupReg3 = 0x13c,
  212. #define NVREG_UNKSETUP3_VAL1 0x200010
  213. NvRegTxRxControl = 0x144,
  214. #define NVREG_TXRXCTL_KICK 0x0001
  215. #define NVREG_TXRXCTL_BIT1 0x0002
  216. #define NVREG_TXRXCTL_BIT2 0x0004
  217. #define NVREG_TXRXCTL_IDLE 0x0008
  218. #define NVREG_TXRXCTL_RESET 0x0010
  219. #define NVREG_TXRXCTL_RXCHECK 0x0400
  220. NvRegMIIStatus = 0x180,
  221. #define NVREG_MIISTAT_ERROR 0x0001
  222. #define NVREG_MIISTAT_LINKCHANGE 0x0008
  223. #define NVREG_MIISTAT_MASK 0x000f
  224. #define NVREG_MIISTAT_MASK2 0x000f
  225. NvRegUnknownSetupReg4 = 0x184,
  226. #define NVREG_UNKSETUP4_VAL 8
  227. NvRegAdapterControl = 0x188,
  228. #define NVREG_ADAPTCTL_START 0x02
  229. #define NVREG_ADAPTCTL_LINKUP 0x04
  230. #define NVREG_ADAPTCTL_PHYVALID 0x40000
  231. #define NVREG_ADAPTCTL_RUNNING 0x100000
  232. #define NVREG_ADAPTCTL_PHYSHIFT 24
  233. NvRegMIISpeed = 0x18c,
  234. #define NVREG_MIISPEED_BIT8 (1<<8)
  235. #define NVREG_MIIDELAY 5
  236. NvRegMIIControl = 0x190,
  237. #define NVREG_MIICTL_INUSE 0x08000
  238. #define NVREG_MIICTL_WRITE 0x00400
  239. #define NVREG_MIICTL_ADDRSHIFT 5
  240. NvRegMIIData = 0x194,
  241. NvRegWakeUpFlags = 0x200,
  242. #define NVREG_WAKEUPFLAGS_VAL 0x7770
  243. #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
  244. #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
  245. #define NVREG_WAKEUPFLAGS_D3SHIFT 12
  246. #define NVREG_WAKEUPFLAGS_D2SHIFT 8
  247. #define NVREG_WAKEUPFLAGS_D1SHIFT 4
  248. #define NVREG_WAKEUPFLAGS_D0SHIFT 0
  249. #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
  250. #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
  251. #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
  252. #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
  253. NvRegPatternCRC = 0x204,
  254. NvRegPatternMask = 0x208,
  255. NvRegPowerCap = 0x268,
  256. #define NVREG_POWERCAP_D3SUPP (1<<30)
  257. #define NVREG_POWERCAP_D2SUPP (1<<26)
  258. #define NVREG_POWERCAP_D1SUPP (1<<25)
  259. NvRegPowerState = 0x26c,
  260. #define NVREG_POWERSTATE_POWEREDUP 0x8000
  261. #define NVREG_POWERSTATE_VALID 0x0100
  262. #define NVREG_POWERSTATE_MASK 0x0003
  263. #define NVREG_POWERSTATE_D0 0x0000
  264. #define NVREG_POWERSTATE_D1 0x0001
  265. #define NVREG_POWERSTATE_D2 0x0002
  266. #define NVREG_POWERSTATE_D3 0x0003
  267. };
  268. /* Big endian: should work, but is untested */
  269. struct ring_desc {
  270. u32 PacketBuffer;
  271. u32 FlagLen;
  272. };
  273. #define FLAG_MASK_V1 0xffff0000
  274. #define FLAG_MASK_V2 0xffffc000
  275. #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
  276. #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
  277. #define NV_TX_LASTPACKET (1<<16)
  278. #define NV_TX_RETRYERROR (1<<19)
  279. #define NV_TX_FORCED_INTERRUPT (1<<24)
  280. #define NV_TX_DEFERRED (1<<26)
  281. #define NV_TX_CARRIERLOST (1<<27)
  282. #define NV_TX_LATECOLLISION (1<<28)
  283. #define NV_TX_UNDERFLOW (1<<29)
  284. #define NV_TX_ERROR (1<<30)
  285. #define NV_TX_VALID (1<<31)
  286. #define NV_TX2_LASTPACKET (1<<29)
  287. #define NV_TX2_RETRYERROR (1<<18)
  288. #define NV_TX2_FORCED_INTERRUPT (1<<30)
  289. #define NV_TX2_DEFERRED (1<<25)
  290. #define NV_TX2_CARRIERLOST (1<<26)
  291. #define NV_TX2_LATECOLLISION (1<<27)
  292. #define NV_TX2_UNDERFLOW (1<<28)
  293. /* error and valid are the same for both */
  294. #define NV_TX2_ERROR (1<<30)
  295. #define NV_TX2_VALID (1<<31)
  296. #define NV_RX_DESCRIPTORVALID (1<<16)
  297. #define NV_RX_MISSEDFRAME (1<<17)
  298. #define NV_RX_SUBSTRACT1 (1<<18)
  299. #define NV_RX_ERROR1 (1<<23)
  300. #define NV_RX_ERROR2 (1<<24)
  301. #define NV_RX_ERROR3 (1<<25)
  302. #define NV_RX_ERROR4 (1<<26)
  303. #define NV_RX_CRCERR (1<<27)
  304. #define NV_RX_OVERFLOW (1<<28)
  305. #define NV_RX_FRAMINGERR (1<<29)
  306. #define NV_RX_ERROR (1<<30)
  307. #define NV_RX_AVAIL (1<<31)
  308. #define NV_RX2_CHECKSUMMASK (0x1C000000)
  309. #define NV_RX2_CHECKSUMOK1 (0x10000000)
  310. #define NV_RX2_CHECKSUMOK2 (0x14000000)
  311. #define NV_RX2_CHECKSUMOK3 (0x18000000)
  312. #define NV_RX2_DESCRIPTORVALID (1<<29)
  313. #define NV_RX2_SUBSTRACT1 (1<<25)
  314. #define NV_RX2_ERROR1 (1<<18)
  315. #define NV_RX2_ERROR2 (1<<19)
  316. #define NV_RX2_ERROR3 (1<<20)
  317. #define NV_RX2_ERROR4 (1<<21)
  318. #define NV_RX2_CRCERR (1<<22)
  319. #define NV_RX2_OVERFLOW (1<<23)
  320. #define NV_RX2_FRAMINGERR (1<<24)
  321. /* error and avail are the same for both */
  322. #define NV_RX2_ERROR (1<<30)
  323. #define NV_RX2_AVAIL (1<<31)
  324. /* Miscelaneous hardware related defines: */
  325. #define NV_PCI_REGSZ 0x270
  326. /* various timeout delays: all in usec */
  327. #define NV_TXRX_RESET_DELAY 4
  328. #define NV_TXSTOP_DELAY1 10
  329. #define NV_TXSTOP_DELAY1MAX 500000
  330. #define NV_TXSTOP_DELAY2 100
  331. #define NV_RXSTOP_DELAY1 10
  332. #define NV_RXSTOP_DELAY1MAX 500000
  333. #define NV_RXSTOP_DELAY2 100
  334. #define NV_SETUP5_DELAY 5
  335. #define NV_SETUP5_DELAYMAX 50000
  336. #define NV_POWERUP_DELAY 5
  337. #define NV_POWERUP_DELAYMAX 5000
  338. #define NV_MIIBUSY_DELAY 50
  339. #define NV_MIIPHY_DELAY 10
  340. #define NV_MIIPHY_DELAYMAX 10000
  341. #define NV_WAKEUPPATTERNS 5
  342. #define NV_WAKEUPMASKENTRIES 4
  343. /* General driver defaults */
  344. #define NV_WATCHDOG_TIMEO (5*HZ)
  345. #define RX_RING 128
  346. #define TX_RING 64
  347. /*
  348. * If your nic mysteriously hangs then try to reduce the limits
  349. * to 1/0: It might be required to set NV_TX_LASTPACKET in the
  350. * last valid ring entry. But this would be impossible to
  351. * implement - probably a disassembly error.
  352. */
  353. #define TX_LIMIT_STOP 63
  354. #define TX_LIMIT_START 62
  355. /* rx/tx mac addr + type + vlan + align + slack*/
  356. #define NV_RX_HEADERS (64)
  357. /* even more slack. */
  358. #define NV_RX_ALLOC_PAD (64)
  359. /* maximum mtu size */
  360. #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
  361. #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
  362. #define OOM_REFILL (1+HZ/20)
  363. #define POLL_WAIT (1+HZ/100)
  364. #define LINK_TIMEOUT (3*HZ)
  365. /*
  366. * desc_ver values:
  367. * This field has two purposes:
  368. * - Newer nics uses a different ring layout. The layout is selected by
  369. * comparing np->desc_ver with DESC_VER_xy.
  370. * - It contains bits that are forced on when writing to NvRegTxRxControl.
  371. */
  372. #define DESC_VER_1 0x0
  373. #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
  374. /* PHY defines */
  375. #define PHY_OUI_MARVELL 0x5043
  376. #define PHY_OUI_CICADA 0x03f1
  377. #define PHYID1_OUI_MASK 0x03ff
  378. #define PHYID1_OUI_SHFT 6
  379. #define PHYID2_OUI_MASK 0xfc00
  380. #define PHYID2_OUI_SHFT 10
  381. #define PHY_INIT1 0x0f000
  382. #define PHY_INIT2 0x0e00
  383. #define PHY_INIT3 0x01000
  384. #define PHY_INIT4 0x0200
  385. #define PHY_INIT5 0x0004
  386. #define PHY_INIT6 0x02000
  387. #define PHY_GIGABIT 0x0100
  388. #define PHY_TIMEOUT 0x1
  389. #define PHY_ERROR 0x2
  390. #define PHY_100 0x1
  391. #define PHY_1000 0x2
  392. #define PHY_HALF 0x100
  393. /* FIXME: MII defines that should be added to <linux/mii.h> */
  394. #define MII_1000BT_CR 0x09
  395. #define MII_1000BT_SR 0x0a
  396. #define ADVERTISE_1000FULL 0x0200
  397. #define ADVERTISE_1000HALF 0x0100
  398. #define LPA_1000FULL 0x0800
  399. #define LPA_1000HALF 0x0400
  400. /*
  401. * SMP locking:
  402. * All hardware access under dev->priv->lock, except the performance
  403. * critical parts:
  404. * - rx is (pseudo-) lockless: it relies on the single-threading provided
  405. * by the arch code for interrupts.
  406. * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
  407. * needs dev->priv->lock :-(
  408. * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
  409. */
  410. /* in dev: base, irq */
  411. struct fe_priv {
  412. spinlock_t lock;
  413. /* General data:
  414. * Locking: spin_lock(&np->lock); */
  415. struct net_device_stats stats;
  416. int in_shutdown;
  417. u32 linkspeed;
  418. int duplex;
  419. int autoneg;
  420. int fixed_mode;
  421. int phyaddr;
  422. int wolenabled;
  423. unsigned int phy_oui;
  424. u16 gigabit;
  425. /* General data: RO fields */
  426. dma_addr_t ring_addr;
  427. struct pci_dev *pci_dev;
  428. u32 orig_mac[2];
  429. u32 irqmask;
  430. u32 desc_ver;
  431. void __iomem *base;
  432. /* rx specific fields.
  433. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  434. */
  435. struct ring_desc *rx_ring;
  436. unsigned int cur_rx, refill_rx;
  437. struct sk_buff *rx_skbuff[RX_RING];
  438. dma_addr_t rx_dma[RX_RING];
  439. unsigned int rx_buf_sz;
  440. unsigned int pkt_limit;
  441. struct timer_list oom_kick;
  442. struct timer_list nic_poll;
  443. /* media detection workaround.
  444. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  445. */
  446. int need_linktimer;
  447. unsigned long link_timeout;
  448. /*
  449. * tx specific fields.
  450. */
  451. struct ring_desc *tx_ring;
  452. unsigned int next_tx, nic_tx;
  453. struct sk_buff *tx_skbuff[TX_RING];
  454. dma_addr_t tx_dma[TX_RING];
  455. u32 tx_flags;
  456. };
  457. /*
  458. * Maximum number of loops until we assume that a bit in the irq mask
  459. * is stuck. Overridable with module param.
  460. */
  461. static int max_interrupt_work = 5;
  462. static inline struct fe_priv *get_nvpriv(struct net_device *dev)
  463. {
  464. return netdev_priv(dev);
  465. }
  466. static inline u8 __iomem *get_hwbase(struct net_device *dev)
  467. {
  468. return get_nvpriv(dev)->base;
  469. }
  470. static inline void pci_push(u8 __iomem *base)
  471. {
  472. /* force out pending posted writes */
  473. readl(base);
  474. }
  475. static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
  476. {
  477. return le32_to_cpu(prd->FlagLen)
  478. & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
  479. }
  480. static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
  481. int delay, int delaymax, const char *msg)
  482. {
  483. u8 __iomem *base = get_hwbase(dev);
  484. pci_push(base);
  485. do {
  486. udelay(delay);
  487. delaymax -= delay;
  488. if (delaymax < 0) {
  489. if (msg)
  490. printk(msg);
  491. return 1;
  492. }
  493. } while ((readl(base + offset) & mask) != target);
  494. return 0;
  495. }
  496. #define MII_READ (-1)
  497. /* mii_rw: read/write a register on the PHY.
  498. *
  499. * Caller must guarantee serialization
  500. */
  501. static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
  502. {
  503. u8 __iomem *base = get_hwbase(dev);
  504. u32 reg;
  505. int retval;
  506. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  507. reg = readl(base + NvRegMIIControl);
  508. if (reg & NVREG_MIICTL_INUSE) {
  509. writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
  510. udelay(NV_MIIBUSY_DELAY);
  511. }
  512. reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
  513. if (value != MII_READ) {
  514. writel(value, base + NvRegMIIData);
  515. reg |= NVREG_MIICTL_WRITE;
  516. }
  517. writel(reg, base + NvRegMIIControl);
  518. if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
  519. NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
  520. dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
  521. dev->name, miireg, addr);
  522. retval = -1;
  523. } else if (value != MII_READ) {
  524. /* it was a write operation - fewer failures are detectable */
  525. dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
  526. dev->name, value, miireg, addr);
  527. retval = 0;
  528. } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
  529. dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
  530. dev->name, miireg, addr);
  531. retval = -1;
  532. } else {
  533. retval = readl(base + NvRegMIIData);
  534. dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
  535. dev->name, miireg, addr, retval);
  536. }
  537. return retval;
  538. }
  539. static int phy_reset(struct net_device *dev)
  540. {
  541. struct fe_priv *np = get_nvpriv(dev);
  542. u32 miicontrol;
  543. unsigned int tries = 0;
  544. miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  545. miicontrol |= BMCR_RESET;
  546. if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
  547. return -1;
  548. }
  549. /* wait for 500ms */
  550. msleep(500);
  551. /* must wait till reset is deasserted */
  552. while (miicontrol & BMCR_RESET) {
  553. msleep(10);
  554. miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  555. /* FIXME: 100 tries seem excessive */
  556. if (tries++ > 100)
  557. return -1;
  558. }
  559. return 0;
  560. }
  561. static int phy_init(struct net_device *dev)
  562. {
  563. struct fe_priv *np = get_nvpriv(dev);
  564. u8 __iomem *base = get_hwbase(dev);
  565. u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
  566. /* set advertise register */
  567. reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  568. reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
  569. if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
  570. printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
  571. return PHY_ERROR;
  572. }
  573. /* get phy interface type */
  574. phyinterface = readl(base + NvRegPhyInterface);
  575. /* see if gigabit phy */
  576. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  577. if (mii_status & PHY_GIGABIT) {
  578. np->gigabit = PHY_GIGABIT;
  579. mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
  580. mii_control_1000 &= ~ADVERTISE_1000HALF;
  581. if (phyinterface & PHY_RGMII)
  582. mii_control_1000 |= ADVERTISE_1000FULL;
  583. else
  584. mii_control_1000 &= ~ADVERTISE_1000FULL;
  585. if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
  586. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  587. return PHY_ERROR;
  588. }
  589. }
  590. else
  591. np->gigabit = 0;
  592. /* reset the phy */
  593. if (phy_reset(dev)) {
  594. printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
  595. return PHY_ERROR;
  596. }
  597. /* phy vendor specific configuration */
  598. if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
  599. phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
  600. phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
  601. phy_reserved |= (PHY_INIT3 | PHY_INIT4);
  602. if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
  603. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  604. return PHY_ERROR;
  605. }
  606. phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  607. phy_reserved |= PHY_INIT5;
  608. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
  609. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  610. return PHY_ERROR;
  611. }
  612. }
  613. if (np->phy_oui == PHY_OUI_CICADA) {
  614. phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
  615. phy_reserved |= PHY_INIT6;
  616. if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
  617. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  618. return PHY_ERROR;
  619. }
  620. }
  621. /* restart auto negotiation */
  622. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  623. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  624. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
  625. return PHY_ERROR;
  626. }
  627. return 0;
  628. }
  629. static void nv_start_rx(struct net_device *dev)
  630. {
  631. struct fe_priv *np = get_nvpriv(dev);
  632. u8 __iomem *base = get_hwbase(dev);
  633. dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
  634. /* Already running? Stop it. */
  635. if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
  636. writel(0, base + NvRegReceiverControl);
  637. pci_push(base);
  638. }
  639. writel(np->linkspeed, base + NvRegLinkSpeed);
  640. pci_push(base);
  641. writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
  642. dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
  643. dev->name, np->duplex, np->linkspeed);
  644. pci_push(base);
  645. }
  646. static void nv_stop_rx(struct net_device *dev)
  647. {
  648. u8 __iomem *base = get_hwbase(dev);
  649. dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
  650. writel(0, base + NvRegReceiverControl);
  651. reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
  652. NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
  653. KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
  654. udelay(NV_RXSTOP_DELAY2);
  655. writel(0, base + NvRegLinkSpeed);
  656. }
  657. static void nv_start_tx(struct net_device *dev)
  658. {
  659. u8 __iomem *base = get_hwbase(dev);
  660. dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
  661. writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
  662. pci_push(base);
  663. }
  664. static void nv_stop_tx(struct net_device *dev)
  665. {
  666. u8 __iomem *base = get_hwbase(dev);
  667. dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
  668. writel(0, base + NvRegTransmitterControl);
  669. reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
  670. NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
  671. KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
  672. udelay(NV_TXSTOP_DELAY2);
  673. writel(0, base + NvRegUnknownTransmitterReg);
  674. }
  675. static void nv_txrx_reset(struct net_device *dev)
  676. {
  677. struct fe_priv *np = get_nvpriv(dev);
  678. u8 __iomem *base = get_hwbase(dev);
  679. dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
  680. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
  681. pci_push(base);
  682. udelay(NV_TXRX_RESET_DELAY);
  683. writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
  684. pci_push(base);
  685. }
  686. /*
  687. * nv_get_stats: dev->get_stats function
  688. * Get latest stats value from the nic.
  689. * Called with read_lock(&dev_base_lock) held for read -
  690. * only synchronized against unregister_netdevice.
  691. */
  692. static struct net_device_stats *nv_get_stats(struct net_device *dev)
  693. {
  694. struct fe_priv *np = get_nvpriv(dev);
  695. /* It seems that the nic always generates interrupts and doesn't
  696. * accumulate errors internally. Thus the current values in np->stats
  697. * are already up to date.
  698. */
  699. return &np->stats;
  700. }
  701. /*
  702. * nv_alloc_rx: fill rx ring entries.
  703. * Return 1 if the allocations for the skbs failed and the
  704. * rx engine is without Available descriptors
  705. */
  706. static int nv_alloc_rx(struct net_device *dev)
  707. {
  708. struct fe_priv *np = get_nvpriv(dev);
  709. unsigned int refill_rx = np->refill_rx;
  710. int nr;
  711. while (np->cur_rx != refill_rx) {
  712. struct sk_buff *skb;
  713. nr = refill_rx % RX_RING;
  714. if (np->rx_skbuff[nr] == NULL) {
  715. skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  716. if (!skb)
  717. break;
  718. skb->dev = dev;
  719. np->rx_skbuff[nr] = skb;
  720. } else {
  721. skb = np->rx_skbuff[nr];
  722. }
  723. np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
  724. PCI_DMA_FROMDEVICE);
  725. np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
  726. wmb();
  727. np->rx_ring[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
  728. dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
  729. dev->name, refill_rx);
  730. refill_rx++;
  731. }
  732. np->refill_rx = refill_rx;
  733. if (np->cur_rx - refill_rx == RX_RING)
  734. return 1;
  735. return 0;
  736. }
  737. static void nv_do_rx_refill(unsigned long data)
  738. {
  739. struct net_device *dev = (struct net_device *) data;
  740. struct fe_priv *np = get_nvpriv(dev);
  741. disable_irq(dev->irq);
  742. if (nv_alloc_rx(dev)) {
  743. spin_lock(&np->lock);
  744. if (!np->in_shutdown)
  745. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  746. spin_unlock(&np->lock);
  747. }
  748. enable_irq(dev->irq);
  749. }
  750. static void nv_init_rx(struct net_device *dev)
  751. {
  752. struct fe_priv *np = get_nvpriv(dev);
  753. int i;
  754. np->cur_rx = RX_RING;
  755. np->refill_rx = 0;
  756. for (i = 0; i < RX_RING; i++)
  757. np->rx_ring[i].FlagLen = 0;
  758. }
  759. static void nv_init_tx(struct net_device *dev)
  760. {
  761. struct fe_priv *np = get_nvpriv(dev);
  762. int i;
  763. np->next_tx = np->nic_tx = 0;
  764. for (i = 0; i < TX_RING; i++)
  765. np->tx_ring[i].FlagLen = 0;
  766. }
  767. static int nv_init_ring(struct net_device *dev)
  768. {
  769. nv_init_tx(dev);
  770. nv_init_rx(dev);
  771. return nv_alloc_rx(dev);
  772. }
  773. static void nv_drain_tx(struct net_device *dev)
  774. {
  775. struct fe_priv *np = get_nvpriv(dev);
  776. int i;
  777. for (i = 0; i < TX_RING; i++) {
  778. np->tx_ring[i].FlagLen = 0;
  779. if (np->tx_skbuff[i]) {
  780. pci_unmap_single(np->pci_dev, np->tx_dma[i],
  781. np->tx_skbuff[i]->len,
  782. PCI_DMA_TODEVICE);
  783. dev_kfree_skb(np->tx_skbuff[i]);
  784. np->tx_skbuff[i] = NULL;
  785. np->stats.tx_dropped++;
  786. }
  787. }
  788. }
  789. static void nv_drain_rx(struct net_device *dev)
  790. {
  791. struct fe_priv *np = get_nvpriv(dev);
  792. int i;
  793. for (i = 0; i < RX_RING; i++) {
  794. np->rx_ring[i].FlagLen = 0;
  795. wmb();
  796. if (np->rx_skbuff[i]) {
  797. pci_unmap_single(np->pci_dev, np->rx_dma[i],
  798. np->rx_skbuff[i]->len,
  799. PCI_DMA_FROMDEVICE);
  800. dev_kfree_skb(np->rx_skbuff[i]);
  801. np->rx_skbuff[i] = NULL;
  802. }
  803. }
  804. }
  805. static void drain_ring(struct net_device *dev)
  806. {
  807. nv_drain_tx(dev);
  808. nv_drain_rx(dev);
  809. }
  810. /*
  811. * nv_start_xmit: dev->hard_start_xmit function
  812. * Called with dev->xmit_lock held.
  813. */
  814. static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
  815. {
  816. struct fe_priv *np = get_nvpriv(dev);
  817. int nr = np->next_tx % TX_RING;
  818. np->tx_skbuff[nr] = skb;
  819. np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
  820. PCI_DMA_TODEVICE);
  821. np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
  822. spin_lock_irq(&np->lock);
  823. wmb();
  824. np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
  825. dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
  826. dev->name, np->next_tx);
  827. {
  828. int j;
  829. for (j=0; j<64; j++) {
  830. if ((j%16) == 0)
  831. dprintk("\n%03x:", j);
  832. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  833. }
  834. dprintk("\n");
  835. }
  836. np->next_tx++;
  837. dev->trans_start = jiffies;
  838. if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
  839. netif_stop_queue(dev);
  840. spin_unlock_irq(&np->lock);
  841. writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
  842. pci_push(get_hwbase(dev));
  843. return 0;
  844. }
  845. /*
  846. * nv_tx_done: check for completed packets, release the skbs.
  847. *
  848. * Caller must own np->lock.
  849. */
  850. static void nv_tx_done(struct net_device *dev)
  851. {
  852. struct fe_priv *np = get_nvpriv(dev);
  853. u32 Flags;
  854. int i;
  855. while (np->nic_tx != np->next_tx) {
  856. i = np->nic_tx % TX_RING;
  857. Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
  858. dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
  859. dev->name, np->nic_tx, Flags);
  860. if (Flags & NV_TX_VALID)
  861. break;
  862. if (np->desc_ver == DESC_VER_1) {
  863. if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
  864. NV_TX_UNDERFLOW|NV_TX_ERROR)) {
  865. if (Flags & NV_TX_UNDERFLOW)
  866. np->stats.tx_fifo_errors++;
  867. if (Flags & NV_TX_CARRIERLOST)
  868. np->stats.tx_carrier_errors++;
  869. np->stats.tx_errors++;
  870. } else {
  871. np->stats.tx_packets++;
  872. np->stats.tx_bytes += np->tx_skbuff[i]->len;
  873. }
  874. } else {
  875. if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
  876. NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
  877. if (Flags & NV_TX2_UNDERFLOW)
  878. np->stats.tx_fifo_errors++;
  879. if (Flags & NV_TX2_CARRIERLOST)
  880. np->stats.tx_carrier_errors++;
  881. np->stats.tx_errors++;
  882. } else {
  883. np->stats.tx_packets++;
  884. np->stats.tx_bytes += np->tx_skbuff[i]->len;
  885. }
  886. }
  887. pci_unmap_single(np->pci_dev, np->tx_dma[i],
  888. np->tx_skbuff[i]->len,
  889. PCI_DMA_TODEVICE);
  890. dev_kfree_skb_irq(np->tx_skbuff[i]);
  891. np->tx_skbuff[i] = NULL;
  892. np->nic_tx++;
  893. }
  894. if (np->next_tx - np->nic_tx < TX_LIMIT_START)
  895. netif_wake_queue(dev);
  896. }
  897. /*
  898. * nv_tx_timeout: dev->tx_timeout function
  899. * Called with dev->xmit_lock held.
  900. */
  901. static void nv_tx_timeout(struct net_device *dev)
  902. {
  903. struct fe_priv *np = get_nvpriv(dev);
  904. u8 __iomem *base = get_hwbase(dev);
  905. printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
  906. readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
  907. {
  908. int i;
  909. printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
  910. dev->name, (unsigned long)np->ring_addr,
  911. np->next_tx, np->nic_tx);
  912. printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
  913. for (i=0;i<0x400;i+= 32) {
  914. printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  915. i,
  916. readl(base + i + 0), readl(base + i + 4),
  917. readl(base + i + 8), readl(base + i + 12),
  918. readl(base + i + 16), readl(base + i + 20),
  919. readl(base + i + 24), readl(base + i + 28));
  920. }
  921. printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
  922. for (i=0;i<TX_RING;i+= 4) {
  923. printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
  924. i,
  925. le32_to_cpu(np->tx_ring[i].PacketBuffer),
  926. le32_to_cpu(np->tx_ring[i].FlagLen),
  927. le32_to_cpu(np->tx_ring[i+1].PacketBuffer),
  928. le32_to_cpu(np->tx_ring[i+1].FlagLen),
  929. le32_to_cpu(np->tx_ring[i+2].PacketBuffer),
  930. le32_to_cpu(np->tx_ring[i+2].FlagLen),
  931. le32_to_cpu(np->tx_ring[i+3].PacketBuffer),
  932. le32_to_cpu(np->tx_ring[i+3].FlagLen));
  933. }
  934. }
  935. spin_lock_irq(&np->lock);
  936. /* 1) stop tx engine */
  937. nv_stop_tx(dev);
  938. /* 2) check that the packets were not sent already: */
  939. nv_tx_done(dev);
  940. /* 3) if there are dead entries: clear everything */
  941. if (np->next_tx != np->nic_tx) {
  942. printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
  943. nv_drain_tx(dev);
  944. np->next_tx = np->nic_tx = 0;
  945. writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  946. netif_wake_queue(dev);
  947. }
  948. /* 4) restart tx engine */
  949. nv_start_tx(dev);
  950. spin_unlock_irq(&np->lock);
  951. }
  952. /*
  953. * Called when the nic notices a mismatch between the actual data len on the
  954. * wire and the len indicated in the 802 header
  955. */
  956. static int nv_getlen(struct net_device *dev, void *packet, int datalen)
  957. {
  958. int hdrlen; /* length of the 802 header */
  959. int protolen; /* length as stored in the proto field */
  960. /* 1) calculate len according to header */
  961. if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
  962. protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
  963. hdrlen = VLAN_HLEN;
  964. } else {
  965. protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
  966. hdrlen = ETH_HLEN;
  967. }
  968. dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
  969. dev->name, datalen, protolen, hdrlen);
  970. if (protolen > ETH_DATA_LEN)
  971. return datalen; /* Value in proto field not a len, no checks possible */
  972. protolen += hdrlen;
  973. /* consistency checks: */
  974. if (datalen > ETH_ZLEN) {
  975. if (datalen >= protolen) {
  976. /* more data on wire than in 802 header, trim of
  977. * additional data.
  978. */
  979. dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
  980. dev->name, protolen);
  981. return protolen;
  982. } else {
  983. /* less data on wire than mentioned in header.
  984. * Discard the packet.
  985. */
  986. dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
  987. dev->name);
  988. return -1;
  989. }
  990. } else {
  991. /* short packet. Accept only if 802 values are also short */
  992. if (protolen > ETH_ZLEN) {
  993. dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
  994. dev->name);
  995. return -1;
  996. }
  997. dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
  998. dev->name, datalen);
  999. return datalen;
  1000. }
  1001. }
  1002. static void nv_rx_process(struct net_device *dev)
  1003. {
  1004. struct fe_priv *np = get_nvpriv(dev);
  1005. u32 Flags;
  1006. for (;;) {
  1007. struct sk_buff *skb;
  1008. int len;
  1009. int i;
  1010. if (np->cur_rx - np->refill_rx >= RX_RING)
  1011. break; /* we scanned the whole ring - do not continue */
  1012. i = np->cur_rx % RX_RING;
  1013. Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
  1014. len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
  1015. dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
  1016. dev->name, np->cur_rx, Flags);
  1017. if (Flags & NV_RX_AVAIL)
  1018. break; /* still owned by hardware, */
  1019. /*
  1020. * the packet is for us - immediately tear down the pci mapping.
  1021. * TODO: check if a prefetch of the first cacheline improves
  1022. * the performance.
  1023. */
  1024. pci_unmap_single(np->pci_dev, np->rx_dma[i],
  1025. np->rx_skbuff[i]->len,
  1026. PCI_DMA_FROMDEVICE);
  1027. {
  1028. int j;
  1029. dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
  1030. for (j=0; j<64; j++) {
  1031. if ((j%16) == 0)
  1032. dprintk("\n%03x:", j);
  1033. dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
  1034. }
  1035. dprintk("\n");
  1036. }
  1037. /* look at what we actually got: */
  1038. if (np->desc_ver == DESC_VER_1) {
  1039. if (!(Flags & NV_RX_DESCRIPTORVALID))
  1040. goto next_pkt;
  1041. if (Flags & NV_RX_MISSEDFRAME) {
  1042. np->stats.rx_missed_errors++;
  1043. np->stats.rx_errors++;
  1044. goto next_pkt;
  1045. }
  1046. if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
  1047. np->stats.rx_errors++;
  1048. goto next_pkt;
  1049. }
  1050. if (Flags & NV_RX_CRCERR) {
  1051. np->stats.rx_crc_errors++;
  1052. np->stats.rx_errors++;
  1053. goto next_pkt;
  1054. }
  1055. if (Flags & NV_RX_OVERFLOW) {
  1056. np->stats.rx_over_errors++;
  1057. np->stats.rx_errors++;
  1058. goto next_pkt;
  1059. }
  1060. if (Flags & NV_RX_ERROR4) {
  1061. len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
  1062. if (len < 0) {
  1063. np->stats.rx_errors++;
  1064. goto next_pkt;
  1065. }
  1066. }
  1067. /* framing errors are soft errors. */
  1068. if (Flags & NV_RX_FRAMINGERR) {
  1069. if (Flags & NV_RX_SUBSTRACT1) {
  1070. len--;
  1071. }
  1072. }
  1073. } else {
  1074. if (!(Flags & NV_RX2_DESCRIPTORVALID))
  1075. goto next_pkt;
  1076. if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
  1077. np->stats.rx_errors++;
  1078. goto next_pkt;
  1079. }
  1080. if (Flags & NV_RX2_CRCERR) {
  1081. np->stats.rx_crc_errors++;
  1082. np->stats.rx_errors++;
  1083. goto next_pkt;
  1084. }
  1085. if (Flags & NV_RX2_OVERFLOW) {
  1086. np->stats.rx_over_errors++;
  1087. np->stats.rx_errors++;
  1088. goto next_pkt;
  1089. }
  1090. if (Flags & NV_RX2_ERROR4) {
  1091. len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
  1092. if (len < 0) {
  1093. np->stats.rx_errors++;
  1094. goto next_pkt;
  1095. }
  1096. }
  1097. /* framing errors are soft errors */
  1098. if (Flags & NV_RX2_FRAMINGERR) {
  1099. if (Flags & NV_RX2_SUBSTRACT1) {
  1100. len--;
  1101. }
  1102. }
  1103. Flags &= NV_RX2_CHECKSUMMASK;
  1104. if (Flags == NV_RX2_CHECKSUMOK1 ||
  1105. Flags == NV_RX2_CHECKSUMOK2 ||
  1106. Flags == NV_RX2_CHECKSUMOK3) {
  1107. dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
  1108. np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
  1109. } else {
  1110. dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
  1111. }
  1112. }
  1113. /* got a valid packet - forward it to the network core */
  1114. skb = np->rx_skbuff[i];
  1115. np->rx_skbuff[i] = NULL;
  1116. skb_put(skb, len);
  1117. skb->protocol = eth_type_trans(skb, dev);
  1118. dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
  1119. dev->name, np->cur_rx, len, skb->protocol);
  1120. netif_rx(skb);
  1121. dev->last_rx = jiffies;
  1122. np->stats.rx_packets++;
  1123. np->stats.rx_bytes += len;
  1124. next_pkt:
  1125. np->cur_rx++;
  1126. }
  1127. }
  1128. static void set_bufsize(struct net_device *dev)
  1129. {
  1130. struct fe_priv *np = netdev_priv(dev);
  1131. if (dev->mtu <= ETH_DATA_LEN)
  1132. np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
  1133. else
  1134. np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
  1135. }
  1136. /*
  1137. * nv_change_mtu: dev->change_mtu function
  1138. * Called with dev_base_lock held for read.
  1139. */
  1140. static int nv_change_mtu(struct net_device *dev, int new_mtu)
  1141. {
  1142. struct fe_priv *np = get_nvpriv(dev);
  1143. int old_mtu;
  1144. if (new_mtu < 64 || new_mtu > np->pkt_limit)
  1145. return -EINVAL;
  1146. old_mtu = dev->mtu;
  1147. dev->mtu = new_mtu;
  1148. /* return early if the buffer sizes will not change */
  1149. if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
  1150. return 0;
  1151. if (old_mtu == new_mtu)
  1152. return 0;
  1153. /* synchronized against open : rtnl_lock() held by caller */
  1154. if (netif_running(dev)) {
  1155. u8 *base = get_hwbase(dev);
  1156. /*
  1157. * It seems that the nic preloads valid ring entries into an
  1158. * internal buffer. The procedure for flushing everything is
  1159. * guessed, there is probably a simpler approach.
  1160. * Changing the MTU is a rare event, it shouldn't matter.
  1161. */
  1162. disable_irq(dev->irq);
  1163. spin_lock_bh(&dev->xmit_lock);
  1164. spin_lock(&np->lock);
  1165. /* stop engines */
  1166. nv_stop_rx(dev);
  1167. nv_stop_tx(dev);
  1168. nv_txrx_reset(dev);
  1169. /* drain rx queue */
  1170. nv_drain_rx(dev);
  1171. nv_drain_tx(dev);
  1172. /* reinit driver view of the rx queue */
  1173. nv_init_rx(dev);
  1174. nv_init_tx(dev);
  1175. /* alloc new rx buffers */
  1176. set_bufsize(dev);
  1177. if (nv_alloc_rx(dev)) {
  1178. if (!np->in_shutdown)
  1179. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  1180. }
  1181. /* reinit nic view of the rx queue */
  1182. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  1183. writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
  1184. writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  1185. writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
  1186. base + NvRegRingSizes);
  1187. pci_push(base);
  1188. writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
  1189. pci_push(base);
  1190. /* restart rx engine */
  1191. nv_start_rx(dev);
  1192. nv_start_tx(dev);
  1193. spin_unlock(&np->lock);
  1194. spin_unlock_bh(&dev->xmit_lock);
  1195. enable_irq(dev->irq);
  1196. }
  1197. return 0;
  1198. }
  1199. /*
  1200. * nv_set_multicast: dev->set_multicast function
  1201. * Called with dev->xmit_lock held.
  1202. */
  1203. static void nv_set_multicast(struct net_device *dev)
  1204. {
  1205. struct fe_priv *np = get_nvpriv(dev);
  1206. u8 __iomem *base = get_hwbase(dev);
  1207. u32 addr[2];
  1208. u32 mask[2];
  1209. u32 pff;
  1210. memset(addr, 0, sizeof(addr));
  1211. memset(mask, 0, sizeof(mask));
  1212. if (dev->flags & IFF_PROMISC) {
  1213. printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
  1214. pff = NVREG_PFF_PROMISC;
  1215. } else {
  1216. pff = NVREG_PFF_MYADDR;
  1217. if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
  1218. u32 alwaysOff[2];
  1219. u32 alwaysOn[2];
  1220. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
  1221. if (dev->flags & IFF_ALLMULTI) {
  1222. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
  1223. } else {
  1224. struct dev_mc_list *walk;
  1225. walk = dev->mc_list;
  1226. while (walk != NULL) {
  1227. u32 a, b;
  1228. a = le32_to_cpu(*(u32 *) walk->dmi_addr);
  1229. b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
  1230. alwaysOn[0] &= a;
  1231. alwaysOff[0] &= ~a;
  1232. alwaysOn[1] &= b;
  1233. alwaysOff[1] &= ~b;
  1234. walk = walk->next;
  1235. }
  1236. }
  1237. addr[0] = alwaysOn[0];
  1238. addr[1] = alwaysOn[1];
  1239. mask[0] = alwaysOn[0] | alwaysOff[0];
  1240. mask[1] = alwaysOn[1] | alwaysOff[1];
  1241. }
  1242. }
  1243. addr[0] |= NVREG_MCASTADDRA_FORCE;
  1244. pff |= NVREG_PFF_ALWAYS;
  1245. spin_lock_irq(&np->lock);
  1246. nv_stop_rx(dev);
  1247. writel(addr[0], base + NvRegMulticastAddrA);
  1248. writel(addr[1], base + NvRegMulticastAddrB);
  1249. writel(mask[0], base + NvRegMulticastMaskA);
  1250. writel(mask[1], base + NvRegMulticastMaskB);
  1251. writel(pff, base + NvRegPacketFilterFlags);
  1252. dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
  1253. dev->name);
  1254. nv_start_rx(dev);
  1255. spin_unlock_irq(&np->lock);
  1256. }
  1257. static int nv_update_linkspeed(struct net_device *dev)
  1258. {
  1259. struct fe_priv *np = get_nvpriv(dev);
  1260. u8 __iomem *base = get_hwbase(dev);
  1261. int adv, lpa;
  1262. int newls = np->linkspeed;
  1263. int newdup = np->duplex;
  1264. int mii_status;
  1265. int retval = 0;
  1266. u32 control_1000, status_1000, phyreg;
  1267. /* BMSR_LSTATUS is latched, read it twice:
  1268. * we want the current value.
  1269. */
  1270. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  1271. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  1272. if (!(mii_status & BMSR_LSTATUS)) {
  1273. dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
  1274. dev->name);
  1275. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1276. newdup = 0;
  1277. retval = 0;
  1278. goto set_speed;
  1279. }
  1280. if (np->autoneg == 0) {
  1281. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
  1282. dev->name, np->fixed_mode);
  1283. if (np->fixed_mode & LPA_100FULL) {
  1284. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  1285. newdup = 1;
  1286. } else if (np->fixed_mode & LPA_100HALF) {
  1287. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  1288. newdup = 0;
  1289. } else if (np->fixed_mode & LPA_10FULL) {
  1290. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1291. newdup = 1;
  1292. } else {
  1293. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1294. newdup = 0;
  1295. }
  1296. retval = 1;
  1297. goto set_speed;
  1298. }
  1299. /* check auto negotiation is complete */
  1300. if (!(mii_status & BMSR_ANEGCOMPLETE)) {
  1301. /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
  1302. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1303. newdup = 0;
  1304. retval = 0;
  1305. dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
  1306. goto set_speed;
  1307. }
  1308. retval = 1;
  1309. if (np->gigabit == PHY_GIGABIT) {
  1310. control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
  1311. status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
  1312. if ((control_1000 & ADVERTISE_1000FULL) &&
  1313. (status_1000 & LPA_1000FULL)) {
  1314. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
  1315. dev->name);
  1316. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
  1317. newdup = 1;
  1318. goto set_speed;
  1319. }
  1320. }
  1321. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1322. lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
  1323. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
  1324. dev->name, adv, lpa);
  1325. /* FIXME: handle parallel detection properly */
  1326. lpa = lpa & adv;
  1327. if (lpa & LPA_100FULL) {
  1328. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  1329. newdup = 1;
  1330. } else if (lpa & LPA_100HALF) {
  1331. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  1332. newdup = 0;
  1333. } else if (lpa & LPA_10FULL) {
  1334. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1335. newdup = 1;
  1336. } else if (lpa & LPA_10HALF) {
  1337. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1338. newdup = 0;
  1339. } else {
  1340. dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
  1341. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  1342. newdup = 0;
  1343. }
  1344. set_speed:
  1345. if (np->duplex == newdup && np->linkspeed == newls)
  1346. return retval;
  1347. dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
  1348. dev->name, np->linkspeed, np->duplex, newls, newdup);
  1349. np->duplex = newdup;
  1350. np->linkspeed = newls;
  1351. if (np->gigabit == PHY_GIGABIT) {
  1352. phyreg = readl(base + NvRegRandomSeed);
  1353. phyreg &= ~(0x3FF00);
  1354. if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
  1355. phyreg |= NVREG_RNDSEED_FORCE3;
  1356. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
  1357. phyreg |= NVREG_RNDSEED_FORCE2;
  1358. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
  1359. phyreg |= NVREG_RNDSEED_FORCE;
  1360. writel(phyreg, base + NvRegRandomSeed);
  1361. }
  1362. phyreg = readl(base + NvRegPhyInterface);
  1363. phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
  1364. if (np->duplex == 0)
  1365. phyreg |= PHY_HALF;
  1366. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
  1367. phyreg |= PHY_100;
  1368. else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  1369. phyreg |= PHY_1000;
  1370. writel(phyreg, base + NvRegPhyInterface);
  1371. writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
  1372. base + NvRegMisc1);
  1373. pci_push(base);
  1374. writel(np->linkspeed, base + NvRegLinkSpeed);
  1375. pci_push(base);
  1376. return retval;
  1377. }
  1378. static void nv_linkchange(struct net_device *dev)
  1379. {
  1380. if (nv_update_linkspeed(dev)) {
  1381. if (netif_carrier_ok(dev)) {
  1382. nv_stop_rx(dev);
  1383. } else {
  1384. netif_carrier_on(dev);
  1385. printk(KERN_INFO "%s: link up.\n", dev->name);
  1386. }
  1387. nv_start_rx(dev);
  1388. } else {
  1389. if (netif_carrier_ok(dev)) {
  1390. netif_carrier_off(dev);
  1391. printk(KERN_INFO "%s: link down.\n", dev->name);
  1392. nv_stop_rx(dev);
  1393. }
  1394. }
  1395. }
  1396. static void nv_link_irq(struct net_device *dev)
  1397. {
  1398. u8 __iomem *base = get_hwbase(dev);
  1399. u32 miistat;
  1400. miistat = readl(base + NvRegMIIStatus);
  1401. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  1402. dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
  1403. if (miistat & (NVREG_MIISTAT_LINKCHANGE))
  1404. nv_linkchange(dev);
  1405. dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
  1406. }
  1407. static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
  1408. {
  1409. struct net_device *dev = (struct net_device *) data;
  1410. struct fe_priv *np = get_nvpriv(dev);
  1411. u8 __iomem *base = get_hwbase(dev);
  1412. u32 events;
  1413. int i;
  1414. dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
  1415. for (i=0; ; i++) {
  1416. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  1417. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  1418. pci_push(base);
  1419. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  1420. if (!(events & np->irqmask))
  1421. break;
  1422. if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
  1423. spin_lock(&np->lock);
  1424. nv_tx_done(dev);
  1425. spin_unlock(&np->lock);
  1426. }
  1427. if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
  1428. nv_rx_process(dev);
  1429. if (nv_alloc_rx(dev)) {
  1430. spin_lock(&np->lock);
  1431. if (!np->in_shutdown)
  1432. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  1433. spin_unlock(&np->lock);
  1434. }
  1435. }
  1436. if (events & NVREG_IRQ_LINK) {
  1437. spin_lock(&np->lock);
  1438. nv_link_irq(dev);
  1439. spin_unlock(&np->lock);
  1440. }
  1441. if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
  1442. spin_lock(&np->lock);
  1443. nv_linkchange(dev);
  1444. spin_unlock(&np->lock);
  1445. np->link_timeout = jiffies + LINK_TIMEOUT;
  1446. }
  1447. if (events & (NVREG_IRQ_TX_ERR)) {
  1448. dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
  1449. dev->name, events);
  1450. }
  1451. if (events & (NVREG_IRQ_UNKNOWN)) {
  1452. printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
  1453. dev->name, events);
  1454. }
  1455. if (i > max_interrupt_work) {
  1456. spin_lock(&np->lock);
  1457. /* disable interrupts on the nic */
  1458. writel(0, base + NvRegIrqMask);
  1459. pci_push(base);
  1460. if (!np->in_shutdown)
  1461. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  1462. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
  1463. spin_unlock(&np->lock);
  1464. break;
  1465. }
  1466. }
  1467. dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
  1468. return IRQ_RETVAL(i);
  1469. }
  1470. static void nv_do_nic_poll(unsigned long data)
  1471. {
  1472. struct net_device *dev = (struct net_device *) data;
  1473. struct fe_priv *np = get_nvpriv(dev);
  1474. u8 __iomem *base = get_hwbase(dev);
  1475. disable_irq(dev->irq);
  1476. /* FIXME: Do we need synchronize_irq(dev->irq) here? */
  1477. /*
  1478. * reenable interrupts on the nic, we have to do this before calling
  1479. * nv_nic_irq because that may decide to do otherwise
  1480. */
  1481. writel(np->irqmask, base + NvRegIrqMask);
  1482. pci_push(base);
  1483. nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
  1484. enable_irq(dev->irq);
  1485. }
  1486. #ifdef CONFIG_NET_POLL_CONTROLLER
  1487. static void nv_poll_controller(struct net_device *dev)
  1488. {
  1489. nv_do_nic_poll((unsigned long) dev);
  1490. }
  1491. #endif
  1492. static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1493. {
  1494. struct fe_priv *np = get_nvpriv(dev);
  1495. strcpy(info->driver, "forcedeth");
  1496. strcpy(info->version, FORCEDETH_VERSION);
  1497. strcpy(info->bus_info, pci_name(np->pci_dev));
  1498. }
  1499. static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  1500. {
  1501. struct fe_priv *np = get_nvpriv(dev);
  1502. wolinfo->supported = WAKE_MAGIC;
  1503. spin_lock_irq(&np->lock);
  1504. if (np->wolenabled)
  1505. wolinfo->wolopts = WAKE_MAGIC;
  1506. spin_unlock_irq(&np->lock);
  1507. }
  1508. static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  1509. {
  1510. struct fe_priv *np = get_nvpriv(dev);
  1511. u8 __iomem *base = get_hwbase(dev);
  1512. spin_lock_irq(&np->lock);
  1513. if (wolinfo->wolopts == 0) {
  1514. writel(0, base + NvRegWakeUpFlags);
  1515. np->wolenabled = 0;
  1516. }
  1517. if (wolinfo->wolopts & WAKE_MAGIC) {
  1518. writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
  1519. np->wolenabled = 1;
  1520. }
  1521. spin_unlock_irq(&np->lock);
  1522. return 0;
  1523. }
  1524. static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  1525. {
  1526. struct fe_priv *np = netdev_priv(dev);
  1527. int adv;
  1528. spin_lock_irq(&np->lock);
  1529. ecmd->port = PORT_MII;
  1530. if (!netif_running(dev)) {
  1531. /* We do not track link speed / duplex setting if the
  1532. * interface is disabled. Force a link check */
  1533. nv_update_linkspeed(dev);
  1534. }
  1535. switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
  1536. case NVREG_LINKSPEED_10:
  1537. ecmd->speed = SPEED_10;
  1538. break;
  1539. case NVREG_LINKSPEED_100:
  1540. ecmd->speed = SPEED_100;
  1541. break;
  1542. case NVREG_LINKSPEED_1000:
  1543. ecmd->speed = SPEED_1000;
  1544. break;
  1545. }
  1546. ecmd->duplex = DUPLEX_HALF;
  1547. if (np->duplex)
  1548. ecmd->duplex = DUPLEX_FULL;
  1549. ecmd->autoneg = np->autoneg;
  1550. ecmd->advertising = ADVERTISED_MII;
  1551. if (np->autoneg) {
  1552. ecmd->advertising |= ADVERTISED_Autoneg;
  1553. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1554. } else {
  1555. adv = np->fixed_mode;
  1556. }
  1557. if (adv & ADVERTISE_10HALF)
  1558. ecmd->advertising |= ADVERTISED_10baseT_Half;
  1559. if (adv & ADVERTISE_10FULL)
  1560. ecmd->advertising |= ADVERTISED_10baseT_Full;
  1561. if (adv & ADVERTISE_100HALF)
  1562. ecmd->advertising |= ADVERTISED_100baseT_Half;
  1563. if (adv & ADVERTISE_100FULL)
  1564. ecmd->advertising |= ADVERTISED_100baseT_Full;
  1565. if (np->autoneg && np->gigabit == PHY_GIGABIT) {
  1566. adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
  1567. if (adv & ADVERTISE_1000FULL)
  1568. ecmd->advertising |= ADVERTISED_1000baseT_Full;
  1569. }
  1570. ecmd->supported = (SUPPORTED_Autoneg |
  1571. SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  1572. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  1573. SUPPORTED_MII);
  1574. if (np->gigabit == PHY_GIGABIT)
  1575. ecmd->supported |= SUPPORTED_1000baseT_Full;
  1576. ecmd->phy_address = np->phyaddr;
  1577. ecmd->transceiver = XCVR_EXTERNAL;
  1578. /* ignore maxtxpkt, maxrxpkt for now */
  1579. spin_unlock_irq(&np->lock);
  1580. return 0;
  1581. }
  1582. static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  1583. {
  1584. struct fe_priv *np = netdev_priv(dev);
  1585. if (ecmd->port != PORT_MII)
  1586. return -EINVAL;
  1587. if (ecmd->transceiver != XCVR_EXTERNAL)
  1588. return -EINVAL;
  1589. if (ecmd->phy_address != np->phyaddr) {
  1590. /* TODO: support switching between multiple phys. Should be
  1591. * trivial, but not enabled due to lack of test hardware. */
  1592. return -EINVAL;
  1593. }
  1594. if (ecmd->autoneg == AUTONEG_ENABLE) {
  1595. u32 mask;
  1596. mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  1597. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  1598. if (np->gigabit == PHY_GIGABIT)
  1599. mask |= ADVERTISED_1000baseT_Full;
  1600. if ((ecmd->advertising & mask) == 0)
  1601. return -EINVAL;
  1602. } else if (ecmd->autoneg == AUTONEG_DISABLE) {
  1603. /* Note: autonegotiation disable, speed 1000 intentionally
  1604. * forbidden - noone should need that. */
  1605. if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
  1606. return -EINVAL;
  1607. if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
  1608. return -EINVAL;
  1609. } else {
  1610. return -EINVAL;
  1611. }
  1612. spin_lock_irq(&np->lock);
  1613. if (ecmd->autoneg == AUTONEG_ENABLE) {
  1614. int adv, bmcr;
  1615. np->autoneg = 1;
  1616. /* advertise only what has been requested */
  1617. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1618. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  1619. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  1620. adv |= ADVERTISE_10HALF;
  1621. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  1622. adv |= ADVERTISE_10FULL;
  1623. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  1624. adv |= ADVERTISE_100HALF;
  1625. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  1626. adv |= ADVERTISE_100FULL;
  1627. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  1628. if (np->gigabit == PHY_GIGABIT) {
  1629. adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
  1630. adv &= ~ADVERTISE_1000FULL;
  1631. if (ecmd->advertising & ADVERTISED_1000baseT_Full)
  1632. adv |= ADVERTISE_1000FULL;
  1633. mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
  1634. }
  1635. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1636. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  1637. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  1638. } else {
  1639. int adv, bmcr;
  1640. np->autoneg = 0;
  1641. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1642. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  1643. if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
  1644. adv |= ADVERTISE_10HALF;
  1645. if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
  1646. adv |= ADVERTISE_10FULL;
  1647. if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
  1648. adv |= ADVERTISE_100HALF;
  1649. if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
  1650. adv |= ADVERTISE_100FULL;
  1651. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  1652. np->fixed_mode = adv;
  1653. if (np->gigabit == PHY_GIGABIT) {
  1654. adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
  1655. adv &= ~ADVERTISE_1000FULL;
  1656. mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
  1657. }
  1658. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1659. bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
  1660. if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
  1661. bmcr |= BMCR_FULLDPLX;
  1662. if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
  1663. bmcr |= BMCR_SPEED100;
  1664. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  1665. if (netif_running(dev)) {
  1666. /* Wait a bit and then reconfigure the nic. */
  1667. udelay(10);
  1668. nv_linkchange(dev);
  1669. }
  1670. }
  1671. spin_unlock_irq(&np->lock);
  1672. return 0;
  1673. }
  1674. #define FORCEDETH_REGS_VER 1
  1675. #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
  1676. static int nv_get_regs_len(struct net_device *dev)
  1677. {
  1678. return FORCEDETH_REGS_SIZE;
  1679. }
  1680. static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
  1681. {
  1682. struct fe_priv *np = get_nvpriv(dev);
  1683. u8 __iomem *base = get_hwbase(dev);
  1684. u32 *rbuf = buf;
  1685. int i;
  1686. regs->version = FORCEDETH_REGS_VER;
  1687. spin_lock_irq(&np->lock);
  1688. for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
  1689. rbuf[i] = readl(base + i*sizeof(u32));
  1690. spin_unlock_irq(&np->lock);
  1691. }
  1692. static int nv_nway_reset(struct net_device *dev)
  1693. {
  1694. struct fe_priv *np = get_nvpriv(dev);
  1695. int ret;
  1696. spin_lock_irq(&np->lock);
  1697. if (np->autoneg) {
  1698. int bmcr;
  1699. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1700. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  1701. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  1702. ret = 0;
  1703. } else {
  1704. ret = -EINVAL;
  1705. }
  1706. spin_unlock_irq(&np->lock);
  1707. return ret;
  1708. }
  1709. static struct ethtool_ops ops = {
  1710. .get_drvinfo = nv_get_drvinfo,
  1711. .get_link = ethtool_op_get_link,
  1712. .get_wol = nv_get_wol,
  1713. .set_wol = nv_set_wol,
  1714. .get_settings = nv_get_settings,
  1715. .set_settings = nv_set_settings,
  1716. .get_regs_len = nv_get_regs_len,
  1717. .get_regs = nv_get_regs,
  1718. .nway_reset = nv_nway_reset,
  1719. };
  1720. static int nv_open(struct net_device *dev)
  1721. {
  1722. struct fe_priv *np = get_nvpriv(dev);
  1723. u8 __iomem *base = get_hwbase(dev);
  1724. int ret, oom, i;
  1725. dprintk(KERN_DEBUG "nv_open: begin\n");
  1726. /* 1) erase previous misconfiguration */
  1727. /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
  1728. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  1729. writel(0, base + NvRegMulticastAddrB);
  1730. writel(0, base + NvRegMulticastMaskA);
  1731. writel(0, base + NvRegMulticastMaskB);
  1732. writel(0, base + NvRegPacketFilterFlags);
  1733. writel(0, base + NvRegTransmitterControl);
  1734. writel(0, base + NvRegReceiverControl);
  1735. writel(0, base + NvRegAdapterControl);
  1736. /* 2) initialize descriptor rings */
  1737. set_bufsize(dev);
  1738. oom = nv_init_ring(dev);
  1739. writel(0, base + NvRegLinkSpeed);
  1740. writel(0, base + NvRegUnknownTransmitterReg);
  1741. nv_txrx_reset(dev);
  1742. writel(0, base + NvRegUnknownSetupReg6);
  1743. np->in_shutdown = 0;
  1744. /* 3) set mac address */
  1745. {
  1746. u32 mac[2];
  1747. mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
  1748. (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
  1749. mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
  1750. writel(mac[0], base + NvRegMacAddrA);
  1751. writel(mac[1], base + NvRegMacAddrB);
  1752. }
  1753. /* 4) give hw rings */
  1754. writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
  1755. writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  1756. writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
  1757. base + NvRegRingSizes);
  1758. /* 5) continue setup */
  1759. writel(np->linkspeed, base + NvRegLinkSpeed);
  1760. writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
  1761. writel(np->desc_ver, base + NvRegTxRxControl);
  1762. pci_push(base);
  1763. writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
  1764. reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
  1765. NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
  1766. KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
  1767. writel(0, base + NvRegUnknownSetupReg4);
  1768. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  1769. writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
  1770. /* 6) continue setup */
  1771. writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
  1772. writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
  1773. writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
  1774. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  1775. writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
  1776. get_random_bytes(&i, sizeof(i));
  1777. writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
  1778. writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
  1779. writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
  1780. writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
  1781. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  1782. writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
  1783. base + NvRegAdapterControl);
  1784. writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
  1785. writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
  1786. writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
  1787. i = readl(base + NvRegPowerState);
  1788. if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
  1789. writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
  1790. pci_push(base);
  1791. udelay(10);
  1792. writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
  1793. writel(0, base + NvRegIrqMask);
  1794. pci_push(base);
  1795. writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
  1796. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  1797. pci_push(base);
  1798. ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
  1799. if (ret)
  1800. goto out_drain;
  1801. /* ask for interrupts */
  1802. writel(np->irqmask, base + NvRegIrqMask);
  1803. spin_lock_irq(&np->lock);
  1804. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  1805. writel(0, base + NvRegMulticastAddrB);
  1806. writel(0, base + NvRegMulticastMaskA);
  1807. writel(0, base + NvRegMulticastMaskB);
  1808. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  1809. /* One manual link speed update: Interrupts are enabled, future link
  1810. * speed changes cause interrupts and are handled by nv_link_irq().
  1811. */
  1812. {
  1813. u32 miistat;
  1814. miistat = readl(base + NvRegMIIStatus);
  1815. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  1816. dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
  1817. }
  1818. ret = nv_update_linkspeed(dev);
  1819. nv_start_rx(dev);
  1820. nv_start_tx(dev);
  1821. netif_start_queue(dev);
  1822. if (ret) {
  1823. netif_carrier_on(dev);
  1824. } else {
  1825. printk("%s: no link during initialization.\n", dev->name);
  1826. netif_carrier_off(dev);
  1827. }
  1828. if (oom)
  1829. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  1830. spin_unlock_irq(&np->lock);
  1831. return 0;
  1832. out_drain:
  1833. drain_ring(dev);
  1834. return ret;
  1835. }
  1836. static int nv_close(struct net_device *dev)
  1837. {
  1838. struct fe_priv *np = get_nvpriv(dev);
  1839. u8 __iomem *base;
  1840. spin_lock_irq(&np->lock);
  1841. np->in_shutdown = 1;
  1842. spin_unlock_irq(&np->lock);
  1843. synchronize_irq(dev->irq);
  1844. del_timer_sync(&np->oom_kick);
  1845. del_timer_sync(&np->nic_poll);
  1846. netif_stop_queue(dev);
  1847. spin_lock_irq(&np->lock);
  1848. nv_stop_tx(dev);
  1849. nv_stop_rx(dev);
  1850. nv_txrx_reset(dev);
  1851. /* disable interrupts on the nic or we will lock up */
  1852. base = get_hwbase(dev);
  1853. writel(0, base + NvRegIrqMask);
  1854. pci_push(base);
  1855. dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
  1856. spin_unlock_irq(&np->lock);
  1857. free_irq(dev->irq, dev);
  1858. drain_ring(dev);
  1859. if (np->wolenabled)
  1860. nv_start_rx(dev);
  1861. /* FIXME: power down nic */
  1862. return 0;
  1863. }
  1864. static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  1865. {
  1866. struct net_device *dev;
  1867. struct fe_priv *np;
  1868. unsigned long addr;
  1869. u8 __iomem *base;
  1870. int err, i;
  1871. dev = alloc_etherdev(sizeof(struct fe_priv));
  1872. err = -ENOMEM;
  1873. if (!dev)
  1874. goto out;
  1875. np = get_nvpriv(dev);
  1876. np->pci_dev = pci_dev;
  1877. spin_lock_init(&np->lock);
  1878. SET_MODULE_OWNER(dev);
  1879. SET_NETDEV_DEV(dev, &pci_dev->dev);
  1880. init_timer(&np->oom_kick);
  1881. np->oom_kick.data = (unsigned long) dev;
  1882. np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
  1883. init_timer(&np->nic_poll);
  1884. np->nic_poll.data = (unsigned long) dev;
  1885. np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
  1886. err = pci_enable_device(pci_dev);
  1887. if (err) {
  1888. printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
  1889. err, pci_name(pci_dev));
  1890. goto out_free;
  1891. }
  1892. pci_set_master(pci_dev);
  1893. err = pci_request_regions(pci_dev, DRV_NAME);
  1894. if (err < 0)
  1895. goto out_disable;
  1896. err = -EINVAL;
  1897. addr = 0;
  1898. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1899. dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
  1900. pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
  1901. pci_resource_len(pci_dev, i),
  1902. pci_resource_flags(pci_dev, i));
  1903. if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
  1904. pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
  1905. addr = pci_resource_start(pci_dev, i);
  1906. break;
  1907. }
  1908. }
  1909. if (i == DEVICE_COUNT_RESOURCE) {
  1910. printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
  1911. pci_name(pci_dev));
  1912. goto out_relreg;
  1913. }
  1914. /* handle different descriptor versions */
  1915. np->desc_ver = DESC_VER_1;
  1916. np->pkt_limit = NV_PKTLIMIT_1;
  1917. if (id->driver_data & DEV_HAS_LARGEDESC) {
  1918. np->desc_ver = DESC_VER_2;
  1919. np->pkt_limit = NV_PKTLIMIT_2;
  1920. }
  1921. err = -ENOMEM;
  1922. np->base = ioremap(addr, NV_PCI_REGSZ);
  1923. if (!np->base)
  1924. goto out_relreg;
  1925. dev->base_addr = (unsigned long)np->base;
  1926. dev->irq = pci_dev->irq;
  1927. np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
  1928. &np->ring_addr);
  1929. if (!np->rx_ring)
  1930. goto out_unmap;
  1931. np->tx_ring = &np->rx_ring[RX_RING];
  1932. dev->open = nv_open;
  1933. dev->stop = nv_close;
  1934. dev->hard_start_xmit = nv_start_xmit;
  1935. dev->get_stats = nv_get_stats;
  1936. dev->change_mtu = nv_change_mtu;
  1937. dev->set_multicast_list = nv_set_multicast;
  1938. #ifdef CONFIG_NET_POLL_CONTROLLER
  1939. dev->poll_controller = nv_poll_controller;
  1940. #endif
  1941. SET_ETHTOOL_OPS(dev, &ops);
  1942. dev->tx_timeout = nv_tx_timeout;
  1943. dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
  1944. pci_set_drvdata(pci_dev, dev);
  1945. /* read the mac address */
  1946. base = get_hwbase(dev);
  1947. np->orig_mac[0] = readl(base + NvRegMacAddrA);
  1948. np->orig_mac[1] = readl(base + NvRegMacAddrB);
  1949. dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
  1950. dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
  1951. dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
  1952. dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
  1953. dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
  1954. dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
  1955. if (!is_valid_ether_addr(dev->dev_addr)) {
  1956. /*
  1957. * Bad mac address. At least one bios sets the mac address
  1958. * to 01:23:45:67:89:ab
  1959. */
  1960. printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
  1961. pci_name(pci_dev),
  1962. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  1963. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  1964. printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
  1965. dev->dev_addr[0] = 0x00;
  1966. dev->dev_addr[1] = 0x00;
  1967. dev->dev_addr[2] = 0x6c;
  1968. get_random_bytes(&dev->dev_addr[3], 3);
  1969. }
  1970. dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
  1971. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  1972. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  1973. /* disable WOL */
  1974. writel(0, base + NvRegWakeUpFlags);
  1975. np->wolenabled = 0;
  1976. if (np->desc_ver == DESC_VER_1) {
  1977. np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
  1978. } else {
  1979. np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
  1980. }
  1981. np->irqmask = NVREG_IRQMASK_WANTED;
  1982. if (id->driver_data & DEV_NEED_TIMERIRQ)
  1983. np->irqmask |= NVREG_IRQ_TIMER;
  1984. if (id->driver_data & DEV_NEED_LINKTIMER) {
  1985. dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
  1986. np->need_linktimer = 1;
  1987. np->link_timeout = jiffies + LINK_TIMEOUT;
  1988. } else {
  1989. dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
  1990. np->need_linktimer = 0;
  1991. }
  1992. /* find a suitable phy */
  1993. for (i = 1; i < 32; i++) {
  1994. int id1, id2;
  1995. spin_lock_irq(&np->lock);
  1996. id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
  1997. spin_unlock_irq(&np->lock);
  1998. if (id1 < 0 || id1 == 0xffff)
  1999. continue;
  2000. spin_lock_irq(&np->lock);
  2001. id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
  2002. spin_unlock_irq(&np->lock);
  2003. if (id2 < 0 || id2 == 0xffff)
  2004. continue;
  2005. id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
  2006. id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
  2007. dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
  2008. pci_name(pci_dev), id1, id2, i);
  2009. np->phyaddr = i;
  2010. np->phy_oui = id1 | id2;
  2011. break;
  2012. }
  2013. if (i == 32) {
  2014. /* PHY in isolate mode? No phy attached and user wants to
  2015. * test loopback? Very odd, but can be correct.
  2016. */
  2017. printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
  2018. pci_name(pci_dev));
  2019. }
  2020. if (i != 32) {
  2021. /* reset it */
  2022. phy_init(dev);
  2023. }
  2024. /* set default link speed settings */
  2025. np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2026. np->duplex = 0;
  2027. np->autoneg = 1;
  2028. err = register_netdev(dev);
  2029. if (err) {
  2030. printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
  2031. goto out_freering;
  2032. }
  2033. printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
  2034. dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
  2035. pci_name(pci_dev));
  2036. return 0;
  2037. out_freering:
  2038. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
  2039. np->rx_ring, np->ring_addr);
  2040. pci_set_drvdata(pci_dev, NULL);
  2041. out_unmap:
  2042. iounmap(get_hwbase(dev));
  2043. out_relreg:
  2044. pci_release_regions(pci_dev);
  2045. out_disable:
  2046. pci_disable_device(pci_dev);
  2047. out_free:
  2048. free_netdev(dev);
  2049. out:
  2050. return err;
  2051. }
  2052. static void __devexit nv_remove(struct pci_dev *pci_dev)
  2053. {
  2054. struct net_device *dev = pci_get_drvdata(pci_dev);
  2055. struct fe_priv *np = get_nvpriv(dev);
  2056. u8 __iomem *base = get_hwbase(dev);
  2057. unregister_netdev(dev);
  2058. /* special op: write back the misordered MAC address - otherwise
  2059. * the next nv_probe would see a wrong address.
  2060. */
  2061. writel(np->orig_mac[0], base + NvRegMacAddrA);
  2062. writel(np->orig_mac[1], base + NvRegMacAddrB);
  2063. /* free all structures */
  2064. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
  2065. iounmap(get_hwbase(dev));
  2066. pci_release_regions(pci_dev);
  2067. pci_disable_device(pci_dev);
  2068. free_netdev(dev);
  2069. pci_set_drvdata(pci_dev, NULL);
  2070. }
  2071. static struct pci_device_id pci_tbl[] = {
  2072. { /* nForce Ethernet Controller */
  2073. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
  2074. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  2075. },
  2076. { /* nForce2 Ethernet Controller */
  2077. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
  2078. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  2079. },
  2080. { /* nForce3 Ethernet Controller */
  2081. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
  2082. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  2083. },
  2084. { /* nForce3 Ethernet Controller */
  2085. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
  2086. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2087. },
  2088. { /* nForce3 Ethernet Controller */
  2089. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
  2090. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2091. },
  2092. { /* nForce3 Ethernet Controller */
  2093. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
  2094. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2095. },
  2096. { /* nForce3 Ethernet Controller */
  2097. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
  2098. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2099. },
  2100. { /* CK804 Ethernet Controller */
  2101. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
  2102. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2103. },
  2104. { /* CK804 Ethernet Controller */
  2105. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
  2106. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2107. },
  2108. { /* MCP04 Ethernet Controller */
  2109. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
  2110. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2111. },
  2112. { /* MCP04 Ethernet Controller */
  2113. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
  2114. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2115. },
  2116. { /* MCP51 Ethernet Controller */
  2117. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
  2118. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  2119. },
  2120. { /* MCP51 Ethernet Controller */
  2121. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
  2122. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  2123. },
  2124. { /* MCP55 Ethernet Controller */
  2125. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
  2126. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2127. },
  2128. { /* MCP55 Ethernet Controller */
  2129. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
  2130. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
  2131. },
  2132. {0,},
  2133. };
  2134. static struct pci_driver driver = {
  2135. .name = "forcedeth",
  2136. .id_table = pci_tbl,
  2137. .probe = nv_probe,
  2138. .remove = __devexit_p(nv_remove),
  2139. };
  2140. static int __init init_nic(void)
  2141. {
  2142. printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
  2143. return pci_module_init(&driver);
  2144. }
  2145. static void __exit exit_nic(void)
  2146. {
  2147. pci_unregister_driver(&driver);
  2148. }
  2149. module_param(max_interrupt_work, int, 0);
  2150. MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
  2151. MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
  2152. MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
  2153. MODULE_LICENSE("GPL");
  2154. MODULE_DEVICE_TABLE(pci, pci_tbl);
  2155. module_init(init_nic);
  2156. module_exit(exit_nic);