shdma-base.c 22 KB

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  1. /*
  2. * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
  3. *
  4. * extracted from shdma.c
  5. *
  6. * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  7. * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  8. * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
  9. * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10. *
  11. * This is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/shdma-base.h>
  17. #include <linux/dmaengine.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/module.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #include "../dmaengine.h"
  25. /* DMA descriptor control */
  26. enum shdma_desc_status {
  27. DESC_IDLE,
  28. DESC_PREPARED,
  29. DESC_SUBMITTED,
  30. DESC_COMPLETED, /* completed, have to call callback */
  31. DESC_WAITING, /* callback called, waiting for ack / re-submit */
  32. };
  33. #define NR_DESCS_PER_CHANNEL 32
  34. #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
  35. #define to_shdma_dev(d) container_of(d, struct shdma_dev, dma_dev)
  36. /*
  37. * For slave DMA we assume, that there is a finite number of DMA slaves in the
  38. * system, and that each such slave can only use a finite number of channels.
  39. * We use slave channel IDs to make sure, that no such slave channel ID is
  40. * allocated more than once.
  41. */
  42. static unsigned int slave_num = 256;
  43. module_param(slave_num, uint, 0444);
  44. /* A bitmask with slave_num bits */
  45. static unsigned long *shdma_slave_used;
  46. /* Called under spin_lock_irq(&schan->chan_lock") */
  47. static void shdma_chan_xfer_ld_queue(struct shdma_chan *schan)
  48. {
  49. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  50. const struct shdma_ops *ops = sdev->ops;
  51. struct shdma_desc *sdesc;
  52. /* DMA work check */
  53. if (ops->channel_busy(schan))
  54. return;
  55. /* Find the first not transferred descriptor */
  56. list_for_each_entry(sdesc, &schan->ld_queue, node)
  57. if (sdesc->mark == DESC_SUBMITTED) {
  58. ops->start_xfer(schan, sdesc);
  59. break;
  60. }
  61. }
  62. static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx)
  63. {
  64. struct shdma_desc *chunk, *c, *desc =
  65. container_of(tx, struct shdma_desc, async_tx),
  66. *last = desc;
  67. struct shdma_chan *schan = to_shdma_chan(tx->chan);
  68. dma_async_tx_callback callback = tx->callback;
  69. dma_cookie_t cookie;
  70. bool power_up;
  71. spin_lock_irq(&schan->chan_lock);
  72. power_up = list_empty(&schan->ld_queue);
  73. cookie = dma_cookie_assign(tx);
  74. /* Mark all chunks of this descriptor as submitted, move to the queue */
  75. list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
  76. /*
  77. * All chunks are on the global ld_free, so, we have to find
  78. * the end of the chain ourselves
  79. */
  80. if (chunk != desc && (chunk->mark == DESC_IDLE ||
  81. chunk->async_tx.cookie > 0 ||
  82. chunk->async_tx.cookie == -EBUSY ||
  83. &chunk->node == &schan->ld_free))
  84. break;
  85. chunk->mark = DESC_SUBMITTED;
  86. /* Callback goes to the last chunk */
  87. chunk->async_tx.callback = NULL;
  88. chunk->cookie = cookie;
  89. list_move_tail(&chunk->node, &schan->ld_queue);
  90. last = chunk;
  91. dev_dbg(schan->dev, "submit #%d@%p on %d\n",
  92. tx->cookie, &last->async_tx, schan->id);
  93. }
  94. last->async_tx.callback = callback;
  95. last->async_tx.callback_param = tx->callback_param;
  96. if (power_up) {
  97. int ret;
  98. schan->pm_state = SHDMA_PM_BUSY;
  99. ret = pm_runtime_get(schan->dev);
  100. spin_unlock_irq(&schan->chan_lock);
  101. if (ret < 0)
  102. dev_err(schan->dev, "%s(): GET = %d\n", __func__, ret);
  103. pm_runtime_barrier(schan->dev);
  104. spin_lock_irq(&schan->chan_lock);
  105. /* Have we been reset, while waiting? */
  106. if (schan->pm_state != SHDMA_PM_ESTABLISHED) {
  107. struct shdma_dev *sdev =
  108. to_shdma_dev(schan->dma_chan.device);
  109. const struct shdma_ops *ops = sdev->ops;
  110. dev_dbg(schan->dev, "Bring up channel %d\n",
  111. schan->id);
  112. /*
  113. * TODO: .xfer_setup() might fail on some platforms.
  114. * Make it int then, on error remove chunks from the
  115. * queue again
  116. */
  117. ops->setup_xfer(schan, schan->slave_id);
  118. if (schan->pm_state == SHDMA_PM_PENDING)
  119. shdma_chan_xfer_ld_queue(schan);
  120. schan->pm_state = SHDMA_PM_ESTABLISHED;
  121. }
  122. } else {
  123. /*
  124. * Tell .device_issue_pending() not to run the queue, interrupts
  125. * will do it anyway
  126. */
  127. schan->pm_state = SHDMA_PM_PENDING;
  128. }
  129. spin_unlock_irq(&schan->chan_lock);
  130. return cookie;
  131. }
  132. /* Called with desc_lock held */
  133. static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan)
  134. {
  135. struct shdma_desc *sdesc;
  136. list_for_each_entry(sdesc, &schan->ld_free, node)
  137. if (sdesc->mark != DESC_PREPARED) {
  138. BUG_ON(sdesc->mark != DESC_IDLE);
  139. list_del(&sdesc->node);
  140. return sdesc;
  141. }
  142. return NULL;
  143. }
  144. static int shdma_alloc_chan_resources(struct dma_chan *chan)
  145. {
  146. struct shdma_chan *schan = to_shdma_chan(chan);
  147. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  148. const struct shdma_ops *ops = sdev->ops;
  149. struct shdma_desc *desc;
  150. struct shdma_slave *slave = chan->private;
  151. int ret, i;
  152. /*
  153. * This relies on the guarantee from dmaengine that alloc_chan_resources
  154. * never runs concurrently with itself or free_chan_resources.
  155. */
  156. if (slave) {
  157. if (slave->slave_id < 0 || slave->slave_id >= slave_num) {
  158. ret = -EINVAL;
  159. goto evalid;
  160. }
  161. if (test_and_set_bit(slave->slave_id, shdma_slave_used)) {
  162. ret = -EBUSY;
  163. goto etestused;
  164. }
  165. ret = ops->set_slave(schan, slave->slave_id);
  166. if (ret < 0)
  167. goto esetslave;
  168. schan->slave_id = slave->slave_id;
  169. } else {
  170. schan->slave_id = -EINVAL;
  171. }
  172. schan->desc = kcalloc(NR_DESCS_PER_CHANNEL,
  173. sdev->desc_size, GFP_KERNEL);
  174. if (!schan->desc) {
  175. ret = -ENOMEM;
  176. goto edescalloc;
  177. }
  178. schan->desc_num = NR_DESCS_PER_CHANNEL;
  179. for (i = 0; i < NR_DESCS_PER_CHANNEL; i++) {
  180. desc = ops->embedded_desc(schan->desc, i);
  181. dma_async_tx_descriptor_init(&desc->async_tx,
  182. &schan->dma_chan);
  183. desc->async_tx.tx_submit = shdma_tx_submit;
  184. desc->mark = DESC_IDLE;
  185. list_add(&desc->node, &schan->ld_free);
  186. }
  187. return NR_DESCS_PER_CHANNEL;
  188. edescalloc:
  189. if (slave)
  190. esetslave:
  191. clear_bit(slave->slave_id, shdma_slave_used);
  192. etestused:
  193. evalid:
  194. chan->private = NULL;
  195. return ret;
  196. }
  197. static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all)
  198. {
  199. struct shdma_desc *desc, *_desc;
  200. /* Is the "exposed" head of a chain acked? */
  201. bool head_acked = false;
  202. dma_cookie_t cookie = 0;
  203. dma_async_tx_callback callback = NULL;
  204. void *param = NULL;
  205. unsigned long flags;
  206. spin_lock_irqsave(&schan->chan_lock, flags);
  207. list_for_each_entry_safe(desc, _desc, &schan->ld_queue, node) {
  208. struct dma_async_tx_descriptor *tx = &desc->async_tx;
  209. BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
  210. BUG_ON(desc->mark != DESC_SUBMITTED &&
  211. desc->mark != DESC_COMPLETED &&
  212. desc->mark != DESC_WAITING);
  213. /*
  214. * queue is ordered, and we use this loop to (1) clean up all
  215. * completed descriptors, and to (2) update descriptor flags of
  216. * any chunks in a (partially) completed chain
  217. */
  218. if (!all && desc->mark == DESC_SUBMITTED &&
  219. desc->cookie != cookie)
  220. break;
  221. if (tx->cookie > 0)
  222. cookie = tx->cookie;
  223. if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
  224. if (schan->dma_chan.completed_cookie != desc->cookie - 1)
  225. dev_dbg(schan->dev,
  226. "Completing cookie %d, expected %d\n",
  227. desc->cookie,
  228. schan->dma_chan.completed_cookie + 1);
  229. schan->dma_chan.completed_cookie = desc->cookie;
  230. }
  231. /* Call callback on the last chunk */
  232. if (desc->mark == DESC_COMPLETED && tx->callback) {
  233. desc->mark = DESC_WAITING;
  234. callback = tx->callback;
  235. param = tx->callback_param;
  236. dev_dbg(schan->dev, "descriptor #%d@%p on %d callback\n",
  237. tx->cookie, tx, schan->id);
  238. BUG_ON(desc->chunks != 1);
  239. break;
  240. }
  241. if (tx->cookie > 0 || tx->cookie == -EBUSY) {
  242. if (desc->mark == DESC_COMPLETED) {
  243. BUG_ON(tx->cookie < 0);
  244. desc->mark = DESC_WAITING;
  245. }
  246. head_acked = async_tx_test_ack(tx);
  247. } else {
  248. switch (desc->mark) {
  249. case DESC_COMPLETED:
  250. desc->mark = DESC_WAITING;
  251. /* Fall through */
  252. case DESC_WAITING:
  253. if (head_acked)
  254. async_tx_ack(&desc->async_tx);
  255. }
  256. }
  257. dev_dbg(schan->dev, "descriptor %p #%d completed.\n",
  258. tx, tx->cookie);
  259. if (((desc->mark == DESC_COMPLETED ||
  260. desc->mark == DESC_WAITING) &&
  261. async_tx_test_ack(&desc->async_tx)) || all) {
  262. /* Remove from ld_queue list */
  263. desc->mark = DESC_IDLE;
  264. list_move(&desc->node, &schan->ld_free);
  265. if (list_empty(&schan->ld_queue)) {
  266. dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
  267. pm_runtime_put(schan->dev);
  268. schan->pm_state = SHDMA_PM_ESTABLISHED;
  269. }
  270. }
  271. }
  272. if (all && !callback)
  273. /*
  274. * Terminating and the loop completed normally: forgive
  275. * uncompleted cookies
  276. */
  277. schan->dma_chan.completed_cookie = schan->dma_chan.cookie;
  278. spin_unlock_irqrestore(&schan->chan_lock, flags);
  279. if (callback)
  280. callback(param);
  281. return callback;
  282. }
  283. /*
  284. * shdma_chan_ld_cleanup - Clean up link descriptors
  285. *
  286. * Clean up the ld_queue of DMA channel.
  287. */
  288. static void shdma_chan_ld_cleanup(struct shdma_chan *schan, bool all)
  289. {
  290. while (__ld_cleanup(schan, all))
  291. ;
  292. }
  293. /*
  294. * shdma_free_chan_resources - Free all resources of the channel.
  295. */
  296. static void shdma_free_chan_resources(struct dma_chan *chan)
  297. {
  298. struct shdma_chan *schan = to_shdma_chan(chan);
  299. struct shdma_dev *sdev = to_shdma_dev(chan->device);
  300. const struct shdma_ops *ops = sdev->ops;
  301. LIST_HEAD(list);
  302. /* Protect against ISR */
  303. spin_lock_irq(&schan->chan_lock);
  304. ops->halt_channel(schan);
  305. spin_unlock_irq(&schan->chan_lock);
  306. /* Now no new interrupts will occur */
  307. /* Prepared and not submitted descriptors can still be on the queue */
  308. if (!list_empty(&schan->ld_queue))
  309. shdma_chan_ld_cleanup(schan, true);
  310. if (schan->slave_id >= 0) {
  311. /* The caller is holding dma_list_mutex */
  312. clear_bit(schan->slave_id, shdma_slave_used);
  313. chan->private = NULL;
  314. }
  315. spin_lock_irq(&schan->chan_lock);
  316. list_splice_init(&schan->ld_free, &list);
  317. schan->desc_num = 0;
  318. spin_unlock_irq(&schan->chan_lock);
  319. kfree(schan->desc);
  320. }
  321. /**
  322. * shdma_add_desc - get, set up and return one transfer descriptor
  323. * @schan: DMA channel
  324. * @flags: DMA transfer flags
  325. * @dst: destination DMA address, incremented when direction equals
  326. * DMA_DEV_TO_MEM or DMA_MEM_TO_MEM
  327. * @src: source DMA address, incremented when direction equals
  328. * DMA_MEM_TO_DEV or DMA_MEM_TO_MEM
  329. * @len: DMA transfer length
  330. * @first: if NULL, set to the current descriptor and cookie set to -EBUSY
  331. * @direction: needed for slave DMA to decide which address to keep constant,
  332. * equals DMA_MEM_TO_MEM for MEMCPY
  333. * Returns 0 or an error
  334. * Locks: called with desc_lock held
  335. */
  336. static struct shdma_desc *shdma_add_desc(struct shdma_chan *schan,
  337. unsigned long flags, dma_addr_t *dst, dma_addr_t *src, size_t *len,
  338. struct shdma_desc **first, enum dma_transfer_direction direction)
  339. {
  340. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  341. const struct shdma_ops *ops = sdev->ops;
  342. struct shdma_desc *new;
  343. size_t copy_size = *len;
  344. if (!copy_size)
  345. return NULL;
  346. /* Allocate the link descriptor from the free list */
  347. new = shdma_get_desc(schan);
  348. if (!new) {
  349. dev_err(schan->dev, "No free link descriptor available\n");
  350. return NULL;
  351. }
  352. ops->desc_setup(schan, new, *src, *dst, &copy_size);
  353. if (!*first) {
  354. /* First desc */
  355. new->async_tx.cookie = -EBUSY;
  356. *first = new;
  357. } else {
  358. /* Other desc - invisible to the user */
  359. new->async_tx.cookie = -EINVAL;
  360. }
  361. dev_dbg(schan->dev,
  362. "chaining (%u/%u)@%x -> %x with %p, cookie %d\n",
  363. copy_size, *len, *src, *dst, &new->async_tx,
  364. new->async_tx.cookie);
  365. new->mark = DESC_PREPARED;
  366. new->async_tx.flags = flags;
  367. new->direction = direction;
  368. *len -= copy_size;
  369. if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
  370. *src += copy_size;
  371. if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
  372. *dst += copy_size;
  373. return new;
  374. }
  375. /*
  376. * shdma_prep_sg - prepare transfer descriptors from an SG list
  377. *
  378. * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
  379. * converted to scatter-gather to guarantee consistent locking and a correct
  380. * list manipulation. For slave DMA direction carries the usual meaning, and,
  381. * logically, the SG list is RAM and the addr variable contains slave address,
  382. * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
  383. * and the SG list contains only one element and points at the source buffer.
  384. */
  385. static struct dma_async_tx_descriptor *shdma_prep_sg(struct shdma_chan *schan,
  386. struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
  387. enum dma_transfer_direction direction, unsigned long flags)
  388. {
  389. struct scatterlist *sg;
  390. struct shdma_desc *first = NULL, *new = NULL /* compiler... */;
  391. LIST_HEAD(tx_list);
  392. int chunks = 0;
  393. unsigned long irq_flags;
  394. int i;
  395. for_each_sg(sgl, sg, sg_len, i)
  396. chunks += DIV_ROUND_UP(sg_dma_len(sg), schan->max_xfer_len);
  397. /* Have to lock the whole loop to protect against concurrent release */
  398. spin_lock_irqsave(&schan->chan_lock, irq_flags);
  399. /*
  400. * Chaining:
  401. * first descriptor is what user is dealing with in all API calls, its
  402. * cookie is at first set to -EBUSY, at tx-submit to a positive
  403. * number
  404. * if more than one chunk is needed further chunks have cookie = -EINVAL
  405. * the last chunk, if not equal to the first, has cookie = -ENOSPC
  406. * all chunks are linked onto the tx_list head with their .node heads
  407. * only during this function, then they are immediately spliced
  408. * back onto the free list in form of a chain
  409. */
  410. for_each_sg(sgl, sg, sg_len, i) {
  411. dma_addr_t sg_addr = sg_dma_address(sg);
  412. size_t len = sg_dma_len(sg);
  413. if (!len)
  414. goto err_get_desc;
  415. do {
  416. dev_dbg(schan->dev, "Add SG #%d@%p[%d], dma %llx\n",
  417. i, sg, len, (unsigned long long)sg_addr);
  418. if (direction == DMA_DEV_TO_MEM)
  419. new = shdma_add_desc(schan, flags,
  420. &sg_addr, addr, &len, &first,
  421. direction);
  422. else
  423. new = shdma_add_desc(schan, flags,
  424. addr, &sg_addr, &len, &first,
  425. direction);
  426. if (!new)
  427. goto err_get_desc;
  428. new->chunks = chunks--;
  429. list_add_tail(&new->node, &tx_list);
  430. } while (len);
  431. }
  432. if (new != first)
  433. new->async_tx.cookie = -ENOSPC;
  434. /* Put them back on the free list, so, they don't get lost */
  435. list_splice_tail(&tx_list, &schan->ld_free);
  436. spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
  437. return &first->async_tx;
  438. err_get_desc:
  439. list_for_each_entry(new, &tx_list, node)
  440. new->mark = DESC_IDLE;
  441. list_splice(&tx_list, &schan->ld_free);
  442. spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
  443. return NULL;
  444. }
  445. static struct dma_async_tx_descriptor *shdma_prep_memcpy(
  446. struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
  447. size_t len, unsigned long flags)
  448. {
  449. struct shdma_chan *schan = to_shdma_chan(chan);
  450. struct scatterlist sg;
  451. if (!chan || !len)
  452. return NULL;
  453. BUG_ON(!schan->desc_num);
  454. sg_init_table(&sg, 1);
  455. sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
  456. offset_in_page(dma_src));
  457. sg_dma_address(&sg) = dma_src;
  458. sg_dma_len(&sg) = len;
  459. return shdma_prep_sg(schan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM, flags);
  460. }
  461. static struct dma_async_tx_descriptor *shdma_prep_slave_sg(
  462. struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
  463. enum dma_transfer_direction direction, unsigned long flags, void *context)
  464. {
  465. struct shdma_chan *schan = to_shdma_chan(chan);
  466. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  467. const struct shdma_ops *ops = sdev->ops;
  468. int slave_id = schan->slave_id;
  469. dma_addr_t slave_addr;
  470. if (!chan)
  471. return NULL;
  472. BUG_ON(!schan->desc_num);
  473. /* Someone calling slave DMA on a generic channel? */
  474. if (slave_id < 0 || !sg_len) {
  475. dev_warn(schan->dev, "%s: bad parameter: len=%d, id=%d\n",
  476. __func__, sg_len, slave_id);
  477. return NULL;
  478. }
  479. slave_addr = ops->slave_addr(schan);
  480. return shdma_prep_sg(schan, sgl, sg_len, &slave_addr,
  481. direction, flags);
  482. }
  483. static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  484. unsigned long arg)
  485. {
  486. struct shdma_chan *schan = to_shdma_chan(chan);
  487. struct shdma_dev *sdev = to_shdma_dev(chan->device);
  488. const struct shdma_ops *ops = sdev->ops;
  489. unsigned long flags;
  490. /* Only supports DMA_TERMINATE_ALL */
  491. if (cmd != DMA_TERMINATE_ALL)
  492. return -ENXIO;
  493. if (!chan)
  494. return -EINVAL;
  495. spin_lock_irqsave(&schan->chan_lock, flags);
  496. ops->halt_channel(schan);
  497. spin_unlock_irqrestore(&schan->chan_lock, flags);
  498. shdma_chan_ld_cleanup(schan, true);
  499. return 0;
  500. }
  501. static void shdma_issue_pending(struct dma_chan *chan)
  502. {
  503. struct shdma_chan *schan = to_shdma_chan(chan);
  504. spin_lock_irq(&schan->chan_lock);
  505. if (schan->pm_state == SHDMA_PM_ESTABLISHED)
  506. shdma_chan_xfer_ld_queue(schan);
  507. else
  508. schan->pm_state = SHDMA_PM_PENDING;
  509. spin_unlock_irq(&schan->chan_lock);
  510. }
  511. static enum dma_status shdma_tx_status(struct dma_chan *chan,
  512. dma_cookie_t cookie,
  513. struct dma_tx_state *txstate)
  514. {
  515. struct shdma_chan *schan = to_shdma_chan(chan);
  516. enum dma_status status;
  517. unsigned long flags;
  518. shdma_chan_ld_cleanup(schan, false);
  519. spin_lock_irqsave(&schan->chan_lock, flags);
  520. status = dma_cookie_status(chan, cookie, txstate);
  521. /*
  522. * If we don't find cookie on the queue, it has been aborted and we have
  523. * to report error
  524. */
  525. if (status != DMA_SUCCESS) {
  526. struct shdma_desc *sdesc;
  527. status = DMA_ERROR;
  528. list_for_each_entry(sdesc, &schan->ld_queue, node)
  529. if (sdesc->cookie == cookie) {
  530. status = DMA_IN_PROGRESS;
  531. break;
  532. }
  533. }
  534. spin_unlock_irqrestore(&schan->chan_lock, flags);
  535. return status;
  536. }
  537. /* Called from error IRQ or NMI */
  538. bool shdma_reset(struct shdma_dev *sdev)
  539. {
  540. const struct shdma_ops *ops = sdev->ops;
  541. struct shdma_chan *schan;
  542. unsigned int handled = 0;
  543. int i;
  544. /* Reset all channels */
  545. shdma_for_each_chan(schan, sdev, i) {
  546. struct shdma_desc *sdesc;
  547. LIST_HEAD(dl);
  548. if (!schan)
  549. continue;
  550. spin_lock(&schan->chan_lock);
  551. /* Stop the channel */
  552. ops->halt_channel(schan);
  553. list_splice_init(&schan->ld_queue, &dl);
  554. if (!list_empty(&dl)) {
  555. dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
  556. pm_runtime_put(schan->dev);
  557. }
  558. schan->pm_state = SHDMA_PM_ESTABLISHED;
  559. spin_unlock(&schan->chan_lock);
  560. /* Complete all */
  561. list_for_each_entry(sdesc, &dl, node) {
  562. struct dma_async_tx_descriptor *tx = &sdesc->async_tx;
  563. sdesc->mark = DESC_IDLE;
  564. if (tx->callback)
  565. tx->callback(tx->callback_param);
  566. }
  567. spin_lock(&schan->chan_lock);
  568. list_splice(&dl, &schan->ld_free);
  569. spin_unlock(&schan->chan_lock);
  570. handled++;
  571. }
  572. return !!handled;
  573. }
  574. EXPORT_SYMBOL(shdma_reset);
  575. static irqreturn_t chan_irq(int irq, void *dev)
  576. {
  577. struct shdma_chan *schan = dev;
  578. const struct shdma_ops *ops =
  579. to_shdma_dev(schan->dma_chan.device)->ops;
  580. irqreturn_t ret;
  581. spin_lock(&schan->chan_lock);
  582. ret = ops->chan_irq(schan, irq) ? IRQ_WAKE_THREAD : IRQ_NONE;
  583. spin_unlock(&schan->chan_lock);
  584. return ret;
  585. }
  586. static irqreturn_t chan_irqt(int irq, void *dev)
  587. {
  588. struct shdma_chan *schan = dev;
  589. const struct shdma_ops *ops =
  590. to_shdma_dev(schan->dma_chan.device)->ops;
  591. struct shdma_desc *sdesc;
  592. spin_lock_irq(&schan->chan_lock);
  593. list_for_each_entry(sdesc, &schan->ld_queue, node) {
  594. if (sdesc->mark == DESC_SUBMITTED &&
  595. ops->desc_completed(schan, sdesc)) {
  596. dev_dbg(schan->dev, "done #%d@%p\n",
  597. sdesc->async_tx.cookie, &sdesc->async_tx);
  598. sdesc->mark = DESC_COMPLETED;
  599. break;
  600. }
  601. }
  602. /* Next desc */
  603. shdma_chan_xfer_ld_queue(schan);
  604. spin_unlock_irq(&schan->chan_lock);
  605. shdma_chan_ld_cleanup(schan, false);
  606. return IRQ_HANDLED;
  607. }
  608. int shdma_request_irq(struct shdma_chan *schan, int irq,
  609. unsigned long flags, const char *name)
  610. {
  611. int ret = request_threaded_irq(irq, chan_irq, chan_irqt,
  612. flags, name, schan);
  613. schan->irq = ret < 0 ? ret : irq;
  614. return ret;
  615. }
  616. EXPORT_SYMBOL(shdma_request_irq);
  617. void shdma_free_irq(struct shdma_chan *schan)
  618. {
  619. if (schan->irq >= 0)
  620. free_irq(schan->irq, schan);
  621. }
  622. EXPORT_SYMBOL(shdma_free_irq);
  623. void shdma_chan_probe(struct shdma_dev *sdev,
  624. struct shdma_chan *schan, int id)
  625. {
  626. schan->pm_state = SHDMA_PM_ESTABLISHED;
  627. /* reference struct dma_device */
  628. schan->dma_chan.device = &sdev->dma_dev;
  629. dma_cookie_init(&schan->dma_chan);
  630. schan->dev = sdev->dma_dev.dev;
  631. schan->id = id;
  632. if (!schan->max_xfer_len)
  633. schan->max_xfer_len = PAGE_SIZE;
  634. spin_lock_init(&schan->chan_lock);
  635. /* Init descripter manage list */
  636. INIT_LIST_HEAD(&schan->ld_queue);
  637. INIT_LIST_HEAD(&schan->ld_free);
  638. /* Add the channel to DMA device channel list */
  639. list_add_tail(&schan->dma_chan.device_node,
  640. &sdev->dma_dev.channels);
  641. sdev->schan[sdev->dma_dev.chancnt++] = schan;
  642. }
  643. EXPORT_SYMBOL(shdma_chan_probe);
  644. void shdma_chan_remove(struct shdma_chan *schan)
  645. {
  646. list_del(&schan->dma_chan.device_node);
  647. }
  648. EXPORT_SYMBOL(shdma_chan_remove);
  649. int shdma_init(struct device *dev, struct shdma_dev *sdev,
  650. int chan_num)
  651. {
  652. struct dma_device *dma_dev = &sdev->dma_dev;
  653. /*
  654. * Require all call-backs for now, they can trivially be made optional
  655. * later as required
  656. */
  657. if (!sdev->ops ||
  658. !sdev->desc_size ||
  659. !sdev->ops->embedded_desc ||
  660. !sdev->ops->start_xfer ||
  661. !sdev->ops->setup_xfer ||
  662. !sdev->ops->set_slave ||
  663. !sdev->ops->desc_setup ||
  664. !sdev->ops->slave_addr ||
  665. !sdev->ops->channel_busy ||
  666. !sdev->ops->halt_channel ||
  667. !sdev->ops->desc_completed)
  668. return -EINVAL;
  669. sdev->schan = kcalloc(chan_num, sizeof(*sdev->schan), GFP_KERNEL);
  670. if (!sdev->schan)
  671. return -ENOMEM;
  672. INIT_LIST_HEAD(&dma_dev->channels);
  673. /* Common and MEMCPY operations */
  674. dma_dev->device_alloc_chan_resources
  675. = shdma_alloc_chan_resources;
  676. dma_dev->device_free_chan_resources = shdma_free_chan_resources;
  677. dma_dev->device_prep_dma_memcpy = shdma_prep_memcpy;
  678. dma_dev->device_tx_status = shdma_tx_status;
  679. dma_dev->device_issue_pending = shdma_issue_pending;
  680. /* Compulsory for DMA_SLAVE fields */
  681. dma_dev->device_prep_slave_sg = shdma_prep_slave_sg;
  682. dma_dev->device_control = shdma_control;
  683. dma_dev->dev = dev;
  684. return 0;
  685. }
  686. EXPORT_SYMBOL(shdma_init);
  687. void shdma_cleanup(struct shdma_dev *sdev)
  688. {
  689. kfree(sdev->schan);
  690. }
  691. EXPORT_SYMBOL(shdma_cleanup);
  692. static int __init shdma_enter(void)
  693. {
  694. shdma_slave_used = kzalloc(DIV_ROUND_UP(slave_num, BITS_PER_LONG) *
  695. sizeof(long), GFP_KERNEL);
  696. if (!shdma_slave_used)
  697. return -ENOMEM;
  698. return 0;
  699. }
  700. module_init(shdma_enter);
  701. static void __exit shdma_exit(void)
  702. {
  703. kfree(shdma_slave_used);
  704. }
  705. module_exit(shdma_exit);
  706. MODULE_LICENSE("GPL v2");
  707. MODULE_DESCRIPTION("SH-DMA driver base library");
  708. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");