lcd.c 35 KB

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  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #include <linux/via-core.h>
  19. #include <linux/via_i2c.h>
  20. #include "global.h"
  21. #define viafb_compact_res(x, y) (((x)<<16)|(y))
  22. /* CLE266 Software Power Sequence */
  23. /* {Mask}, {Data}, {Delay} */
  24. int PowerSequenceOn[3][3] = { {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06},
  25. {0x19, 0x1FE, 0x01} };
  26. int PowerSequenceOff[3][3] = { {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00},
  27. {0xD2, 0x19, 0x01} };
  28. static struct _lcd_scaling_factor lcd_scaling_factor = {
  29. /* LCD Horizontal Scaling Factor Register */
  30. {LCD_HOR_SCALING_FACTOR_REG_NUM,
  31. {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
  32. /* LCD Vertical Scaling Factor Register */
  33. {LCD_VER_SCALING_FACTOR_REG_NUM,
  34. {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
  35. };
  36. static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
  37. /* LCD Horizontal Scaling Factor Register */
  38. {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
  39. /* LCD Vertical Scaling Factor Register */
  40. {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
  41. };
  42. static int check_lvds_chip(int device_id_subaddr, int device_id);
  43. static bool lvds_identify_integratedlvds(void);
  44. static void __devinit fp_id_to_vindex(int panel_id);
  45. static int lvds_register_read(int index);
  46. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  47. int panel_vres);
  48. static void via_pitch_alignment_patch_lcd(
  49. struct lvds_setting_information *plvds_setting_info,
  50. struct lvds_chip_information
  51. *plvds_chip_info);
  52. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  53. *plvds_setting_info,
  54. struct lvds_chip_information *plvds_chip_info);
  55. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  56. *plvds_setting_info,
  57. struct lvds_chip_information *plvds_chip_info);
  58. static void lcd_patch_skew(struct lvds_setting_information
  59. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
  60. static void integrated_lvds_disable(struct lvds_setting_information
  61. *plvds_setting_info,
  62. struct lvds_chip_information *plvds_chip_info);
  63. static void integrated_lvds_enable(struct lvds_setting_information
  64. *plvds_setting_info,
  65. struct lvds_chip_information *plvds_chip_info);
  66. static void lcd_powersequence_off(void);
  67. static void lcd_powersequence_on(void);
  68. static void fill_lcd_format(void);
  69. static void check_diport_of_integrated_lvds(
  70. struct lvds_chip_information *plvds_chip_info,
  71. struct lvds_setting_information
  72. *plvds_setting_info);
  73. static struct display_timing lcd_centering_timging(struct display_timing
  74. mode_crt_reg,
  75. struct display_timing panel_crt_reg);
  76. static int check_lvds_chip(int device_id_subaddr, int device_id)
  77. {
  78. if (lvds_register_read(device_id_subaddr) == device_id)
  79. return OK;
  80. else
  81. return FAIL;
  82. }
  83. void __devinit viafb_init_lcd_size(void)
  84. {
  85. DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
  86. fp_id_to_vindex(viafb_lcd_panel_id);
  87. viaparinfo->lvds_setting_info2->lcd_panel_id =
  88. viaparinfo->lvds_setting_info->lcd_panel_id;
  89. viaparinfo->lvds_setting_info2->lcd_panel_hres =
  90. viaparinfo->lvds_setting_info->lcd_panel_hres;
  91. viaparinfo->lvds_setting_info2->lcd_panel_vres =
  92. viaparinfo->lvds_setting_info->lcd_panel_vres;
  93. viaparinfo->lvds_setting_info2->device_lcd_dualedge =
  94. viaparinfo->lvds_setting_info->device_lcd_dualedge;
  95. viaparinfo->lvds_setting_info2->LCDDithering =
  96. viaparinfo->lvds_setting_info->LCDDithering;
  97. }
  98. static bool lvds_identify_integratedlvds(void)
  99. {
  100. if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
  101. /* Two dual channel LCD (Internal LVDS + External LVDS): */
  102. /* If we have an external LVDS, such as VT1636, we should
  103. have its chip ID already. */
  104. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  105. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  106. INTEGRATED_LVDS;
  107. DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
  108. "(Internal LVDS + External LVDS)\n");
  109. } else {
  110. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  111. INTEGRATED_LVDS;
  112. DEBUG_MSG(KERN_INFO "Not found external LVDS, "
  113. "so can't support two dual channel LVDS!\n");
  114. }
  115. } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
  116. /* Two single channel LCD (Internal LVDS + Internal LVDS): */
  117. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  118. INTEGRATED_LVDS;
  119. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  120. INTEGRATED_LVDS;
  121. DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
  122. "(Internal LVDS + Internal LVDS)\n");
  123. } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
  124. /* If we have found external LVDS, just use it,
  125. otherwise, we will use internal LVDS as default. */
  126. if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  127. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  128. INTEGRATED_LVDS;
  129. DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
  130. }
  131. } else {
  132. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  133. NON_LVDS_TRANSMITTER;
  134. DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
  135. return false;
  136. }
  137. return true;
  138. }
  139. int __devinit viafb_lvds_trasmitter_identify(void)
  140. {
  141. if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
  142. viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
  143. DEBUG_MSG(KERN_INFO
  144. "Found VIA VT1636 LVDS on port i2c 0x31\n");
  145. } else {
  146. if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
  147. viaparinfo->chip_info->lvds_chip_info.i2c_port =
  148. VIA_PORT_2C;
  149. DEBUG_MSG(KERN_INFO
  150. "Found VIA VT1636 LVDS on port gpio 0x2c\n");
  151. }
  152. }
  153. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
  154. lvds_identify_integratedlvds();
  155. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  156. return true;
  157. /* Check for VT1631: */
  158. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
  159. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  160. VT1631_LVDS_I2C_ADDR;
  161. if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
  162. DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
  163. DEBUG_MSG(KERN_INFO "\n %2d",
  164. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  165. DEBUG_MSG(KERN_INFO "\n %2d",
  166. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  167. return OK;
  168. }
  169. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  170. NON_LVDS_TRANSMITTER;
  171. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  172. VT1631_LVDS_I2C_ADDR;
  173. return FAIL;
  174. }
  175. static void __devinit fp_id_to_vindex(int panel_id)
  176. {
  177. DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
  178. if (panel_id > LCD_PANEL_ID_MAXIMUM)
  179. viafb_lcd_panel_id = panel_id =
  180. viafb_read_reg(VIACR, CR3F) & 0x0F;
  181. switch (panel_id) {
  182. case 0x0:
  183. viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
  184. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  185. viaparinfo->lvds_setting_info->lcd_panel_id =
  186. LCD_PANEL_ID0_640X480;
  187. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  188. viaparinfo->lvds_setting_info->LCDDithering = 1;
  189. break;
  190. case 0x1:
  191. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  192. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  193. viaparinfo->lvds_setting_info->lcd_panel_id =
  194. LCD_PANEL_ID1_800X600;
  195. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  196. viaparinfo->lvds_setting_info->LCDDithering = 1;
  197. break;
  198. case 0x2:
  199. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  200. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  201. viaparinfo->lvds_setting_info->lcd_panel_id =
  202. LCD_PANEL_ID2_1024X768;
  203. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  204. viaparinfo->lvds_setting_info->LCDDithering = 1;
  205. break;
  206. case 0x3:
  207. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  208. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  209. viaparinfo->lvds_setting_info->lcd_panel_id =
  210. LCD_PANEL_ID3_1280X768;
  211. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  212. viaparinfo->lvds_setting_info->LCDDithering = 1;
  213. break;
  214. case 0x4:
  215. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  216. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  217. viaparinfo->lvds_setting_info->lcd_panel_id =
  218. LCD_PANEL_ID4_1280X1024;
  219. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  220. viaparinfo->lvds_setting_info->LCDDithering = 1;
  221. break;
  222. case 0x5:
  223. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  224. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  225. viaparinfo->lvds_setting_info->lcd_panel_id =
  226. LCD_PANEL_ID5_1400X1050;
  227. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  228. viaparinfo->lvds_setting_info->LCDDithering = 1;
  229. break;
  230. case 0x6:
  231. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  232. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  233. viaparinfo->lvds_setting_info->lcd_panel_id =
  234. LCD_PANEL_ID6_1600X1200;
  235. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  236. viaparinfo->lvds_setting_info->LCDDithering = 1;
  237. break;
  238. case 0x8:
  239. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  240. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  241. viaparinfo->lvds_setting_info->lcd_panel_id =
  242. LCD_PANEL_IDA_800X480;
  243. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  244. viaparinfo->lvds_setting_info->LCDDithering = 1;
  245. break;
  246. case 0x9:
  247. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  248. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  249. viaparinfo->lvds_setting_info->lcd_panel_id =
  250. LCD_PANEL_ID2_1024X768;
  251. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  252. viaparinfo->lvds_setting_info->LCDDithering = 1;
  253. break;
  254. case 0xA:
  255. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  256. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  257. viaparinfo->lvds_setting_info->lcd_panel_id =
  258. LCD_PANEL_ID2_1024X768;
  259. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  260. viaparinfo->lvds_setting_info->LCDDithering = 0;
  261. break;
  262. case 0xB:
  263. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  264. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  265. viaparinfo->lvds_setting_info->lcd_panel_id =
  266. LCD_PANEL_ID2_1024X768;
  267. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  268. viaparinfo->lvds_setting_info->LCDDithering = 0;
  269. break;
  270. case 0xC:
  271. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  272. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  273. viaparinfo->lvds_setting_info->lcd_panel_id =
  274. LCD_PANEL_ID3_1280X768;
  275. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  276. viaparinfo->lvds_setting_info->LCDDithering = 0;
  277. break;
  278. case 0xD:
  279. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  280. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  281. viaparinfo->lvds_setting_info->lcd_panel_id =
  282. LCD_PANEL_ID4_1280X1024;
  283. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  284. viaparinfo->lvds_setting_info->LCDDithering = 0;
  285. break;
  286. case 0xE:
  287. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  288. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  289. viaparinfo->lvds_setting_info->lcd_panel_id =
  290. LCD_PANEL_ID5_1400X1050;
  291. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  292. viaparinfo->lvds_setting_info->LCDDithering = 0;
  293. break;
  294. case 0xF:
  295. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  296. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  297. viaparinfo->lvds_setting_info->lcd_panel_id =
  298. LCD_PANEL_ID6_1600X1200;
  299. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  300. viaparinfo->lvds_setting_info->LCDDithering = 0;
  301. break;
  302. case 0x10:
  303. viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
  304. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  305. viaparinfo->lvds_setting_info->lcd_panel_id =
  306. LCD_PANEL_ID7_1366X768;
  307. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  308. viaparinfo->lvds_setting_info->LCDDithering = 0;
  309. break;
  310. case 0x11:
  311. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  312. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  313. viaparinfo->lvds_setting_info->lcd_panel_id =
  314. LCD_PANEL_ID8_1024X600;
  315. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  316. viaparinfo->lvds_setting_info->LCDDithering = 1;
  317. break;
  318. case 0x12:
  319. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  320. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  321. viaparinfo->lvds_setting_info->lcd_panel_id =
  322. LCD_PANEL_ID3_1280X768;
  323. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  324. viaparinfo->lvds_setting_info->LCDDithering = 1;
  325. break;
  326. case 0x13:
  327. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  328. viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
  329. viaparinfo->lvds_setting_info->lcd_panel_id =
  330. LCD_PANEL_ID9_1280X800;
  331. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  332. viaparinfo->lvds_setting_info->LCDDithering = 1;
  333. break;
  334. case 0x14:
  335. viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
  336. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  337. viaparinfo->lvds_setting_info->lcd_panel_id =
  338. LCD_PANEL_IDB_1360X768;
  339. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  340. viaparinfo->lvds_setting_info->LCDDithering = 0;
  341. break;
  342. case 0x15:
  343. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  344. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  345. viaparinfo->lvds_setting_info->lcd_panel_id =
  346. LCD_PANEL_ID3_1280X768;
  347. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  348. viaparinfo->lvds_setting_info->LCDDithering = 0;
  349. break;
  350. case 0x16:
  351. viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
  352. viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
  353. viaparinfo->lvds_setting_info->lcd_panel_id =
  354. LCD_PANEL_IDC_480X640;
  355. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  356. viaparinfo->lvds_setting_info->LCDDithering = 1;
  357. break;
  358. case 0x17:
  359. /* OLPC XO-1.5 panel */
  360. viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
  361. viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
  362. viaparinfo->lvds_setting_info->lcd_panel_id =
  363. LCD_PANEL_IDD_1200X900;
  364. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  365. viaparinfo->lvds_setting_info->LCDDithering = 0;
  366. break;
  367. default:
  368. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  369. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  370. viaparinfo->lvds_setting_info->lcd_panel_id =
  371. LCD_PANEL_ID1_800X600;
  372. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  373. viaparinfo->lvds_setting_info->LCDDithering = 1;
  374. }
  375. }
  376. static int lvds_register_read(int index)
  377. {
  378. u8 data;
  379. viafb_i2c_readbyte(VIA_PORT_2C,
  380. (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
  381. (u8) index, &data);
  382. return data;
  383. }
  384. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  385. int panel_vres)
  386. {
  387. int reg_value = 0;
  388. int viafb_load_reg_num;
  389. struct io_register *reg = NULL;
  390. DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
  391. /* LCD Scaling Enable */
  392. viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
  393. /* Check if expansion for horizontal */
  394. if (set_hres < panel_hres) {
  395. /* Load Horizontal Scaling Factor */
  396. switch (viaparinfo->chip_info->gfx_chip_name) {
  397. case UNICHROME_CLE266:
  398. case UNICHROME_K400:
  399. reg_value =
  400. CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  401. viafb_load_reg_num =
  402. lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
  403. reg_num;
  404. reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
  405. viafb_load_reg(reg_value,
  406. viafb_load_reg_num, reg, VIACR);
  407. break;
  408. case UNICHROME_K800:
  409. case UNICHROME_PM800:
  410. case UNICHROME_CN700:
  411. case UNICHROME_CX700:
  412. case UNICHROME_K8M890:
  413. case UNICHROME_P4M890:
  414. case UNICHROME_P4M900:
  415. case UNICHROME_CN750:
  416. case UNICHROME_VX800:
  417. case UNICHROME_VX855:
  418. reg_value =
  419. K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  420. /* Horizontal scaling enabled */
  421. viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
  422. viafb_load_reg_num =
  423. lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
  424. reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
  425. viafb_load_reg(reg_value,
  426. viafb_load_reg_num, reg, VIACR);
  427. break;
  428. }
  429. DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
  430. } else {
  431. /* Horizontal scaling disabled */
  432. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
  433. }
  434. /* Check if expansion for vertical */
  435. if (set_vres < panel_vres) {
  436. /* Load Vertical Scaling Factor */
  437. switch (viaparinfo->chip_info->gfx_chip_name) {
  438. case UNICHROME_CLE266:
  439. case UNICHROME_K400:
  440. reg_value =
  441. CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  442. viafb_load_reg_num =
  443. lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
  444. reg_num;
  445. reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
  446. viafb_load_reg(reg_value,
  447. viafb_load_reg_num, reg, VIACR);
  448. break;
  449. case UNICHROME_K800:
  450. case UNICHROME_PM800:
  451. case UNICHROME_CN700:
  452. case UNICHROME_CX700:
  453. case UNICHROME_K8M890:
  454. case UNICHROME_P4M890:
  455. case UNICHROME_P4M900:
  456. case UNICHROME_CN750:
  457. case UNICHROME_VX800:
  458. case UNICHROME_VX855:
  459. reg_value =
  460. K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  461. /* Vertical scaling enabled */
  462. viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
  463. viafb_load_reg_num =
  464. lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
  465. reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
  466. viafb_load_reg(reg_value,
  467. viafb_load_reg_num, reg, VIACR);
  468. break;
  469. }
  470. DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
  471. } else {
  472. /* Vertical scaling disabled */
  473. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
  474. }
  475. }
  476. static void via_pitch_alignment_patch_lcd(
  477. struct lvds_setting_information *plvds_setting_info,
  478. struct lvds_chip_information
  479. *plvds_chip_info)
  480. {
  481. unsigned char cr13, cr35, cr65, cr66, cr67;
  482. unsigned long dwScreenPitch = 0;
  483. unsigned long dwPitch;
  484. dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
  485. if (dwPitch & 0x1F) {
  486. dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
  487. if (plvds_setting_info->iga_path == IGA2) {
  488. if (plvds_setting_info->bpp > 8) {
  489. cr66 = (unsigned char)(dwScreenPitch & 0xFF);
  490. viafb_write_reg(CR66, VIACR, cr66);
  491. cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
  492. cr67 |=
  493. (unsigned
  494. char)((dwScreenPitch & 0x300) >> 8);
  495. viafb_write_reg(CR67, VIACR, cr67);
  496. }
  497. /* Fetch Count */
  498. cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
  499. cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
  500. viafb_write_reg(CR67, VIACR, cr67);
  501. cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
  502. cr65 += 2;
  503. viafb_write_reg(CR65, VIACR, cr65);
  504. } else {
  505. if (plvds_setting_info->bpp > 8) {
  506. cr13 = (unsigned char)(dwScreenPitch & 0xFF);
  507. viafb_write_reg(CR13, VIACR, cr13);
  508. cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
  509. cr35 |=
  510. (unsigned
  511. char)((dwScreenPitch & 0x700) >> 3);
  512. viafb_write_reg(CR35, VIACR, cr35);
  513. }
  514. }
  515. }
  516. }
  517. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  518. *plvds_setting_info,
  519. struct lvds_chip_information *plvds_chip_info)
  520. {
  521. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  522. switch (viaparinfo->chip_info->gfx_chip_name) {
  523. case UNICHROME_P4M900:
  524. viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
  525. plvds_chip_info);
  526. break;
  527. case UNICHROME_P4M890:
  528. viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
  529. plvds_chip_info);
  530. break;
  531. }
  532. }
  533. }
  534. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  535. *plvds_setting_info,
  536. struct lvds_chip_information *plvds_chip_info)
  537. {
  538. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  539. switch (viaparinfo->chip_info->gfx_chip_name) {
  540. case UNICHROME_CX700:
  541. viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
  542. plvds_chip_info);
  543. break;
  544. }
  545. }
  546. }
  547. static void lcd_patch_skew(struct lvds_setting_information
  548. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
  549. {
  550. DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
  551. switch (plvds_chip_info->output_interface) {
  552. case INTERFACE_DVP0:
  553. lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
  554. break;
  555. case INTERFACE_DVP1:
  556. lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
  557. break;
  558. case INTERFACE_DFP_LOW:
  559. if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
  560. viafb_write_reg_mask(CR99, VIACR, 0x08,
  561. BIT0 + BIT1 + BIT2 + BIT3);
  562. }
  563. break;
  564. }
  565. }
  566. /* LCD Set Mode */
  567. void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
  568. struct lvds_setting_information *plvds_setting_info,
  569. struct lvds_chip_information *plvds_chip_info)
  570. {
  571. int set_iga = plvds_setting_info->iga_path;
  572. int mode_bpp = plvds_setting_info->bpp;
  573. int set_hres = plvds_setting_info->h_active;
  574. int set_vres = plvds_setting_info->v_active;
  575. int panel_hres = plvds_setting_info->lcd_panel_hres;
  576. int panel_vres = plvds_setting_info->lcd_panel_vres;
  577. u32 pll_D_N;
  578. struct display_timing mode_crt_reg, panel_crt_reg;
  579. struct crt_mode_table *panel_crt_table = NULL;
  580. struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
  581. panel_vres);
  582. DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
  583. /* Get mode table */
  584. mode_crt_reg = mode_crt_table->crtc;
  585. /* Get panel table Pointer */
  586. panel_crt_table = vmode_tbl->crtc;
  587. panel_crt_reg = panel_crt_table->crtc;
  588. DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
  589. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
  590. viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
  591. plvds_setting_info->vclk = panel_crt_table->clk;
  592. if (set_iga == IGA1) {
  593. /* IGA1 doesn't have LCD scaling, so set it as centering. */
  594. viafb_load_crtc_timing(lcd_centering_timging
  595. (mode_crt_reg, panel_crt_reg), IGA1);
  596. } else {
  597. /* Expansion */
  598. if (plvds_setting_info->display_method == LCD_EXPANDSION
  599. && (set_hres < panel_hres || set_vres < panel_vres)) {
  600. /* expansion timing IGA2 loaded panel set timing*/
  601. viafb_load_crtc_timing(panel_crt_reg, IGA2);
  602. DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
  603. load_lcd_scaling(set_hres, set_vres, panel_hres,
  604. panel_vres);
  605. DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
  606. } else { /* Centering */
  607. /* centering timing IGA2 always loaded panel
  608. and mode releative timing */
  609. viafb_load_crtc_timing(lcd_centering_timging
  610. (mode_crt_reg, panel_crt_reg), IGA2);
  611. viafb_write_reg_mask(CR79, VIACR, 0x00,
  612. BIT0 + BIT1 + BIT2);
  613. /* LCD scaling disabled */
  614. }
  615. }
  616. /* Fetch count for IGA2 only */
  617. viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
  618. if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
  619. && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
  620. viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
  621. fill_lcd_format();
  622. pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
  623. DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
  624. viafb_set_vclock(pll_D_N, set_iga);
  625. lcd_patch_skew(plvds_setting_info, plvds_chip_info);
  626. /* If K8M800, enable LCD Prefetch Mode. */
  627. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
  628. || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
  629. viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
  630. /* Patch for non 32bit alignment mode */
  631. via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
  632. }
  633. static void integrated_lvds_disable(struct lvds_setting_information
  634. *plvds_setting_info,
  635. struct lvds_chip_information *plvds_chip_info)
  636. {
  637. bool turn_off_first_powersequence = false;
  638. bool turn_off_second_powersequence = false;
  639. if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
  640. turn_off_first_powersequence = true;
  641. if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
  642. turn_off_first_powersequence = true;
  643. if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
  644. turn_off_second_powersequence = true;
  645. if (turn_off_second_powersequence) {
  646. /* Use second power sequence control: */
  647. /* Turn off power sequence. */
  648. viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
  649. /* Turn off back light. */
  650. viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
  651. }
  652. if (turn_off_first_powersequence) {
  653. /* Use first power sequence control: */
  654. /* Turn off power sequence. */
  655. viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
  656. /* Turn off back light. */
  657. viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
  658. }
  659. /* Turn DFP High/Low Pad off. */
  660. viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
  661. /* Power off LVDS channel. */
  662. switch (plvds_chip_info->output_interface) {
  663. case INTERFACE_LVDS0:
  664. {
  665. viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
  666. break;
  667. }
  668. case INTERFACE_LVDS1:
  669. {
  670. viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
  671. break;
  672. }
  673. case INTERFACE_LVDS0LVDS1:
  674. {
  675. viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
  676. break;
  677. }
  678. }
  679. }
  680. static void integrated_lvds_enable(struct lvds_setting_information
  681. *plvds_setting_info,
  682. struct lvds_chip_information *plvds_chip_info)
  683. {
  684. DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
  685. plvds_chip_info->output_interface);
  686. if (plvds_setting_info->lcd_mode == LCD_SPWG)
  687. viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
  688. else
  689. viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
  690. switch (plvds_chip_info->output_interface) {
  691. case INTERFACE_LVDS0LVDS1:
  692. case INTERFACE_LVDS0:
  693. /* Use first power sequence control: */
  694. /* Use hardware control power sequence. */
  695. viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
  696. /* Turn on back light. */
  697. viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
  698. /* Turn on hardware power sequence. */
  699. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  700. break;
  701. case INTERFACE_LVDS1:
  702. /* Use second power sequence control: */
  703. /* Use hardware control power sequence. */
  704. viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
  705. /* Turn on back light. */
  706. viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
  707. /* Turn on hardware power sequence. */
  708. viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
  709. break;
  710. }
  711. /* Turn DFP High/Low pad on. */
  712. viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
  713. /* Power on LVDS channel. */
  714. switch (plvds_chip_info->output_interface) {
  715. case INTERFACE_LVDS0:
  716. {
  717. viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
  718. break;
  719. }
  720. case INTERFACE_LVDS1:
  721. {
  722. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
  723. break;
  724. }
  725. case INTERFACE_LVDS0LVDS1:
  726. {
  727. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
  728. break;
  729. }
  730. }
  731. }
  732. void viafb_lcd_disable(void)
  733. {
  734. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  735. lcd_powersequence_off();
  736. /* DI1 pad off */
  737. viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
  738. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  739. if (viafb_LCD2_ON
  740. && (INTEGRATED_LVDS ==
  741. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  742. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  743. &viaparinfo->chip_info->lvds_chip_info2);
  744. if (INTEGRATED_LVDS ==
  745. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  746. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  747. &viaparinfo->chip_info->lvds_chip_info);
  748. if (VT1636_LVDS == viaparinfo->chip_info->
  749. lvds_chip_info.lvds_chip_name)
  750. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  751. &viaparinfo->chip_info->lvds_chip_info);
  752. } else if (VT1636_LVDS ==
  753. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  754. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  755. &viaparinfo->chip_info->lvds_chip_info);
  756. } else {
  757. /* DFP-HL pad off */
  758. viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
  759. /* Backlight off */
  760. viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
  761. /* 24 bit DI data paht off */
  762. viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
  763. }
  764. /* Disable expansion bit */
  765. viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
  766. /* Simultaneout disabled */
  767. viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
  768. }
  769. static void set_lcd_output_path(int set_iga, int output_interface)
  770. {
  771. switch (output_interface) {
  772. case INTERFACE_DFP:
  773. if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
  774. || (UNICHROME_P4M890 ==
  775. viaparinfo->chip_info->gfx_chip_name))
  776. viafb_write_reg_mask(CR97, VIACR, 0x84,
  777. BIT7 + BIT2 + BIT1 + BIT0);
  778. case INTERFACE_DVP0:
  779. case INTERFACE_DVP1:
  780. case INTERFACE_DFP_HIGH:
  781. case INTERFACE_DFP_LOW:
  782. if (set_iga == IGA2)
  783. viafb_write_reg(CR91, VIACR, 0x00);
  784. break;
  785. }
  786. }
  787. void viafb_lcd_enable(void)
  788. {
  789. viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
  790. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  791. set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path,
  792. viaparinfo->chip_info->lvds_chip_info.output_interface);
  793. if (viafb_LCD2_ON)
  794. set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path,
  795. viaparinfo->chip_info->
  796. lvds_chip_info2.output_interface);
  797. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  798. /* DI1 pad on */
  799. viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
  800. lcd_powersequence_on();
  801. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  802. if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
  803. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  804. integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
  805. &viaparinfo->chip_info->lvds_chip_info2);
  806. if (INTEGRATED_LVDS ==
  807. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  808. integrated_lvds_enable(viaparinfo->lvds_setting_info,
  809. &viaparinfo->chip_info->lvds_chip_info);
  810. if (VT1636_LVDS == viaparinfo->chip_info->
  811. lvds_chip_info.lvds_chip_name)
  812. viafb_enable_lvds_vt1636(viaparinfo->
  813. lvds_setting_info, &viaparinfo->chip_info->
  814. lvds_chip_info);
  815. } else if (VT1636_LVDS ==
  816. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  817. viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
  818. &viaparinfo->chip_info->lvds_chip_info);
  819. } else {
  820. /* DFP-HL pad on */
  821. viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
  822. /* Backlight on */
  823. viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
  824. /* 24 bit DI data paht on */
  825. viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
  826. /* LCD enabled */
  827. viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
  828. }
  829. }
  830. static void lcd_powersequence_off(void)
  831. {
  832. int i, mask, data;
  833. /* Software control power sequence */
  834. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  835. for (i = 0; i < 3; i++) {
  836. mask = PowerSequenceOff[0][i];
  837. data = PowerSequenceOff[1][i] & mask;
  838. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  839. udelay(PowerSequenceOff[2][i]);
  840. }
  841. /* Disable LCD */
  842. viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
  843. }
  844. static void lcd_powersequence_on(void)
  845. {
  846. int i, mask, data;
  847. /* Software control power sequence */
  848. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  849. /* Enable LCD */
  850. viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
  851. for (i = 0; i < 3; i++) {
  852. mask = PowerSequenceOn[0][i];
  853. data = PowerSequenceOn[1][i] & mask;
  854. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  855. udelay(PowerSequenceOn[2][i]);
  856. }
  857. udelay(1);
  858. }
  859. static void fill_lcd_format(void)
  860. {
  861. u8 bdithering = 0, bdual = 0;
  862. if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
  863. bdual = BIT4;
  864. if (viaparinfo->lvds_setting_info->LCDDithering)
  865. bdithering = BIT0;
  866. /* Dual & Dithering */
  867. viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
  868. }
  869. static void check_diport_of_integrated_lvds(
  870. struct lvds_chip_information *plvds_chip_info,
  871. struct lvds_setting_information
  872. *plvds_setting_info)
  873. {
  874. /* Determine LCD DI Port by hardware layout. */
  875. switch (viafb_display_hardware_layout) {
  876. case HW_LAYOUT_LCD_ONLY:
  877. {
  878. if (plvds_setting_info->device_lcd_dualedge) {
  879. plvds_chip_info->output_interface =
  880. INTERFACE_LVDS0LVDS1;
  881. } else {
  882. plvds_chip_info->output_interface =
  883. INTERFACE_LVDS0;
  884. }
  885. break;
  886. }
  887. case HW_LAYOUT_DVI_ONLY:
  888. {
  889. plvds_chip_info->output_interface = INTERFACE_NONE;
  890. break;
  891. }
  892. case HW_LAYOUT_LCD1_LCD2:
  893. case HW_LAYOUT_LCD_EXTERNAL_LCD2:
  894. {
  895. plvds_chip_info->output_interface =
  896. INTERFACE_LVDS0LVDS1;
  897. break;
  898. }
  899. case HW_LAYOUT_LCD_DVI:
  900. {
  901. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  902. break;
  903. }
  904. default:
  905. {
  906. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  907. break;
  908. }
  909. }
  910. DEBUG_MSG(KERN_INFO
  911. "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
  912. viafb_display_hardware_layout,
  913. plvds_chip_info->output_interface);
  914. }
  915. void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information
  916. *plvds_chip_info,
  917. struct lvds_setting_information
  918. *plvds_setting_info)
  919. {
  920. if (INTERFACE_NONE != plvds_chip_info->output_interface) {
  921. /*Do nothing, lcd port is specified by module parameter */
  922. return;
  923. }
  924. switch (plvds_chip_info->lvds_chip_name) {
  925. case VT1636_LVDS:
  926. switch (viaparinfo->chip_info->gfx_chip_name) {
  927. case UNICHROME_CX700:
  928. plvds_chip_info->output_interface = INTERFACE_DVP1;
  929. break;
  930. case UNICHROME_CN700:
  931. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  932. break;
  933. default:
  934. plvds_chip_info->output_interface = INTERFACE_DVP0;
  935. break;
  936. }
  937. break;
  938. case INTEGRATED_LVDS:
  939. check_diport_of_integrated_lvds(plvds_chip_info,
  940. plvds_setting_info);
  941. break;
  942. default:
  943. switch (viaparinfo->chip_info->gfx_chip_name) {
  944. case UNICHROME_K8M890:
  945. case UNICHROME_P4M900:
  946. case UNICHROME_P4M890:
  947. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  948. break;
  949. default:
  950. plvds_chip_info->output_interface = INTERFACE_DFP;
  951. break;
  952. }
  953. break;
  954. }
  955. }
  956. static struct display_timing lcd_centering_timging(struct display_timing
  957. mode_crt_reg,
  958. struct display_timing panel_crt_reg)
  959. {
  960. struct display_timing crt_reg;
  961. crt_reg.hor_total = panel_crt_reg.hor_total;
  962. crt_reg.hor_addr = mode_crt_reg.hor_addr;
  963. crt_reg.hor_blank_start =
  964. (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
  965. crt_reg.hor_addr;
  966. crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
  967. crt_reg.hor_sync_start =
  968. (panel_crt_reg.hor_sync_start -
  969. panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
  970. crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
  971. crt_reg.ver_total = panel_crt_reg.ver_total;
  972. crt_reg.ver_addr = mode_crt_reg.ver_addr;
  973. crt_reg.ver_blank_start =
  974. (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
  975. crt_reg.ver_addr;
  976. crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
  977. crt_reg.ver_sync_start =
  978. (panel_crt_reg.ver_sync_start -
  979. panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
  980. crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
  981. return crt_reg;
  982. }
  983. bool viafb_lcd_get_mobile_state(bool *mobile)
  984. {
  985. unsigned char *romptr, *tableptr;
  986. u8 core_base;
  987. unsigned char *biosptr;
  988. /* Rom address */
  989. u32 romaddr = 0x000C0000;
  990. u16 start_pattern = 0;
  991. biosptr = ioremap(romaddr, 0x10000);
  992. memcpy(&start_pattern, biosptr, 2);
  993. /* Compare pattern */
  994. if (start_pattern == 0xAA55) {
  995. /* Get the start of Table */
  996. /* 0x1B means BIOS offset position */
  997. romptr = biosptr + 0x1B;
  998. tableptr = biosptr + *((u16 *) romptr);
  999. /* Get the start of biosver structure */
  1000. /* 18 means BIOS version position. */
  1001. romptr = tableptr + 18;
  1002. romptr = biosptr + *((u16 *) romptr);
  1003. /* The offset should be 44, but the
  1004. actual image is less three char. */
  1005. /* pRom += 44; */
  1006. romptr += 41;
  1007. core_base = *romptr++;
  1008. if (core_base & 0x8)
  1009. *mobile = false;
  1010. else
  1011. *mobile = true;
  1012. /* release memory */
  1013. iounmap(biosptr);
  1014. return true;
  1015. } else {
  1016. iounmap(biosptr);
  1017. return false;
  1018. }
  1019. }