init.c 45 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915
  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/moduleparam.h>
  17. #include <linux/errno.h>
  18. #include <linux/of.h>
  19. #include <linux/mmc/sdio_func.h>
  20. #include "core.h"
  21. #include "cfg80211.h"
  22. #include "target.h"
  23. #include "debug.h"
  24. #include "hif-ops.h"
  25. unsigned int debug_mask;
  26. static unsigned int testmode;
  27. static bool suspend_cutpower;
  28. static unsigned int uart_debug;
  29. module_param(debug_mask, uint, 0644);
  30. module_param(testmode, uint, 0644);
  31. module_param(suspend_cutpower, bool, 0444);
  32. module_param(uart_debug, uint, 0644);
  33. static const struct ath6kl_hw hw_list[] = {
  34. {
  35. .id = AR6003_HW_2_0_VERSION,
  36. .name = "ar6003 hw 2.0",
  37. .dataset_patch_addr = 0x57e884,
  38. .app_load_addr = 0x543180,
  39. .board_ext_data_addr = 0x57e500,
  40. .reserved_ram_size = 6912,
  41. .refclk_hz = 26000000,
  42. .uarttx_pin = 8,
  43. /* hw2.0 needs override address hardcoded */
  44. .app_start_override_addr = 0x944C00,
  45. .fw = {
  46. .dir = AR6003_HW_2_0_FW_DIR,
  47. .otp = AR6003_HW_2_0_OTP_FILE,
  48. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  49. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  50. .patch = AR6003_HW_2_0_PATCH_FILE,
  51. },
  52. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  53. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  54. },
  55. {
  56. .id = AR6003_HW_2_1_1_VERSION,
  57. .name = "ar6003 hw 2.1.1",
  58. .dataset_patch_addr = 0x57ff74,
  59. .app_load_addr = 0x1234,
  60. .board_ext_data_addr = 0x542330,
  61. .reserved_ram_size = 512,
  62. .refclk_hz = 26000000,
  63. .uarttx_pin = 8,
  64. .testscript_addr = 0x57ef74,
  65. .fw = {
  66. .dir = AR6003_HW_2_1_1_FW_DIR,
  67. .otp = AR6003_HW_2_1_1_OTP_FILE,
  68. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  69. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  70. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  71. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  72. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  73. },
  74. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  75. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  76. },
  77. {
  78. .id = AR6004_HW_1_0_VERSION,
  79. .name = "ar6004 hw 1.0",
  80. .dataset_patch_addr = 0x57e884,
  81. .app_load_addr = 0x1234,
  82. .board_ext_data_addr = 0x437000,
  83. .reserved_ram_size = 19456,
  84. .board_addr = 0x433900,
  85. .refclk_hz = 26000000,
  86. .uarttx_pin = 11,
  87. .fw = {
  88. .dir = AR6004_HW_1_0_FW_DIR,
  89. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  90. },
  91. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  92. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  93. },
  94. {
  95. .id = AR6004_HW_1_1_VERSION,
  96. .name = "ar6004 hw 1.1",
  97. .dataset_patch_addr = 0x57e884,
  98. .app_load_addr = 0x1234,
  99. .board_ext_data_addr = 0x437000,
  100. .reserved_ram_size = 11264,
  101. .board_addr = 0x43d400,
  102. .refclk_hz = 40000000,
  103. .uarttx_pin = 11,
  104. .fw = {
  105. .dir = AR6004_HW_1_1_FW_DIR,
  106. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  107. },
  108. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  109. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  110. },
  111. };
  112. /*
  113. * Include definitions here that can be used to tune the WLAN module
  114. * behavior. Different customers can tune the behavior as per their needs,
  115. * here.
  116. */
  117. /*
  118. * This configuration item enable/disable keepalive support.
  119. * Keepalive support: In the absence of any data traffic to AP, null
  120. * frames will be sent to the AP at periodic interval, to keep the association
  121. * active. This configuration item defines the periodic interval.
  122. * Use value of zero to disable keepalive support
  123. * Default: 60 seconds
  124. */
  125. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  126. /*
  127. * This configuration item sets the value of disconnect timeout
  128. * Firmware delays sending the disconnec event to the host for this
  129. * timeout after is gets disconnected from the current AP.
  130. * If the firmware successly roams within the disconnect timeout
  131. * it sends a new connect event
  132. */
  133. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  134. #define ATH6KL_DATA_OFFSET 64
  135. struct sk_buff *ath6kl_buf_alloc(int size)
  136. {
  137. struct sk_buff *skb;
  138. u16 reserved;
  139. /* Add chacheline space at front and back of buffer */
  140. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  141. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  142. skb = dev_alloc_skb(size + reserved);
  143. if (skb)
  144. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  145. return skb;
  146. }
  147. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  148. {
  149. vif->ssid_len = 0;
  150. memset(vif->ssid, 0, sizeof(vif->ssid));
  151. vif->dot11_auth_mode = OPEN_AUTH;
  152. vif->auth_mode = NONE_AUTH;
  153. vif->prwise_crypto = NONE_CRYPT;
  154. vif->prwise_crypto_len = 0;
  155. vif->grp_crypto = NONE_CRYPT;
  156. vif->grp_crypto_len = 0;
  157. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  158. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  159. memset(vif->bssid, 0, sizeof(vif->bssid));
  160. vif->bss_ch = 0;
  161. }
  162. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  163. {
  164. u32 address, data;
  165. struct host_app_area host_app_area;
  166. /* Fetch the address of the host_app_area_s
  167. * instance in the host interest area */
  168. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  169. address = TARG_VTOP(ar->target_type, address);
  170. if (ath6kl_diag_read32(ar, address, &data))
  171. return -EIO;
  172. address = TARG_VTOP(ar->target_type, data);
  173. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  174. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  175. sizeof(struct host_app_area)))
  176. return -EIO;
  177. return 0;
  178. }
  179. static inline void set_ac2_ep_map(struct ath6kl *ar,
  180. u8 ac,
  181. enum htc_endpoint_id ep)
  182. {
  183. ar->ac2ep_map[ac] = ep;
  184. ar->ep2ac_map[ep] = ac;
  185. }
  186. /* connect to a service */
  187. static int ath6kl_connectservice(struct ath6kl *ar,
  188. struct htc_service_connect_req *con_req,
  189. char *desc)
  190. {
  191. int status;
  192. struct htc_service_connect_resp response;
  193. memset(&response, 0, sizeof(response));
  194. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  195. if (status) {
  196. ath6kl_err("failed to connect to %s service status:%d\n",
  197. desc, status);
  198. return status;
  199. }
  200. switch (con_req->svc_id) {
  201. case WMI_CONTROL_SVC:
  202. if (test_bit(WMI_ENABLED, &ar->flag))
  203. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  204. ar->ctrl_ep = response.endpoint;
  205. break;
  206. case WMI_DATA_BE_SVC:
  207. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  208. break;
  209. case WMI_DATA_BK_SVC:
  210. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  211. break;
  212. case WMI_DATA_VI_SVC:
  213. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  214. break;
  215. case WMI_DATA_VO_SVC:
  216. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  217. break;
  218. default:
  219. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  220. return -EINVAL;
  221. }
  222. return 0;
  223. }
  224. static int ath6kl_init_service_ep(struct ath6kl *ar)
  225. {
  226. struct htc_service_connect_req connect;
  227. memset(&connect, 0, sizeof(connect));
  228. /* these fields are the same for all service endpoints */
  229. connect.ep_cb.rx = ath6kl_rx;
  230. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  231. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  232. /*
  233. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  234. * gets called.
  235. */
  236. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  237. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  238. if (!connect.ep_cb.rx_refill_thresh)
  239. connect.ep_cb.rx_refill_thresh++;
  240. /* connect to control service */
  241. connect.svc_id = WMI_CONTROL_SVC;
  242. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  243. return -EIO;
  244. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  245. /*
  246. * Limit the HTC message size on the send path, although e can
  247. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  248. * (802.3) frames on the send path.
  249. */
  250. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  251. /*
  252. * To reduce the amount of committed memory for larger A_MSDU
  253. * frames, use the recv-alloc threshold mechanism for larger
  254. * packets.
  255. */
  256. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  257. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  258. /*
  259. * For the remaining data services set the connection flag to
  260. * reduce dribbling, if configured to do so.
  261. */
  262. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  263. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  264. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  265. connect.svc_id = WMI_DATA_BE_SVC;
  266. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  267. return -EIO;
  268. /* connect to back-ground map this to WMI LOW_PRI */
  269. connect.svc_id = WMI_DATA_BK_SVC;
  270. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  271. return -EIO;
  272. /* connect to Video service, map this to to HI PRI */
  273. connect.svc_id = WMI_DATA_VI_SVC;
  274. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  275. return -EIO;
  276. /*
  277. * Connect to VO service, this is currently not mapped to a WMI
  278. * priority stream due to historical reasons. WMI originally
  279. * defined 3 priorities over 3 mailboxes We can change this when
  280. * WMI is reworked so that priorities are not dependent on
  281. * mailboxes.
  282. */
  283. connect.svc_id = WMI_DATA_VO_SVC;
  284. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  285. return -EIO;
  286. return 0;
  287. }
  288. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  289. {
  290. ath6kl_init_profile_info(vif);
  291. vif->def_txkey_index = 0;
  292. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  293. vif->ch_hint = 0;
  294. }
  295. /*
  296. * Set HTC/Mbox operational parameters, this can only be called when the
  297. * target is in the BMI phase.
  298. */
  299. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  300. u8 htc_ctrl_buf)
  301. {
  302. int status;
  303. u32 blk_size;
  304. blk_size = ar->mbox_info.block_size;
  305. if (htc_ctrl_buf)
  306. blk_size |= ((u32)htc_ctrl_buf) << 16;
  307. /* set the host interest area for the block size */
  308. status = ath6kl_bmi_write(ar,
  309. ath6kl_get_hi_item_addr(ar,
  310. HI_ITEM(hi_mbox_io_block_sz)),
  311. (u8 *)&blk_size,
  312. 4);
  313. if (status) {
  314. ath6kl_err("bmi_write_memory for IO block size failed\n");
  315. goto out;
  316. }
  317. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  318. blk_size,
  319. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  320. if (mbox_isr_yield_val) {
  321. /* set the host interest area for the mbox ISR yield limit */
  322. status = ath6kl_bmi_write(ar,
  323. ath6kl_get_hi_item_addr(ar,
  324. HI_ITEM(hi_mbox_isr_yield_limit)),
  325. (u8 *)&mbox_isr_yield_val,
  326. 4);
  327. if (status) {
  328. ath6kl_err("bmi_write_memory for yield limit failed\n");
  329. goto out;
  330. }
  331. }
  332. out:
  333. return status;
  334. }
  335. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  336. {
  337. int status = 0;
  338. int ret;
  339. /*
  340. * Configure the device for rx dot11 header rules. "0,0" are the
  341. * default values. Required if checksum offload is needed. Set
  342. * RxMetaVersion to 2.
  343. */
  344. if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  345. ar->rx_meta_ver, 0, 0)) {
  346. ath6kl_err("unable to set the rx frame format\n");
  347. status = -EIO;
  348. }
  349. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN)
  350. if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  351. IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
  352. ath6kl_err("unable to set power save fail event policy\n");
  353. status = -EIO;
  354. }
  355. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER))
  356. if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  357. WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) {
  358. ath6kl_err("unable to set barker preamble policy\n");
  359. status = -EIO;
  360. }
  361. if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  362. WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) {
  363. ath6kl_err("unable to set keep alive interval\n");
  364. status = -EIO;
  365. }
  366. if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  367. WLAN_CONFIG_DISCONNECT_TIMEOUT)) {
  368. ath6kl_err("unable to set disconnect timeout\n");
  369. status = -EIO;
  370. }
  371. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST))
  372. if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) {
  373. ath6kl_err("unable to set txop bursting\n");
  374. status = -EIO;
  375. }
  376. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  377. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  378. P2P_FLAG_CAPABILITIES_REQ |
  379. P2P_FLAG_MACADDR_REQ |
  380. P2P_FLAG_HMODEL_REQ);
  381. if (ret) {
  382. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
  383. "capabilities (%d) - assuming P2P not "
  384. "supported\n", ret);
  385. ar->p2p = false;
  386. }
  387. }
  388. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  389. /* Enable Probe Request reporting for P2P */
  390. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  391. if (ret) {
  392. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
  393. "Request reporting (%d)\n", ret);
  394. }
  395. }
  396. return status;
  397. }
  398. int ath6kl_configure_target(struct ath6kl *ar)
  399. {
  400. u32 param, ram_reserved_size;
  401. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  402. int i, status;
  403. param = uart_debug;
  404. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  405. HI_ITEM(hi_serial_enable)), (u8 *)&param, 4)) {
  406. ath6kl_err("bmi_write_memory for uart debug failed\n");
  407. return -EIO;
  408. }
  409. /*
  410. * Note: Even though the firmware interface type is
  411. * chosen as BSS_STA for all three interfaces, can
  412. * be configured to IBSS/AP as long as the fw submode
  413. * remains normal mode (0 - AP, STA and IBSS). But
  414. * due to an target assert in firmware only one interface is
  415. * configured for now.
  416. */
  417. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  418. for (i = 0; i < ar->vif_max; i++)
  419. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  420. /*
  421. * By default, submodes :
  422. * vif[0] - AP/STA/IBSS
  423. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  424. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  425. */
  426. for (i = 0; i < ar->max_norm_iface; i++)
  427. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  428. (i * HI_OPTION_FW_SUBMODE_BITS);
  429. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  430. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  431. (i * HI_OPTION_FW_SUBMODE_BITS);
  432. if (ar->p2p && ar->vif_max == 1)
  433. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  434. param = HTC_PROTOCOL_VERSION;
  435. if (ath6kl_bmi_write(ar,
  436. ath6kl_get_hi_item_addr(ar,
  437. HI_ITEM(hi_app_host_interest)),
  438. (u8 *)&param, 4) != 0) {
  439. ath6kl_err("bmi_write_memory for htc version failed\n");
  440. return -EIO;
  441. }
  442. /* set the firmware mode to STA/IBSS/AP */
  443. param = 0;
  444. if (ath6kl_bmi_read(ar,
  445. ath6kl_get_hi_item_addr(ar,
  446. HI_ITEM(hi_option_flag)),
  447. (u8 *)&param, 4) != 0) {
  448. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  449. return -EIO;
  450. }
  451. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  452. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  453. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  454. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  455. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  456. if (ath6kl_bmi_write(ar,
  457. ath6kl_get_hi_item_addr(ar,
  458. HI_ITEM(hi_option_flag)),
  459. (u8 *)&param,
  460. 4) != 0) {
  461. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  462. return -EIO;
  463. }
  464. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  465. /*
  466. * Hardcode the address use for the extended board data
  467. * Ideally this should be pre-allocate by the OS at boot time
  468. * But since it is a new feature and board data is loaded
  469. * at init time, we have to workaround this from host.
  470. * It is difficult to patch the firmware boot code,
  471. * but possible in theory.
  472. */
  473. param = ar->hw.board_ext_data_addr;
  474. ram_reserved_size = ar->hw.reserved_ram_size;
  475. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  476. HI_ITEM(hi_board_ext_data)),
  477. (u8 *)&param, 4) != 0) {
  478. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  479. return -EIO;
  480. }
  481. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  482. HI_ITEM(hi_end_ram_reserve_sz)),
  483. (u8 *)&ram_reserved_size, 4) != 0) {
  484. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  485. return -EIO;
  486. }
  487. /* set the block size for the target */
  488. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  489. /* use default number of control buffers */
  490. return -EIO;
  491. /* Configure GPIO AR600x UART */
  492. param = ar->hw.uarttx_pin;
  493. status = ath6kl_bmi_write(ar,
  494. ath6kl_get_hi_item_addr(ar,
  495. HI_ITEM(hi_dbg_uart_txpin)),
  496. (u8 *)&param, 4);
  497. if (status)
  498. return status;
  499. /* Configure target refclk_hz */
  500. param = ar->hw.refclk_hz;
  501. status = ath6kl_bmi_write(ar,
  502. ath6kl_get_hi_item_addr(ar,
  503. HI_ITEM(hi_refclk_hz)),
  504. (u8 *)&param, 4);
  505. if (status)
  506. return status;
  507. return 0;
  508. }
  509. void ath6kl_core_free(struct ath6kl *ar)
  510. {
  511. wiphy_free(ar->wiphy);
  512. }
  513. void ath6kl_core_cleanup(struct ath6kl *ar)
  514. {
  515. ath6kl_hif_power_off(ar);
  516. destroy_workqueue(ar->ath6kl_wq);
  517. if (ar->htc_target)
  518. ath6kl_htc_cleanup(ar->htc_target);
  519. ath6kl_cookie_cleanup(ar);
  520. ath6kl_cleanup_amsdu_rxbufs(ar);
  521. ath6kl_bmi_cleanup(ar);
  522. ath6kl_debug_cleanup(ar);
  523. kfree(ar->fw_board);
  524. kfree(ar->fw_otp);
  525. kfree(ar->fw);
  526. kfree(ar->fw_patch);
  527. kfree(ar->fw_testscript);
  528. ath6kl_deinit_ieee80211_hw(ar);
  529. }
  530. /* firmware upload */
  531. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  532. u8 **fw, size_t *fw_len)
  533. {
  534. const struct firmware *fw_entry;
  535. int ret;
  536. ret = request_firmware(&fw_entry, filename, ar->dev);
  537. if (ret)
  538. return ret;
  539. *fw_len = fw_entry->size;
  540. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  541. if (*fw == NULL)
  542. ret = -ENOMEM;
  543. release_firmware(fw_entry);
  544. return ret;
  545. }
  546. #ifdef CONFIG_OF
  547. /*
  548. * Check the device tree for a board-id and use it to construct
  549. * the pathname to the firmware file. Used (for now) to find a
  550. * fallback to the "bdata.bin" file--typically a symlink to the
  551. * appropriate board-specific file.
  552. */
  553. static bool check_device_tree(struct ath6kl *ar)
  554. {
  555. static const char *board_id_prop = "atheros,board-id";
  556. struct device_node *node;
  557. char board_filename[64];
  558. const char *board_id;
  559. int ret;
  560. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  561. board_id = of_get_property(node, board_id_prop, NULL);
  562. if (board_id == NULL) {
  563. ath6kl_warn("No \"%s\" property on %s node.\n",
  564. board_id_prop, node->name);
  565. continue;
  566. }
  567. snprintf(board_filename, sizeof(board_filename),
  568. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  569. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  570. &ar->fw_board_len);
  571. if (ret) {
  572. ath6kl_err("Failed to get DT board file %s: %d\n",
  573. board_filename, ret);
  574. continue;
  575. }
  576. return true;
  577. }
  578. return false;
  579. }
  580. #else
  581. static bool check_device_tree(struct ath6kl *ar)
  582. {
  583. return false;
  584. }
  585. #endif /* CONFIG_OF */
  586. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  587. {
  588. const char *filename;
  589. int ret;
  590. if (ar->fw_board != NULL)
  591. return 0;
  592. if (WARN_ON(ar->hw.fw_board == NULL))
  593. return -EINVAL;
  594. filename = ar->hw.fw_board;
  595. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  596. &ar->fw_board_len);
  597. if (ret == 0) {
  598. /* managed to get proper board file */
  599. return 0;
  600. }
  601. if (check_device_tree(ar)) {
  602. /* got board file from device tree */
  603. return 0;
  604. }
  605. /* there was no proper board file, try to use default instead */
  606. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  607. filename, ret);
  608. filename = ar->hw.fw_default_board;
  609. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  610. &ar->fw_board_len);
  611. if (ret) {
  612. ath6kl_err("Failed to get default board file %s: %d\n",
  613. filename, ret);
  614. return ret;
  615. }
  616. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  617. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  618. return 0;
  619. }
  620. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  621. {
  622. char filename[100];
  623. int ret;
  624. if (ar->fw_otp != NULL)
  625. return 0;
  626. if (ar->hw.fw.otp == NULL) {
  627. ath6kl_dbg(ATH6KL_DBG_BOOT,
  628. "no OTP file configured for this hw\n");
  629. return 0;
  630. }
  631. snprintf(filename, sizeof(filename), "%s/%s",
  632. ar->hw.fw.dir, ar->hw.fw.otp);
  633. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  634. &ar->fw_otp_len);
  635. if (ret) {
  636. ath6kl_err("Failed to get OTP file %s: %d\n",
  637. filename, ret);
  638. return ret;
  639. }
  640. return 0;
  641. }
  642. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  643. {
  644. char filename[100];
  645. int ret;
  646. if (ar->fw != NULL)
  647. return 0;
  648. if (testmode) {
  649. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n",
  650. testmode);
  651. if (testmode == 2) {
  652. if (ar->hw.fw.utf == NULL) {
  653. ath6kl_warn("testmode 2 not supported\n");
  654. return -EOPNOTSUPP;
  655. }
  656. snprintf(filename, sizeof(filename), "%s/%s",
  657. ar->hw.fw.dir, ar->hw.fw.utf);
  658. } else {
  659. if (ar->hw.fw.tcmd == NULL) {
  660. ath6kl_warn("testmode 1 not supported\n");
  661. return -EOPNOTSUPP;
  662. }
  663. snprintf(filename, sizeof(filename), "%s/%s",
  664. ar->hw.fw.dir, ar->hw.fw.tcmd);
  665. }
  666. set_bit(TESTMODE, &ar->flag);
  667. goto get_fw;
  668. }
  669. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  670. if (WARN_ON(ar->hw.fw.fw == NULL))
  671. return -EINVAL;
  672. snprintf(filename, sizeof(filename), "%s/%s",
  673. ar->hw.fw.dir, ar->hw.fw.fw);
  674. get_fw:
  675. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  676. if (ret) {
  677. ath6kl_err("Failed to get firmware file %s: %d\n",
  678. filename, ret);
  679. return ret;
  680. }
  681. return 0;
  682. }
  683. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  684. {
  685. char filename[100];
  686. int ret;
  687. if (ar->fw_patch != NULL)
  688. return 0;
  689. if (ar->hw.fw.patch == NULL)
  690. return 0;
  691. snprintf(filename, sizeof(filename), "%s/%s",
  692. ar->hw.fw.dir, ar->hw.fw.patch);
  693. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  694. &ar->fw_patch_len);
  695. if (ret) {
  696. ath6kl_err("Failed to get patch file %s: %d\n",
  697. filename, ret);
  698. return ret;
  699. }
  700. return 0;
  701. }
  702. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  703. {
  704. char filename[100];
  705. int ret;
  706. if (testmode != 2)
  707. return 0;
  708. if (ar->fw_testscript != NULL)
  709. return 0;
  710. if (ar->hw.fw.testscript == NULL)
  711. return 0;
  712. snprintf(filename, sizeof(filename), "%s/%s",
  713. ar->hw.fw.dir, ar->hw.fw.testscript);
  714. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  715. &ar->fw_testscript_len);
  716. if (ret) {
  717. ath6kl_err("Failed to get testscript file %s: %d\n",
  718. filename, ret);
  719. return ret;
  720. }
  721. return 0;
  722. }
  723. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  724. {
  725. int ret;
  726. ret = ath6kl_fetch_otp_file(ar);
  727. if (ret)
  728. return ret;
  729. ret = ath6kl_fetch_fw_file(ar);
  730. if (ret)
  731. return ret;
  732. ret = ath6kl_fetch_patch_file(ar);
  733. if (ret)
  734. return ret;
  735. ret = ath6kl_fetch_testscript_file(ar);
  736. if (ret)
  737. return ret;
  738. return 0;
  739. }
  740. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  741. {
  742. size_t magic_len, len, ie_len;
  743. const struct firmware *fw;
  744. struct ath6kl_fw_ie *hdr;
  745. char filename[100];
  746. const u8 *data;
  747. int ret, ie_id, i, index, bit;
  748. __le32 *val;
  749. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  750. ret = request_firmware(&fw, filename, ar->dev);
  751. if (ret)
  752. return ret;
  753. data = fw->data;
  754. len = fw->size;
  755. /* magic also includes the null byte, check that as well */
  756. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  757. if (len < magic_len) {
  758. ret = -EINVAL;
  759. goto out;
  760. }
  761. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  762. ret = -EINVAL;
  763. goto out;
  764. }
  765. len -= magic_len;
  766. data += magic_len;
  767. /* loop elements */
  768. while (len > sizeof(struct ath6kl_fw_ie)) {
  769. /* hdr is unaligned! */
  770. hdr = (struct ath6kl_fw_ie *) data;
  771. ie_id = le32_to_cpup(&hdr->id);
  772. ie_len = le32_to_cpup(&hdr->len);
  773. len -= sizeof(*hdr);
  774. data += sizeof(*hdr);
  775. if (len < ie_len) {
  776. ret = -EINVAL;
  777. goto out;
  778. }
  779. switch (ie_id) {
  780. case ATH6KL_FW_IE_OTP_IMAGE:
  781. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  782. ie_len);
  783. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  784. if (ar->fw_otp == NULL) {
  785. ret = -ENOMEM;
  786. goto out;
  787. }
  788. ar->fw_otp_len = ie_len;
  789. break;
  790. case ATH6KL_FW_IE_FW_IMAGE:
  791. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  792. ie_len);
  793. ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
  794. if (ar->fw == NULL) {
  795. ret = -ENOMEM;
  796. goto out;
  797. }
  798. ar->fw_len = ie_len;
  799. break;
  800. case ATH6KL_FW_IE_PATCH_IMAGE:
  801. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  802. ie_len);
  803. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  804. if (ar->fw_patch == NULL) {
  805. ret = -ENOMEM;
  806. goto out;
  807. }
  808. ar->fw_patch_len = ie_len;
  809. break;
  810. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  811. val = (__le32 *) data;
  812. ar->hw.reserved_ram_size = le32_to_cpup(val);
  813. ath6kl_dbg(ATH6KL_DBG_BOOT,
  814. "found reserved ram size ie 0x%d\n",
  815. ar->hw.reserved_ram_size);
  816. break;
  817. case ATH6KL_FW_IE_CAPABILITIES:
  818. if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
  819. break;
  820. ath6kl_dbg(ATH6KL_DBG_BOOT,
  821. "found firmware capabilities ie (%zd B)\n",
  822. ie_len);
  823. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  824. index = i / 8;
  825. bit = i % 8;
  826. if (data[index] & (1 << bit))
  827. __set_bit(i, ar->fw_capabilities);
  828. }
  829. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  830. ar->fw_capabilities,
  831. sizeof(ar->fw_capabilities));
  832. break;
  833. case ATH6KL_FW_IE_PATCH_ADDR:
  834. if (ie_len != sizeof(*val))
  835. break;
  836. val = (__le32 *) data;
  837. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  838. ath6kl_dbg(ATH6KL_DBG_BOOT,
  839. "found patch address ie 0x%x\n",
  840. ar->hw.dataset_patch_addr);
  841. break;
  842. case ATH6KL_FW_IE_BOARD_ADDR:
  843. if (ie_len != sizeof(*val))
  844. break;
  845. val = (__le32 *) data;
  846. ar->hw.board_addr = le32_to_cpup(val);
  847. ath6kl_dbg(ATH6KL_DBG_BOOT,
  848. "found board address ie 0x%x\n",
  849. ar->hw.board_addr);
  850. break;
  851. case ATH6KL_FW_IE_VIF_MAX:
  852. if (ie_len != sizeof(*val))
  853. break;
  854. val = (__le32 *) data;
  855. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  856. ATH6KL_VIF_MAX);
  857. if (ar->vif_max > 1 && !ar->p2p)
  858. ar->max_norm_iface = 2;
  859. ath6kl_dbg(ATH6KL_DBG_BOOT,
  860. "found vif max ie %d\n", ar->vif_max);
  861. break;
  862. default:
  863. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  864. le32_to_cpup(&hdr->id));
  865. break;
  866. }
  867. len -= ie_len;
  868. data += ie_len;
  869. };
  870. ret = 0;
  871. out:
  872. release_firmware(fw);
  873. return ret;
  874. }
  875. static int ath6kl_fetch_firmwares(struct ath6kl *ar)
  876. {
  877. int ret;
  878. ret = ath6kl_fetch_board_file(ar);
  879. if (ret)
  880. return ret;
  881. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  882. if (ret == 0) {
  883. ar->fw_api = 3;
  884. goto out;
  885. }
  886. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  887. if (ret == 0) {
  888. ar->fw_api = 2;
  889. goto out;
  890. }
  891. ret = ath6kl_fetch_fw_api1(ar);
  892. if (ret)
  893. return ret;
  894. ar->fw_api = 1;
  895. out:
  896. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  897. return 0;
  898. }
  899. static int ath6kl_upload_board_file(struct ath6kl *ar)
  900. {
  901. u32 board_address, board_ext_address, param;
  902. u32 board_data_size, board_ext_data_size;
  903. int ret;
  904. if (WARN_ON(ar->fw_board == NULL))
  905. return -ENOENT;
  906. /*
  907. * Determine where in Target RAM to write Board Data.
  908. * For AR6004, host determine Target RAM address for
  909. * writing board data.
  910. */
  911. if (ar->hw.board_addr != 0) {
  912. board_address = ar->hw.board_addr;
  913. ath6kl_bmi_write(ar,
  914. ath6kl_get_hi_item_addr(ar,
  915. HI_ITEM(hi_board_data)),
  916. (u8 *) &board_address, 4);
  917. } else {
  918. ath6kl_bmi_read(ar,
  919. ath6kl_get_hi_item_addr(ar,
  920. HI_ITEM(hi_board_data)),
  921. (u8 *) &board_address, 4);
  922. }
  923. /* determine where in target ram to write extended board data */
  924. ath6kl_bmi_read(ar,
  925. ath6kl_get_hi_item_addr(ar,
  926. HI_ITEM(hi_board_ext_data)),
  927. (u8 *) &board_ext_address, 4);
  928. if (ar->target_type == TARGET_TYPE_AR6003 &&
  929. board_ext_address == 0) {
  930. ath6kl_err("Failed to get board file target address.\n");
  931. return -EINVAL;
  932. }
  933. switch (ar->target_type) {
  934. case TARGET_TYPE_AR6003:
  935. board_data_size = AR6003_BOARD_DATA_SZ;
  936. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  937. break;
  938. case TARGET_TYPE_AR6004:
  939. board_data_size = AR6004_BOARD_DATA_SZ;
  940. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  941. break;
  942. default:
  943. WARN_ON(1);
  944. return -EINVAL;
  945. break;
  946. }
  947. if (board_ext_address &&
  948. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  949. /* write extended board data */
  950. ath6kl_dbg(ATH6KL_DBG_BOOT,
  951. "writing extended board data to 0x%x (%d B)\n",
  952. board_ext_address, board_ext_data_size);
  953. ret = ath6kl_bmi_write(ar, board_ext_address,
  954. ar->fw_board + board_data_size,
  955. board_ext_data_size);
  956. if (ret) {
  957. ath6kl_err("Failed to write extended board data: %d\n",
  958. ret);
  959. return ret;
  960. }
  961. /* record that extended board data is initialized */
  962. param = (board_ext_data_size << 16) | 1;
  963. ath6kl_bmi_write(ar,
  964. ath6kl_get_hi_item_addr(ar,
  965. HI_ITEM(hi_board_ext_data_config)),
  966. (unsigned char *) &param, 4);
  967. }
  968. if (ar->fw_board_len < board_data_size) {
  969. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  970. ret = -EINVAL;
  971. return ret;
  972. }
  973. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  974. board_address, board_data_size);
  975. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  976. board_data_size);
  977. if (ret) {
  978. ath6kl_err("Board file bmi write failed: %d\n", ret);
  979. return ret;
  980. }
  981. /* record the fact that Board Data IS initialized */
  982. param = 1;
  983. ath6kl_bmi_write(ar,
  984. ath6kl_get_hi_item_addr(ar,
  985. HI_ITEM(hi_board_data_initialized)),
  986. (u8 *)&param, 4);
  987. return ret;
  988. }
  989. static int ath6kl_upload_otp(struct ath6kl *ar)
  990. {
  991. u32 address, param;
  992. bool from_hw = false;
  993. int ret;
  994. if (ar->fw_otp == NULL)
  995. return 0;
  996. address = ar->hw.app_load_addr;
  997. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  998. ar->fw_otp_len);
  999. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  1000. ar->fw_otp_len);
  1001. if (ret) {
  1002. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  1003. return ret;
  1004. }
  1005. /* read firmware start address */
  1006. ret = ath6kl_bmi_read(ar,
  1007. ath6kl_get_hi_item_addr(ar,
  1008. HI_ITEM(hi_app_start)),
  1009. (u8 *) &address, sizeof(address));
  1010. if (ret) {
  1011. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  1012. return ret;
  1013. }
  1014. if (ar->hw.app_start_override_addr == 0) {
  1015. ar->hw.app_start_override_addr = address;
  1016. from_hw = true;
  1017. }
  1018. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  1019. from_hw ? " (from hw)" : "",
  1020. ar->hw.app_start_override_addr);
  1021. /* execute the OTP code */
  1022. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  1023. ar->hw.app_start_override_addr);
  1024. param = 0;
  1025. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  1026. return ret;
  1027. }
  1028. static int ath6kl_upload_firmware(struct ath6kl *ar)
  1029. {
  1030. u32 address;
  1031. int ret;
  1032. if (WARN_ON(ar->fw == NULL))
  1033. return 0;
  1034. address = ar->hw.app_load_addr;
  1035. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  1036. address, ar->fw_len);
  1037. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  1038. if (ret) {
  1039. ath6kl_err("Failed to write firmware: %d\n", ret);
  1040. return ret;
  1041. }
  1042. /*
  1043. * Set starting address for firmware
  1044. * Don't need to setup app_start override addr on AR6004
  1045. */
  1046. if (ar->target_type != TARGET_TYPE_AR6004) {
  1047. address = ar->hw.app_start_override_addr;
  1048. ath6kl_bmi_set_app_start(ar, address);
  1049. }
  1050. return ret;
  1051. }
  1052. static int ath6kl_upload_patch(struct ath6kl *ar)
  1053. {
  1054. u32 address, param;
  1055. int ret;
  1056. if (ar->fw_patch == NULL)
  1057. return 0;
  1058. address = ar->hw.dataset_patch_addr;
  1059. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1060. address, ar->fw_patch_len);
  1061. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1062. if (ret) {
  1063. ath6kl_err("Failed to write patch file: %d\n", ret);
  1064. return ret;
  1065. }
  1066. param = address;
  1067. ath6kl_bmi_write(ar,
  1068. ath6kl_get_hi_item_addr(ar,
  1069. HI_ITEM(hi_dset_list_head)),
  1070. (unsigned char *) &param, 4);
  1071. return 0;
  1072. }
  1073. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1074. {
  1075. u32 address, param;
  1076. int ret;
  1077. if (testmode != 2)
  1078. return 0;
  1079. if (ar->fw_testscript == NULL)
  1080. return 0;
  1081. address = ar->hw.testscript_addr;
  1082. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1083. address, ar->fw_testscript_len);
  1084. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1085. ar->fw_testscript_len);
  1086. if (ret) {
  1087. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1088. return ret;
  1089. }
  1090. param = address;
  1091. ath6kl_bmi_write(ar,
  1092. ath6kl_get_hi_item_addr(ar,
  1093. HI_ITEM(hi_ota_testscript)),
  1094. (unsigned char *) &param, 4);
  1095. param = 4096;
  1096. ath6kl_bmi_write(ar,
  1097. ath6kl_get_hi_item_addr(ar,
  1098. HI_ITEM(hi_end_ram_reserve_sz)),
  1099. (unsigned char *) &param, 4);
  1100. param = 1;
  1101. ath6kl_bmi_write(ar,
  1102. ath6kl_get_hi_item_addr(ar,
  1103. HI_ITEM(hi_test_apps_related)),
  1104. (unsigned char *) &param, 4);
  1105. return 0;
  1106. }
  1107. static int ath6kl_init_upload(struct ath6kl *ar)
  1108. {
  1109. u32 param, options, sleep, address;
  1110. int status = 0;
  1111. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1112. ar->target_type != TARGET_TYPE_AR6004)
  1113. return -EINVAL;
  1114. /* temporarily disable system sleep */
  1115. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1116. status = ath6kl_bmi_reg_read(ar, address, &param);
  1117. if (status)
  1118. return status;
  1119. options = param;
  1120. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1121. status = ath6kl_bmi_reg_write(ar, address, param);
  1122. if (status)
  1123. return status;
  1124. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1125. status = ath6kl_bmi_reg_read(ar, address, &param);
  1126. if (status)
  1127. return status;
  1128. sleep = param;
  1129. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1130. status = ath6kl_bmi_reg_write(ar, address, param);
  1131. if (status)
  1132. return status;
  1133. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1134. options, sleep);
  1135. /* program analog PLL register */
  1136. /* no need to control 40/44MHz clock on AR6004 */
  1137. if (ar->target_type != TARGET_TYPE_AR6004) {
  1138. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1139. 0xF9104001);
  1140. if (status)
  1141. return status;
  1142. /* Run at 80/88MHz by default */
  1143. param = SM(CPU_CLOCK_STANDARD, 1);
  1144. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1145. status = ath6kl_bmi_reg_write(ar, address, param);
  1146. if (status)
  1147. return status;
  1148. }
  1149. param = 0;
  1150. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1151. param = SM(LPO_CAL_ENABLE, 1);
  1152. status = ath6kl_bmi_reg_write(ar, address, param);
  1153. if (status)
  1154. return status;
  1155. /* WAR to avoid SDIO CRC err */
  1156. if (ar->version.target_ver == AR6003_HW_2_0_VERSION) {
  1157. ath6kl_err("temporary war to avoid sdio crc error\n");
  1158. param = 0x20;
  1159. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1160. status = ath6kl_bmi_reg_write(ar, address, param);
  1161. if (status)
  1162. return status;
  1163. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1164. status = ath6kl_bmi_reg_write(ar, address, param);
  1165. if (status)
  1166. return status;
  1167. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1168. status = ath6kl_bmi_reg_write(ar, address, param);
  1169. if (status)
  1170. return status;
  1171. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1172. status = ath6kl_bmi_reg_write(ar, address, param);
  1173. if (status)
  1174. return status;
  1175. }
  1176. /* write EEPROM data to Target RAM */
  1177. status = ath6kl_upload_board_file(ar);
  1178. if (status)
  1179. return status;
  1180. /* transfer One time Programmable data */
  1181. status = ath6kl_upload_otp(ar);
  1182. if (status)
  1183. return status;
  1184. /* Download Target firmware */
  1185. status = ath6kl_upload_firmware(ar);
  1186. if (status)
  1187. return status;
  1188. status = ath6kl_upload_patch(ar);
  1189. if (status)
  1190. return status;
  1191. /* Download the test script */
  1192. status = ath6kl_upload_testscript(ar);
  1193. if (status)
  1194. return status;
  1195. /* Restore system sleep */
  1196. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1197. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1198. if (status)
  1199. return status;
  1200. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1201. param = options | 0x20;
  1202. status = ath6kl_bmi_reg_write(ar, address, param);
  1203. if (status)
  1204. return status;
  1205. return status;
  1206. }
  1207. static int ath6kl_init_hw_params(struct ath6kl *ar)
  1208. {
  1209. const struct ath6kl_hw *hw;
  1210. int i;
  1211. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1212. hw = &hw_list[i];
  1213. if (hw->id == ar->version.target_ver)
  1214. break;
  1215. }
  1216. if (i == ARRAY_SIZE(hw_list)) {
  1217. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1218. ar->version.target_ver);
  1219. return -EINVAL;
  1220. }
  1221. ar->hw = *hw;
  1222. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1223. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1224. ar->version.target_ver, ar->target_type,
  1225. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1226. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1227. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1228. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1229. ar->hw.reserved_ram_size);
  1230. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1231. "refclk_hz %d uarttx_pin %d",
  1232. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1233. return 0;
  1234. }
  1235. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1236. {
  1237. switch (type) {
  1238. case ATH6KL_HIF_TYPE_SDIO:
  1239. return "sdio";
  1240. case ATH6KL_HIF_TYPE_USB:
  1241. return "usb";
  1242. }
  1243. return NULL;
  1244. }
  1245. int ath6kl_init_hw_start(struct ath6kl *ar)
  1246. {
  1247. long timeleft;
  1248. int ret, i;
  1249. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1250. ret = ath6kl_hif_power_on(ar);
  1251. if (ret)
  1252. return ret;
  1253. ret = ath6kl_configure_target(ar);
  1254. if (ret)
  1255. goto err_power_off;
  1256. ret = ath6kl_init_upload(ar);
  1257. if (ret)
  1258. goto err_power_off;
  1259. /* Do we need to finish the BMI phase */
  1260. /* FIXME: return error from ath6kl_bmi_done() */
  1261. if (ath6kl_bmi_done(ar)) {
  1262. ret = -EIO;
  1263. goto err_power_off;
  1264. }
  1265. /*
  1266. * The reason we have to wait for the target here is that the
  1267. * driver layer has to init BMI in order to set the host block
  1268. * size.
  1269. */
  1270. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1271. ret = -EIO;
  1272. goto err_power_off;
  1273. }
  1274. if (ath6kl_init_service_ep(ar)) {
  1275. ret = -EIO;
  1276. goto err_cleanup_scatter;
  1277. }
  1278. /* setup credit distribution */
  1279. ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
  1280. /* start HTC */
  1281. ret = ath6kl_htc_start(ar->htc_target);
  1282. if (ret) {
  1283. /* FIXME: call this */
  1284. ath6kl_cookie_cleanup(ar);
  1285. goto err_cleanup_scatter;
  1286. }
  1287. /* Wait for Wmi event to be ready */
  1288. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1289. test_bit(WMI_READY,
  1290. &ar->flag),
  1291. WMI_TIMEOUT);
  1292. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1293. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1294. ath6kl_info("%s %s fw %s api %d%s\n",
  1295. ar->hw.name,
  1296. ath6kl_init_get_hif_name(ar->hif_type),
  1297. ar->wiphy->fw_version,
  1298. ar->fw_api,
  1299. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1300. }
  1301. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1302. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1303. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1304. ret = -EIO;
  1305. goto err_htc_stop;
  1306. }
  1307. if (!timeleft || signal_pending(current)) {
  1308. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1309. ret = -EIO;
  1310. goto err_htc_stop;
  1311. }
  1312. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1313. /* communicate the wmi protocol verision to the target */
  1314. /* FIXME: return error */
  1315. if ((ath6kl_set_host_app_area(ar)) != 0)
  1316. ath6kl_err("unable to set the host app area\n");
  1317. for (i = 0; i < ar->vif_max; i++) {
  1318. ret = ath6kl_target_config_wlan_params(ar, i);
  1319. if (ret)
  1320. goto err_htc_stop;
  1321. }
  1322. ar->state = ATH6KL_STATE_ON;
  1323. return 0;
  1324. err_htc_stop:
  1325. ath6kl_htc_stop(ar->htc_target);
  1326. err_cleanup_scatter:
  1327. ath6kl_hif_cleanup_scatter(ar);
  1328. err_power_off:
  1329. ath6kl_hif_power_off(ar);
  1330. return ret;
  1331. }
  1332. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1333. {
  1334. int ret;
  1335. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1336. ath6kl_htc_stop(ar->htc_target);
  1337. ath6kl_hif_stop(ar);
  1338. ath6kl_bmi_reset(ar);
  1339. ret = ath6kl_hif_power_off(ar);
  1340. if (ret)
  1341. ath6kl_warn("failed to power off hif: %d\n", ret);
  1342. ar->state = ATH6KL_STATE_OFF;
  1343. return 0;
  1344. }
  1345. int ath6kl_core_init(struct ath6kl *ar)
  1346. {
  1347. struct ath6kl_bmi_target_info targ_info;
  1348. struct net_device *ndev;
  1349. int ret = 0, i;
  1350. ar->ath6kl_wq = create_singlethread_workqueue("ath6kl");
  1351. if (!ar->ath6kl_wq)
  1352. return -ENOMEM;
  1353. ret = ath6kl_bmi_init(ar);
  1354. if (ret)
  1355. goto err_wq;
  1356. /*
  1357. * Turn on power to get hardware (target) version and leave power
  1358. * on delibrately as we will boot the hardware anyway within few
  1359. * seconds.
  1360. */
  1361. ret = ath6kl_hif_power_on(ar);
  1362. if (ret)
  1363. goto err_bmi_cleanup;
  1364. ret = ath6kl_bmi_get_target_info(ar, &targ_info);
  1365. if (ret)
  1366. goto err_power_off;
  1367. ar->version.target_ver = le32_to_cpu(targ_info.version);
  1368. ar->target_type = le32_to_cpu(targ_info.type);
  1369. ar->wiphy->hw_version = le32_to_cpu(targ_info.version);
  1370. ret = ath6kl_init_hw_params(ar);
  1371. if (ret)
  1372. goto err_power_off;
  1373. ar->htc_target = ath6kl_htc_create(ar);
  1374. if (!ar->htc_target) {
  1375. ret = -ENOMEM;
  1376. goto err_power_off;
  1377. }
  1378. ret = ath6kl_fetch_firmwares(ar);
  1379. if (ret)
  1380. goto err_htc_cleanup;
  1381. /* FIXME: we should free all firmwares in the error cases below */
  1382. /* Indicate that WMI is enabled (although not ready yet) */
  1383. set_bit(WMI_ENABLED, &ar->flag);
  1384. ar->wmi = ath6kl_wmi_init(ar);
  1385. if (!ar->wmi) {
  1386. ath6kl_err("failed to initialize wmi\n");
  1387. ret = -EIO;
  1388. goto err_htc_cleanup;
  1389. }
  1390. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: got wmi @ 0x%p.\n", __func__, ar->wmi);
  1391. ret = ath6kl_register_ieee80211_hw(ar);
  1392. if (ret)
  1393. goto err_node_cleanup;
  1394. ret = ath6kl_debug_init(ar);
  1395. if (ret) {
  1396. wiphy_unregister(ar->wiphy);
  1397. goto err_node_cleanup;
  1398. }
  1399. for (i = 0; i < ar->vif_max; i++)
  1400. ar->avail_idx_map |= BIT(i);
  1401. rtnl_lock();
  1402. /* Add an initial station interface */
  1403. ndev = ath6kl_interface_add(ar, "wlan%d", NL80211_IFTYPE_STATION, 0,
  1404. INFRA_NETWORK);
  1405. rtnl_unlock();
  1406. if (!ndev) {
  1407. ath6kl_err("Failed to instantiate a network device\n");
  1408. ret = -ENOMEM;
  1409. wiphy_unregister(ar->wiphy);
  1410. goto err_debug_init;
  1411. }
  1412. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n",
  1413. __func__, ndev->name, ndev, ar);
  1414. /* setup access class priority mappings */
  1415. ar->ac_stream_pri_map[WMM_AC_BK] = 0; /* lowest */
  1416. ar->ac_stream_pri_map[WMM_AC_BE] = 1;
  1417. ar->ac_stream_pri_map[WMM_AC_VI] = 2;
  1418. ar->ac_stream_pri_map[WMM_AC_VO] = 3; /* highest */
  1419. /* give our connected endpoints some buffers */
  1420. ath6kl_rx_refill(ar->htc_target, ar->ctrl_ep);
  1421. ath6kl_rx_refill(ar->htc_target, ar->ac2ep_map[WMM_AC_BE]);
  1422. /* allocate some buffers that handle larger AMSDU frames */
  1423. ath6kl_refill_amsdu_rxbufs(ar, ATH6KL_MAX_AMSDU_RX_BUFFERS);
  1424. ath6kl_cookie_init(ar);
  1425. ar->conf_flags = ATH6KL_CONF_IGNORE_ERP_BARKER |
  1426. ATH6KL_CONF_ENABLE_11N | ATH6KL_CONF_ENABLE_TX_BURST;
  1427. if (suspend_cutpower)
  1428. ar->conf_flags |= ATH6KL_CONF_SUSPEND_CUTPOWER;
  1429. ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM |
  1430. WIPHY_FLAG_HAVE_AP_SME |
  1431. WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
  1432. WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD;
  1433. if (test_bit(ATH6KL_FW_CAPABILITY_SCHED_SCAN, ar->fw_capabilities))
  1434. ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
  1435. ar->wiphy->probe_resp_offload =
  1436. NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS |
  1437. NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 |
  1438. NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P |
  1439. NL80211_PROBE_RESP_OFFLOAD_SUPPORT_80211U;
  1440. set_bit(FIRST_BOOT, &ar->flag);
  1441. ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  1442. ret = ath6kl_init_hw_start(ar);
  1443. if (ret) {
  1444. ath6kl_err("Failed to start hardware: %d\n", ret);
  1445. goto err_rxbuf_cleanup;
  1446. }
  1447. /*
  1448. * Set mac address which is received in ready event
  1449. * FIXME: Move to ath6kl_interface_add()
  1450. */
  1451. memcpy(ndev->dev_addr, ar->mac_addr, ETH_ALEN);
  1452. return ret;
  1453. err_rxbuf_cleanup:
  1454. ath6kl_htc_flush_rx_buf(ar->htc_target);
  1455. ath6kl_cleanup_amsdu_rxbufs(ar);
  1456. rtnl_lock();
  1457. ath6kl_cfg80211_vif_cleanup(netdev_priv(ndev));
  1458. rtnl_unlock();
  1459. wiphy_unregister(ar->wiphy);
  1460. err_debug_init:
  1461. ath6kl_debug_cleanup(ar);
  1462. err_node_cleanup:
  1463. ath6kl_wmi_shutdown(ar->wmi);
  1464. clear_bit(WMI_ENABLED, &ar->flag);
  1465. ar->wmi = NULL;
  1466. err_htc_cleanup:
  1467. ath6kl_htc_cleanup(ar->htc_target);
  1468. err_power_off:
  1469. ath6kl_hif_power_off(ar);
  1470. err_bmi_cleanup:
  1471. ath6kl_bmi_cleanup(ar);
  1472. err_wq:
  1473. destroy_workqueue(ar->ath6kl_wq);
  1474. return ret;
  1475. }
  1476. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1477. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1478. {
  1479. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1480. bool discon_issued;
  1481. netif_stop_queue(vif->ndev);
  1482. clear_bit(WLAN_ENABLED, &vif->flags);
  1483. if (wmi_ready) {
  1484. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1485. test_bit(CONNECT_PEND, &vif->flags);
  1486. ath6kl_disconnect(vif);
  1487. del_timer(&vif->disconnect_timer);
  1488. if (discon_issued)
  1489. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1490. (vif->nw_type & AP_NETWORK) ?
  1491. bcast_mac : vif->bssid,
  1492. 0, NULL, 0);
  1493. }
  1494. if (vif->scan_req) {
  1495. cfg80211_scan_done(vif->scan_req, true);
  1496. vif->scan_req = NULL;
  1497. }
  1498. }
  1499. void ath6kl_stop_txrx(struct ath6kl *ar)
  1500. {
  1501. struct ath6kl_vif *vif, *tmp_vif;
  1502. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1503. if (down_interruptible(&ar->sem)) {
  1504. ath6kl_err("down_interruptible failed\n");
  1505. return;
  1506. }
  1507. spin_lock_bh(&ar->list_lock);
  1508. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1509. list_del(&vif->list);
  1510. spin_unlock_bh(&ar->list_lock);
  1511. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1512. rtnl_lock();
  1513. ath6kl_cfg80211_vif_cleanup(vif);
  1514. rtnl_unlock();
  1515. spin_lock_bh(&ar->list_lock);
  1516. }
  1517. spin_unlock_bh(&ar->list_lock);
  1518. clear_bit(WMI_READY, &ar->flag);
  1519. /*
  1520. * After wmi_shudown all WMI events will be dropped. We
  1521. * need to cleanup the buffers allocated in AP mode and
  1522. * give disconnect notification to stack, which usually
  1523. * happens in the disconnect_event. Simulate the disconnect
  1524. * event by calling the function directly. Sometimes
  1525. * disconnect_event will be received when the debug logs
  1526. * are collected.
  1527. */
  1528. ath6kl_wmi_shutdown(ar->wmi);
  1529. clear_bit(WMI_ENABLED, &ar->flag);
  1530. if (ar->htc_target) {
  1531. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1532. ath6kl_htc_stop(ar->htc_target);
  1533. }
  1534. /*
  1535. * Try to reset the device if we can. The driver may have been
  1536. * configure NOT to reset the target during a debug session.
  1537. */
  1538. ath6kl_dbg(ATH6KL_DBG_TRC,
  1539. "attempting to reset target on instance destroy\n");
  1540. ath6kl_reset_device(ar, ar->target_type, true, true);
  1541. clear_bit(WLAN_ENABLED, &ar->flag);
  1542. }