cx23885-dvb.c 30 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "max2165.h"
  39. #include "tda10048.h"
  40. #include "tuner-xc2028.h"
  41. #include "tuner-simple.h"
  42. #include "dib7000p.h"
  43. #include "dibx000_common.h"
  44. #include "zl10353.h"
  45. #include "stv0900.h"
  46. #include "stv0900_reg.h"
  47. #include "stv6110.h"
  48. #include "lnbh24.h"
  49. #include "cx24116.h"
  50. #include "cimax2.h"
  51. #include "lgs8gxx.h"
  52. #include "netup-eeprom.h"
  53. #include "netup-init.h"
  54. #include "lgdt3305.h"
  55. #include "atbm8830.h"
  56. #include "ds3000.h"
  57. #include "cx23885-f300.h"
  58. static unsigned int debug;
  59. #define dprintk(level, fmt, arg...)\
  60. do { if (debug >= level)\
  61. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  62. } while (0)
  63. /* ------------------------------------------------------------------ */
  64. static unsigned int alt_tuner;
  65. module_param(alt_tuner, int, 0644);
  66. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  67. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  68. /* ------------------------------------------------------------------ */
  69. static int dvb_buf_setup(struct videobuf_queue *q,
  70. unsigned int *count, unsigned int *size)
  71. {
  72. struct cx23885_tsport *port = q->priv_data;
  73. port->ts_packet_size = 188 * 4;
  74. port->ts_packet_count = 32;
  75. *size = port->ts_packet_size * port->ts_packet_count;
  76. *count = 32;
  77. return 0;
  78. }
  79. static int dvb_buf_prepare(struct videobuf_queue *q,
  80. struct videobuf_buffer *vb, enum v4l2_field field)
  81. {
  82. struct cx23885_tsport *port = q->priv_data;
  83. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  84. }
  85. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  86. {
  87. struct cx23885_tsport *port = q->priv_data;
  88. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  89. }
  90. static void dvb_buf_release(struct videobuf_queue *q,
  91. struct videobuf_buffer *vb)
  92. {
  93. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  94. }
  95. static struct videobuf_queue_ops dvb_qops = {
  96. .buf_setup = dvb_buf_setup,
  97. .buf_prepare = dvb_buf_prepare,
  98. .buf_queue = dvb_buf_queue,
  99. .buf_release = dvb_buf_release,
  100. };
  101. static struct s5h1409_config hauppauge_generic_config = {
  102. .demod_address = 0x32 >> 1,
  103. .output_mode = S5H1409_SERIAL_OUTPUT,
  104. .gpio = S5H1409_GPIO_ON,
  105. .qam_if = 44000,
  106. .inversion = S5H1409_INVERSION_OFF,
  107. .status_mode = S5H1409_DEMODLOCKING,
  108. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  109. };
  110. static struct tda10048_config hauppauge_hvr1200_config = {
  111. .demod_address = 0x10 >> 1,
  112. .output_mode = TDA10048_SERIAL_OUTPUT,
  113. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  114. .inversion = TDA10048_INVERSION_ON,
  115. .dtv6_if_freq_khz = TDA10048_IF_3300,
  116. .dtv7_if_freq_khz = TDA10048_IF_3800,
  117. .dtv8_if_freq_khz = TDA10048_IF_4300,
  118. .clk_freq_khz = TDA10048_CLK_16000,
  119. };
  120. static struct tda10048_config hauppauge_hvr1210_config = {
  121. .demod_address = 0x10 >> 1,
  122. .output_mode = TDA10048_SERIAL_OUTPUT,
  123. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  124. .inversion = TDA10048_INVERSION_ON,
  125. .dtv6_if_freq_khz = TDA10048_IF_3300,
  126. .dtv7_if_freq_khz = TDA10048_IF_3500,
  127. .dtv8_if_freq_khz = TDA10048_IF_4000,
  128. .clk_freq_khz = TDA10048_CLK_16000,
  129. };
  130. static struct s5h1409_config hauppauge_ezqam_config = {
  131. .demod_address = 0x32 >> 1,
  132. .output_mode = S5H1409_SERIAL_OUTPUT,
  133. .gpio = S5H1409_GPIO_OFF,
  134. .qam_if = 4000,
  135. .inversion = S5H1409_INVERSION_ON,
  136. .status_mode = S5H1409_DEMODLOCKING,
  137. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  138. };
  139. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  140. .demod_address = 0x32 >> 1,
  141. .output_mode = S5H1409_SERIAL_OUTPUT,
  142. .gpio = S5H1409_GPIO_OFF,
  143. .qam_if = 44000,
  144. .inversion = S5H1409_INVERSION_OFF,
  145. .status_mode = S5H1409_DEMODLOCKING,
  146. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  147. };
  148. static struct s5h1409_config hauppauge_hvr1500_config = {
  149. .demod_address = 0x32 >> 1,
  150. .output_mode = S5H1409_SERIAL_OUTPUT,
  151. .gpio = S5H1409_GPIO_OFF,
  152. .inversion = S5H1409_INVERSION_OFF,
  153. .status_mode = S5H1409_DEMODLOCKING,
  154. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  155. };
  156. static struct mt2131_config hauppauge_generic_tunerconfig = {
  157. 0x61
  158. };
  159. static struct lgdt330x_config fusionhdtv_5_express = {
  160. .demod_address = 0x0e,
  161. .demod_chip = LGDT3303,
  162. .serial_mpeg = 0x40,
  163. };
  164. static struct s5h1409_config hauppauge_hvr1500q_config = {
  165. .demod_address = 0x32 >> 1,
  166. .output_mode = S5H1409_SERIAL_OUTPUT,
  167. .gpio = S5H1409_GPIO_ON,
  168. .qam_if = 44000,
  169. .inversion = S5H1409_INVERSION_OFF,
  170. .status_mode = S5H1409_DEMODLOCKING,
  171. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  172. };
  173. static struct s5h1409_config dvico_s5h1409_config = {
  174. .demod_address = 0x32 >> 1,
  175. .output_mode = S5H1409_SERIAL_OUTPUT,
  176. .gpio = S5H1409_GPIO_ON,
  177. .qam_if = 44000,
  178. .inversion = S5H1409_INVERSION_OFF,
  179. .status_mode = S5H1409_DEMODLOCKING,
  180. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  181. };
  182. static struct s5h1411_config dvico_s5h1411_config = {
  183. .output_mode = S5H1411_SERIAL_OUTPUT,
  184. .gpio = S5H1411_GPIO_ON,
  185. .qam_if = S5H1411_IF_44000,
  186. .vsb_if = S5H1411_IF_44000,
  187. .inversion = S5H1411_INVERSION_OFF,
  188. .status_mode = S5H1411_DEMODLOCKING,
  189. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  190. };
  191. static struct s5h1411_config hcw_s5h1411_config = {
  192. .output_mode = S5H1411_SERIAL_OUTPUT,
  193. .gpio = S5H1411_GPIO_OFF,
  194. .vsb_if = S5H1411_IF_44000,
  195. .qam_if = S5H1411_IF_4000,
  196. .inversion = S5H1411_INVERSION_ON,
  197. .status_mode = S5H1411_DEMODLOCKING,
  198. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  199. };
  200. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  201. .i2c_address = 0x61,
  202. .if_khz = 5380,
  203. };
  204. static struct xc5000_config dvico_xc5000_tunerconfig = {
  205. .i2c_address = 0x64,
  206. .if_khz = 5380,
  207. };
  208. static struct tda829x_config tda829x_no_probe = {
  209. .probe_tuner = TDA829X_DONT_PROBE,
  210. };
  211. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  212. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  213. .if_lvl = 6, .rfagc_top = 0x37 },
  214. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  215. .if_lvl = 6, .rfagc_top = 0x37 },
  216. };
  217. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  218. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  219. .if_lvl = 1, .rfagc_top = 0x37, },
  220. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  221. .if_lvl = 1, .rfagc_top = 0x37, },
  222. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  223. .if_lvl = 1, .rfagc_top = 0x37, },
  224. };
  225. static struct tda18271_config hauppauge_tda18271_config = {
  226. .std_map = &hauppauge_tda18271_std_map,
  227. .gate = TDA18271_GATE_ANALOG,
  228. .output_opt = TDA18271_OUTPUT_LT_OFF,
  229. };
  230. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  231. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  232. .gate = TDA18271_GATE_ANALOG,
  233. .output_opt = TDA18271_OUTPUT_LT_OFF,
  234. };
  235. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  236. .gate = TDA18271_GATE_DIGITAL,
  237. .output_opt = TDA18271_OUTPUT_LT_OFF,
  238. };
  239. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  240. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  241. .if_lvl = 1, .rfagc_top = 0x58 },
  242. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  243. .if_lvl = 1, .rfagc_top = 0x58 },
  244. };
  245. static struct tda18271_config hauppauge_hvr127x_config = {
  246. .std_map = &hauppauge_hvr127x_std_map,
  247. .output_opt = TDA18271_OUTPUT_LT_OFF,
  248. };
  249. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  250. .i2c_addr = 0x0e,
  251. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  252. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  253. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  254. .deny_i2c_rptr = 1,
  255. .spectral_inversion = 1,
  256. .qam_if_khz = 4000,
  257. .vsb_if_khz = 3250,
  258. };
  259. static struct dibx000_agc_config xc3028_agc_config = {
  260. BAND_VHF | BAND_UHF, /* band_caps */
  261. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  262. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  263. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  264. * P_agc_nb_est=2, P_agc_write=0
  265. */
  266. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  267. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  268. 712, /* inv_gain */
  269. 21, /* time_stabiliz */
  270. 0, /* alpha_level */
  271. 118, /* thlock */
  272. 0, /* wbd_inv */
  273. 2867, /* wbd_ref */
  274. 0, /* wbd_sel */
  275. 2, /* wbd_alpha */
  276. 0, /* agc1_max */
  277. 0, /* agc1_min */
  278. 39718, /* agc2_max */
  279. 9930, /* agc2_min */
  280. 0, /* agc1_pt1 */
  281. 0, /* agc1_pt2 */
  282. 0, /* agc1_pt3 */
  283. 0, /* agc1_slope1 */
  284. 0, /* agc1_slope2 */
  285. 0, /* agc2_pt1 */
  286. 128, /* agc2_pt2 */
  287. 29, /* agc2_slope1 */
  288. 29, /* agc2_slope2 */
  289. 17, /* alpha_mant */
  290. 27, /* alpha_exp */
  291. 23, /* beta_mant */
  292. 51, /* beta_exp */
  293. 1, /* perform_agc_softsplit */
  294. };
  295. /* PLL Configuration for COFDM BW_MHz = 8.000000
  296. * With external clock = 30.000000 */
  297. static struct dibx000_bandwidth_config xc3028_bw_config = {
  298. 60000, /* internal */
  299. 30000, /* sampling */
  300. 1, /* pll_cfg: prediv */
  301. 8, /* pll_cfg: ratio */
  302. 3, /* pll_cfg: range */
  303. 1, /* pll_cfg: reset */
  304. 0, /* pll_cfg: bypass */
  305. 0, /* misc: refdiv */
  306. 0, /* misc: bypclk_div */
  307. 1, /* misc: IO_CLK_en_core */
  308. 1, /* misc: ADClkSrc */
  309. 0, /* misc: modulo */
  310. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  311. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  312. 20452225, /* timf */
  313. 30000000 /* xtal_hz */
  314. };
  315. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  316. .output_mpeg2_in_188_bytes = 1,
  317. .hostbus_diversity = 1,
  318. .tuner_is_baseband = 0,
  319. .update_lna = NULL,
  320. .agc_config_count = 1,
  321. .agc = &xc3028_agc_config,
  322. .bw = &xc3028_bw_config,
  323. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  324. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  325. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  326. .pwm_freq_div = 0,
  327. .agc_control = NULL,
  328. .spur_protect = 0,
  329. .output_mode = OUTMODE_MPEG2_SERIAL,
  330. };
  331. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  332. .demod_address = 0x0f,
  333. .if2 = 45600,
  334. .no_tuner = 1,
  335. .disable_i2c_gate_ctrl = 1,
  336. };
  337. static struct stv0900_reg stv0900_ts_regs[] = {
  338. { R0900_TSGENERAL, 0x00 },
  339. { R0900_P1_TSSPEED, 0x40 },
  340. { R0900_P2_TSSPEED, 0x40 },
  341. { R0900_P1_TSCFGM, 0xc0 },
  342. { R0900_P2_TSCFGM, 0xc0 },
  343. { R0900_P1_TSCFGH, 0xe0 },
  344. { R0900_P2_TSCFGH, 0xe0 },
  345. { R0900_P1_TSCFGL, 0x20 },
  346. { R0900_P2_TSCFGL, 0x20 },
  347. { 0xffff, 0xff }, /* terminate */
  348. };
  349. static struct stv0900_config netup_stv0900_config = {
  350. .demod_address = 0x68,
  351. .demod_mode = 1, /* dual */
  352. .xtal = 8000000,
  353. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  354. .diseqc_mode = 2,/* 2/3 PWM */
  355. .ts_config_regs = stv0900_ts_regs,
  356. .tun1_maddress = 0,/* 0x60 */
  357. .tun2_maddress = 3,/* 0x63 */
  358. .tun1_adc = 1,/* 1 Vpp */
  359. .tun2_adc = 1,/* 1 Vpp */
  360. };
  361. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  362. .i2c_address = 0x60,
  363. .mclk = 16000000,
  364. .clk_div = 1,
  365. .gain = 8, /* +16 dB - maximum gain */
  366. };
  367. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  368. .i2c_address = 0x63,
  369. .mclk = 16000000,
  370. .clk_div = 1,
  371. .gain = 8, /* +16 dB - maximum gain */
  372. };
  373. static struct cx24116_config tbs_cx24116_config = {
  374. .demod_address = 0x55,
  375. };
  376. static struct ds3000_config tevii_ds3000_config = {
  377. .demod_address = 0x68,
  378. };
  379. static struct cx24116_config dvbworld_cx24116_config = {
  380. .demod_address = 0x05,
  381. };
  382. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  383. .prod = LGS8GXX_PROD_LGS8GL5,
  384. .demod_address = 0x19,
  385. .serial_ts = 0,
  386. .ts_clk_pol = 1,
  387. .ts_clk_gated = 1,
  388. .if_clk_freq = 30400, /* 30.4 MHz */
  389. .if_freq = 5380, /* 5.38 MHz */
  390. .if_neg_center = 1,
  391. .ext_adc = 0,
  392. .adc_signed = 0,
  393. .if_neg_edge = 0,
  394. };
  395. static struct xc5000_config mygica_x8506_xc5000_config = {
  396. .i2c_address = 0x61,
  397. .if_khz = 5380,
  398. };
  399. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  400. struct dvb_frontend_parameters *param)
  401. {
  402. struct cx23885_tsport *port = fe->dvb->priv;
  403. struct cx23885_dev *dev = port->dev;
  404. switch (dev->board) {
  405. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  406. switch (param->u.vsb.modulation) {
  407. case VSB_8:
  408. cx23885_gpio_clear(dev, GPIO_5);
  409. break;
  410. case QAM_64:
  411. case QAM_256:
  412. default:
  413. cx23885_gpio_set(dev, GPIO_5);
  414. break;
  415. }
  416. break;
  417. case CX23885_BOARD_MYGICA_X8506:
  418. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  419. /* Select Digital TV */
  420. cx23885_gpio_set(dev, GPIO_0);
  421. break;
  422. }
  423. return 0;
  424. }
  425. static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
  426. unsigned int cmd, void *parg,
  427. unsigned int stage)
  428. {
  429. int err = 0;
  430. switch (stage) {
  431. case DVB_FE_IOCTL_PRE:
  432. switch (cmd) {
  433. case FE_SET_FRONTEND:
  434. err = cx23885_dvb_set_frontend(fe,
  435. (struct dvb_frontend_parameters *) parg);
  436. break;
  437. }
  438. break;
  439. case DVB_FE_IOCTL_POST:
  440. /* no post-ioctl handling required */
  441. break;
  442. }
  443. return err;
  444. };
  445. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  446. .prod = LGS8GXX_PROD_LGS8G75,
  447. .demod_address = 0x19,
  448. .serial_ts = 0,
  449. .ts_clk_pol = 1,
  450. .ts_clk_gated = 1,
  451. .if_clk_freq = 30400, /* 30.4 MHz */
  452. .if_freq = 6500, /* 6.50 MHz */
  453. .if_neg_center = 1,
  454. .ext_adc = 0,
  455. .adc_signed = 1,
  456. .adc_vpp = 2, /* 1.6 Vpp */
  457. .if_neg_edge = 1,
  458. };
  459. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  460. .i2c_address = 0x61,
  461. .if_khz = 6500,
  462. };
  463. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  464. .prod = ATBM8830_PROD_8830,
  465. .demod_address = 0x44,
  466. .serial_ts = 0,
  467. .ts_sampling_edge = 1,
  468. .ts_clk_gated = 0,
  469. .osc_clk_freq = 30400, /* in kHz */
  470. .if_freq = 0, /* zero IF */
  471. .zif_swap_iq = 1,
  472. .agc_min = 0x2E,
  473. .agc_max = 0xFF,
  474. .agc_hold_loop = 0,
  475. };
  476. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  477. .i2c_address = 0x60,
  478. .osc_clk = 20
  479. };
  480. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  481. .prod = ATBM8830_PROD_8830,
  482. .demod_address = 0x44,
  483. .serial_ts = 1,
  484. .ts_sampling_edge = 1,
  485. .ts_clk_gated = 0,
  486. .osc_clk_freq = 30400, /* in kHz */
  487. .if_freq = 0, /* zero IF */
  488. .zif_swap_iq = 1,
  489. .agc_min = 0x2E,
  490. .agc_max = 0xFF,
  491. .agc_hold_loop = 0,
  492. };
  493. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  494. .i2c_address = 0x60,
  495. .osc_clk = 20
  496. };
  497. static int dvb_register(struct cx23885_tsport *port)
  498. {
  499. struct cx23885_dev *dev = port->dev;
  500. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  501. struct videobuf_dvb_frontend *fe0;
  502. int ret;
  503. /* Get the first frontend */
  504. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  505. if (!fe0)
  506. return -EINVAL;
  507. /* init struct videobuf_dvb */
  508. fe0->dvb.name = dev->name;
  509. /* init frontend */
  510. switch (dev->board) {
  511. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  512. i2c_bus = &dev->i2c_bus[0];
  513. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  514. &hauppauge_generic_config,
  515. &i2c_bus->i2c_adap);
  516. if (fe0->dvb.frontend != NULL) {
  517. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  518. &i2c_bus->i2c_adap,
  519. &hauppauge_generic_tunerconfig, 0);
  520. }
  521. break;
  522. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  523. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  524. i2c_bus = &dev->i2c_bus[0];
  525. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  526. &hauppauge_lgdt3305_config,
  527. &i2c_bus->i2c_adap);
  528. if (fe0->dvb.frontend != NULL) {
  529. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  530. 0x60, &dev->i2c_bus[1].i2c_adap,
  531. &hauppauge_hvr127x_config);
  532. }
  533. break;
  534. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  535. i2c_bus = &dev->i2c_bus[0];
  536. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  537. &hcw_s5h1411_config,
  538. &i2c_bus->i2c_adap);
  539. if (fe0->dvb.frontend != NULL) {
  540. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  541. 0x60, &dev->i2c_bus[1].i2c_adap,
  542. &hauppauge_tda18271_config);
  543. }
  544. break;
  545. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  546. i2c_bus = &dev->i2c_bus[0];
  547. switch (alt_tuner) {
  548. case 1:
  549. fe0->dvb.frontend =
  550. dvb_attach(s5h1409_attach,
  551. &hauppauge_ezqam_config,
  552. &i2c_bus->i2c_adap);
  553. if (fe0->dvb.frontend != NULL) {
  554. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  555. &dev->i2c_bus[1].i2c_adap, 0x42,
  556. &tda829x_no_probe);
  557. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  558. 0x60, &dev->i2c_bus[1].i2c_adap,
  559. &hauppauge_tda18271_config);
  560. }
  561. break;
  562. case 0:
  563. default:
  564. fe0->dvb.frontend =
  565. dvb_attach(s5h1409_attach,
  566. &hauppauge_generic_config,
  567. &i2c_bus->i2c_adap);
  568. if (fe0->dvb.frontend != NULL)
  569. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  570. &i2c_bus->i2c_adap,
  571. &hauppauge_generic_tunerconfig, 0);
  572. break;
  573. }
  574. break;
  575. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  576. i2c_bus = &dev->i2c_bus[0];
  577. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  578. &hauppauge_hvr1800lp_config,
  579. &i2c_bus->i2c_adap);
  580. if (fe0->dvb.frontend != NULL) {
  581. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  582. &i2c_bus->i2c_adap,
  583. &hauppauge_generic_tunerconfig, 0);
  584. }
  585. break;
  586. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  587. i2c_bus = &dev->i2c_bus[0];
  588. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  589. &fusionhdtv_5_express,
  590. &i2c_bus->i2c_adap);
  591. if (fe0->dvb.frontend != NULL) {
  592. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  593. &i2c_bus->i2c_adap, 0x61,
  594. TUNER_LG_TDVS_H06XF);
  595. }
  596. break;
  597. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  598. i2c_bus = &dev->i2c_bus[1];
  599. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  600. &hauppauge_hvr1500q_config,
  601. &dev->i2c_bus[0].i2c_adap);
  602. if (fe0->dvb.frontend != NULL)
  603. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  604. &i2c_bus->i2c_adap,
  605. &hauppauge_hvr1500q_tunerconfig);
  606. break;
  607. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  608. i2c_bus = &dev->i2c_bus[1];
  609. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  610. &hauppauge_hvr1500_config,
  611. &dev->i2c_bus[0].i2c_adap);
  612. if (fe0->dvb.frontend != NULL) {
  613. struct dvb_frontend *fe;
  614. struct xc2028_config cfg = {
  615. .i2c_adap = &i2c_bus->i2c_adap,
  616. .i2c_addr = 0x61,
  617. };
  618. static struct xc2028_ctrl ctl = {
  619. .fname = XC2028_DEFAULT_FIRMWARE,
  620. .max_len = 64,
  621. .demod = XC3028_FE_OREN538,
  622. };
  623. fe = dvb_attach(xc2028_attach,
  624. fe0->dvb.frontend, &cfg);
  625. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  626. fe->ops.tuner_ops.set_config(fe, &ctl);
  627. }
  628. break;
  629. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  630. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  631. i2c_bus = &dev->i2c_bus[0];
  632. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  633. &hauppauge_hvr1200_config,
  634. &i2c_bus->i2c_adap);
  635. if (fe0->dvb.frontend != NULL) {
  636. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  637. &dev->i2c_bus[1].i2c_adap, 0x42,
  638. &tda829x_no_probe);
  639. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  640. 0x60, &dev->i2c_bus[1].i2c_adap,
  641. &hauppauge_hvr1200_tuner_config);
  642. }
  643. break;
  644. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  645. i2c_bus = &dev->i2c_bus[0];
  646. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  647. &hauppauge_hvr1210_config,
  648. &i2c_bus->i2c_adap);
  649. if (fe0->dvb.frontend != NULL) {
  650. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  651. 0x60, &dev->i2c_bus[1].i2c_adap,
  652. &hauppauge_hvr1210_tuner_config);
  653. }
  654. break;
  655. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  656. i2c_bus = &dev->i2c_bus[0];
  657. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  658. &i2c_bus->i2c_adap,
  659. 0x12, &hauppauge_hvr1400_dib7000_config);
  660. if (fe0->dvb.frontend != NULL) {
  661. struct dvb_frontend *fe;
  662. struct xc2028_config cfg = {
  663. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  664. .i2c_addr = 0x64,
  665. };
  666. static struct xc2028_ctrl ctl = {
  667. .fname = XC3028L_DEFAULT_FIRMWARE,
  668. .max_len = 64,
  669. .demod = 5000,
  670. /* This is true for all demods with
  671. v36 firmware? */
  672. .type = XC2028_D2633,
  673. };
  674. fe = dvb_attach(xc2028_attach,
  675. fe0->dvb.frontend, &cfg);
  676. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  677. fe->ops.tuner_ops.set_config(fe, &ctl);
  678. }
  679. break;
  680. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  681. i2c_bus = &dev->i2c_bus[port->nr - 1];
  682. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  683. &dvico_s5h1409_config,
  684. &i2c_bus->i2c_adap);
  685. if (fe0->dvb.frontend == NULL)
  686. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  687. &dvico_s5h1411_config,
  688. &i2c_bus->i2c_adap);
  689. if (fe0->dvb.frontend != NULL)
  690. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  691. &i2c_bus->i2c_adap,
  692. &dvico_xc5000_tunerconfig);
  693. break;
  694. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  695. i2c_bus = &dev->i2c_bus[port->nr - 1];
  696. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  697. &dvico_fusionhdtv_xc3028,
  698. &i2c_bus->i2c_adap);
  699. if (fe0->dvb.frontend != NULL) {
  700. struct dvb_frontend *fe;
  701. struct xc2028_config cfg = {
  702. .i2c_adap = &i2c_bus->i2c_adap,
  703. .i2c_addr = 0x61,
  704. };
  705. static struct xc2028_ctrl ctl = {
  706. .fname = XC2028_DEFAULT_FIRMWARE,
  707. .max_len = 64,
  708. .demod = XC3028_FE_ZARLINK456,
  709. };
  710. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  711. &cfg);
  712. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  713. fe->ops.tuner_ops.set_config(fe, &ctl);
  714. }
  715. break;
  716. }
  717. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  718. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  719. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  720. i2c_bus = &dev->i2c_bus[0];
  721. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  722. &dvico_fusionhdtv_xc3028,
  723. &i2c_bus->i2c_adap);
  724. if (fe0->dvb.frontend != NULL) {
  725. struct dvb_frontend *fe;
  726. struct xc2028_config cfg = {
  727. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  728. .i2c_addr = 0x61,
  729. };
  730. static struct xc2028_ctrl ctl = {
  731. .fname = XC2028_DEFAULT_FIRMWARE,
  732. .max_len = 64,
  733. .demod = XC3028_FE_ZARLINK456,
  734. };
  735. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  736. &cfg);
  737. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  738. fe->ops.tuner_ops.set_config(fe, &ctl);
  739. }
  740. break;
  741. case CX23885_BOARD_TBS_6920:
  742. i2c_bus = &dev->i2c_bus[1];
  743. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  744. &tbs_cx24116_config,
  745. &i2c_bus->i2c_adap);
  746. if (fe0->dvb.frontend != NULL)
  747. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  748. break;
  749. case CX23885_BOARD_TEVII_S470:
  750. i2c_bus = &dev->i2c_bus[1];
  751. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  752. &tevii_ds3000_config,
  753. &i2c_bus->i2c_adap);
  754. if (fe0->dvb.frontend != NULL)
  755. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  756. break;
  757. case CX23885_BOARD_DVBWORLD_2005:
  758. i2c_bus = &dev->i2c_bus[1];
  759. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  760. &dvbworld_cx24116_config,
  761. &i2c_bus->i2c_adap);
  762. break;
  763. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  764. i2c_bus = &dev->i2c_bus[0];
  765. switch (port->nr) {
  766. /* port B */
  767. case 1:
  768. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  769. &netup_stv0900_config,
  770. &i2c_bus->i2c_adap, 0);
  771. if (fe0->dvb.frontend != NULL) {
  772. if (dvb_attach(stv6110_attach,
  773. fe0->dvb.frontend,
  774. &netup_stv6110_tunerconfig_a,
  775. &i2c_bus->i2c_adap)) {
  776. if (!dvb_attach(lnbh24_attach,
  777. fe0->dvb.frontend,
  778. &i2c_bus->i2c_adap,
  779. LNBH24_PCL | LNBH24_TTX,
  780. LNBH24_TEN, 0x09))
  781. printk(KERN_ERR
  782. "No LNBH24 found!\n");
  783. }
  784. }
  785. break;
  786. /* port C */
  787. case 2:
  788. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  789. &netup_stv0900_config,
  790. &i2c_bus->i2c_adap, 1);
  791. if (fe0->dvb.frontend != NULL) {
  792. if (dvb_attach(stv6110_attach,
  793. fe0->dvb.frontend,
  794. &netup_stv6110_tunerconfig_b,
  795. &i2c_bus->i2c_adap)) {
  796. if (!dvb_attach(lnbh24_attach,
  797. fe0->dvb.frontend,
  798. &i2c_bus->i2c_adap,
  799. LNBH24_PCL | LNBH24_TTX,
  800. LNBH24_TEN, 0x0a))
  801. printk(KERN_ERR
  802. "No LNBH24 found!\n");
  803. }
  804. }
  805. break;
  806. }
  807. break;
  808. case CX23885_BOARD_MYGICA_X8506:
  809. i2c_bus = &dev->i2c_bus[0];
  810. i2c_bus2 = &dev->i2c_bus[1];
  811. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  812. &mygica_x8506_lgs8gl5_config,
  813. &i2c_bus->i2c_adap);
  814. if (fe0->dvb.frontend != NULL) {
  815. dvb_attach(xc5000_attach,
  816. fe0->dvb.frontend,
  817. &i2c_bus2->i2c_adap,
  818. &mygica_x8506_xc5000_config);
  819. }
  820. break;
  821. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  822. i2c_bus = &dev->i2c_bus[0];
  823. i2c_bus2 = &dev->i2c_bus[1];
  824. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  825. &magicpro_prohdtve2_lgs8g75_config,
  826. &i2c_bus->i2c_adap);
  827. if (fe0->dvb.frontend != NULL) {
  828. dvb_attach(xc5000_attach,
  829. fe0->dvb.frontend,
  830. &i2c_bus2->i2c_adap,
  831. &magicpro_prohdtve2_xc5000_config);
  832. }
  833. break;
  834. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  835. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  836. i2c_bus = &dev->i2c_bus[0];
  837. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  838. &hcw_s5h1411_config,
  839. &i2c_bus->i2c_adap);
  840. if (fe0->dvb.frontend != NULL)
  841. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  842. 0x60, &dev->i2c_bus[0].i2c_adap,
  843. &hauppauge_tda18271_config);
  844. break;
  845. case CX23885_BOARD_MYGICA_X8558PRO:
  846. switch (port->nr) {
  847. /* port B */
  848. case 1:
  849. i2c_bus = &dev->i2c_bus[0];
  850. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  851. &mygica_x8558pro_atbm8830_cfg1,
  852. &i2c_bus->i2c_adap);
  853. if (fe0->dvb.frontend != NULL) {
  854. dvb_attach(max2165_attach,
  855. fe0->dvb.frontend,
  856. &i2c_bus->i2c_adap,
  857. &mygic_x8558pro_max2165_cfg1);
  858. }
  859. break;
  860. /* port C */
  861. case 2:
  862. i2c_bus = &dev->i2c_bus[1];
  863. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  864. &mygica_x8558pro_atbm8830_cfg2,
  865. &i2c_bus->i2c_adap);
  866. if (fe0->dvb.frontend != NULL) {
  867. dvb_attach(max2165_attach,
  868. fe0->dvb.frontend,
  869. &i2c_bus->i2c_adap,
  870. &mygic_x8558pro_max2165_cfg2);
  871. }
  872. break;
  873. }
  874. break;
  875. default:
  876. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  877. " isn't supported yet\n",
  878. dev->name);
  879. break;
  880. }
  881. if (NULL == fe0->dvb.frontend) {
  882. printk(KERN_ERR "%s: frontend initialization failed\n",
  883. dev->name);
  884. return -1;
  885. }
  886. /* define general-purpose callback pointer */
  887. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  888. /* Put the analog decoder in standby to keep it quiet */
  889. call_all(dev, core, s_power, 0);
  890. if (fe0->dvb.frontend->ops.analog_ops.standby)
  891. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  892. /* register everything */
  893. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  894. &dev->pci->dev, adapter_nr, 0,
  895. cx23885_dvb_fe_ioctl_override);
  896. /* init CI & MAC */
  897. switch (dev->board) {
  898. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  899. static struct netup_card_info cinfo;
  900. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  901. memcpy(port->frontends.adapter.proposed_mac,
  902. cinfo.port[port->nr - 1].mac, 6);
  903. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  904. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  905. port->nr,
  906. port->frontends.adapter.proposed_mac[0],
  907. port->frontends.adapter.proposed_mac[1],
  908. port->frontends.adapter.proposed_mac[2],
  909. port->frontends.adapter.proposed_mac[3],
  910. port->frontends.adapter.proposed_mac[4],
  911. port->frontends.adapter.proposed_mac[5]);
  912. netup_ci_init(port);
  913. break;
  914. }
  915. }
  916. return ret;
  917. }
  918. int cx23885_dvb_register(struct cx23885_tsport *port)
  919. {
  920. struct videobuf_dvb_frontend *fe0;
  921. struct cx23885_dev *dev = port->dev;
  922. int err, i;
  923. /* Here we need to allocate the correct number of frontends,
  924. * as reflected in the cards struct. The reality is that currently
  925. * no cx23885 boards support this - yet. But, if we don't modify this
  926. * code then the second frontend would never be allocated (later)
  927. * and fail with error before the attach in dvb_register().
  928. * Without these changes we risk an OOPS later. The changes here
  929. * are for safety, and should provide a good foundation for the
  930. * future addition of any multi-frontend cx23885 based boards.
  931. */
  932. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  933. port->num_frontends);
  934. for (i = 1; i <= port->num_frontends; i++) {
  935. if (videobuf_dvb_alloc_frontend(
  936. &port->frontends, i) == NULL) {
  937. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  938. return -ENOMEM;
  939. }
  940. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  941. if (!fe0)
  942. err = -EINVAL;
  943. dprintk(1, "%s\n", __func__);
  944. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  945. dev->board,
  946. dev->name,
  947. dev->pci_bus,
  948. dev->pci_slot);
  949. err = -ENODEV;
  950. /* dvb stuff */
  951. /* We have to init the queue for each frontend on a port. */
  952. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  953. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  954. &dev->pci->dev, &port->slock,
  955. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  956. sizeof(struct cx23885_buffer), port);
  957. }
  958. err = dvb_register(port);
  959. if (err != 0)
  960. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  961. __func__, err);
  962. return err;
  963. }
  964. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  965. {
  966. struct videobuf_dvb_frontend *fe0;
  967. /* FIXME: in an error condition where the we have
  968. * an expected number of frontends (attach problem)
  969. * then this might not clean up correctly, if 1
  970. * is invalid.
  971. * This comment only applies to future boards IF they
  972. * implement MFE support.
  973. */
  974. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  975. if (fe0->dvb.frontend)
  976. videobuf_dvb_unregister_bus(&port->frontends);
  977. switch (port->dev->board) {
  978. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  979. netup_ci_exit(port);
  980. break;
  981. }
  982. return 0;
  983. }