nouveau_state.c 27 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin
  3. * Copyright 2008 Stuart Bennett
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. */
  25. #include <linux/swab.h>
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "drm_sarea.h"
  29. #include "drm_crtc_helper.h"
  30. #include <linux/vgaarb.h>
  31. #include "nouveau_drv.h"
  32. #include "nouveau_drm.h"
  33. #include "nv50_display.h"
  34. static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  35. static void nouveau_stub_takedown(struct drm_device *dev) {}
  36. static int nouveau_init_engine_ptrs(struct drm_device *dev)
  37. {
  38. struct drm_nouveau_private *dev_priv = dev->dev_private;
  39. struct nouveau_engine *engine = &dev_priv->engine;
  40. switch (dev_priv->chipset & 0xf0) {
  41. case 0x00:
  42. engine->instmem.init = nv04_instmem_init;
  43. engine->instmem.takedown = nv04_instmem_takedown;
  44. engine->instmem.suspend = nv04_instmem_suspend;
  45. engine->instmem.resume = nv04_instmem_resume;
  46. engine->instmem.populate = nv04_instmem_populate;
  47. engine->instmem.clear = nv04_instmem_clear;
  48. engine->instmem.bind = nv04_instmem_bind;
  49. engine->instmem.unbind = nv04_instmem_unbind;
  50. engine->instmem.prepare_access = nv04_instmem_prepare_access;
  51. engine->instmem.finish_access = nv04_instmem_finish_access;
  52. engine->mc.init = nv04_mc_init;
  53. engine->mc.takedown = nv04_mc_takedown;
  54. engine->timer.init = nv04_timer_init;
  55. engine->timer.read = nv04_timer_read;
  56. engine->timer.takedown = nv04_timer_takedown;
  57. engine->fb.init = nv04_fb_init;
  58. engine->fb.takedown = nv04_fb_takedown;
  59. engine->graph.grclass = nv04_graph_grclass;
  60. engine->graph.init = nv04_graph_init;
  61. engine->graph.takedown = nv04_graph_takedown;
  62. engine->graph.fifo_access = nv04_graph_fifo_access;
  63. engine->graph.channel = nv04_graph_channel;
  64. engine->graph.create_context = nv04_graph_create_context;
  65. engine->graph.destroy_context = nv04_graph_destroy_context;
  66. engine->graph.load_context = nv04_graph_load_context;
  67. engine->graph.unload_context = nv04_graph_unload_context;
  68. engine->fifo.channels = 16;
  69. engine->fifo.init = nv04_fifo_init;
  70. engine->fifo.takedown = nouveau_stub_takedown;
  71. engine->fifo.disable = nv04_fifo_disable;
  72. engine->fifo.enable = nv04_fifo_enable;
  73. engine->fifo.reassign = nv04_fifo_reassign;
  74. engine->fifo.cache_flush = nv04_fifo_cache_flush;
  75. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  76. engine->fifo.channel_id = nv04_fifo_channel_id;
  77. engine->fifo.create_context = nv04_fifo_create_context;
  78. engine->fifo.destroy_context = nv04_fifo_destroy_context;
  79. engine->fifo.load_context = nv04_fifo_load_context;
  80. engine->fifo.unload_context = nv04_fifo_unload_context;
  81. break;
  82. case 0x10:
  83. engine->instmem.init = nv04_instmem_init;
  84. engine->instmem.takedown = nv04_instmem_takedown;
  85. engine->instmem.suspend = nv04_instmem_suspend;
  86. engine->instmem.resume = nv04_instmem_resume;
  87. engine->instmem.populate = nv04_instmem_populate;
  88. engine->instmem.clear = nv04_instmem_clear;
  89. engine->instmem.bind = nv04_instmem_bind;
  90. engine->instmem.unbind = nv04_instmem_unbind;
  91. engine->instmem.prepare_access = nv04_instmem_prepare_access;
  92. engine->instmem.finish_access = nv04_instmem_finish_access;
  93. engine->mc.init = nv04_mc_init;
  94. engine->mc.takedown = nv04_mc_takedown;
  95. engine->timer.init = nv04_timer_init;
  96. engine->timer.read = nv04_timer_read;
  97. engine->timer.takedown = nv04_timer_takedown;
  98. engine->fb.init = nv10_fb_init;
  99. engine->fb.takedown = nv10_fb_takedown;
  100. engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
  101. engine->graph.grclass = nv10_graph_grclass;
  102. engine->graph.init = nv10_graph_init;
  103. engine->graph.takedown = nv10_graph_takedown;
  104. engine->graph.channel = nv10_graph_channel;
  105. engine->graph.create_context = nv10_graph_create_context;
  106. engine->graph.destroy_context = nv10_graph_destroy_context;
  107. engine->graph.fifo_access = nv04_graph_fifo_access;
  108. engine->graph.load_context = nv10_graph_load_context;
  109. engine->graph.unload_context = nv10_graph_unload_context;
  110. engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
  111. engine->fifo.channels = 32;
  112. engine->fifo.init = nv10_fifo_init;
  113. engine->fifo.takedown = nouveau_stub_takedown;
  114. engine->fifo.disable = nv04_fifo_disable;
  115. engine->fifo.enable = nv04_fifo_enable;
  116. engine->fifo.reassign = nv04_fifo_reassign;
  117. engine->fifo.cache_flush = nv04_fifo_cache_flush;
  118. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  119. engine->fifo.channel_id = nv10_fifo_channel_id;
  120. engine->fifo.create_context = nv10_fifo_create_context;
  121. engine->fifo.destroy_context = nv10_fifo_destroy_context;
  122. engine->fifo.load_context = nv10_fifo_load_context;
  123. engine->fifo.unload_context = nv10_fifo_unload_context;
  124. break;
  125. case 0x20:
  126. engine->instmem.init = nv04_instmem_init;
  127. engine->instmem.takedown = nv04_instmem_takedown;
  128. engine->instmem.suspend = nv04_instmem_suspend;
  129. engine->instmem.resume = nv04_instmem_resume;
  130. engine->instmem.populate = nv04_instmem_populate;
  131. engine->instmem.clear = nv04_instmem_clear;
  132. engine->instmem.bind = nv04_instmem_bind;
  133. engine->instmem.unbind = nv04_instmem_unbind;
  134. engine->instmem.prepare_access = nv04_instmem_prepare_access;
  135. engine->instmem.finish_access = nv04_instmem_finish_access;
  136. engine->mc.init = nv04_mc_init;
  137. engine->mc.takedown = nv04_mc_takedown;
  138. engine->timer.init = nv04_timer_init;
  139. engine->timer.read = nv04_timer_read;
  140. engine->timer.takedown = nv04_timer_takedown;
  141. engine->fb.init = nv10_fb_init;
  142. engine->fb.takedown = nv10_fb_takedown;
  143. engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
  144. engine->graph.grclass = nv20_graph_grclass;
  145. engine->graph.init = nv20_graph_init;
  146. engine->graph.takedown = nv20_graph_takedown;
  147. engine->graph.channel = nv10_graph_channel;
  148. engine->graph.create_context = nv20_graph_create_context;
  149. engine->graph.destroy_context = nv20_graph_destroy_context;
  150. engine->graph.fifo_access = nv04_graph_fifo_access;
  151. engine->graph.load_context = nv20_graph_load_context;
  152. engine->graph.unload_context = nv20_graph_unload_context;
  153. engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
  154. engine->fifo.channels = 32;
  155. engine->fifo.init = nv10_fifo_init;
  156. engine->fifo.takedown = nouveau_stub_takedown;
  157. engine->fifo.disable = nv04_fifo_disable;
  158. engine->fifo.enable = nv04_fifo_enable;
  159. engine->fifo.reassign = nv04_fifo_reassign;
  160. engine->fifo.cache_flush = nv04_fifo_cache_flush;
  161. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  162. engine->fifo.channel_id = nv10_fifo_channel_id;
  163. engine->fifo.create_context = nv10_fifo_create_context;
  164. engine->fifo.destroy_context = nv10_fifo_destroy_context;
  165. engine->fifo.load_context = nv10_fifo_load_context;
  166. engine->fifo.unload_context = nv10_fifo_unload_context;
  167. break;
  168. case 0x30:
  169. engine->instmem.init = nv04_instmem_init;
  170. engine->instmem.takedown = nv04_instmem_takedown;
  171. engine->instmem.suspend = nv04_instmem_suspend;
  172. engine->instmem.resume = nv04_instmem_resume;
  173. engine->instmem.populate = nv04_instmem_populate;
  174. engine->instmem.clear = nv04_instmem_clear;
  175. engine->instmem.bind = nv04_instmem_bind;
  176. engine->instmem.unbind = nv04_instmem_unbind;
  177. engine->instmem.prepare_access = nv04_instmem_prepare_access;
  178. engine->instmem.finish_access = nv04_instmem_finish_access;
  179. engine->mc.init = nv04_mc_init;
  180. engine->mc.takedown = nv04_mc_takedown;
  181. engine->timer.init = nv04_timer_init;
  182. engine->timer.read = nv04_timer_read;
  183. engine->timer.takedown = nv04_timer_takedown;
  184. engine->fb.init = nv10_fb_init;
  185. engine->fb.takedown = nv10_fb_takedown;
  186. engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
  187. engine->graph.grclass = nv30_graph_grclass;
  188. engine->graph.init = nv30_graph_init;
  189. engine->graph.takedown = nv20_graph_takedown;
  190. engine->graph.fifo_access = nv04_graph_fifo_access;
  191. engine->graph.channel = nv10_graph_channel;
  192. engine->graph.create_context = nv20_graph_create_context;
  193. engine->graph.destroy_context = nv20_graph_destroy_context;
  194. engine->graph.load_context = nv20_graph_load_context;
  195. engine->graph.unload_context = nv20_graph_unload_context;
  196. engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
  197. engine->fifo.channels = 32;
  198. engine->fifo.init = nv10_fifo_init;
  199. engine->fifo.takedown = nouveau_stub_takedown;
  200. engine->fifo.disable = nv04_fifo_disable;
  201. engine->fifo.enable = nv04_fifo_enable;
  202. engine->fifo.reassign = nv04_fifo_reassign;
  203. engine->fifo.cache_flush = nv04_fifo_cache_flush;
  204. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  205. engine->fifo.channel_id = nv10_fifo_channel_id;
  206. engine->fifo.create_context = nv10_fifo_create_context;
  207. engine->fifo.destroy_context = nv10_fifo_destroy_context;
  208. engine->fifo.load_context = nv10_fifo_load_context;
  209. engine->fifo.unload_context = nv10_fifo_unload_context;
  210. break;
  211. case 0x40:
  212. case 0x60:
  213. engine->instmem.init = nv04_instmem_init;
  214. engine->instmem.takedown = nv04_instmem_takedown;
  215. engine->instmem.suspend = nv04_instmem_suspend;
  216. engine->instmem.resume = nv04_instmem_resume;
  217. engine->instmem.populate = nv04_instmem_populate;
  218. engine->instmem.clear = nv04_instmem_clear;
  219. engine->instmem.bind = nv04_instmem_bind;
  220. engine->instmem.unbind = nv04_instmem_unbind;
  221. engine->instmem.prepare_access = nv04_instmem_prepare_access;
  222. engine->instmem.finish_access = nv04_instmem_finish_access;
  223. engine->mc.init = nv40_mc_init;
  224. engine->mc.takedown = nv40_mc_takedown;
  225. engine->timer.init = nv04_timer_init;
  226. engine->timer.read = nv04_timer_read;
  227. engine->timer.takedown = nv04_timer_takedown;
  228. engine->fb.init = nv40_fb_init;
  229. engine->fb.takedown = nv40_fb_takedown;
  230. engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
  231. engine->graph.grclass = nv40_graph_grclass;
  232. engine->graph.init = nv40_graph_init;
  233. engine->graph.takedown = nv40_graph_takedown;
  234. engine->graph.fifo_access = nv04_graph_fifo_access;
  235. engine->graph.channel = nv40_graph_channel;
  236. engine->graph.create_context = nv40_graph_create_context;
  237. engine->graph.destroy_context = nv40_graph_destroy_context;
  238. engine->graph.load_context = nv40_graph_load_context;
  239. engine->graph.unload_context = nv40_graph_unload_context;
  240. engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
  241. engine->fifo.channels = 32;
  242. engine->fifo.init = nv40_fifo_init;
  243. engine->fifo.takedown = nouveau_stub_takedown;
  244. engine->fifo.disable = nv04_fifo_disable;
  245. engine->fifo.enable = nv04_fifo_enable;
  246. engine->fifo.reassign = nv04_fifo_reassign;
  247. engine->fifo.cache_flush = nv04_fifo_cache_flush;
  248. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  249. engine->fifo.channel_id = nv10_fifo_channel_id;
  250. engine->fifo.create_context = nv40_fifo_create_context;
  251. engine->fifo.destroy_context = nv40_fifo_destroy_context;
  252. engine->fifo.load_context = nv40_fifo_load_context;
  253. engine->fifo.unload_context = nv40_fifo_unload_context;
  254. break;
  255. case 0x50:
  256. case 0x80: /* gotta love NVIDIA's consistency.. */
  257. case 0x90:
  258. case 0xA0:
  259. engine->instmem.init = nv50_instmem_init;
  260. engine->instmem.takedown = nv50_instmem_takedown;
  261. engine->instmem.suspend = nv50_instmem_suspend;
  262. engine->instmem.resume = nv50_instmem_resume;
  263. engine->instmem.populate = nv50_instmem_populate;
  264. engine->instmem.clear = nv50_instmem_clear;
  265. engine->instmem.bind = nv50_instmem_bind;
  266. engine->instmem.unbind = nv50_instmem_unbind;
  267. engine->instmem.prepare_access = nv50_instmem_prepare_access;
  268. engine->instmem.finish_access = nv50_instmem_finish_access;
  269. engine->mc.init = nv50_mc_init;
  270. engine->mc.takedown = nv50_mc_takedown;
  271. engine->timer.init = nv04_timer_init;
  272. engine->timer.read = nv04_timer_read;
  273. engine->timer.takedown = nv04_timer_takedown;
  274. engine->fb.init = nouveau_stub_init;
  275. engine->fb.takedown = nouveau_stub_takedown;
  276. engine->graph.grclass = nv50_graph_grclass;
  277. engine->graph.init = nv50_graph_init;
  278. engine->graph.takedown = nv50_graph_takedown;
  279. engine->graph.fifo_access = nv50_graph_fifo_access;
  280. engine->graph.channel = nv50_graph_channel;
  281. engine->graph.create_context = nv50_graph_create_context;
  282. engine->graph.destroy_context = nv50_graph_destroy_context;
  283. engine->graph.load_context = nv50_graph_load_context;
  284. engine->graph.unload_context = nv50_graph_unload_context;
  285. engine->fifo.channels = 128;
  286. engine->fifo.init = nv50_fifo_init;
  287. engine->fifo.takedown = nv50_fifo_takedown;
  288. engine->fifo.disable = nv04_fifo_disable;
  289. engine->fifo.enable = nv04_fifo_enable;
  290. engine->fifo.reassign = nv04_fifo_reassign;
  291. engine->fifo.channel_id = nv50_fifo_channel_id;
  292. engine->fifo.create_context = nv50_fifo_create_context;
  293. engine->fifo.destroy_context = nv50_fifo_destroy_context;
  294. engine->fifo.load_context = nv50_fifo_load_context;
  295. engine->fifo.unload_context = nv50_fifo_unload_context;
  296. break;
  297. default:
  298. NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
  299. return 1;
  300. }
  301. return 0;
  302. }
  303. static unsigned int
  304. nouveau_vga_set_decode(void *priv, bool state)
  305. {
  306. struct drm_device *dev = priv;
  307. struct drm_nouveau_private *dev_priv = dev->dev_private;
  308. if (dev_priv->chipset >= 0x40)
  309. nv_wr32(dev, 0x88054, state);
  310. else
  311. nv_wr32(dev, 0x1854, state);
  312. if (state)
  313. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  314. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  315. else
  316. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  317. }
  318. static int
  319. nouveau_card_init_channel(struct drm_device *dev)
  320. {
  321. struct drm_nouveau_private *dev_priv = dev->dev_private;
  322. struct nouveau_gpuobj *gpuobj;
  323. int ret;
  324. ret = nouveau_channel_alloc(dev, &dev_priv->channel,
  325. (struct drm_file *)-2,
  326. NvDmaFB, NvDmaTT);
  327. if (ret)
  328. return ret;
  329. gpuobj = NULL;
  330. ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
  331. 0, nouveau_mem_fb_amount(dev),
  332. NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
  333. &gpuobj);
  334. if (ret)
  335. goto out_err;
  336. ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
  337. gpuobj, NULL);
  338. if (ret)
  339. goto out_err;
  340. gpuobj = NULL;
  341. ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
  342. dev_priv->gart_info.aper_size,
  343. NV_DMA_ACCESS_RW, &gpuobj, NULL);
  344. if (ret)
  345. goto out_err;
  346. ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
  347. gpuobj, NULL);
  348. if (ret)
  349. goto out_err;
  350. return 0;
  351. out_err:
  352. nouveau_gpuobj_del(dev, &gpuobj);
  353. nouveau_channel_free(dev_priv->channel);
  354. dev_priv->channel = NULL;
  355. return ret;
  356. }
  357. int
  358. nouveau_card_init(struct drm_device *dev)
  359. {
  360. struct drm_nouveau_private *dev_priv = dev->dev_private;
  361. struct nouveau_engine *engine;
  362. int ret;
  363. NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
  364. if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
  365. return 0;
  366. vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
  367. /* Initialise internal driver API hooks */
  368. ret = nouveau_init_engine_ptrs(dev);
  369. if (ret)
  370. goto out;
  371. engine = &dev_priv->engine;
  372. dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
  373. /* Parse BIOS tables / Run init tables if card not POSTed */
  374. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  375. ret = nouveau_bios_init(dev);
  376. if (ret)
  377. goto out;
  378. }
  379. ret = nouveau_gpuobj_early_init(dev);
  380. if (ret)
  381. goto out_bios;
  382. /* Initialise instance memory, must happen before mem_init so we
  383. * know exactly how much VRAM we're able to use for "normal"
  384. * purposes.
  385. */
  386. ret = engine->instmem.init(dev);
  387. if (ret)
  388. goto out_gpuobj_early;
  389. /* Setup the memory manager */
  390. ret = nouveau_mem_init(dev);
  391. if (ret)
  392. goto out_instmem;
  393. ret = nouveau_gpuobj_init(dev);
  394. if (ret)
  395. goto out_mem;
  396. /* PMC */
  397. ret = engine->mc.init(dev);
  398. if (ret)
  399. goto out_gpuobj;
  400. /* PTIMER */
  401. ret = engine->timer.init(dev);
  402. if (ret)
  403. goto out_mc;
  404. /* PFB */
  405. ret = engine->fb.init(dev);
  406. if (ret)
  407. goto out_timer;
  408. if (nouveau_noaccel)
  409. engine->graph.accel_blocked = true;
  410. else {
  411. /* PGRAPH */
  412. ret = engine->graph.init(dev);
  413. if (ret)
  414. goto out_fb;
  415. /* PFIFO */
  416. ret = engine->fifo.init(dev);
  417. if (ret)
  418. goto out_graph;
  419. }
  420. /* this call irq_preinstall, register irq handler and
  421. * call irq_postinstall
  422. */
  423. ret = drm_irq_install(dev);
  424. if (ret)
  425. goto out_fifo;
  426. ret = drm_vblank_init(dev, 0);
  427. if (ret)
  428. goto out_irq;
  429. /* what about PVIDEO/PCRTC/PRAMDAC etc? */
  430. if (!engine->graph.accel_blocked) {
  431. ret = nouveau_card_init_channel(dev);
  432. if (ret)
  433. goto out_irq;
  434. }
  435. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  436. if (dev_priv->card_type >= NV_50)
  437. ret = nv50_display_create(dev);
  438. else
  439. ret = nv04_display_create(dev);
  440. if (ret)
  441. goto out_irq;
  442. }
  443. ret = nouveau_backlight_init(dev);
  444. if (ret)
  445. NV_ERROR(dev, "Error %d registering backlight\n", ret);
  446. dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
  447. if (drm_core_check_feature(dev, DRIVER_MODESET))
  448. drm_helper_initial_config(dev);
  449. return 0;
  450. out_irq:
  451. drm_irq_uninstall(dev);
  452. out_fifo:
  453. if (!nouveau_noaccel)
  454. engine->fifo.takedown(dev);
  455. out_graph:
  456. if (!nouveau_noaccel)
  457. engine->graph.takedown(dev);
  458. out_fb:
  459. engine->fb.takedown(dev);
  460. out_timer:
  461. engine->timer.takedown(dev);
  462. out_mc:
  463. engine->mc.takedown(dev);
  464. out_gpuobj:
  465. nouveau_gpuobj_takedown(dev);
  466. out_mem:
  467. nouveau_mem_close(dev);
  468. out_instmem:
  469. engine->instmem.takedown(dev);
  470. out_gpuobj_early:
  471. nouveau_gpuobj_late_takedown(dev);
  472. out_bios:
  473. nouveau_bios_takedown(dev);
  474. out:
  475. vga_client_register(dev->pdev, NULL, NULL, NULL);
  476. return ret;
  477. }
  478. static void nouveau_card_takedown(struct drm_device *dev)
  479. {
  480. struct drm_nouveau_private *dev_priv = dev->dev_private;
  481. struct nouveau_engine *engine = &dev_priv->engine;
  482. NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
  483. if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
  484. nouveau_backlight_exit(dev);
  485. if (dev_priv->channel) {
  486. nouveau_channel_free(dev_priv->channel);
  487. dev_priv->channel = NULL;
  488. }
  489. if (!nouveau_noaccel) {
  490. engine->fifo.takedown(dev);
  491. engine->graph.takedown(dev);
  492. }
  493. engine->fb.takedown(dev);
  494. engine->timer.takedown(dev);
  495. engine->mc.takedown(dev);
  496. mutex_lock(&dev->struct_mutex);
  497. ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  498. ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
  499. mutex_unlock(&dev->struct_mutex);
  500. nouveau_sgdma_takedown(dev);
  501. nouveau_gpuobj_takedown(dev);
  502. nouveau_mem_close(dev);
  503. engine->instmem.takedown(dev);
  504. if (drm_core_check_feature(dev, DRIVER_MODESET))
  505. drm_irq_uninstall(dev);
  506. nouveau_gpuobj_late_takedown(dev);
  507. nouveau_bios_takedown(dev);
  508. vga_client_register(dev->pdev, NULL, NULL, NULL);
  509. dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
  510. }
  511. }
  512. /* here a client dies, release the stuff that was allocated for its
  513. * file_priv */
  514. void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
  515. {
  516. nouveau_channel_cleanup(dev, file_priv);
  517. }
  518. /* first module load, setup the mmio/fb mapping */
  519. /* KMS: we need mmio at load time, not when the first drm client opens. */
  520. int nouveau_firstopen(struct drm_device *dev)
  521. {
  522. return 0;
  523. }
  524. /* if we have an OF card, copy vbios to RAMIN */
  525. static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
  526. {
  527. #if defined(__powerpc__)
  528. int size, i;
  529. const uint32_t *bios;
  530. struct device_node *dn = pci_device_to_OF_node(dev->pdev);
  531. if (!dn) {
  532. NV_INFO(dev, "Unable to get the OF node\n");
  533. return;
  534. }
  535. bios = of_get_property(dn, "NVDA,BMP", &size);
  536. if (bios) {
  537. for (i = 0; i < size; i += 4)
  538. nv_wi32(dev, i, bios[i/4]);
  539. NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
  540. } else {
  541. NV_INFO(dev, "Unable to get the OF bios\n");
  542. }
  543. #endif
  544. }
  545. int nouveau_load(struct drm_device *dev, unsigned long flags)
  546. {
  547. struct drm_nouveau_private *dev_priv;
  548. uint32_t reg0;
  549. resource_size_t mmio_start_offs;
  550. dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
  551. if (!dev_priv)
  552. return -ENOMEM;
  553. dev->dev_private = dev_priv;
  554. dev_priv->dev = dev;
  555. dev_priv->flags = flags & NOUVEAU_FLAGS;
  556. dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
  557. NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
  558. dev->pci_vendor, dev->pci_device, dev->pdev->class);
  559. dev_priv->acpi_dsm = nouveau_dsm_probe(dev);
  560. if (dev_priv->acpi_dsm)
  561. nouveau_hybrid_setup(dev);
  562. dev_priv->wq = create_workqueue("nouveau");
  563. if (!dev_priv->wq)
  564. return -EINVAL;
  565. /* resource 0 is mmio regs */
  566. /* resource 1 is linear FB */
  567. /* resource 2 is RAMIN (mmio regs + 0x1000000) */
  568. /* resource 6 is bios */
  569. /* map the mmio regs */
  570. mmio_start_offs = pci_resource_start(dev->pdev, 0);
  571. dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
  572. if (!dev_priv->mmio) {
  573. NV_ERROR(dev, "Unable to initialize the mmio mapping. "
  574. "Please report your setup to " DRIVER_EMAIL "\n");
  575. return -EINVAL;
  576. }
  577. NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
  578. (unsigned long long)mmio_start_offs);
  579. #ifdef __BIG_ENDIAN
  580. /* Put the card in BE mode if it's not */
  581. if (nv_rd32(dev, NV03_PMC_BOOT_1))
  582. nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
  583. DRM_MEMORYBARRIER();
  584. #endif
  585. /* Time to determine the card architecture */
  586. reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
  587. /* We're dealing with >=NV10 */
  588. if ((reg0 & 0x0f000000) > 0) {
  589. /* Bit 27-20 contain the architecture in hex */
  590. dev_priv->chipset = (reg0 & 0xff00000) >> 20;
  591. /* NV04 or NV05 */
  592. } else if ((reg0 & 0xff00fff0) == 0x20004000) {
  593. if (reg0 & 0x00f00000)
  594. dev_priv->chipset = 0x05;
  595. else
  596. dev_priv->chipset = 0x04;
  597. } else
  598. dev_priv->chipset = 0xff;
  599. switch (dev_priv->chipset & 0xf0) {
  600. case 0x00:
  601. case 0x10:
  602. case 0x20:
  603. case 0x30:
  604. dev_priv->card_type = dev_priv->chipset & 0xf0;
  605. break;
  606. case 0x40:
  607. case 0x60:
  608. dev_priv->card_type = NV_40;
  609. break;
  610. case 0x50:
  611. case 0x80:
  612. case 0x90:
  613. case 0xa0:
  614. dev_priv->card_type = NV_50;
  615. break;
  616. default:
  617. NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
  618. return -EINVAL;
  619. }
  620. NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
  621. dev_priv->card_type, reg0);
  622. /* map larger RAMIN aperture on NV40 cards */
  623. dev_priv->ramin = NULL;
  624. if (dev_priv->card_type >= NV_40) {
  625. int ramin_bar = 2;
  626. if (pci_resource_len(dev->pdev, ramin_bar) == 0)
  627. ramin_bar = 3;
  628. dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
  629. dev_priv->ramin = ioremap(
  630. pci_resource_start(dev->pdev, ramin_bar),
  631. dev_priv->ramin_size);
  632. if (!dev_priv->ramin) {
  633. NV_ERROR(dev, "Failed to init RAMIN mapping, "
  634. "limited instance memory available\n");
  635. }
  636. }
  637. /* On older cards (or if the above failed), create a map covering
  638. * the BAR0 PRAMIN aperture */
  639. if (!dev_priv->ramin) {
  640. dev_priv->ramin_size = 1 * 1024 * 1024;
  641. dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
  642. dev_priv->ramin_size);
  643. if (!dev_priv->ramin) {
  644. NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
  645. return -ENOMEM;
  646. }
  647. }
  648. nouveau_OF_copy_vbios_to_ramin(dev);
  649. /* Special flags */
  650. if (dev->pci_device == 0x01a0)
  651. dev_priv->flags |= NV_NFORCE;
  652. else if (dev->pci_device == 0x01f0)
  653. dev_priv->flags |= NV_NFORCE2;
  654. /* For kernel modesetting, init card now and bring up fbcon */
  655. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  656. int ret = nouveau_card_init(dev);
  657. if (ret)
  658. return ret;
  659. }
  660. return 0;
  661. }
  662. static void nouveau_close(struct drm_device *dev)
  663. {
  664. struct drm_nouveau_private *dev_priv = dev->dev_private;
  665. /* In the case of an error dev_priv may not be allocated yet */
  666. if (dev_priv)
  667. nouveau_card_takedown(dev);
  668. }
  669. /* KMS: we need mmio at load time, not when the first drm client opens. */
  670. void nouveau_lastclose(struct drm_device *dev)
  671. {
  672. if (drm_core_check_feature(dev, DRIVER_MODESET))
  673. return;
  674. nouveau_close(dev);
  675. }
  676. int nouveau_unload(struct drm_device *dev)
  677. {
  678. struct drm_nouveau_private *dev_priv = dev->dev_private;
  679. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  680. if (dev_priv->card_type >= NV_50)
  681. nv50_display_destroy(dev);
  682. else
  683. nv04_display_destroy(dev);
  684. nouveau_close(dev);
  685. }
  686. iounmap(dev_priv->mmio);
  687. iounmap(dev_priv->ramin);
  688. kfree(dev_priv);
  689. dev->dev_private = NULL;
  690. return 0;
  691. }
  692. int
  693. nouveau_ioctl_card_init(struct drm_device *dev, void *data,
  694. struct drm_file *file_priv)
  695. {
  696. return nouveau_card_init(dev);
  697. }
  698. int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
  699. struct drm_file *file_priv)
  700. {
  701. struct drm_nouveau_private *dev_priv = dev->dev_private;
  702. struct drm_nouveau_getparam *getparam = data;
  703. NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
  704. switch (getparam->param) {
  705. case NOUVEAU_GETPARAM_CHIPSET_ID:
  706. getparam->value = dev_priv->chipset;
  707. break;
  708. case NOUVEAU_GETPARAM_PCI_VENDOR:
  709. getparam->value = dev->pci_vendor;
  710. break;
  711. case NOUVEAU_GETPARAM_PCI_DEVICE:
  712. getparam->value = dev->pci_device;
  713. break;
  714. case NOUVEAU_GETPARAM_BUS_TYPE:
  715. if (drm_device_is_agp(dev))
  716. getparam->value = NV_AGP;
  717. else if (drm_device_is_pcie(dev))
  718. getparam->value = NV_PCIE;
  719. else
  720. getparam->value = NV_PCI;
  721. break;
  722. case NOUVEAU_GETPARAM_FB_PHYSICAL:
  723. getparam->value = dev_priv->fb_phys;
  724. break;
  725. case NOUVEAU_GETPARAM_AGP_PHYSICAL:
  726. getparam->value = dev_priv->gart_info.aper_base;
  727. break;
  728. case NOUVEAU_GETPARAM_PCI_PHYSICAL:
  729. if (dev->sg) {
  730. getparam->value = (unsigned long)dev->sg->virtual;
  731. } else {
  732. NV_ERROR(dev, "Requested PCIGART address, "
  733. "while no PCIGART was created\n");
  734. return -EINVAL;
  735. }
  736. break;
  737. case NOUVEAU_GETPARAM_FB_SIZE:
  738. getparam->value = dev_priv->fb_available_size;
  739. break;
  740. case NOUVEAU_GETPARAM_AGP_SIZE:
  741. getparam->value = dev_priv->gart_info.aper_size;
  742. break;
  743. case NOUVEAU_GETPARAM_VM_VRAM_BASE:
  744. getparam->value = dev_priv->vm_vram_base;
  745. break;
  746. case NOUVEAU_GETPARAM_GRAPH_UNITS:
  747. /* NV40 and NV50 versions are quite different, but register
  748. * address is the same. User is supposed to know the card
  749. * family anyway... */
  750. if (dev_priv->chipset >= 0x40) {
  751. getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
  752. break;
  753. }
  754. /* FALLTHRU */
  755. default:
  756. NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
  757. return -EINVAL;
  758. }
  759. return 0;
  760. }
  761. int
  762. nouveau_ioctl_setparam(struct drm_device *dev, void *data,
  763. struct drm_file *file_priv)
  764. {
  765. struct drm_nouveau_setparam *setparam = data;
  766. NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
  767. switch (setparam->param) {
  768. default:
  769. NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
  770. return -EINVAL;
  771. }
  772. return 0;
  773. }
  774. /* Wait until (value(reg) & mask) == val, up until timeout has hit */
  775. bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
  776. uint32_t reg, uint32_t mask, uint32_t val)
  777. {
  778. struct drm_nouveau_private *dev_priv = dev->dev_private;
  779. struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  780. uint64_t start = ptimer->read(dev);
  781. do {
  782. if ((nv_rd32(dev, reg) & mask) == val)
  783. return true;
  784. } while (ptimer->read(dev) - start < timeout);
  785. return false;
  786. }
  787. /* Waits for PGRAPH to go completely idle */
  788. bool nouveau_wait_for_idle(struct drm_device *dev)
  789. {
  790. if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
  791. NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
  792. nv_rd32(dev, NV04_PGRAPH_STATUS));
  793. return false;
  794. }
  795. return true;
  796. }