i915_drv.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600
  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include <linux/console.h>
  35. #include "drm_crtc_helper.h"
  36. static int i915_modeset = -1;
  37. module_param_named(modeset, i915_modeset, int, 0400);
  38. unsigned int i915_fbpercrtc = 0;
  39. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  40. unsigned int i915_powersave = 1;
  41. module_param_named(powersave, i915_powersave, int, 0400);
  42. unsigned int i915_lvds_downclock = 0;
  43. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  44. static struct drm_driver driver;
  45. #define INTEL_VGA_DEVICE(id, info) { \
  46. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  47. .class_mask = 0xffff00, \
  48. .vendor = 0x8086, \
  49. .device = id, \
  50. .subvendor = PCI_ANY_ID, \
  51. .subdevice = PCI_ANY_ID, \
  52. .driver_data = (unsigned long) info }
  53. const static struct intel_device_info intel_i830_info = {
  54. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  55. };
  56. const static struct intel_device_info intel_845g_info = {
  57. .is_i8xx = 1,
  58. };
  59. const static struct intel_device_info intel_i85x_info = {
  60. .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
  61. };
  62. const static struct intel_device_info intel_i865g_info = {
  63. .is_i8xx = 1,
  64. };
  65. const static struct intel_device_info intel_i915g_info = {
  66. .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
  67. };
  68. const static struct intel_device_info intel_i915gm_info = {
  69. .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  70. .cursor_needs_physical = 1,
  71. };
  72. const static struct intel_device_info intel_i945g_info = {
  73. .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
  74. };
  75. const static struct intel_device_info intel_i945gm_info = {
  76. .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
  77. .has_hotplug = 1, .cursor_needs_physical = 1,
  78. };
  79. const static struct intel_device_info intel_i965g_info = {
  80. .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
  81. };
  82. const static struct intel_device_info intel_i965gm_info = {
  83. .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
  84. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
  85. .has_hotplug = 1,
  86. };
  87. const static struct intel_device_info intel_g33_info = {
  88. .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  89. .has_hotplug = 1,
  90. };
  91. const static struct intel_device_info intel_g45_info = {
  92. .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  93. .has_pipe_cxsr = 1,
  94. .has_hotplug = 1,
  95. };
  96. const static struct intel_device_info intel_gm45_info = {
  97. .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
  98. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  99. .has_pipe_cxsr = 1,
  100. .has_hotplug = 1,
  101. };
  102. const static struct intel_device_info intel_pineview_info = {
  103. .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
  104. .need_gfx_hws = 1,
  105. .has_hotplug = 1,
  106. };
  107. const static struct intel_device_info intel_ironlake_d_info = {
  108. .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  109. .has_pipe_cxsr = 1,
  110. .has_hotplug = 1,
  111. };
  112. const static struct intel_device_info intel_ironlake_m_info = {
  113. .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
  114. .need_gfx_hws = 1, .has_rc6 = 1,
  115. .has_hotplug = 1,
  116. };
  117. const static struct intel_device_info intel_sandybridge_d_info = {
  118. .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
  119. .has_pipe_cxsr = 1,
  120. .has_hotplug = 1,
  121. };
  122. const static struct pci_device_id pciidlist[] = {
  123. INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
  124. INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
  125. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
  126. INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
  127. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
  128. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
  129. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
  130. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
  131. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
  132. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
  133. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
  134. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
  135. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
  136. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
  137. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
  138. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
  139. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
  140. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
  141. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
  142. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
  143. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
  144. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
  145. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
  146. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
  147. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
  148. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
  149. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  150. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  151. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  152. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  153. INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  154. {0, 0, 0}
  155. };
  156. #if defined(CONFIG_DRM_I915_KMS)
  157. MODULE_DEVICE_TABLE(pci, pciidlist);
  158. #endif
  159. static int i915_drm_freeze(struct drm_device *dev)
  160. {
  161. struct drm_i915_private *dev_priv = dev->dev_private;
  162. pci_save_state(dev->pdev);
  163. /* If KMS is active, we do the leavevt stuff here */
  164. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  165. int error = i915_gem_idle(dev);
  166. if (error) {
  167. dev_err(&dev->pdev->dev,
  168. "GEM idle failed, resume might fail\n");
  169. return error;
  170. }
  171. drm_irq_uninstall(dev);
  172. }
  173. i915_save_state(dev);
  174. intel_opregion_free(dev, 1);
  175. /* Modeset on resume, not lid events */
  176. dev_priv->modeset_on_lid = 0;
  177. return 0;
  178. }
  179. static int i915_suspend(struct drm_device *dev, pm_message_t state)
  180. {
  181. int error;
  182. if (!dev || !dev->dev_private) {
  183. DRM_ERROR("dev: %p\n", dev);
  184. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  185. return -ENODEV;
  186. }
  187. if (state.event == PM_EVENT_PRETHAW)
  188. return 0;
  189. error = i915_drm_freeze(dev);
  190. if (error)
  191. return error;
  192. if (state.event == PM_EVENT_SUSPEND) {
  193. /* Shut down the device */
  194. pci_disable_device(dev->pdev);
  195. pci_set_power_state(dev->pdev, PCI_D3hot);
  196. }
  197. return 0;
  198. }
  199. static int i915_drm_thaw(struct drm_device *dev)
  200. {
  201. struct drm_i915_private *dev_priv = dev->dev_private;
  202. int error = 0;
  203. i915_restore_state(dev);
  204. intel_opregion_init(dev, 1);
  205. /* KMS EnterVT equivalent */
  206. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  207. mutex_lock(&dev->struct_mutex);
  208. dev_priv->mm.suspended = 0;
  209. error = i915_gem_init_ringbuffer(dev);
  210. mutex_unlock(&dev->struct_mutex);
  211. drm_irq_install(dev);
  212. /* Resume the modeset for every activated CRTC */
  213. drm_helper_resume_force_mode(dev);
  214. }
  215. dev_priv->modeset_on_lid = 0;
  216. return error;
  217. }
  218. static int i915_resume(struct drm_device *dev)
  219. {
  220. if (pci_enable_device(dev->pdev))
  221. return -EIO;
  222. pci_set_master(dev->pdev);
  223. return i915_drm_thaw(dev);
  224. }
  225. /**
  226. * i965_reset - reset chip after a hang
  227. * @dev: drm device to reset
  228. * @flags: reset domains
  229. *
  230. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  231. * reset or otherwise an error code.
  232. *
  233. * Procedure is fairly simple:
  234. * - reset the chip using the reset reg
  235. * - re-init context state
  236. * - re-init hardware status page
  237. * - re-init ring buffer
  238. * - re-init interrupt state
  239. * - re-init display
  240. */
  241. int i965_reset(struct drm_device *dev, u8 flags)
  242. {
  243. drm_i915_private_t *dev_priv = dev->dev_private;
  244. unsigned long timeout;
  245. u8 gdrst;
  246. /*
  247. * We really should only reset the display subsystem if we actually
  248. * need to
  249. */
  250. bool need_display = true;
  251. mutex_lock(&dev->struct_mutex);
  252. /*
  253. * Clear request list
  254. */
  255. i915_gem_retire_requests(dev);
  256. if (need_display)
  257. i915_save_display(dev);
  258. if (IS_I965G(dev) || IS_G4X(dev)) {
  259. /*
  260. * Set the domains we want to reset, then the reset bit (bit 0).
  261. * Clear the reset bit after a while and wait for hardware status
  262. * bit (bit 1) to be set
  263. */
  264. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  265. pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
  266. udelay(50);
  267. pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
  268. /* ...we don't want to loop forever though, 500ms should be plenty */
  269. timeout = jiffies + msecs_to_jiffies(500);
  270. do {
  271. udelay(100);
  272. pci_read_config_byte(dev->pdev, GDRST, &gdrst);
  273. } while ((gdrst & 0x1) && time_after(timeout, jiffies));
  274. if (gdrst & 0x1) {
  275. WARN(true, "i915: Failed to reset chip\n");
  276. mutex_unlock(&dev->struct_mutex);
  277. return -EIO;
  278. }
  279. } else {
  280. DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
  281. return -ENODEV;
  282. }
  283. /* Ok, now get things going again... */
  284. /*
  285. * Everything depends on having the GTT running, so we need to start
  286. * there. Fortunately we don't need to do this unless we reset the
  287. * chip at a PCI level.
  288. *
  289. * Next we need to restore the context, but we don't use those
  290. * yet either...
  291. *
  292. * Ring buffer needs to be re-initialized in the KMS case, or if X
  293. * was running at the time of the reset (i.e. we weren't VT
  294. * switched away).
  295. */
  296. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  297. !dev_priv->mm.suspended) {
  298. drm_i915_ring_buffer_t *ring = &dev_priv->ring;
  299. struct drm_gem_object *obj = ring->ring_obj;
  300. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  301. dev_priv->mm.suspended = 0;
  302. /* Stop the ring if it's running. */
  303. I915_WRITE(PRB0_CTL, 0);
  304. I915_WRITE(PRB0_TAIL, 0);
  305. I915_WRITE(PRB0_HEAD, 0);
  306. /* Initialize the ring. */
  307. I915_WRITE(PRB0_START, obj_priv->gtt_offset);
  308. I915_WRITE(PRB0_CTL,
  309. ((obj->size - 4096) & RING_NR_PAGES) |
  310. RING_NO_REPORT |
  311. RING_VALID);
  312. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  313. i915_kernel_lost_context(dev);
  314. else {
  315. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  316. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  317. ring->space = ring->head - (ring->tail + 8);
  318. if (ring->space < 0)
  319. ring->space += ring->Size;
  320. }
  321. mutex_unlock(&dev->struct_mutex);
  322. drm_irq_uninstall(dev);
  323. drm_irq_install(dev);
  324. mutex_lock(&dev->struct_mutex);
  325. }
  326. /*
  327. * Display needs restore too...
  328. */
  329. if (need_display)
  330. i915_restore_display(dev);
  331. mutex_unlock(&dev->struct_mutex);
  332. return 0;
  333. }
  334. static int __devinit
  335. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  336. {
  337. return drm_get_dev(pdev, ent, &driver);
  338. }
  339. static void
  340. i915_pci_remove(struct pci_dev *pdev)
  341. {
  342. struct drm_device *dev = pci_get_drvdata(pdev);
  343. drm_put_dev(dev);
  344. }
  345. static int i915_pm_suspend(struct device *dev)
  346. {
  347. struct pci_dev *pdev = to_pci_dev(dev);
  348. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  349. int error;
  350. if (!drm_dev || !drm_dev->dev_private) {
  351. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  352. return -ENODEV;
  353. }
  354. error = i915_drm_freeze(drm_dev);
  355. if (error)
  356. return error;
  357. pci_disable_device(pdev);
  358. pci_set_power_state(pdev, PCI_D3hot);
  359. return 0;
  360. }
  361. static int i915_pm_resume(struct device *dev)
  362. {
  363. struct pci_dev *pdev = to_pci_dev(dev);
  364. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  365. return i915_resume(drm_dev);
  366. }
  367. static int i915_pm_freeze(struct device *dev)
  368. {
  369. struct pci_dev *pdev = to_pci_dev(dev);
  370. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  371. if (!drm_dev || !drm_dev->dev_private) {
  372. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  373. return -ENODEV;
  374. }
  375. return i915_drm_freeze(drm_dev);
  376. }
  377. static int i915_pm_thaw(struct device *dev)
  378. {
  379. struct pci_dev *pdev = to_pci_dev(dev);
  380. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  381. return i915_drm_thaw(drm_dev);
  382. }
  383. static int i915_pm_poweroff(struct device *dev)
  384. {
  385. struct pci_dev *pdev = to_pci_dev(dev);
  386. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  387. return i915_drm_freeze(drm_dev);
  388. }
  389. const struct dev_pm_ops i915_pm_ops = {
  390. .suspend = i915_pm_suspend,
  391. .resume = i915_pm_resume,
  392. .freeze = i915_pm_freeze,
  393. .thaw = i915_pm_thaw,
  394. .poweroff = i915_pm_poweroff,
  395. .restore = i915_pm_resume,
  396. };
  397. static struct vm_operations_struct i915_gem_vm_ops = {
  398. .fault = i915_gem_fault,
  399. .open = drm_gem_vm_open,
  400. .close = drm_gem_vm_close,
  401. };
  402. static struct drm_driver driver = {
  403. /* don't use mtrr's here, the Xserver or user space app should
  404. * deal with them for intel hardware.
  405. */
  406. .driver_features =
  407. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  408. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  409. .load = i915_driver_load,
  410. .unload = i915_driver_unload,
  411. .open = i915_driver_open,
  412. .lastclose = i915_driver_lastclose,
  413. .preclose = i915_driver_preclose,
  414. .postclose = i915_driver_postclose,
  415. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  416. .suspend = i915_suspend,
  417. .resume = i915_resume,
  418. .device_is_agp = i915_driver_device_is_agp,
  419. .enable_vblank = i915_enable_vblank,
  420. .disable_vblank = i915_disable_vblank,
  421. .irq_preinstall = i915_driver_irq_preinstall,
  422. .irq_postinstall = i915_driver_irq_postinstall,
  423. .irq_uninstall = i915_driver_irq_uninstall,
  424. .irq_handler = i915_driver_irq_handler,
  425. .reclaim_buffers = drm_core_reclaim_buffers,
  426. .get_map_ofs = drm_core_get_map_ofs,
  427. .get_reg_ofs = drm_core_get_reg_ofs,
  428. .master_create = i915_master_create,
  429. .master_destroy = i915_master_destroy,
  430. #if defined(CONFIG_DEBUG_FS)
  431. .debugfs_init = i915_debugfs_init,
  432. .debugfs_cleanup = i915_debugfs_cleanup,
  433. #endif
  434. .gem_init_object = i915_gem_init_object,
  435. .gem_free_object = i915_gem_free_object,
  436. .gem_vm_ops = &i915_gem_vm_ops,
  437. .ioctls = i915_ioctls,
  438. .fops = {
  439. .owner = THIS_MODULE,
  440. .open = drm_open,
  441. .release = drm_release,
  442. .unlocked_ioctl = drm_ioctl,
  443. .mmap = drm_gem_mmap,
  444. .poll = drm_poll,
  445. .fasync = drm_fasync,
  446. .read = drm_read,
  447. #ifdef CONFIG_COMPAT
  448. .compat_ioctl = i915_compat_ioctl,
  449. #endif
  450. },
  451. .pci_driver = {
  452. .name = DRIVER_NAME,
  453. .id_table = pciidlist,
  454. .probe = i915_pci_probe,
  455. .remove = i915_pci_remove,
  456. .driver.pm = &i915_pm_ops,
  457. },
  458. .name = DRIVER_NAME,
  459. .desc = DRIVER_DESC,
  460. .date = DRIVER_DATE,
  461. .major = DRIVER_MAJOR,
  462. .minor = DRIVER_MINOR,
  463. .patchlevel = DRIVER_PATCHLEVEL,
  464. };
  465. static int __init i915_init(void)
  466. {
  467. driver.num_ioctls = i915_max_ioctl;
  468. i915_gem_shrinker_init();
  469. /*
  470. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  471. * explicitly disabled with the module pararmeter.
  472. *
  473. * Otherwise, just follow the parameter (defaulting to off).
  474. *
  475. * Allow optional vga_text_mode_force boot option to override
  476. * the default behavior.
  477. */
  478. #if defined(CONFIG_DRM_I915_KMS)
  479. if (i915_modeset != 0)
  480. driver.driver_features |= DRIVER_MODESET;
  481. #endif
  482. if (i915_modeset == 1)
  483. driver.driver_features |= DRIVER_MODESET;
  484. #ifdef CONFIG_VGA_CONSOLE
  485. if (vgacon_text_force() && i915_modeset == -1)
  486. driver.driver_features &= ~DRIVER_MODESET;
  487. #endif
  488. if (!(driver.driver_features & DRIVER_MODESET)) {
  489. driver.suspend = i915_suspend;
  490. driver.resume = i915_resume;
  491. }
  492. return drm_init(&driver);
  493. }
  494. static void __exit i915_exit(void)
  495. {
  496. i915_gem_shrinker_exit();
  497. drm_exit(&driver);
  498. }
  499. module_init(i915_init);
  500. module_exit(i915_exit);
  501. MODULE_AUTHOR(DRIVER_AUTHOR);
  502. MODULE_DESCRIPTION(DRIVER_DESC);
  503. MODULE_LICENSE("GPL and additional rights");