oxygen_pcm.c 21 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
  26. [PCM_A] = {
  27. .info = SNDRV_PCM_INFO_MMAP |
  28. SNDRV_PCM_INFO_MMAP_VALID |
  29. SNDRV_PCM_INFO_INTERLEAVED |
  30. SNDRV_PCM_INFO_PAUSE |
  31. SNDRV_PCM_INFO_SYNC_START,
  32. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  33. SNDRV_PCM_FMTBIT_S32_LE,
  34. .rates = SNDRV_PCM_RATE_32000 |
  35. SNDRV_PCM_RATE_44100 |
  36. SNDRV_PCM_RATE_48000 |
  37. SNDRV_PCM_RATE_64000 |
  38. SNDRV_PCM_RATE_88200 |
  39. SNDRV_PCM_RATE_96000 |
  40. SNDRV_PCM_RATE_176400 |
  41. SNDRV_PCM_RATE_192000,
  42. .rate_min = 32000,
  43. .rate_max = 192000,
  44. .channels_min = 2,
  45. .channels_max = 2,
  46. .buffer_bytes_max = 256 * 1024,
  47. .period_bytes_min = 128,
  48. .period_bytes_max = 128 * 1024,
  49. .periods_min = 2,
  50. .periods_max = 2048,
  51. },
  52. [PCM_B] = {
  53. .info = SNDRV_PCM_INFO_MMAP |
  54. SNDRV_PCM_INFO_MMAP_VALID |
  55. SNDRV_PCM_INFO_INTERLEAVED |
  56. SNDRV_PCM_INFO_PAUSE |
  57. SNDRV_PCM_INFO_SYNC_START,
  58. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  59. SNDRV_PCM_FMTBIT_S32_LE,
  60. .rates = SNDRV_PCM_RATE_32000 |
  61. SNDRV_PCM_RATE_44100 |
  62. SNDRV_PCM_RATE_48000 |
  63. SNDRV_PCM_RATE_64000 |
  64. SNDRV_PCM_RATE_88200 |
  65. SNDRV_PCM_RATE_96000 |
  66. SNDRV_PCM_RATE_176400 |
  67. SNDRV_PCM_RATE_192000,
  68. .rate_min = 32000,
  69. .rate_max = 192000,
  70. .channels_min = 2,
  71. .channels_max = 2,
  72. .buffer_bytes_max = 256 * 1024,
  73. .period_bytes_min = 128,
  74. .period_bytes_max = 128 * 1024,
  75. .periods_min = 2,
  76. .periods_max = 2048,
  77. },
  78. [PCM_C] = {
  79. .info = SNDRV_PCM_INFO_MMAP |
  80. SNDRV_PCM_INFO_MMAP_VALID |
  81. SNDRV_PCM_INFO_INTERLEAVED |
  82. SNDRV_PCM_INFO_PAUSE |
  83. SNDRV_PCM_INFO_SYNC_START,
  84. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  85. SNDRV_PCM_FMTBIT_S32_LE,
  86. .rates = SNDRV_PCM_RATE_44100 |
  87. SNDRV_PCM_RATE_48000 |
  88. SNDRV_PCM_RATE_88200 |
  89. SNDRV_PCM_RATE_96000,
  90. .rate_min = 44100,
  91. .rate_max = 96000,
  92. .channels_min = 2,
  93. .channels_max = 2,
  94. .buffer_bytes_max = 256 * 1024,
  95. .period_bytes_min = 128,
  96. .period_bytes_max = 128 * 1024,
  97. .periods_min = 2,
  98. .periods_max = 2048,
  99. },
  100. [PCM_SPDIF] = {
  101. .info = SNDRV_PCM_INFO_MMAP |
  102. SNDRV_PCM_INFO_MMAP_VALID |
  103. SNDRV_PCM_INFO_INTERLEAVED |
  104. SNDRV_PCM_INFO_PAUSE |
  105. SNDRV_PCM_INFO_SYNC_START,
  106. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  107. SNDRV_PCM_FMTBIT_S32_LE,
  108. .rates = SNDRV_PCM_RATE_32000 |
  109. SNDRV_PCM_RATE_44100 |
  110. SNDRV_PCM_RATE_48000 |
  111. SNDRV_PCM_RATE_64000 |
  112. SNDRV_PCM_RATE_88200 |
  113. SNDRV_PCM_RATE_96000 |
  114. SNDRV_PCM_RATE_176400 |
  115. SNDRV_PCM_RATE_192000,
  116. .rate_min = 32000,
  117. .rate_max = 192000,
  118. .channels_min = 2,
  119. .channels_max = 2,
  120. .buffer_bytes_max = 256 * 1024,
  121. .period_bytes_min = 128,
  122. .period_bytes_max = 128 * 1024,
  123. .periods_min = 2,
  124. .periods_max = 2048,
  125. },
  126. [PCM_MULTICH] = {
  127. .info = SNDRV_PCM_INFO_MMAP |
  128. SNDRV_PCM_INFO_MMAP_VALID |
  129. SNDRV_PCM_INFO_INTERLEAVED |
  130. SNDRV_PCM_INFO_PAUSE |
  131. SNDRV_PCM_INFO_SYNC_START,
  132. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  133. SNDRV_PCM_FMTBIT_S32_LE,
  134. .rates = SNDRV_PCM_RATE_32000 |
  135. SNDRV_PCM_RATE_44100 |
  136. SNDRV_PCM_RATE_48000 |
  137. SNDRV_PCM_RATE_64000 |
  138. SNDRV_PCM_RATE_88200 |
  139. SNDRV_PCM_RATE_96000 |
  140. SNDRV_PCM_RATE_176400 |
  141. SNDRV_PCM_RATE_192000,
  142. .rate_min = 32000,
  143. .rate_max = 192000,
  144. .channels_min = 2,
  145. .channels_max = 8,
  146. .buffer_bytes_max = 2048 * 1024,
  147. .period_bytes_min = 128,
  148. .period_bytes_max = 256 * 1024,
  149. .periods_min = 2,
  150. .periods_max = 16384,
  151. },
  152. [PCM_AC97] = {
  153. .info = SNDRV_PCM_INFO_MMAP |
  154. SNDRV_PCM_INFO_MMAP_VALID |
  155. SNDRV_PCM_INFO_INTERLEAVED |
  156. SNDRV_PCM_INFO_PAUSE |
  157. SNDRV_PCM_INFO_SYNC_START,
  158. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  159. .rates = SNDRV_PCM_RATE_48000,
  160. .rate_min = 48000,
  161. .rate_max = 48000,
  162. .channels_min = 2,
  163. .channels_max = 2,
  164. .buffer_bytes_max = 256 * 1024,
  165. .period_bytes_min = 128,
  166. .period_bytes_max = 128 * 1024,
  167. .periods_min = 2,
  168. .periods_max = 2048,
  169. },
  170. };
  171. static inline unsigned int
  172. oxygen_substream_channel(struct snd_pcm_substream *substream)
  173. {
  174. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  175. }
  176. static int oxygen_open(struct snd_pcm_substream *substream,
  177. unsigned int channel)
  178. {
  179. struct oxygen *chip = snd_pcm_substream_chip(substream);
  180. struct snd_pcm_runtime *runtime = substream->runtime;
  181. int err;
  182. runtime->private_data = (void *)(uintptr_t)channel;
  183. runtime->hw = oxygen_hardware[channel];
  184. if (chip->model->pcm_hardware_filter)
  185. chip->model->pcm_hardware_filter(channel, &runtime->hw);
  186. err = snd_pcm_hw_constraint_step(runtime, 0,
  187. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  188. if (err < 0)
  189. return err;
  190. err = snd_pcm_hw_constraint_step(runtime, 0,
  191. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  192. if (err < 0)
  193. return err;
  194. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  195. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  196. if (err < 0)
  197. return err;
  198. }
  199. if (runtime->hw.channels_max > 2) {
  200. err = snd_pcm_hw_constraint_step(runtime, 0,
  201. SNDRV_PCM_HW_PARAM_CHANNELS,
  202. 2);
  203. if (err < 0)
  204. return err;
  205. }
  206. snd_pcm_set_sync(substream);
  207. chip->streams[channel] = substream;
  208. mutex_lock(&chip->mutex);
  209. chip->pcm_active |= 1 << channel;
  210. if (channel == PCM_SPDIF) {
  211. chip->spdif_pcm_bits = chip->spdif_bits;
  212. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  213. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  214. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  215. SNDRV_CTL_EVENT_MASK_INFO,
  216. &chip->controls[CONTROL_SPDIF_PCM]->id);
  217. }
  218. mutex_unlock(&chip->mutex);
  219. return 0;
  220. }
  221. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  222. {
  223. return oxygen_open(substream, PCM_A);
  224. }
  225. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  226. {
  227. return oxygen_open(substream, PCM_B);
  228. }
  229. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  230. {
  231. return oxygen_open(substream, PCM_C);
  232. }
  233. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  234. {
  235. return oxygen_open(substream, PCM_SPDIF);
  236. }
  237. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  238. {
  239. return oxygen_open(substream, PCM_MULTICH);
  240. }
  241. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  242. {
  243. return oxygen_open(substream, PCM_AC97);
  244. }
  245. static int oxygen_close(struct snd_pcm_substream *substream)
  246. {
  247. struct oxygen *chip = snd_pcm_substream_chip(substream);
  248. unsigned int channel = oxygen_substream_channel(substream);
  249. mutex_lock(&chip->mutex);
  250. chip->pcm_active &= ~(1 << channel);
  251. if (channel == PCM_SPDIF) {
  252. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  253. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  254. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  255. SNDRV_CTL_EVENT_MASK_INFO,
  256. &chip->controls[CONTROL_SPDIF_PCM]->id);
  257. }
  258. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  259. oxygen_update_spdif_source(chip);
  260. mutex_unlock(&chip->mutex);
  261. chip->streams[channel] = NULL;
  262. return 0;
  263. }
  264. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  265. {
  266. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  267. return OXYGEN_FORMAT_24;
  268. else
  269. return OXYGEN_FORMAT_16;
  270. }
  271. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  272. {
  273. switch (params_rate(hw_params)) {
  274. case 32000:
  275. return OXYGEN_RATE_32000;
  276. case 44100:
  277. return OXYGEN_RATE_44100;
  278. default: /* 48000 */
  279. return OXYGEN_RATE_48000;
  280. case 64000:
  281. return OXYGEN_RATE_64000;
  282. case 88200:
  283. return OXYGEN_RATE_88200;
  284. case 96000:
  285. return OXYGEN_RATE_96000;
  286. case 176400:
  287. return OXYGEN_RATE_176400;
  288. case 192000:
  289. return OXYGEN_RATE_192000;
  290. }
  291. }
  292. static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
  293. {
  294. return params_rate(hw_params) <= 96000
  295. ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
  296. }
  297. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  298. {
  299. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  300. return OXYGEN_I2S_BITS_24;
  301. else
  302. return OXYGEN_I2S_BITS_16;
  303. }
  304. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  305. {
  306. switch (params_channels(hw_params)) {
  307. default: /* 2 */
  308. return OXYGEN_PLAY_CHANNELS_2;
  309. case 4:
  310. return OXYGEN_PLAY_CHANNELS_4;
  311. case 6:
  312. return OXYGEN_PLAY_CHANNELS_6;
  313. case 8:
  314. return OXYGEN_PLAY_CHANNELS_8;
  315. }
  316. }
  317. static const unsigned int channel_base_registers[PCM_COUNT] = {
  318. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  319. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  320. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  321. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  322. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  323. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  324. };
  325. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  326. struct snd_pcm_hw_params *hw_params)
  327. {
  328. struct oxygen *chip = snd_pcm_substream_chip(substream);
  329. unsigned int channel = oxygen_substream_channel(substream);
  330. int err;
  331. err = snd_pcm_lib_malloc_pages(substream,
  332. params_buffer_bytes(hw_params));
  333. if (err < 0)
  334. return err;
  335. oxygen_write32(chip, channel_base_registers[channel],
  336. (u32)substream->runtime->dma_addr);
  337. if (channel == PCM_MULTICH) {
  338. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  339. params_buffer_bytes(hw_params) / 4 - 1);
  340. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  341. params_period_bytes(hw_params) / 4 - 1);
  342. } else {
  343. oxygen_write16(chip, channel_base_registers[channel] + 4,
  344. params_buffer_bytes(hw_params) / 4 - 1);
  345. oxygen_write16(chip, channel_base_registers[channel] + 6,
  346. params_period_bytes(hw_params) / 4 - 1);
  347. }
  348. return 0;
  349. }
  350. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  351. struct snd_pcm_hw_params *hw_params)
  352. {
  353. struct oxygen *chip = snd_pcm_substream_chip(substream);
  354. int err;
  355. err = oxygen_hw_params(substream, hw_params);
  356. if (err < 0)
  357. return err;
  358. spin_lock_irq(&chip->reg_lock);
  359. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  360. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  361. OXYGEN_REC_FORMAT_A_MASK);
  362. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  363. oxygen_rate(hw_params) |
  364. oxygen_i2s_mclk(hw_params) |
  365. chip->model->adc_i2s_format |
  366. oxygen_i2s_bits(hw_params),
  367. OXYGEN_I2S_RATE_MASK |
  368. OXYGEN_I2S_FORMAT_MASK |
  369. OXYGEN_I2S_MCLK_MASK |
  370. OXYGEN_I2S_BITS_MASK);
  371. oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08);
  372. spin_unlock_irq(&chip->reg_lock);
  373. mutex_lock(&chip->mutex);
  374. chip->model->set_adc_params(chip, hw_params);
  375. mutex_unlock(&chip->mutex);
  376. return 0;
  377. }
  378. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  379. struct snd_pcm_hw_params *hw_params)
  380. {
  381. struct oxygen *chip = snd_pcm_substream_chip(substream);
  382. int err;
  383. err = oxygen_hw_params(substream, hw_params);
  384. if (err < 0)
  385. return err;
  386. spin_lock_irq(&chip->reg_lock);
  387. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  388. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  389. OXYGEN_REC_FORMAT_B_MASK);
  390. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  391. oxygen_rate(hw_params) |
  392. oxygen_i2s_mclk(hw_params) |
  393. chip->model->adc_i2s_format |
  394. oxygen_i2s_bits(hw_params),
  395. OXYGEN_I2S_RATE_MASK |
  396. OXYGEN_I2S_FORMAT_MASK |
  397. OXYGEN_I2S_MCLK_MASK |
  398. OXYGEN_I2S_BITS_MASK);
  399. oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10);
  400. spin_unlock_irq(&chip->reg_lock);
  401. mutex_lock(&chip->mutex);
  402. chip->model->set_adc_params(chip, hw_params);
  403. mutex_unlock(&chip->mutex);
  404. return 0;
  405. }
  406. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  407. struct snd_pcm_hw_params *hw_params)
  408. {
  409. struct oxygen *chip = snd_pcm_substream_chip(substream);
  410. int err;
  411. err = oxygen_hw_params(substream, hw_params);
  412. if (err < 0)
  413. return err;
  414. spin_lock_irq(&chip->reg_lock);
  415. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  416. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  417. OXYGEN_REC_FORMAT_C_MASK);
  418. oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x20);
  419. spin_unlock_irq(&chip->reg_lock);
  420. return 0;
  421. }
  422. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  423. struct snd_pcm_hw_params *hw_params)
  424. {
  425. struct oxygen *chip = snd_pcm_substream_chip(substream);
  426. int err;
  427. err = oxygen_hw_params(substream, hw_params);
  428. if (err < 0)
  429. return err;
  430. spin_lock_irq(&chip->reg_lock);
  431. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  432. OXYGEN_SPDIF_OUT_ENABLE);
  433. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  434. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  435. OXYGEN_SPDIF_FORMAT_MASK);
  436. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  437. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  438. OXYGEN_SPDIF_OUT_RATE_MASK);
  439. oxygen_update_spdif_source(chip);
  440. spin_unlock_irq(&chip->reg_lock);
  441. return 0;
  442. }
  443. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  444. struct snd_pcm_hw_params *hw_params)
  445. {
  446. struct oxygen *chip = snd_pcm_substream_chip(substream);
  447. int err;
  448. err = oxygen_hw_params(substream, hw_params);
  449. if (err < 0)
  450. return err;
  451. spin_lock_irq(&chip->reg_lock);
  452. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  453. oxygen_play_channels(hw_params),
  454. OXYGEN_PLAY_CHANNELS_MASK);
  455. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  456. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  457. OXYGEN_MULTICH_FORMAT_MASK);
  458. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  459. oxygen_rate(hw_params) |
  460. chip->model->dac_i2s_format |
  461. oxygen_i2s_bits(hw_params),
  462. OXYGEN_I2S_RATE_MASK |
  463. OXYGEN_I2S_FORMAT_MASK |
  464. OXYGEN_I2S_BITS_MASK);
  465. oxygen_clear_bits16(chip, OXYGEN_PLAY_ROUTING, 0x001f);
  466. oxygen_update_dac_routing(chip);
  467. oxygen_update_spdif_source(chip);
  468. spin_unlock_irq(&chip->reg_lock);
  469. mutex_lock(&chip->mutex);
  470. chip->model->set_dac_params(chip, hw_params);
  471. mutex_unlock(&chip->mutex);
  472. return 0;
  473. }
  474. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  475. {
  476. struct oxygen *chip = snd_pcm_substream_chip(substream);
  477. unsigned int channel = oxygen_substream_channel(substream);
  478. spin_lock_irq(&chip->reg_lock);
  479. chip->interrupt_mask &= ~(1 << channel);
  480. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  481. spin_unlock_irq(&chip->reg_lock);
  482. return snd_pcm_lib_free_pages(substream);
  483. }
  484. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  485. {
  486. struct oxygen *chip = snd_pcm_substream_chip(substream);
  487. spin_lock_irq(&chip->reg_lock);
  488. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  489. OXYGEN_SPDIF_OUT_ENABLE);
  490. spin_unlock_irq(&chip->reg_lock);
  491. return oxygen_hw_free(substream);
  492. }
  493. static int oxygen_prepare(struct snd_pcm_substream *substream)
  494. {
  495. struct oxygen *chip = snd_pcm_substream_chip(substream);
  496. unsigned int channel = oxygen_substream_channel(substream);
  497. unsigned int channel_mask = 1 << channel;
  498. spin_lock_irq(&chip->reg_lock);
  499. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  500. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  501. chip->interrupt_mask |= channel_mask;
  502. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  503. spin_unlock_irq(&chip->reg_lock);
  504. return 0;
  505. }
  506. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  507. {
  508. struct oxygen *chip = snd_pcm_substream_chip(substream);
  509. struct snd_pcm_substream *s;
  510. unsigned int mask = 0;
  511. int running;
  512. switch (cmd) {
  513. case SNDRV_PCM_TRIGGER_STOP:
  514. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  515. running = 0;
  516. break;
  517. case SNDRV_PCM_TRIGGER_START:
  518. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  519. running = 1;
  520. break;
  521. default:
  522. return -EINVAL;
  523. }
  524. snd_pcm_group_for_each_entry(s, substream) {
  525. if (snd_pcm_substream_chip(s) == chip) {
  526. mask |= 1 << oxygen_substream_channel(s);
  527. snd_pcm_trigger_done(s, substream);
  528. }
  529. }
  530. spin_lock(&chip->reg_lock);
  531. if (running)
  532. chip->pcm_running |= mask;
  533. else
  534. chip->pcm_running &= ~mask;
  535. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  536. spin_unlock(&chip->reg_lock);
  537. return 0;
  538. }
  539. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  540. {
  541. struct oxygen *chip = snd_pcm_substream_chip(substream);
  542. struct snd_pcm_runtime *runtime = substream->runtime;
  543. unsigned int channel = oxygen_substream_channel(substream);
  544. u32 curr_addr;
  545. /* no spinlock, this read should be atomic */
  546. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  547. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  548. }
  549. static struct snd_pcm_ops oxygen_rec_a_ops = {
  550. .open = oxygen_rec_a_open,
  551. .close = oxygen_close,
  552. .ioctl = snd_pcm_lib_ioctl,
  553. .hw_params = oxygen_rec_a_hw_params,
  554. .hw_free = oxygen_hw_free,
  555. .prepare = oxygen_prepare,
  556. .trigger = oxygen_trigger,
  557. .pointer = oxygen_pointer,
  558. };
  559. static struct snd_pcm_ops oxygen_rec_b_ops = {
  560. .open = oxygen_rec_b_open,
  561. .close = oxygen_close,
  562. .ioctl = snd_pcm_lib_ioctl,
  563. .hw_params = oxygen_rec_b_hw_params,
  564. .hw_free = oxygen_hw_free,
  565. .prepare = oxygen_prepare,
  566. .trigger = oxygen_trigger,
  567. .pointer = oxygen_pointer,
  568. };
  569. static struct snd_pcm_ops oxygen_rec_c_ops = {
  570. .open = oxygen_rec_c_open,
  571. .close = oxygen_close,
  572. .ioctl = snd_pcm_lib_ioctl,
  573. .hw_params = oxygen_rec_c_hw_params,
  574. .hw_free = oxygen_hw_free,
  575. .prepare = oxygen_prepare,
  576. .trigger = oxygen_trigger,
  577. .pointer = oxygen_pointer,
  578. };
  579. static struct snd_pcm_ops oxygen_spdif_ops = {
  580. .open = oxygen_spdif_open,
  581. .close = oxygen_close,
  582. .ioctl = snd_pcm_lib_ioctl,
  583. .hw_params = oxygen_spdif_hw_params,
  584. .hw_free = oxygen_spdif_hw_free,
  585. .prepare = oxygen_prepare,
  586. .trigger = oxygen_trigger,
  587. .pointer = oxygen_pointer,
  588. };
  589. static struct snd_pcm_ops oxygen_multich_ops = {
  590. .open = oxygen_multich_open,
  591. .close = oxygen_close,
  592. .ioctl = snd_pcm_lib_ioctl,
  593. .hw_params = oxygen_multich_hw_params,
  594. .hw_free = oxygen_hw_free,
  595. .prepare = oxygen_prepare,
  596. .trigger = oxygen_trigger,
  597. .pointer = oxygen_pointer,
  598. };
  599. static struct snd_pcm_ops oxygen_ac97_ops = {
  600. .open = oxygen_ac97_open,
  601. .close = oxygen_close,
  602. .ioctl = snd_pcm_lib_ioctl,
  603. .hw_params = oxygen_hw_params,
  604. .hw_free = oxygen_hw_free,
  605. .prepare = oxygen_prepare,
  606. .trigger = oxygen_trigger,
  607. .pointer = oxygen_pointer,
  608. };
  609. static void oxygen_pcm_free(struct snd_pcm *pcm)
  610. {
  611. snd_pcm_lib_preallocate_free_for_all(pcm);
  612. }
  613. int __devinit oxygen_pcm_init(struct oxygen *chip)
  614. {
  615. struct snd_pcm *pcm;
  616. int outs, ins;
  617. int err;
  618. outs = 1; /* OXYGEN_CHANNEL_MULTICH is always used */
  619. ins = !!(chip->model->used_channels & (OXYGEN_CHANNEL_A |
  620. OXYGEN_CHANNEL_B));
  621. err = snd_pcm_new(chip->card, "Analog", 0, outs, ins, &pcm);
  622. if (err < 0)
  623. return err;
  624. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
  625. if (chip->model->used_channels & OXYGEN_CHANNEL_A)
  626. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  627. &oxygen_rec_a_ops);
  628. else if (chip->model->used_channels & OXYGEN_CHANNEL_B)
  629. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  630. &oxygen_rec_b_ops);
  631. pcm->private_data = chip;
  632. pcm->private_free = oxygen_pcm_free;
  633. strcpy(pcm->name, "Analog");
  634. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  635. SNDRV_DMA_TYPE_DEV,
  636. snd_dma_pci_data(chip->pci),
  637. 512 * 1024, 2048 * 1024);
  638. if (ins)
  639. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  640. SNDRV_DMA_TYPE_DEV,
  641. snd_dma_pci_data(chip->pci),
  642. 128 * 1024, 256 * 1024);
  643. outs = !!(chip->model->used_channels & OXYGEN_CHANNEL_SPDIF);
  644. ins = !!(chip->model->used_channels & OXYGEN_CHANNEL_C);
  645. if (outs | ins) {
  646. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  647. if (err < 0)
  648. return err;
  649. if (outs)
  650. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  651. &oxygen_spdif_ops);
  652. if (ins)
  653. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  654. &oxygen_rec_c_ops);
  655. pcm->private_data = chip;
  656. pcm->private_free = oxygen_pcm_free;
  657. strcpy(pcm->name, "Digital");
  658. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  659. snd_dma_pci_data(chip->pci),
  660. 128 * 1024, 256 * 1024);
  661. }
  662. outs = chip->has_ac97_1 &&
  663. (chip->model->used_channels & OXYGEN_CHANNEL_AC97);
  664. ins = (chip->model->used_channels & (OXYGEN_CHANNEL_A |
  665. OXYGEN_CHANNEL_B))
  666. == (OXYGEN_CHANNEL_A | OXYGEN_CHANNEL_B);
  667. if (outs | ins) {
  668. err = snd_pcm_new(chip->card, ins ? "Analog2" : "AC97",
  669. 2, outs, ins, &pcm);
  670. if (err < 0)
  671. return err;
  672. if (outs)
  673. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  674. &oxygen_ac97_ops);
  675. if (ins)
  676. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  677. &oxygen_rec_b_ops);
  678. pcm->private_data = chip;
  679. pcm->private_free = oxygen_pcm_free;
  680. strcpy(pcm->name, ins ? "Analog 2" : "Front Panel");
  681. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  682. snd_dma_pci_data(chip->pci),
  683. 128 * 1024, 256 * 1024);
  684. }
  685. return 0;
  686. }