smsc911x.c 55 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. ***************************************************************************
  21. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  22. * Partly uses io macros from smc91x.c by Nicolas Pitre
  23. *
  24. * Supported devices:
  25. * LAN9115, LAN9116, LAN9117, LAN9118
  26. * LAN9215, LAN9216, LAN9217, LAN9218
  27. * LAN9210, LAN9211
  28. * LAN9220, LAN9221
  29. *
  30. */
  31. #include <linux/crc32.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/ethtool.h>
  36. #include <linux/init.h>
  37. #include <linux/ioport.h>
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/platform_device.h>
  42. #include <linux/sched.h>
  43. #include <linux/slab.h>
  44. #include <linux/timer.h>
  45. #include <linux/version.h>
  46. #include <linux/bug.h>
  47. #include <linux/bitops.h>
  48. #include <linux/irq.h>
  49. #include <linux/io.h>
  50. #include <linux/phy.h>
  51. #include <linux/smsc911x.h>
  52. #include "smsc911x.h"
  53. #define SMSC_CHIPNAME "smsc911x"
  54. #define SMSC_MDIONAME "smsc911x-mdio"
  55. #define SMSC_DRV_VERSION "2008-10-21"
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(SMSC_DRV_VERSION);
  58. #if USE_DEBUG > 0
  59. static int debug = 16;
  60. #else
  61. static int debug = 3;
  62. #endif
  63. module_param(debug, int, 0);
  64. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  65. struct smsc911x_data {
  66. void __iomem *ioaddr;
  67. unsigned int idrev;
  68. /* used to decide which workarounds apply */
  69. unsigned int generation;
  70. /* device configuration (copied from platform_data during probe) */
  71. struct smsc911x_platform_config config;
  72. /* This needs to be acquired before calling any of below:
  73. * smsc911x_mac_read(), smsc911x_mac_write()
  74. */
  75. spinlock_t mac_lock;
  76. /* spinlock to ensure 16-bit accesses are serialised.
  77. * unused with a 32-bit bus */
  78. spinlock_t dev_lock;
  79. struct phy_device *phy_dev;
  80. struct mii_bus *mii_bus;
  81. int phy_irq[PHY_MAX_ADDR];
  82. unsigned int using_extphy;
  83. int last_duplex;
  84. int last_carrier;
  85. u32 msg_enable;
  86. unsigned int gpio_setting;
  87. unsigned int gpio_orig_setting;
  88. struct net_device *dev;
  89. struct napi_struct napi;
  90. unsigned int software_irq_signal;
  91. #ifdef USE_PHY_WORK_AROUND
  92. #define MIN_PACKET_SIZE (64)
  93. char loopback_tx_pkt[MIN_PACKET_SIZE];
  94. char loopback_rx_pkt[MIN_PACKET_SIZE];
  95. unsigned int resetcount;
  96. #endif
  97. /* Members for Multicast filter workaround */
  98. unsigned int multicast_update_pending;
  99. unsigned int set_bits_mask;
  100. unsigned int clear_bits_mask;
  101. unsigned int hashhi;
  102. unsigned int hashlo;
  103. };
  104. /* The 16-bit access functions are significantly slower, due to the locking
  105. * necessary. If your bus hardware can be configured to do this for you
  106. * (in response to a single 32-bit operation from software), you should use
  107. * the 32-bit access functions instead. */
  108. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  109. {
  110. if (pdata->config.flags & SMSC911X_USE_32BIT)
  111. return readl(pdata->ioaddr + reg);
  112. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  113. u32 data;
  114. unsigned long flags;
  115. /* these two 16-bit reads must be performed consecutively, so
  116. * must not be interrupted by our own ISR (which would start
  117. * another read operation) */
  118. spin_lock_irqsave(&pdata->dev_lock, flags);
  119. data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  120. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  121. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  122. return data;
  123. }
  124. BUG();
  125. return 0;
  126. }
  127. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  128. u32 val)
  129. {
  130. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  131. writel(val, pdata->ioaddr + reg);
  132. return;
  133. }
  134. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  135. unsigned long flags;
  136. /* these two 16-bit writes must be performed consecutively, so
  137. * must not be interrupted by our own ISR (which would start
  138. * another read operation) */
  139. spin_lock_irqsave(&pdata->dev_lock, flags);
  140. writew(val & 0xFFFF, pdata->ioaddr + reg);
  141. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  142. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  143. return;
  144. }
  145. BUG();
  146. }
  147. /* Writes a packet to the TX_DATA_FIFO */
  148. static inline void
  149. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  150. unsigned int wordcount)
  151. {
  152. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  153. writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  154. return;
  155. }
  156. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  157. while (wordcount--)
  158. smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  159. return;
  160. }
  161. BUG();
  162. }
  163. /* Reads a packet out of the RX_DATA_FIFO */
  164. static inline void
  165. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  166. unsigned int wordcount)
  167. {
  168. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  169. readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  170. return;
  171. }
  172. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  173. while (wordcount--)
  174. *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  175. return;
  176. }
  177. BUG();
  178. }
  179. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  180. * and smsc911x_mac_write, so assumes mac_lock is held */
  181. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  182. {
  183. int i;
  184. u32 val;
  185. SMSC_ASSERT_MAC_LOCK(pdata);
  186. for (i = 0; i < 40; i++) {
  187. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  188. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  189. return 0;
  190. }
  191. SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
  192. "MAC_CSR_CMD: 0x%08X", val);
  193. return -EIO;
  194. }
  195. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  196. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  197. {
  198. unsigned int temp;
  199. SMSC_ASSERT_MAC_LOCK(pdata);
  200. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  201. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  202. SMSC_WARNING(HW, "MAC busy at entry");
  203. return 0xFFFFFFFF;
  204. }
  205. /* Send the MAC cmd */
  206. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  207. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  208. /* Workaround for hardware read-after-write restriction */
  209. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  210. /* Wait for the read to complete */
  211. if (likely(smsc911x_mac_complete(pdata) == 0))
  212. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  213. SMSC_WARNING(HW, "MAC busy after read");
  214. return 0xFFFFFFFF;
  215. }
  216. /* Set a mac register, mac_lock must be acquired before calling */
  217. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  218. unsigned int offset, u32 val)
  219. {
  220. unsigned int temp;
  221. SMSC_ASSERT_MAC_LOCK(pdata);
  222. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  223. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  224. SMSC_WARNING(HW,
  225. "smsc911x_mac_write failed, MAC busy at entry");
  226. return;
  227. }
  228. /* Send data to write */
  229. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  230. /* Write the actual data */
  231. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  232. MAC_CSR_CMD_CSR_BUSY_));
  233. /* Workaround for hardware read-after-write restriction */
  234. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  235. /* Wait for the write to complete */
  236. if (likely(smsc911x_mac_complete(pdata) == 0))
  237. return;
  238. SMSC_WARNING(HW,
  239. "smsc911x_mac_write failed, MAC busy after write");
  240. }
  241. /* Get a phy register */
  242. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  243. {
  244. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  245. unsigned long flags;
  246. unsigned int addr;
  247. int i, reg;
  248. spin_lock_irqsave(&pdata->mac_lock, flags);
  249. /* Confirm MII not busy */
  250. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  251. SMSC_WARNING(HW,
  252. "MII is busy in smsc911x_mii_read???");
  253. reg = -EIO;
  254. goto out;
  255. }
  256. /* Set the address, index & direction (read from PHY) */
  257. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  258. smsc911x_mac_write(pdata, MII_ACC, addr);
  259. /* Wait for read to complete w/ timeout */
  260. for (i = 0; i < 100; i++)
  261. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  262. reg = smsc911x_mac_read(pdata, MII_DATA);
  263. goto out;
  264. }
  265. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  266. reg = -EIO;
  267. out:
  268. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  269. return reg;
  270. }
  271. /* Set a phy register */
  272. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  273. u16 val)
  274. {
  275. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  276. unsigned long flags;
  277. unsigned int addr;
  278. int i, reg;
  279. spin_lock_irqsave(&pdata->mac_lock, flags);
  280. /* Confirm MII not busy */
  281. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  282. SMSC_WARNING(HW,
  283. "MII is busy in smsc911x_mii_write???");
  284. reg = -EIO;
  285. goto out;
  286. }
  287. /* Put the data to write in the MAC */
  288. smsc911x_mac_write(pdata, MII_DATA, val);
  289. /* Set the address, index & direction (write to PHY) */
  290. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  291. MII_ACC_MII_WRITE_;
  292. smsc911x_mac_write(pdata, MII_ACC, addr);
  293. /* Wait for write to complete w/ timeout */
  294. for (i = 0; i < 100; i++)
  295. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  296. reg = 0;
  297. goto out;
  298. }
  299. SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
  300. reg = -EIO;
  301. out:
  302. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  303. return reg;
  304. }
  305. /* Autodetects and initialises external phy for SMSC9115 and SMSC9117 flavors.
  306. * If something goes wrong, returns -ENODEV to revert back to internal phy.
  307. * Performed at initialisation only, so interrupts are enabled */
  308. static int smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  309. {
  310. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  311. /* External phy is requested, supported, and detected */
  312. if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  313. /* Switch to external phy. Assuming tx and rx are stopped
  314. * because smsc911x_phy_initialise is called before
  315. * smsc911x_rx_initialise and tx_initialise. */
  316. /* Disable phy clocks to the MAC */
  317. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  318. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  319. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  320. udelay(10); /* Enough time for clocks to stop */
  321. /* Switch to external phy */
  322. hwcfg |= HW_CFG_EXT_PHY_EN_;
  323. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  324. /* Enable phy clocks to the MAC */
  325. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  326. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  327. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  328. udelay(10); /* Enough time for clocks to restart */
  329. hwcfg |= HW_CFG_SMI_SEL_;
  330. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  331. SMSC_TRACE(HW, "Successfully switched to external PHY");
  332. pdata->using_extphy = 1;
  333. } else {
  334. SMSC_WARNING(HW, "No external PHY detected, "
  335. "Using internal PHY instead.");
  336. /* Use internal phy */
  337. return -ENODEV;
  338. }
  339. return 0;
  340. }
  341. /* Fetches a tx status out of the status fifo */
  342. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  343. {
  344. unsigned int result =
  345. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  346. if (result != 0)
  347. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  348. return result;
  349. }
  350. /* Fetches the next rx status */
  351. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  352. {
  353. unsigned int result =
  354. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  355. if (result != 0)
  356. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  357. return result;
  358. }
  359. #ifdef USE_PHY_WORK_AROUND
  360. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  361. {
  362. unsigned int tries;
  363. u32 wrsz;
  364. u32 rdsz;
  365. ulong bufp;
  366. for (tries = 0; tries < 10; tries++) {
  367. unsigned int txcmd_a;
  368. unsigned int txcmd_b;
  369. unsigned int status;
  370. unsigned int pktlength;
  371. unsigned int i;
  372. /* Zero-out rx packet memory */
  373. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  374. /* Write tx packet to 118 */
  375. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  376. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  377. txcmd_a |= MIN_PACKET_SIZE;
  378. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  379. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  380. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  381. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  382. wrsz = MIN_PACKET_SIZE + 3;
  383. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  384. wrsz >>= 2;
  385. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  386. /* Wait till transmit is done */
  387. i = 60;
  388. do {
  389. udelay(5);
  390. status = smsc911x_tx_get_txstatus(pdata);
  391. } while ((i--) && (!status));
  392. if (!status) {
  393. SMSC_WARNING(HW, "Failed to transmit "
  394. "during loopback test");
  395. continue;
  396. }
  397. if (status & TX_STS_ES_) {
  398. SMSC_WARNING(HW, "Transmit encountered "
  399. "errors during loopback test");
  400. continue;
  401. }
  402. /* Wait till receive is done */
  403. i = 60;
  404. do {
  405. udelay(5);
  406. status = smsc911x_rx_get_rxstatus(pdata);
  407. } while ((i--) && (!status));
  408. if (!status) {
  409. SMSC_WARNING(HW,
  410. "Failed to receive during loopback test");
  411. continue;
  412. }
  413. if (status & RX_STS_ES_) {
  414. SMSC_WARNING(HW, "Receive encountered "
  415. "errors during loopback test");
  416. continue;
  417. }
  418. pktlength = ((status & 0x3FFF0000UL) >> 16);
  419. bufp = (ulong)pdata->loopback_rx_pkt;
  420. rdsz = pktlength + 3;
  421. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  422. rdsz >>= 2;
  423. smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  424. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  425. SMSC_WARNING(HW, "Unexpected packet size "
  426. "during loop back test, size=%d, will retry",
  427. pktlength);
  428. } else {
  429. unsigned int j;
  430. int mismatch = 0;
  431. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  432. if (pdata->loopback_tx_pkt[j]
  433. != pdata->loopback_rx_pkt[j]) {
  434. mismatch = 1;
  435. break;
  436. }
  437. }
  438. if (!mismatch) {
  439. SMSC_TRACE(HW, "Successfully verified "
  440. "loopback packet");
  441. return 0;
  442. } else {
  443. SMSC_WARNING(HW, "Data mismatch "
  444. "during loop back test, will retry");
  445. }
  446. }
  447. }
  448. return -EIO;
  449. }
  450. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  451. {
  452. struct phy_device *phy_dev = pdata->phy_dev;
  453. unsigned int temp;
  454. unsigned int i = 100000;
  455. BUG_ON(!phy_dev);
  456. BUG_ON(!phy_dev->bus);
  457. SMSC_TRACE(HW, "Performing PHY BCR Reset");
  458. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  459. do {
  460. msleep(1);
  461. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  462. MII_BMCR);
  463. } while ((i--) && (temp & BMCR_RESET));
  464. if (temp & BMCR_RESET) {
  465. SMSC_WARNING(HW, "PHY reset failed to complete.");
  466. return -EIO;
  467. }
  468. /* Extra delay required because the phy may not be completed with
  469. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  470. * enough delay but using 1ms here to be safe */
  471. msleep(1);
  472. return 0;
  473. }
  474. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  475. {
  476. struct smsc911x_data *pdata = netdev_priv(dev);
  477. struct phy_device *phy_dev = pdata->phy_dev;
  478. int result = -EIO;
  479. unsigned int i, val;
  480. unsigned long flags;
  481. /* Initialise tx packet using broadcast destination address */
  482. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  483. /* Use incrementing source address */
  484. for (i = 6; i < 12; i++)
  485. pdata->loopback_tx_pkt[i] = (char)i;
  486. /* Set length type field */
  487. pdata->loopback_tx_pkt[12] = 0x00;
  488. pdata->loopback_tx_pkt[13] = 0x00;
  489. for (i = 14; i < MIN_PACKET_SIZE; i++)
  490. pdata->loopback_tx_pkt[i] = (char)i;
  491. val = smsc911x_reg_read(pdata, HW_CFG);
  492. val &= HW_CFG_TX_FIF_SZ_;
  493. val |= HW_CFG_SF_;
  494. smsc911x_reg_write(pdata, HW_CFG, val);
  495. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  496. smsc911x_reg_write(pdata, RX_CFG,
  497. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  498. for (i = 0; i < 10; i++) {
  499. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  500. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  501. BMCR_LOOPBACK | BMCR_FULLDPLX);
  502. /* Enable MAC tx/rx, FD */
  503. spin_lock_irqsave(&pdata->mac_lock, flags);
  504. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  505. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  506. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  507. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  508. result = 0;
  509. break;
  510. }
  511. pdata->resetcount++;
  512. /* Disable MAC rx */
  513. spin_lock_irqsave(&pdata->mac_lock, flags);
  514. smsc911x_mac_write(pdata, MAC_CR, 0);
  515. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  516. smsc911x_phy_reset(pdata);
  517. }
  518. /* Disable MAC */
  519. spin_lock_irqsave(&pdata->mac_lock, flags);
  520. smsc911x_mac_write(pdata, MAC_CR, 0);
  521. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  522. /* Cancel PHY loopback mode */
  523. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  524. smsc911x_reg_write(pdata, TX_CFG, 0);
  525. smsc911x_reg_write(pdata, RX_CFG, 0);
  526. return result;
  527. }
  528. #endif /* USE_PHY_WORK_AROUND */
  529. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  530. {
  531. struct phy_device *phy_dev = pdata->phy_dev;
  532. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  533. u32 flow;
  534. unsigned long flags;
  535. if (phy_dev->duplex == DUPLEX_FULL) {
  536. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  537. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  538. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  539. if (cap & FLOW_CTRL_RX)
  540. flow = 0xFFFF0002;
  541. else
  542. flow = 0;
  543. if (cap & FLOW_CTRL_TX)
  544. afc |= 0xF;
  545. else
  546. afc &= ~0xF;
  547. SMSC_TRACE(HW, "rx pause %s, tx pause %s",
  548. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  549. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  550. } else {
  551. SMSC_TRACE(HW, "half duplex");
  552. flow = 0;
  553. afc |= 0xF;
  554. }
  555. spin_lock_irqsave(&pdata->mac_lock, flags);
  556. smsc911x_mac_write(pdata, FLOW, flow);
  557. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  558. smsc911x_reg_write(pdata, AFC_CFG, afc);
  559. }
  560. /* Update link mode if anything has changed. Called periodically when the
  561. * PHY is in polling mode, even if nothing has changed. */
  562. static void smsc911x_phy_adjust_link(struct net_device *dev)
  563. {
  564. struct smsc911x_data *pdata = netdev_priv(dev);
  565. struct phy_device *phy_dev = pdata->phy_dev;
  566. unsigned long flags;
  567. int carrier;
  568. if (phy_dev->duplex != pdata->last_duplex) {
  569. unsigned int mac_cr;
  570. SMSC_TRACE(HW, "duplex state has changed");
  571. spin_lock_irqsave(&pdata->mac_lock, flags);
  572. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  573. if (phy_dev->duplex) {
  574. SMSC_TRACE(HW,
  575. "configuring for full duplex mode");
  576. mac_cr |= MAC_CR_FDPX_;
  577. } else {
  578. SMSC_TRACE(HW,
  579. "configuring for half duplex mode");
  580. mac_cr &= ~MAC_CR_FDPX_;
  581. }
  582. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  583. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  584. smsc911x_phy_update_flowcontrol(pdata);
  585. pdata->last_duplex = phy_dev->duplex;
  586. }
  587. carrier = netif_carrier_ok(dev);
  588. if (carrier != pdata->last_carrier) {
  589. SMSC_TRACE(HW, "carrier state has changed");
  590. if (carrier) {
  591. SMSC_TRACE(HW, "configuring for carrier OK");
  592. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  593. (!pdata->using_extphy)) {
  594. /* Restore orginal GPIO configuration */
  595. pdata->gpio_setting = pdata->gpio_orig_setting;
  596. smsc911x_reg_write(pdata, GPIO_CFG,
  597. pdata->gpio_setting);
  598. }
  599. } else {
  600. SMSC_TRACE(HW, "configuring for no carrier");
  601. /* Check global setting that LED1
  602. * usage is 10/100 indicator */
  603. pdata->gpio_setting = smsc911x_reg_read(pdata,
  604. GPIO_CFG);
  605. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
  606. && (!pdata->using_extphy)) {
  607. /* Force 10/100 LED off, after saving
  608. * orginal GPIO configuration */
  609. pdata->gpio_orig_setting = pdata->gpio_setting;
  610. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  611. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  612. | GPIO_CFG_GPIODIR0_
  613. | GPIO_CFG_GPIOD0_);
  614. smsc911x_reg_write(pdata, GPIO_CFG,
  615. pdata->gpio_setting);
  616. }
  617. }
  618. pdata->last_carrier = carrier;
  619. }
  620. }
  621. static int smsc911x_mii_probe(struct net_device *dev)
  622. {
  623. struct smsc911x_data *pdata = netdev_priv(dev);
  624. struct phy_device *phydev = NULL;
  625. int phy_addr;
  626. /* find the first phy */
  627. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  628. if (pdata->mii_bus->phy_map[phy_addr]) {
  629. phydev = pdata->mii_bus->phy_map[phy_addr];
  630. SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
  631. phy_addr, phydev->addr, phydev->phy_id);
  632. break;
  633. }
  634. }
  635. if (!phydev) {
  636. pr_err("%s: no PHY found\n", dev->name);
  637. return -ENODEV;
  638. }
  639. phydev = phy_connect(dev, dev_name(&phydev->dev),
  640. &smsc911x_phy_adjust_link, 0, pdata->config.phy_interface);
  641. if (IS_ERR(phydev)) {
  642. pr_err("%s: Could not attach to PHY\n", dev->name);
  643. return PTR_ERR(phydev);
  644. }
  645. pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  646. dev->name, phydev->drv->name,
  647. dev_name(&phydev->dev), phydev->irq);
  648. /* mask with MAC supported features */
  649. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  650. SUPPORTED_Asym_Pause);
  651. phydev->advertising = phydev->supported;
  652. pdata->phy_dev = phydev;
  653. pdata->last_duplex = -1;
  654. pdata->last_carrier = -1;
  655. #ifdef USE_PHY_WORK_AROUND
  656. if (smsc911x_phy_loopbacktest(dev) < 0) {
  657. SMSC_WARNING(HW, "Failed Loop Back Test");
  658. return -ENODEV;
  659. }
  660. SMSC_TRACE(HW, "Passed Loop Back Test");
  661. #endif /* USE_PHY_WORK_AROUND */
  662. SMSC_TRACE(HW, "phy initialised succesfully");
  663. return 0;
  664. }
  665. static int __devinit smsc911x_mii_init(struct platform_device *pdev,
  666. struct net_device *dev)
  667. {
  668. struct smsc911x_data *pdata = netdev_priv(dev);
  669. int err = -ENXIO, i;
  670. pdata->mii_bus = mdiobus_alloc();
  671. if (!pdata->mii_bus) {
  672. err = -ENOMEM;
  673. goto err_out_1;
  674. }
  675. pdata->mii_bus->name = SMSC_MDIONAME;
  676. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  677. pdata->mii_bus->priv = pdata;
  678. pdata->mii_bus->read = smsc911x_mii_read;
  679. pdata->mii_bus->write = smsc911x_mii_write;
  680. pdata->mii_bus->irq = pdata->phy_irq;
  681. for (i = 0; i < PHY_MAX_ADDR; ++i)
  682. pdata->mii_bus->irq[i] = PHY_POLL;
  683. pdata->mii_bus->parent = &pdev->dev;
  684. pdata->using_extphy = 0;
  685. switch (pdata->idrev & 0xFFFF0000) {
  686. case 0x01170000:
  687. case 0x01150000:
  688. case 0x117A0000:
  689. case 0x115A0000:
  690. /* External PHY supported, try to autodetect */
  691. if (smsc911x_phy_initialise_external(pdata) < 0) {
  692. SMSC_TRACE(HW, "No external PHY detected, "
  693. "using internal PHY");
  694. }
  695. break;
  696. default:
  697. SMSC_TRACE(HW, "External PHY is not supported, "
  698. "using internal PHY");
  699. break;
  700. }
  701. if (!pdata->using_extphy) {
  702. /* Mask all PHYs except ID 1 (internal) */
  703. pdata->mii_bus->phy_mask = ~(1 << 1);
  704. }
  705. if (mdiobus_register(pdata->mii_bus)) {
  706. SMSC_WARNING(PROBE, "Error registering mii bus");
  707. goto err_out_free_bus_2;
  708. }
  709. if (smsc911x_mii_probe(dev) < 0) {
  710. SMSC_WARNING(PROBE, "Error registering mii bus");
  711. goto err_out_unregister_bus_3;
  712. }
  713. return 0;
  714. err_out_unregister_bus_3:
  715. mdiobus_unregister(pdata->mii_bus);
  716. err_out_free_bus_2:
  717. mdiobus_free(pdata->mii_bus);
  718. err_out_1:
  719. return err;
  720. }
  721. /* Gets the number of tx statuses in the fifo */
  722. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  723. {
  724. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  725. & TX_FIFO_INF_TSUSED_) >> 16;
  726. }
  727. /* Reads tx statuses and increments counters where necessary */
  728. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  729. {
  730. struct smsc911x_data *pdata = netdev_priv(dev);
  731. unsigned int tx_stat;
  732. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  733. if (unlikely(tx_stat & 0x80000000)) {
  734. /* In this driver the packet tag is used as the packet
  735. * length. Since a packet length can never reach the
  736. * size of 0x8000, this bit is reserved. It is worth
  737. * noting that the "reserved bit" in the warning above
  738. * does not reference a hardware defined reserved bit
  739. * but rather a driver defined one.
  740. */
  741. SMSC_WARNING(HW,
  742. "Packet tag reserved bit is high");
  743. } else {
  744. if (unlikely(tx_stat & 0x00008000)) {
  745. dev->stats.tx_errors++;
  746. } else {
  747. dev->stats.tx_packets++;
  748. dev->stats.tx_bytes += (tx_stat >> 16);
  749. }
  750. if (unlikely(tx_stat & 0x00000100)) {
  751. dev->stats.collisions += 16;
  752. dev->stats.tx_aborted_errors += 1;
  753. } else {
  754. dev->stats.collisions +=
  755. ((tx_stat >> 3) & 0xF);
  756. }
  757. if (unlikely(tx_stat & 0x00000800))
  758. dev->stats.tx_carrier_errors += 1;
  759. if (unlikely(tx_stat & 0x00000200)) {
  760. dev->stats.collisions++;
  761. dev->stats.tx_aborted_errors++;
  762. }
  763. }
  764. }
  765. }
  766. /* Increments the Rx error counters */
  767. static void
  768. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  769. {
  770. int crc_err = 0;
  771. if (unlikely(rxstat & 0x00008000)) {
  772. dev->stats.rx_errors++;
  773. if (unlikely(rxstat & 0x00000002)) {
  774. dev->stats.rx_crc_errors++;
  775. crc_err = 1;
  776. }
  777. }
  778. if (likely(!crc_err)) {
  779. if (unlikely((rxstat & 0x00001020) == 0x00001020)) {
  780. /* Frame type indicates length,
  781. * and length error is set */
  782. dev->stats.rx_length_errors++;
  783. }
  784. if (rxstat & RX_STS_MCAST_)
  785. dev->stats.multicast++;
  786. }
  787. }
  788. /* Quickly dumps bad packets */
  789. static void
  790. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
  791. {
  792. unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
  793. if (likely(pktwords >= 4)) {
  794. unsigned int timeout = 500;
  795. unsigned int val;
  796. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  797. do {
  798. udelay(1);
  799. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  800. } while (--timeout && (val & RX_DP_CTRL_RX_FFWD_));
  801. if (unlikely(timeout == 0))
  802. SMSC_WARNING(HW, "Timed out waiting for "
  803. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  804. } else {
  805. unsigned int temp;
  806. while (pktwords--)
  807. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  808. }
  809. }
  810. /* NAPI poll function */
  811. static int smsc911x_poll(struct napi_struct *napi, int budget)
  812. {
  813. struct smsc911x_data *pdata =
  814. container_of(napi, struct smsc911x_data, napi);
  815. struct net_device *dev = pdata->dev;
  816. int npackets = 0;
  817. while (likely(netif_running(dev)) && (npackets < budget)) {
  818. unsigned int pktlength;
  819. unsigned int pktwords;
  820. struct sk_buff *skb;
  821. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  822. if (!rxstat) {
  823. unsigned int temp;
  824. /* We processed all packets available. Tell NAPI it can
  825. * stop polling then re-enable rx interrupts */
  826. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  827. netif_rx_complete(napi);
  828. temp = smsc911x_reg_read(pdata, INT_EN);
  829. temp |= INT_EN_RSFL_EN_;
  830. smsc911x_reg_write(pdata, INT_EN, temp);
  831. break;
  832. }
  833. /* Count packet for NAPI scheduling, even if it has an error.
  834. * Error packets still require cycles to discard */
  835. npackets++;
  836. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  837. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  838. smsc911x_rx_counterrors(dev, rxstat);
  839. if (unlikely(rxstat & RX_STS_ES_)) {
  840. SMSC_WARNING(RX_ERR,
  841. "Discarding packet with error bit set");
  842. /* Packet has an error, discard it and continue with
  843. * the next */
  844. smsc911x_rx_fastforward(pdata, pktwords);
  845. dev->stats.rx_dropped++;
  846. continue;
  847. }
  848. skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
  849. if (unlikely(!skb)) {
  850. SMSC_WARNING(RX_ERR,
  851. "Unable to allocate skb for rx packet");
  852. /* Drop the packet and stop this polling iteration */
  853. smsc911x_rx_fastforward(pdata, pktwords);
  854. dev->stats.rx_dropped++;
  855. break;
  856. }
  857. skb->data = skb->head;
  858. skb_reset_tail_pointer(skb);
  859. /* Align IP on 16B boundary */
  860. skb_reserve(skb, NET_IP_ALIGN);
  861. skb_put(skb, pktlength - 4);
  862. smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
  863. pktwords);
  864. skb->protocol = eth_type_trans(skb, dev);
  865. skb->ip_summed = CHECKSUM_NONE;
  866. netif_receive_skb(skb);
  867. /* Update counters */
  868. dev->stats.rx_packets++;
  869. dev->stats.rx_bytes += (pktlength - 4);
  870. dev->last_rx = jiffies;
  871. }
  872. /* Return total received packets */
  873. return npackets;
  874. }
  875. /* Returns hash bit number for given MAC address
  876. * Example:
  877. * 01 00 5E 00 00 01 -> returns bit number 31 */
  878. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  879. {
  880. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  881. }
  882. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  883. {
  884. /* Performs the multicast & mac_cr update. This is called when
  885. * safe on the current hardware, and with the mac_lock held */
  886. unsigned int mac_cr;
  887. SMSC_ASSERT_MAC_LOCK(pdata);
  888. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  889. mac_cr |= pdata->set_bits_mask;
  890. mac_cr &= ~(pdata->clear_bits_mask);
  891. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  892. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  893. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  894. SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  895. mac_cr, pdata->hashhi, pdata->hashlo);
  896. }
  897. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  898. {
  899. unsigned int mac_cr;
  900. /* This function is only called for older LAN911x devices
  901. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  902. * be modified during Rx - newer devices immediately update the
  903. * registers.
  904. *
  905. * This is called from interrupt context */
  906. spin_lock(&pdata->mac_lock);
  907. /* Check Rx has stopped */
  908. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  909. SMSC_WARNING(DRV, "Rx not stopped");
  910. /* Perform the update - safe to do now Rx has stopped */
  911. smsc911x_rx_multicast_update(pdata);
  912. /* Re-enable Rx */
  913. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  914. mac_cr |= MAC_CR_RXEN_;
  915. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  916. pdata->multicast_update_pending = 0;
  917. spin_unlock(&pdata->mac_lock);
  918. }
  919. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  920. {
  921. unsigned int timeout;
  922. unsigned int temp;
  923. /* Reset the LAN911x */
  924. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  925. timeout = 10;
  926. do {
  927. udelay(10);
  928. temp = smsc911x_reg_read(pdata, HW_CFG);
  929. } while ((--timeout) && (temp & HW_CFG_SRST_));
  930. if (unlikely(temp & HW_CFG_SRST_)) {
  931. SMSC_WARNING(DRV, "Failed to complete reset");
  932. return -EIO;
  933. }
  934. return 0;
  935. }
  936. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  937. static void
  938. smsc911x_set_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  939. {
  940. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  941. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  942. (dev_addr[1] << 8) | dev_addr[0];
  943. SMSC_ASSERT_MAC_LOCK(pdata);
  944. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  945. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  946. }
  947. static int smsc911x_open(struct net_device *dev)
  948. {
  949. struct smsc911x_data *pdata = netdev_priv(dev);
  950. unsigned int timeout;
  951. unsigned int temp;
  952. unsigned int intcfg;
  953. /* if the phy is not yet registered, retry later*/
  954. if (!pdata->phy_dev) {
  955. SMSC_WARNING(HW, "phy_dev is NULL");
  956. return -EAGAIN;
  957. }
  958. if (!is_valid_ether_addr(dev->dev_addr)) {
  959. SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
  960. return -EADDRNOTAVAIL;
  961. }
  962. /* Reset the LAN911x */
  963. if (smsc911x_soft_reset(pdata)) {
  964. SMSC_WARNING(HW, "soft reset failed");
  965. return -EIO;
  966. }
  967. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  968. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  969. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  970. timeout = 50;
  971. while ((timeout--) &&
  972. (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
  973. udelay(10);
  974. }
  975. if (unlikely(timeout == 0))
  976. SMSC_WARNING(IFUP,
  977. "Timed out waiting for EEPROM busy bit to clear");
  978. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  979. /* The soft reset above cleared the device's MAC address,
  980. * restore it from local copy (set in probe) */
  981. spin_lock_irq(&pdata->mac_lock);
  982. smsc911x_set_mac_address(pdata, dev->dev_addr);
  983. spin_unlock_irq(&pdata->mac_lock);
  984. /* Initialise irqs, but leave all sources disabled */
  985. smsc911x_reg_write(pdata, INT_EN, 0);
  986. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  987. /* Set interrupt deassertion to 100uS */
  988. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  989. if (pdata->config.irq_polarity) {
  990. SMSC_TRACE(IFUP, "irq polarity: active high");
  991. intcfg |= INT_CFG_IRQ_POL_;
  992. } else {
  993. SMSC_TRACE(IFUP, "irq polarity: active low");
  994. }
  995. if (pdata->config.irq_type) {
  996. SMSC_TRACE(IFUP, "irq type: push-pull");
  997. intcfg |= INT_CFG_IRQ_TYPE_;
  998. } else {
  999. SMSC_TRACE(IFUP, "irq type: open drain");
  1000. }
  1001. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1002. SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
  1003. pdata->software_irq_signal = 0;
  1004. smp_wmb();
  1005. temp = smsc911x_reg_read(pdata, INT_EN);
  1006. temp |= INT_EN_SW_INT_EN_;
  1007. smsc911x_reg_write(pdata, INT_EN, temp);
  1008. timeout = 1000;
  1009. while (timeout--) {
  1010. if (pdata->software_irq_signal)
  1011. break;
  1012. msleep(1);
  1013. }
  1014. if (!pdata->software_irq_signal) {
  1015. dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
  1016. dev->irq);
  1017. return -ENODEV;
  1018. }
  1019. SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
  1020. dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1021. (unsigned long)pdata->ioaddr, dev->irq);
  1022. /* Reset the last known duplex and carrier */
  1023. pdata->last_duplex = -1;
  1024. pdata->last_carrier = -1;
  1025. /* Bring the PHY up */
  1026. phy_start(pdata->phy_dev);
  1027. temp = smsc911x_reg_read(pdata, HW_CFG);
  1028. /* Preserve TX FIFO size and external PHY configuration */
  1029. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1030. temp |= HW_CFG_SF_;
  1031. smsc911x_reg_write(pdata, HW_CFG, temp);
  1032. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1033. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1034. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1035. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1036. /* set RX Data offset to 2 bytes for alignment */
  1037. smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
  1038. /* enable NAPI polling before enabling RX interrupts */
  1039. napi_enable(&pdata->napi);
  1040. temp = smsc911x_reg_read(pdata, INT_EN);
  1041. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_);
  1042. smsc911x_reg_write(pdata, INT_EN, temp);
  1043. spin_lock_irq(&pdata->mac_lock);
  1044. temp = smsc911x_mac_read(pdata, MAC_CR);
  1045. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1046. smsc911x_mac_write(pdata, MAC_CR, temp);
  1047. spin_unlock_irq(&pdata->mac_lock);
  1048. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1049. netif_start_queue(dev);
  1050. return 0;
  1051. }
  1052. /* Entry point for stopping the interface */
  1053. static int smsc911x_stop(struct net_device *dev)
  1054. {
  1055. struct smsc911x_data *pdata = netdev_priv(dev);
  1056. unsigned int temp;
  1057. /* Disable all device interrupts */
  1058. temp = smsc911x_reg_read(pdata, INT_CFG);
  1059. temp &= ~INT_CFG_IRQ_EN_;
  1060. smsc911x_reg_write(pdata, INT_CFG, temp);
  1061. /* Stop Tx and Rx polling */
  1062. netif_stop_queue(dev);
  1063. napi_disable(&pdata->napi);
  1064. /* At this point all Rx and Tx activity is stopped */
  1065. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1066. smsc911x_tx_update_txcounters(dev);
  1067. /* Bring the PHY down */
  1068. if (pdata->phy_dev)
  1069. phy_stop(pdata->phy_dev);
  1070. SMSC_TRACE(IFDOWN, "Interface stopped");
  1071. return 0;
  1072. }
  1073. /* Entry point for transmitting a packet */
  1074. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1075. {
  1076. struct smsc911x_data *pdata = netdev_priv(dev);
  1077. unsigned int freespace;
  1078. unsigned int tx_cmd_a;
  1079. unsigned int tx_cmd_b;
  1080. unsigned int temp;
  1081. u32 wrsz;
  1082. ulong bufp;
  1083. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1084. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1085. SMSC_WARNING(TX_ERR,
  1086. "Tx data fifo low, space available: %d", freespace);
  1087. /* Word alignment adjustment */
  1088. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1089. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1090. tx_cmd_a |= (unsigned int)skb->len;
  1091. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1092. tx_cmd_b |= (unsigned int)skb->len;
  1093. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1094. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1095. bufp = (ulong)skb->data & (~0x3);
  1096. wrsz = (u32)skb->len + 3;
  1097. wrsz += (u32)((ulong)skb->data & 0x3);
  1098. wrsz >>= 2;
  1099. smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1100. freespace -= (skb->len + 32);
  1101. dev_kfree_skb(skb);
  1102. dev->trans_start = jiffies;
  1103. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1104. smsc911x_tx_update_txcounters(dev);
  1105. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1106. netif_stop_queue(dev);
  1107. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1108. temp &= 0x00FFFFFF;
  1109. temp |= 0x32000000;
  1110. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1111. }
  1112. return NETDEV_TX_OK;
  1113. }
  1114. /* Entry point for getting status counters */
  1115. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1116. {
  1117. struct smsc911x_data *pdata = netdev_priv(dev);
  1118. smsc911x_tx_update_txcounters(dev);
  1119. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1120. return &dev->stats;
  1121. }
  1122. /* Entry point for setting addressing modes */
  1123. static void smsc911x_set_multicast_list(struct net_device *dev)
  1124. {
  1125. struct smsc911x_data *pdata = netdev_priv(dev);
  1126. unsigned long flags;
  1127. if (dev->flags & IFF_PROMISC) {
  1128. /* Enabling promiscuous mode */
  1129. pdata->set_bits_mask = MAC_CR_PRMS_;
  1130. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1131. pdata->hashhi = 0;
  1132. pdata->hashlo = 0;
  1133. } else if (dev->flags & IFF_ALLMULTI) {
  1134. /* Enabling all multicast mode */
  1135. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1136. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1137. pdata->hashhi = 0;
  1138. pdata->hashlo = 0;
  1139. } else if (dev->mc_count > 0) {
  1140. /* Enabling specific multicast addresses */
  1141. unsigned int hash_high = 0;
  1142. unsigned int hash_low = 0;
  1143. unsigned int count = 0;
  1144. struct dev_mc_list *mc_list = dev->mc_list;
  1145. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1146. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1147. while (mc_list) {
  1148. count++;
  1149. if ((mc_list->dmi_addrlen) == ETH_ALEN) {
  1150. unsigned int bitnum =
  1151. smsc911x_hash(mc_list->dmi_addr);
  1152. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1153. if (bitnum & 0x20)
  1154. hash_high |= mask;
  1155. else
  1156. hash_low |= mask;
  1157. } else {
  1158. SMSC_WARNING(DRV, "dmi_addrlen != 6");
  1159. }
  1160. mc_list = mc_list->next;
  1161. }
  1162. if (count != (unsigned int)dev->mc_count)
  1163. SMSC_WARNING(DRV, "mc_count != dev->mc_count");
  1164. pdata->hashhi = hash_high;
  1165. pdata->hashlo = hash_low;
  1166. } else {
  1167. /* Enabling local MAC address only */
  1168. pdata->set_bits_mask = 0;
  1169. pdata->clear_bits_mask =
  1170. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1171. pdata->hashhi = 0;
  1172. pdata->hashlo = 0;
  1173. }
  1174. spin_lock_irqsave(&pdata->mac_lock, flags);
  1175. if (pdata->generation <= 1) {
  1176. /* Older hardware revision - cannot change these flags while
  1177. * receiving data */
  1178. if (!pdata->multicast_update_pending) {
  1179. unsigned int temp;
  1180. SMSC_TRACE(HW, "scheduling mcast update");
  1181. pdata->multicast_update_pending = 1;
  1182. /* Request the hardware to stop, then perform the
  1183. * update when we get an RX_STOP interrupt */
  1184. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1185. temp = smsc911x_reg_read(pdata, INT_EN);
  1186. temp |= INT_EN_RXSTOP_INT_EN_;
  1187. smsc911x_reg_write(pdata, INT_EN, temp);
  1188. temp = smsc911x_mac_read(pdata, MAC_CR);
  1189. temp &= ~(MAC_CR_RXEN_);
  1190. smsc911x_mac_write(pdata, MAC_CR, temp);
  1191. } else {
  1192. /* There is another update pending, this should now
  1193. * use the newer values */
  1194. }
  1195. } else {
  1196. /* Newer hardware revision - can write immediately */
  1197. smsc911x_rx_multicast_update(pdata);
  1198. }
  1199. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1200. }
  1201. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1202. {
  1203. struct net_device *dev = dev_id;
  1204. struct smsc911x_data *pdata = netdev_priv(dev);
  1205. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1206. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1207. int serviced = IRQ_NONE;
  1208. u32 temp;
  1209. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1210. temp = smsc911x_reg_read(pdata, INT_EN);
  1211. temp &= (~INT_EN_SW_INT_EN_);
  1212. smsc911x_reg_write(pdata, INT_EN, temp);
  1213. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1214. pdata->software_irq_signal = 1;
  1215. smp_wmb();
  1216. serviced = IRQ_HANDLED;
  1217. }
  1218. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1219. /* Called when there is a multicast update scheduled and
  1220. * it is now safe to complete the update */
  1221. SMSC_TRACE(INTR, "RX Stop interrupt");
  1222. temp = smsc911x_reg_read(pdata, INT_EN);
  1223. temp &= (~INT_EN_RXSTOP_INT_EN_);
  1224. smsc911x_reg_write(pdata, INT_EN, temp);
  1225. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1226. smsc911x_rx_multicast_update_workaround(pdata);
  1227. serviced = IRQ_HANDLED;
  1228. }
  1229. if (intsts & inten & INT_STS_TDFA_) {
  1230. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1231. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1232. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1233. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1234. netif_wake_queue(dev);
  1235. serviced = IRQ_HANDLED;
  1236. }
  1237. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1238. SMSC_TRACE(INTR, "RX Error interrupt");
  1239. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1240. serviced = IRQ_HANDLED;
  1241. }
  1242. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1243. if (likely(netif_rx_schedule_prep(&pdata->napi))) {
  1244. /* Disable Rx interrupts */
  1245. temp = smsc911x_reg_read(pdata, INT_EN);
  1246. temp &= (~INT_EN_RSFL_EN_);
  1247. smsc911x_reg_write(pdata, INT_EN, temp);
  1248. /* Schedule a NAPI poll */
  1249. __netif_rx_schedule(&pdata->napi);
  1250. } else {
  1251. SMSC_WARNING(RX_ERR,
  1252. "netif_rx_schedule_prep failed");
  1253. }
  1254. serviced = IRQ_HANDLED;
  1255. }
  1256. return serviced;
  1257. }
  1258. #ifdef CONFIG_NET_POLL_CONTROLLER
  1259. static void smsc911x_poll_controller(struct net_device *dev)
  1260. {
  1261. disable_irq(dev->irq);
  1262. smsc911x_irqhandler(0, dev);
  1263. enable_irq(dev->irq);
  1264. }
  1265. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1266. /* Standard ioctls for mii-tool */
  1267. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1268. {
  1269. struct smsc911x_data *pdata = netdev_priv(dev);
  1270. if (!netif_running(dev) || !pdata->phy_dev)
  1271. return -EINVAL;
  1272. return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
  1273. }
  1274. static int
  1275. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1276. {
  1277. struct smsc911x_data *pdata = netdev_priv(dev);
  1278. cmd->maxtxpkt = 1;
  1279. cmd->maxrxpkt = 1;
  1280. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1281. }
  1282. static int
  1283. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1284. {
  1285. struct smsc911x_data *pdata = netdev_priv(dev);
  1286. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1287. }
  1288. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1289. struct ethtool_drvinfo *info)
  1290. {
  1291. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1292. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1293. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1294. sizeof(info->bus_info));
  1295. }
  1296. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1297. {
  1298. struct smsc911x_data *pdata = netdev_priv(dev);
  1299. return phy_start_aneg(pdata->phy_dev);
  1300. }
  1301. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1302. {
  1303. struct smsc911x_data *pdata = netdev_priv(dev);
  1304. return pdata->msg_enable;
  1305. }
  1306. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1307. {
  1308. struct smsc911x_data *pdata = netdev_priv(dev);
  1309. pdata->msg_enable = level;
  1310. }
  1311. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1312. {
  1313. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1314. sizeof(u32);
  1315. }
  1316. static void
  1317. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1318. void *buf)
  1319. {
  1320. struct smsc911x_data *pdata = netdev_priv(dev);
  1321. struct phy_device *phy_dev = pdata->phy_dev;
  1322. unsigned long flags;
  1323. unsigned int i;
  1324. unsigned int j = 0;
  1325. u32 *data = buf;
  1326. regs->version = pdata->idrev;
  1327. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1328. data[j++] = smsc911x_reg_read(pdata, i);
  1329. for (i = MAC_CR; i <= WUCSR; i++) {
  1330. spin_lock_irqsave(&pdata->mac_lock, flags);
  1331. data[j++] = smsc911x_mac_read(pdata, i);
  1332. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1333. }
  1334. for (i = 0; i <= 31; i++)
  1335. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1336. }
  1337. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1338. {
  1339. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1340. temp &= ~GPIO_CFG_EEPR_EN_;
  1341. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1342. msleep(1);
  1343. }
  1344. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1345. {
  1346. int timeout = 100;
  1347. u32 e2cmd;
  1348. SMSC_TRACE(DRV, "op 0x%08x", op);
  1349. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1350. SMSC_WARNING(DRV, "Busy at start");
  1351. return -EBUSY;
  1352. }
  1353. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1354. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1355. do {
  1356. msleep(1);
  1357. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1358. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1359. if (!timeout) {
  1360. SMSC_TRACE(DRV, "TIMED OUT");
  1361. return -EAGAIN;
  1362. }
  1363. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1364. SMSC_TRACE(DRV, "Error occured during eeprom operation");
  1365. return -EINVAL;
  1366. }
  1367. return 0;
  1368. }
  1369. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1370. u8 address, u8 *data)
  1371. {
  1372. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1373. int ret;
  1374. SMSC_TRACE(DRV, "address 0x%x", address);
  1375. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1376. if (!ret)
  1377. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1378. return ret;
  1379. }
  1380. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1381. u8 address, u8 data)
  1382. {
  1383. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1384. int ret;
  1385. SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
  1386. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1387. if (!ret) {
  1388. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1389. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1390. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1391. }
  1392. return ret;
  1393. }
  1394. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1395. {
  1396. return SMSC911X_EEPROM_SIZE;
  1397. }
  1398. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1399. struct ethtool_eeprom *eeprom, u8 *data)
  1400. {
  1401. struct smsc911x_data *pdata = netdev_priv(dev);
  1402. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1403. int len;
  1404. int i;
  1405. smsc911x_eeprom_enable_access(pdata);
  1406. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1407. for (i = 0; i < len; i++) {
  1408. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1409. if (ret < 0) {
  1410. eeprom->len = 0;
  1411. return ret;
  1412. }
  1413. }
  1414. memcpy(data, &eeprom_data[eeprom->offset], len);
  1415. eeprom->len = len;
  1416. return 0;
  1417. }
  1418. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1419. struct ethtool_eeprom *eeprom, u8 *data)
  1420. {
  1421. int ret;
  1422. struct smsc911x_data *pdata = netdev_priv(dev);
  1423. smsc911x_eeprom_enable_access(pdata);
  1424. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1425. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1426. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1427. /* Single byte write, according to man page */
  1428. eeprom->len = 1;
  1429. return ret;
  1430. }
  1431. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1432. .get_settings = smsc911x_ethtool_getsettings,
  1433. .set_settings = smsc911x_ethtool_setsettings,
  1434. .get_link = ethtool_op_get_link,
  1435. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1436. .nway_reset = smsc911x_ethtool_nwayreset,
  1437. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1438. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1439. .get_regs_len = smsc911x_ethtool_getregslen,
  1440. .get_regs = smsc911x_ethtool_getregs,
  1441. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1442. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1443. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1444. };
  1445. static const struct net_device_ops smsc911x_netdev_ops = {
  1446. .ndo_open = smsc911x_open,
  1447. .ndo_stop = smsc911x_stop,
  1448. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1449. .ndo_get_stats = smsc911x_get_stats,
  1450. .ndo_set_multicast_list = smsc911x_set_multicast_list,
  1451. .ndo_do_ioctl = smsc911x_do_ioctl,
  1452. .ndo_validate_addr = eth_validate_addr,
  1453. .ndo_set_mac_address = eth_mac_addr,
  1454. #ifdef CONFIG_NET_POLL_CONTROLLER
  1455. .ndo_poll_controller = smsc911x_poll_controller,
  1456. #endif
  1457. };
  1458. /* Initializing private device structures, only called from probe */
  1459. static int __devinit smsc911x_init(struct net_device *dev)
  1460. {
  1461. struct smsc911x_data *pdata = netdev_priv(dev);
  1462. unsigned int byte_test;
  1463. SMSC_TRACE(PROBE, "Driver Parameters:");
  1464. SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
  1465. (unsigned long)pdata->ioaddr);
  1466. SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
  1467. SMSC_TRACE(PROBE, "PHY will be autodetected.");
  1468. spin_lock_init(&pdata->dev_lock);
  1469. if (pdata->ioaddr == 0) {
  1470. SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
  1471. return -ENODEV;
  1472. }
  1473. /* Check byte ordering */
  1474. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1475. SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
  1476. if (byte_test == 0x43218765) {
  1477. SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
  1478. "applying WORD_SWAP");
  1479. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1480. /* 1 dummy read of BYTE_TEST is needed after a write to
  1481. * WORD_SWAP before its contents are valid */
  1482. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1483. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1484. }
  1485. if (byte_test != 0x87654321) {
  1486. SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
  1487. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1488. SMSC_WARNING(PROBE,
  1489. "top 16 bits equal to bottom 16 bits");
  1490. SMSC_TRACE(PROBE, "This may mean the chip is set "
  1491. "for 32 bit while the bus is reading 16 bit");
  1492. }
  1493. return -ENODEV;
  1494. }
  1495. /* Default generation to zero (all workarounds apply) */
  1496. pdata->generation = 0;
  1497. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1498. switch (pdata->idrev & 0xFFFF0000) {
  1499. case 0x01180000:
  1500. case 0x01170000:
  1501. case 0x01160000:
  1502. case 0x01150000:
  1503. /* LAN911[5678] family */
  1504. pdata->generation = pdata->idrev & 0x0000FFFF;
  1505. break;
  1506. case 0x118A0000:
  1507. case 0x117A0000:
  1508. case 0x116A0000:
  1509. case 0x115A0000:
  1510. /* LAN921[5678] family */
  1511. pdata->generation = 3;
  1512. break;
  1513. case 0x92100000:
  1514. case 0x92110000:
  1515. case 0x92200000:
  1516. case 0x92210000:
  1517. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1518. pdata->generation = 4;
  1519. break;
  1520. default:
  1521. SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
  1522. pdata->idrev);
  1523. return -ENODEV;
  1524. }
  1525. SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
  1526. pdata->idrev, pdata->generation);
  1527. if (pdata->generation == 0)
  1528. SMSC_WARNING(PROBE,
  1529. "This driver is not intended for this chip revision");
  1530. /* Reset the LAN911x */
  1531. if (smsc911x_soft_reset(pdata))
  1532. return -ENODEV;
  1533. /* Disable all interrupt sources until we bring the device up */
  1534. smsc911x_reg_write(pdata, INT_EN, 0);
  1535. ether_setup(dev);
  1536. dev->flags |= IFF_MULTICAST;
  1537. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1538. dev->netdev_ops = &smsc911x_netdev_ops;
  1539. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1540. return 0;
  1541. }
  1542. static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
  1543. {
  1544. struct net_device *dev;
  1545. struct smsc911x_data *pdata;
  1546. struct resource *res;
  1547. dev = platform_get_drvdata(pdev);
  1548. BUG_ON(!dev);
  1549. pdata = netdev_priv(dev);
  1550. BUG_ON(!pdata);
  1551. BUG_ON(!pdata->ioaddr);
  1552. BUG_ON(!pdata->phy_dev);
  1553. SMSC_TRACE(IFDOWN, "Stopping driver.");
  1554. phy_disconnect(pdata->phy_dev);
  1555. pdata->phy_dev = NULL;
  1556. mdiobus_unregister(pdata->mii_bus);
  1557. mdiobus_free(pdata->mii_bus);
  1558. platform_set_drvdata(pdev, NULL);
  1559. unregister_netdev(dev);
  1560. free_irq(dev->irq, dev);
  1561. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1562. "smsc911x-memory");
  1563. if (!res)
  1564. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1565. release_mem_region(res->start, res->end - res->start);
  1566. iounmap(pdata->ioaddr);
  1567. free_netdev(dev);
  1568. return 0;
  1569. }
  1570. static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
  1571. {
  1572. struct net_device *dev;
  1573. struct smsc911x_data *pdata;
  1574. struct smsc911x_platform_config *config = pdev->dev.platform_data;
  1575. struct resource *res;
  1576. unsigned int intcfg = 0;
  1577. int res_size;
  1578. int retval;
  1579. DECLARE_MAC_BUF(mac);
  1580. pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
  1581. /* platform data specifies irq & dynamic bus configuration */
  1582. if (!pdev->dev.platform_data) {
  1583. pr_warning("%s: platform_data not provided\n", SMSC_CHIPNAME);
  1584. retval = -ENODEV;
  1585. goto out_0;
  1586. }
  1587. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1588. "smsc911x-memory");
  1589. if (!res)
  1590. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1591. if (!res) {
  1592. pr_warning("%s: Could not allocate resource.\n",
  1593. SMSC_CHIPNAME);
  1594. retval = -ENODEV;
  1595. goto out_0;
  1596. }
  1597. res_size = res->end - res->start;
  1598. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1599. retval = -EBUSY;
  1600. goto out_0;
  1601. }
  1602. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1603. if (!dev) {
  1604. pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
  1605. retval = -ENOMEM;
  1606. goto out_release_io_1;
  1607. }
  1608. SET_NETDEV_DEV(dev, &pdev->dev);
  1609. pdata = netdev_priv(dev);
  1610. dev->irq = platform_get_irq(pdev, 0);
  1611. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1612. /* copy config parameters across to pdata */
  1613. memcpy(&pdata->config, config, sizeof(pdata->config));
  1614. pdata->dev = dev;
  1615. pdata->msg_enable = ((1 << debug) - 1);
  1616. if (pdata->ioaddr == NULL) {
  1617. SMSC_WARNING(PROBE,
  1618. "Error smsc911x base address invalid");
  1619. retval = -ENOMEM;
  1620. goto out_free_netdev_2;
  1621. }
  1622. retval = smsc911x_init(dev);
  1623. if (retval < 0)
  1624. goto out_unmap_io_3;
  1625. /* configure irq polarity and type before connecting isr */
  1626. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  1627. intcfg |= INT_CFG_IRQ_POL_;
  1628. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  1629. intcfg |= INT_CFG_IRQ_TYPE_;
  1630. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1631. /* Ensure interrupts are globally disabled before connecting ISR */
  1632. smsc911x_reg_write(pdata, INT_EN, 0);
  1633. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1634. retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED,
  1635. dev->name, dev);
  1636. if (retval) {
  1637. SMSC_WARNING(PROBE,
  1638. "Unable to claim requested irq: %d", dev->irq);
  1639. goto out_unmap_io_3;
  1640. }
  1641. platform_set_drvdata(pdev, dev);
  1642. retval = register_netdev(dev);
  1643. if (retval) {
  1644. SMSC_WARNING(PROBE,
  1645. "Error %i registering device", retval);
  1646. goto out_unset_drvdata_4;
  1647. } else {
  1648. SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
  1649. }
  1650. spin_lock_init(&pdata->mac_lock);
  1651. retval = smsc911x_mii_init(pdev, dev);
  1652. if (retval) {
  1653. SMSC_WARNING(PROBE,
  1654. "Error %i initialising mii", retval);
  1655. goto out_unregister_netdev_5;
  1656. }
  1657. spin_lock_irq(&pdata->mac_lock);
  1658. /* Check if mac address has been specified when bringing interface up */
  1659. if (is_valid_ether_addr(dev->dev_addr)) {
  1660. smsc911x_set_mac_address(pdata, dev->dev_addr);
  1661. SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
  1662. } else {
  1663. /* Try reading mac address from device. if EEPROM is present
  1664. * it will already have been set */
  1665. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1666. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1667. dev->dev_addr[0] = (u8)(mac_low32);
  1668. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1669. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1670. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1671. dev->dev_addr[4] = (u8)(mac_high16);
  1672. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1673. if (is_valid_ether_addr(dev->dev_addr)) {
  1674. /* eeprom values are valid so use them */
  1675. SMSC_TRACE(PROBE,
  1676. "Mac Address is read from LAN911x EEPROM");
  1677. } else {
  1678. /* eeprom values are invalid, generate random MAC */
  1679. random_ether_addr(dev->dev_addr);
  1680. smsc911x_set_mac_address(pdata, dev->dev_addr);
  1681. SMSC_TRACE(PROBE,
  1682. "MAC Address is set to random_ether_addr");
  1683. }
  1684. }
  1685. spin_unlock_irq(&pdata->mac_lock);
  1686. dev_info(&dev->dev, "MAC Address: %s\n",
  1687. print_mac(mac, dev->dev_addr));
  1688. return 0;
  1689. out_unregister_netdev_5:
  1690. unregister_netdev(dev);
  1691. out_unset_drvdata_4:
  1692. platform_set_drvdata(pdev, NULL);
  1693. free_irq(dev->irq, dev);
  1694. out_unmap_io_3:
  1695. iounmap(pdata->ioaddr);
  1696. out_free_netdev_2:
  1697. free_netdev(dev);
  1698. out_release_io_1:
  1699. release_mem_region(res->start, res->end - res->start);
  1700. out_0:
  1701. return retval;
  1702. }
  1703. static struct platform_driver smsc911x_driver = {
  1704. .probe = smsc911x_drv_probe,
  1705. .remove = smsc911x_drv_remove,
  1706. .driver = {
  1707. .name = SMSC_CHIPNAME,
  1708. },
  1709. };
  1710. /* Entry point for loading the module */
  1711. static int __init smsc911x_init_module(void)
  1712. {
  1713. return platform_driver_register(&smsc911x_driver);
  1714. }
  1715. /* entry point for unloading the module */
  1716. static void __exit smsc911x_cleanup_module(void)
  1717. {
  1718. platform_driver_unregister(&smsc911x_driver);
  1719. }
  1720. module_init(smsc911x_init_module);
  1721. module_exit(smsc911x_cleanup_module);