exynos_mct.c 14 KB

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  1. /* linux/arch/arm/mach-exynos4/mct.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * EXYNOS4 MCT(Multi-Core Timer) support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/sched.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/clockchips.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/delay.h>
  20. #include <linux/percpu.h>
  21. #include <linux/of.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/of_address.h>
  24. #include <linux/clocksource.h>
  25. #include <asm/localtimer.h>
  26. #include <asm/mach/time.h>
  27. #define EXYNOS4_MCTREG(x) (x)
  28. #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
  29. #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
  30. #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
  31. #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
  32. #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
  33. #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
  34. #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
  35. #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
  36. #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
  37. #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
  38. #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
  39. #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
  40. #define EXYNOS4_MCT_L_MASK (0xffffff00)
  41. #define MCT_L_TCNTB_OFFSET (0x00)
  42. #define MCT_L_ICNTB_OFFSET (0x08)
  43. #define MCT_L_TCON_OFFSET (0x20)
  44. #define MCT_L_INT_CSTAT_OFFSET (0x30)
  45. #define MCT_L_INT_ENB_OFFSET (0x34)
  46. #define MCT_L_WSTAT_OFFSET (0x40)
  47. #define MCT_G_TCON_START (1 << 8)
  48. #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
  49. #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
  50. #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
  51. #define MCT_L_TCON_INT_START (1 << 1)
  52. #define MCT_L_TCON_TIMER_START (1 << 0)
  53. #define TICK_BASE_CNT 1
  54. enum {
  55. MCT_INT_SPI,
  56. MCT_INT_PPI
  57. };
  58. enum {
  59. MCT_G0_IRQ,
  60. MCT_G1_IRQ,
  61. MCT_G2_IRQ,
  62. MCT_G3_IRQ,
  63. MCT_L0_IRQ,
  64. MCT_L1_IRQ,
  65. MCT_L2_IRQ,
  66. MCT_L3_IRQ,
  67. MCT_NR_IRQS,
  68. };
  69. static void __iomem *reg_base;
  70. static unsigned long clk_rate;
  71. static unsigned int mct_int_type;
  72. static int mct_irqs[MCT_NR_IRQS];
  73. struct mct_clock_event_device {
  74. struct clock_event_device *evt;
  75. unsigned long base;
  76. char name[10];
  77. };
  78. static void exynos4_mct_write(unsigned int value, unsigned long offset)
  79. {
  80. unsigned long stat_addr;
  81. u32 mask;
  82. u32 i;
  83. __raw_writel(value, reg_base + offset);
  84. if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
  85. stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
  86. switch (offset & EXYNOS4_MCT_L_MASK) {
  87. case MCT_L_TCON_OFFSET:
  88. mask = 1 << 3; /* L_TCON write status */
  89. break;
  90. case MCT_L_ICNTB_OFFSET:
  91. mask = 1 << 1; /* L_ICNTB write status */
  92. break;
  93. case MCT_L_TCNTB_OFFSET:
  94. mask = 1 << 0; /* L_TCNTB write status */
  95. break;
  96. default:
  97. return;
  98. }
  99. } else {
  100. switch (offset) {
  101. case EXYNOS4_MCT_G_TCON:
  102. stat_addr = EXYNOS4_MCT_G_WSTAT;
  103. mask = 1 << 16; /* G_TCON write status */
  104. break;
  105. case EXYNOS4_MCT_G_COMP0_L:
  106. stat_addr = EXYNOS4_MCT_G_WSTAT;
  107. mask = 1 << 0; /* G_COMP0_L write status */
  108. break;
  109. case EXYNOS4_MCT_G_COMP0_U:
  110. stat_addr = EXYNOS4_MCT_G_WSTAT;
  111. mask = 1 << 1; /* G_COMP0_U write status */
  112. break;
  113. case EXYNOS4_MCT_G_COMP0_ADD_INCR:
  114. stat_addr = EXYNOS4_MCT_G_WSTAT;
  115. mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
  116. break;
  117. case EXYNOS4_MCT_G_CNT_L:
  118. stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
  119. mask = 1 << 0; /* G_CNT_L write status */
  120. break;
  121. case EXYNOS4_MCT_G_CNT_U:
  122. stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
  123. mask = 1 << 1; /* G_CNT_U write status */
  124. break;
  125. default:
  126. return;
  127. }
  128. }
  129. /* Wait maximum 1 ms until written values are applied */
  130. for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
  131. if (__raw_readl(reg_base + stat_addr) & mask) {
  132. __raw_writel(mask, reg_base + stat_addr);
  133. return;
  134. }
  135. panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
  136. }
  137. /* Clocksource handling */
  138. static void exynos4_mct_frc_start(u32 hi, u32 lo)
  139. {
  140. u32 reg;
  141. exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
  142. exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
  143. reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
  144. reg |= MCT_G_TCON_START;
  145. exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
  146. }
  147. static cycle_t exynos4_frc_read(struct clocksource *cs)
  148. {
  149. unsigned int lo, hi;
  150. u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
  151. do {
  152. hi = hi2;
  153. lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
  154. hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
  155. } while (hi != hi2);
  156. return ((cycle_t)hi << 32) | lo;
  157. }
  158. static void exynos4_frc_resume(struct clocksource *cs)
  159. {
  160. exynos4_mct_frc_start(0, 0);
  161. }
  162. struct clocksource mct_frc = {
  163. .name = "mct-frc",
  164. .rating = 400,
  165. .read = exynos4_frc_read,
  166. .mask = CLOCKSOURCE_MASK(64),
  167. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  168. .resume = exynos4_frc_resume,
  169. };
  170. static void __init exynos4_clocksource_init(void)
  171. {
  172. exynos4_mct_frc_start(0, 0);
  173. if (clocksource_register_hz(&mct_frc, clk_rate))
  174. panic("%s: can't register clocksource\n", mct_frc.name);
  175. }
  176. static void exynos4_mct_comp0_stop(void)
  177. {
  178. unsigned int tcon;
  179. tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
  180. tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
  181. exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
  182. exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
  183. }
  184. static void exynos4_mct_comp0_start(enum clock_event_mode mode,
  185. unsigned long cycles)
  186. {
  187. unsigned int tcon;
  188. cycle_t comp_cycle;
  189. tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
  190. if (mode == CLOCK_EVT_MODE_PERIODIC) {
  191. tcon |= MCT_G_TCON_COMP0_AUTO_INC;
  192. exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
  193. }
  194. comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
  195. exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
  196. exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
  197. exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
  198. tcon |= MCT_G_TCON_COMP0_ENABLE;
  199. exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
  200. }
  201. static int exynos4_comp_set_next_event(unsigned long cycles,
  202. struct clock_event_device *evt)
  203. {
  204. exynos4_mct_comp0_start(evt->mode, cycles);
  205. return 0;
  206. }
  207. static void exynos4_comp_set_mode(enum clock_event_mode mode,
  208. struct clock_event_device *evt)
  209. {
  210. unsigned long cycles_per_jiffy;
  211. exynos4_mct_comp0_stop();
  212. switch (mode) {
  213. case CLOCK_EVT_MODE_PERIODIC:
  214. cycles_per_jiffy =
  215. (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
  216. exynos4_mct_comp0_start(mode, cycles_per_jiffy);
  217. break;
  218. case CLOCK_EVT_MODE_ONESHOT:
  219. case CLOCK_EVT_MODE_UNUSED:
  220. case CLOCK_EVT_MODE_SHUTDOWN:
  221. case CLOCK_EVT_MODE_RESUME:
  222. break;
  223. }
  224. }
  225. static struct clock_event_device mct_comp_device = {
  226. .name = "mct-comp",
  227. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  228. .rating = 250,
  229. .set_next_event = exynos4_comp_set_next_event,
  230. .set_mode = exynos4_comp_set_mode,
  231. };
  232. static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
  233. {
  234. struct clock_event_device *evt = dev_id;
  235. exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
  236. evt->event_handler(evt);
  237. return IRQ_HANDLED;
  238. }
  239. static struct irqaction mct_comp_event_irq = {
  240. .name = "mct_comp_irq",
  241. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  242. .handler = exynos4_mct_comp_isr,
  243. .dev_id = &mct_comp_device,
  244. };
  245. static void exynos4_clockevent_init(void)
  246. {
  247. mct_comp_device.cpumask = cpumask_of(0);
  248. clockevents_config_and_register(&mct_comp_device, clk_rate,
  249. 0xf, 0xffffffff);
  250. setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
  251. }
  252. #ifdef CONFIG_LOCAL_TIMERS
  253. static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
  254. /* Clock event handling */
  255. static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
  256. {
  257. unsigned long tmp;
  258. unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
  259. unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
  260. tmp = __raw_readl(reg_base + offset);
  261. if (tmp & mask) {
  262. tmp &= ~mask;
  263. exynos4_mct_write(tmp, offset);
  264. }
  265. }
  266. static void exynos4_mct_tick_start(unsigned long cycles,
  267. struct mct_clock_event_device *mevt)
  268. {
  269. unsigned long tmp;
  270. exynos4_mct_tick_stop(mevt);
  271. tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
  272. /* update interrupt count buffer */
  273. exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
  274. /* enable MCT tick interrupt */
  275. exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
  276. tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
  277. tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
  278. MCT_L_TCON_INTERVAL_MODE;
  279. exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
  280. }
  281. static int exynos4_tick_set_next_event(unsigned long cycles,
  282. struct clock_event_device *evt)
  283. {
  284. struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
  285. exynos4_mct_tick_start(cycles, mevt);
  286. return 0;
  287. }
  288. static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
  289. struct clock_event_device *evt)
  290. {
  291. struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
  292. unsigned long cycles_per_jiffy;
  293. exynos4_mct_tick_stop(mevt);
  294. switch (mode) {
  295. case CLOCK_EVT_MODE_PERIODIC:
  296. cycles_per_jiffy =
  297. (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
  298. exynos4_mct_tick_start(cycles_per_jiffy, mevt);
  299. break;
  300. case CLOCK_EVT_MODE_ONESHOT:
  301. case CLOCK_EVT_MODE_UNUSED:
  302. case CLOCK_EVT_MODE_SHUTDOWN:
  303. case CLOCK_EVT_MODE_RESUME:
  304. break;
  305. }
  306. }
  307. static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
  308. {
  309. struct clock_event_device *evt = mevt->evt;
  310. /*
  311. * This is for supporting oneshot mode.
  312. * Mct would generate interrupt periodically
  313. * without explicit stopping.
  314. */
  315. if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
  316. exynos4_mct_tick_stop(mevt);
  317. /* Clear the MCT tick interrupt */
  318. if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
  319. exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
  320. return 1;
  321. } else {
  322. return 0;
  323. }
  324. }
  325. static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
  326. {
  327. struct mct_clock_event_device *mevt = dev_id;
  328. struct clock_event_device *evt = mevt->evt;
  329. exynos4_mct_tick_clear(mevt);
  330. evt->event_handler(evt);
  331. return IRQ_HANDLED;
  332. }
  333. static struct irqaction mct_tick0_event_irq = {
  334. .name = "mct_tick0_irq",
  335. .flags = IRQF_TIMER | IRQF_NOBALANCING,
  336. .handler = exynos4_mct_tick_isr,
  337. };
  338. static struct irqaction mct_tick1_event_irq = {
  339. .name = "mct_tick1_irq",
  340. .flags = IRQF_TIMER | IRQF_NOBALANCING,
  341. .handler = exynos4_mct_tick_isr,
  342. };
  343. static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
  344. {
  345. struct mct_clock_event_device *mevt;
  346. unsigned int cpu = smp_processor_id();
  347. mevt = this_cpu_ptr(&percpu_mct_tick);
  348. mevt->evt = evt;
  349. mevt->base = EXYNOS4_MCT_L_BASE(cpu);
  350. sprintf(mevt->name, "mct_tick%d", cpu);
  351. evt->name = mevt->name;
  352. evt->cpumask = cpumask_of(cpu);
  353. evt->set_next_event = exynos4_tick_set_next_event;
  354. evt->set_mode = exynos4_tick_set_mode;
  355. evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
  356. evt->rating = 450;
  357. clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
  358. 0xf, 0x7fffffff);
  359. exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
  360. if (mct_int_type == MCT_INT_SPI) {
  361. if (cpu == 0) {
  362. mct_tick0_event_irq.dev_id = mevt;
  363. evt->irq = mct_irqs[MCT_L0_IRQ];
  364. setup_irq(evt->irq, &mct_tick0_event_irq);
  365. } else {
  366. mct_tick1_event_irq.dev_id = mevt;
  367. evt->irq = mct_irqs[MCT_L1_IRQ];
  368. setup_irq(evt->irq, &mct_tick1_event_irq);
  369. irq_set_affinity(evt->irq, cpumask_of(1));
  370. }
  371. } else {
  372. enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
  373. }
  374. return 0;
  375. }
  376. static void exynos4_local_timer_stop(struct clock_event_device *evt)
  377. {
  378. unsigned int cpu = smp_processor_id();
  379. evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
  380. if (mct_int_type == MCT_INT_SPI)
  381. if (cpu == 0)
  382. remove_irq(evt->irq, &mct_tick0_event_irq);
  383. else
  384. remove_irq(evt->irq, &mct_tick1_event_irq);
  385. else
  386. disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
  387. }
  388. static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
  389. .setup = exynos4_local_timer_setup,
  390. .stop = exynos4_local_timer_stop,
  391. };
  392. #endif /* CONFIG_LOCAL_TIMERS */
  393. static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
  394. {
  395. struct clk *mct_clk, *tick_clk;
  396. tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
  397. clk_get(NULL, "fin_pll");
  398. if (IS_ERR(tick_clk))
  399. panic("%s: unable to determine tick clock rate\n", __func__);
  400. clk_rate = clk_get_rate(tick_clk);
  401. mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
  402. if (IS_ERR(mct_clk))
  403. panic("%s: unable to retrieve mct clock instance\n", __func__);
  404. clk_prepare_enable(mct_clk);
  405. reg_base = base;
  406. if (!reg_base)
  407. panic("%s: unable to ioremap mct address space\n", __func__);
  408. #ifdef CONFIG_LOCAL_TIMERS
  409. if (mct_int_type == MCT_INT_PPI) {
  410. int err;
  411. err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
  412. exynos4_mct_tick_isr, "MCT",
  413. &percpu_mct_tick);
  414. WARN(err, "MCT: can't request IRQ %d (%d)\n",
  415. mct_irqs[MCT_L0_IRQ], err);
  416. }
  417. local_timer_register(&exynos4_mct_tick_ops);
  418. #endif /* CONFIG_LOCAL_TIMERS */
  419. }
  420. void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
  421. {
  422. mct_irqs[MCT_G0_IRQ] = irq_g0;
  423. mct_irqs[MCT_L0_IRQ] = irq_l0;
  424. mct_irqs[MCT_L1_IRQ] = irq_l1;
  425. mct_int_type = MCT_INT_SPI;
  426. exynos4_timer_resources(NULL, base);
  427. exynos4_clocksource_init();
  428. exynos4_clockevent_init();
  429. }
  430. static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
  431. {
  432. u32 nr_irqs, i;
  433. mct_int_type = int_type;
  434. /* This driver uses only one global timer interrupt */
  435. mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
  436. /*
  437. * Find out the number of local irqs specified. The local
  438. * timer irqs are specified after the four global timer
  439. * irqs are specified.
  440. */
  441. #ifdef CONFIG_OF
  442. nr_irqs = of_irq_count(np);
  443. #else
  444. nr_irqs = 0;
  445. #endif
  446. for (i = MCT_L0_IRQ; i < nr_irqs; i++)
  447. mct_irqs[i] = irq_of_parse_and_map(np, i);
  448. exynos4_timer_resources(np, of_iomap(np, 0));
  449. exynos4_clocksource_init();
  450. exynos4_clockevent_init();
  451. }
  452. static void __init mct_init_spi(struct device_node *np)
  453. {
  454. return mct_init_dt(np, MCT_INT_SPI);
  455. }
  456. static void __init mct_init_ppi(struct device_node *np)
  457. {
  458. return mct_init_dt(np, MCT_INT_PPI);
  459. }
  460. CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
  461. CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);