r8a7790.dtsi 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210
  1. /*
  2. * Device Tree Source for the r8a7790 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. / {
  11. compatible = "renesas,r8a7790";
  12. interrupt-parent = <&gic>;
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a15";
  21. reg = <0>;
  22. clock-frequency = <1300000000>;
  23. };
  24. cpu1: cpu@1 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a15";
  27. reg = <1>;
  28. clock-frequency = <1300000000>;
  29. };
  30. cpu2: cpu@2 {
  31. device_type = "cpu";
  32. compatible = "arm,cortex-a15";
  33. reg = <2>;
  34. clock-frequency = <1300000000>;
  35. };
  36. cpu3: cpu@3 {
  37. device_type = "cpu";
  38. compatible = "arm,cortex-a15";
  39. reg = <3>;
  40. clock-frequency = <1300000000>;
  41. };
  42. };
  43. gic: interrupt-controller@f1001000 {
  44. compatible = "arm,cortex-a15-gic";
  45. #interrupt-cells = <3>;
  46. #address-cells = <0>;
  47. interrupt-controller;
  48. reg = <0 0xf1001000 0 0x1000>,
  49. <0 0xf1002000 0 0x1000>,
  50. <0 0xf1004000 0 0x2000>,
  51. <0 0xf1006000 0 0x2000>;
  52. interrupts = <1 9 0xf04>;
  53. };
  54. gpio0: gpio@ffc40000 {
  55. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  56. reg = <0 0xffc40000 0 0x2c>;
  57. interrupt-parent = <&gic>;
  58. interrupts = <0 4 0x4>;
  59. #gpio-cells = <2>;
  60. gpio-controller;
  61. gpio-ranges = <&pfc 0 0 32>;
  62. #interrupt-cells = <2>;
  63. interrupt-controller;
  64. };
  65. gpio1: gpio@ffc41000 {
  66. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  67. reg = <0 0xffc41000 0 0x2c>;
  68. interrupt-parent = <&gic>;
  69. interrupts = <0 5 0x4>;
  70. #gpio-cells = <2>;
  71. gpio-controller;
  72. gpio-ranges = <&pfc 0 32 32>;
  73. #interrupt-cells = <2>;
  74. interrupt-controller;
  75. };
  76. gpio2: gpio@ffc42000 {
  77. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  78. reg = <0 0xffc42000 0 0x2c>;
  79. interrupt-parent = <&gic>;
  80. interrupts = <0 6 0x4>;
  81. #gpio-cells = <2>;
  82. gpio-controller;
  83. gpio-ranges = <&pfc 0 64 32>;
  84. #interrupt-cells = <2>;
  85. interrupt-controller;
  86. };
  87. gpio3: gpio@ffc43000 {
  88. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  89. reg = <0 0xffc43000 0 0x2c>;
  90. interrupt-parent = <&gic>;
  91. interrupts = <0 7 0x4>;
  92. #gpio-cells = <2>;
  93. gpio-controller;
  94. gpio-ranges = <&pfc 0 96 32>;
  95. #interrupt-cells = <2>;
  96. interrupt-controller;
  97. };
  98. gpio4: gpio@ffc44000 {
  99. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  100. reg = <0 0xffc44000 0 0x2c>;
  101. interrupt-parent = <&gic>;
  102. interrupts = <0 8 0x4>;
  103. #gpio-cells = <2>;
  104. gpio-controller;
  105. gpio-ranges = <&pfc 0 128 32>;
  106. #interrupt-cells = <2>;
  107. interrupt-controller;
  108. };
  109. gpio5: gpio@ffc45000 {
  110. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  111. reg = <0 0xffc45000 0 0x2c>;
  112. interrupt-parent = <&gic>;
  113. interrupts = <0 9 0x4>;
  114. #gpio-cells = <2>;
  115. gpio-controller;
  116. gpio-ranges = <&pfc 0 160 32>;
  117. #interrupt-cells = <2>;
  118. interrupt-controller;
  119. };
  120. timer {
  121. compatible = "arm,armv7-timer";
  122. interrupts = <1 13 0xf08>,
  123. <1 14 0xf08>,
  124. <1 11 0xf08>,
  125. <1 10 0xf08>;
  126. };
  127. irqc0: interrupt-controller@e61c0000 {
  128. compatible = "renesas,irqc";
  129. #interrupt-cells = <2>;
  130. interrupt-controller;
  131. reg = <0 0xe61c0000 0 0x200>;
  132. interrupt-parent = <&gic>;
  133. interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
  134. };
  135. mmcif0: mmcif@ee200000 {
  136. compatible = "renesas,sh-mmcif";
  137. reg = <0 0xee200000 0 0x80>;
  138. interrupt-parent = <&gic>;
  139. interrupts = <0 169 0x4>;
  140. reg-io-width = <4>;
  141. status = "disabled";
  142. };
  143. mmcif1: mmcif@ee220000 {
  144. compatible = "renesas,sh-mmcif";
  145. reg = <0 0xee220000 0 0x80>;
  146. interrupt-parent = <&gic>;
  147. interrupts = <0 170 0x4>;
  148. reg-io-width = <4>;
  149. status = "disabled";
  150. };
  151. pfc: pfc@e6060000 {
  152. compatible = "renesas,pfc-r8a7790";
  153. reg = <0 0xe6060000 0 0x250>;
  154. #gpio-range-cells = <3>;
  155. };
  156. sdhi0: sdhi@ee100000 {
  157. compatible = "renesas,r8a7790-sdhi";
  158. reg = <0 0xee100000 0 0x100>;
  159. interrupt-parent = <&gic>;
  160. interrupts = <0 165 4>;
  161. cap-sd-highspeed;
  162. status = "disabled";
  163. };
  164. sdhi1: sdhi@ee120000 {
  165. compatible = "renesas,r8a7790-sdhi";
  166. reg = <0 0xee120000 0 0x100>;
  167. interrupt-parent = <&gic>;
  168. interrupts = <0 166 4>;
  169. cap-sd-highspeed;
  170. status = "disabled";
  171. };
  172. sdhi2: sdhi@ee140000 {
  173. compatible = "renesas,r8a7790-sdhi";
  174. reg = <0 0xee140000 0 0x100>;
  175. interrupt-parent = <&gic>;
  176. interrupts = <0 167 4>;
  177. cap-sd-highspeed;
  178. status = "disabled";
  179. };
  180. sdhi3: sdhi@ee160000 {
  181. compatible = "renesas,r8a7790-sdhi";
  182. reg = <0 0xee160000 0 0x100>;
  183. interrupt-parent = <&gic>;
  184. interrupts = <0 168 4>;
  185. cap-sd-highspeed;
  186. status = "disabled";
  187. };
  188. };