sm501fb.c 42 KB

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  1. /* linux/drivers/video/sm501fb.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Vincent Sanders <vince@simtec.co.uk>
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Framebuffer driver for the Silicon Motion SM501
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/string.h>
  17. #include <linux/mm.h>
  18. #include <linux/tty.h>
  19. #include <linux/slab.h>
  20. #include <linux/delay.h>
  21. #include <linux/fb.h>
  22. #include <linux/init.h>
  23. #include <linux/vmalloc.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/workqueue.h>
  27. #include <linux/wait.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/clk.h>
  30. #include <asm/io.h>
  31. #include <asm/uaccess.h>
  32. #include <asm/div64.h>
  33. #ifdef CONFIG_PM
  34. #include <linux/pm.h>
  35. #endif
  36. #include <linux/sm501.h>
  37. #include <linux/sm501-regs.h>
  38. #define NR_PALETTE 256
  39. enum sm501_controller {
  40. HEAD_CRT = 0,
  41. HEAD_PANEL = 1,
  42. };
  43. /* SM501 memory adress */
  44. struct sm501_mem {
  45. unsigned long size;
  46. unsigned long sm_addr;
  47. void __iomem *k_addr;
  48. };
  49. /* private data that is shared between all frambuffers* */
  50. struct sm501fb_info {
  51. struct device *dev;
  52. struct fb_info *fb[2]; /* fb info for both heads */
  53. struct resource *fbmem_res; /* framebuffer resource */
  54. struct resource *regs_res; /* registers resource */
  55. struct sm501_platdata_fb *pdata; /* our platform data */
  56. unsigned long pm_crt_ctrl; /* pm: crt ctrl save */
  57. int irq;
  58. int swap_endian; /* set to swap rgb=>bgr */
  59. void __iomem *regs; /* remapped registers */
  60. void __iomem *fbmem; /* remapped framebuffer */
  61. size_t fbmem_len; /* length of remapped region */
  62. };
  63. /* per-framebuffer private data */
  64. struct sm501fb_par {
  65. u32 pseudo_palette[16];
  66. enum sm501_controller head;
  67. struct sm501_mem cursor;
  68. struct sm501_mem screen;
  69. struct fb_ops ops;
  70. void *store_fb;
  71. void *store_cursor;
  72. void __iomem *cursor_regs;
  73. struct sm501fb_info *info;
  74. };
  75. /* Helper functions */
  76. static inline int h_total(struct fb_var_screeninfo *var)
  77. {
  78. return var->xres + var->left_margin +
  79. var->right_margin + var->hsync_len;
  80. }
  81. static inline int v_total(struct fb_var_screeninfo *var)
  82. {
  83. return var->yres + var->upper_margin +
  84. var->lower_margin + var->vsync_len;
  85. }
  86. /* sm501fb_sync_regs()
  87. *
  88. * This call is mainly for PCI bus systems where we need to
  89. * ensure that any writes to the bus are completed before the
  90. * next phase, or after completing a function.
  91. */
  92. static inline void sm501fb_sync_regs(struct sm501fb_info *info)
  93. {
  94. readl(info->regs);
  95. }
  96. /* sm501_alloc_mem
  97. *
  98. * This is an attempt to lay out memory for the two framebuffers and
  99. * everything else
  100. *
  101. * |fbmem_res->start fbmem_res->end|
  102. * | |
  103. * |fb[0].fix.smem_start | |fb[1].fix.smem_start | 2K |
  104. * |-> fb[0].fix.smem_len <-| spare |-> fb[1].fix.smem_len <-|-> cursors <-|
  105. *
  106. * The "spare" space is for the 2d engine data
  107. * the fixed is space for the cursors (2x1Kbyte)
  108. *
  109. * we need to allocate memory for the 2D acceleration engine
  110. * command list and the data for the engine to deal with.
  111. *
  112. * - all allocations must be 128bit aligned
  113. * - cursors are 64x64x2 bits (1Kbyte)
  114. *
  115. */
  116. #define SM501_MEMF_CURSOR (1)
  117. #define SM501_MEMF_PANEL (2)
  118. #define SM501_MEMF_CRT (4)
  119. #define SM501_MEMF_ACCEL (8)
  120. static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
  121. unsigned int why, size_t size)
  122. {
  123. unsigned int ptr = 0;
  124. switch (why) {
  125. case SM501_MEMF_CURSOR:
  126. ptr = inf->fbmem_len - size;
  127. inf->fbmem_len = ptr;
  128. break;
  129. case SM501_MEMF_PANEL:
  130. ptr = inf->fbmem_len - size;
  131. if (ptr < inf->fb[0]->fix.smem_len)
  132. return -ENOMEM;
  133. break;
  134. case SM501_MEMF_CRT:
  135. ptr = 0;
  136. break;
  137. case SM501_MEMF_ACCEL:
  138. ptr = inf->fb[0]->fix.smem_len;
  139. if ((ptr + size) >
  140. (inf->fb[1]->fix.smem_start - inf->fbmem_res->start))
  141. return -ENOMEM;
  142. break;
  143. default:
  144. return -EINVAL;
  145. }
  146. mem->size = size;
  147. mem->sm_addr = ptr;
  148. mem->k_addr = inf->fbmem + ptr;
  149. dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
  150. __func__, mem->sm_addr, mem->k_addr, why, size);
  151. return 0;
  152. }
  153. /* sm501fb_ps_to_hz
  154. *
  155. * Converts a period in picoseconds to Hz.
  156. *
  157. * Note, we try to keep this in Hz to minimise rounding with
  158. * the limited PLL settings on the SM501.
  159. */
  160. static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
  161. {
  162. unsigned long long numerator=1000000000000ULL;
  163. /* 10^12 / picosecond period gives frequency in Hz */
  164. do_div(numerator, psvalue);
  165. return (unsigned long)numerator;
  166. }
  167. /* sm501fb_hz_to_ps is identical to the oposite transform */
  168. #define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
  169. /* sm501fb_setup_gamma
  170. *
  171. * Programs a linear 1.0 gamma ramp in case the gamma
  172. * correction is enabled without programming anything else.
  173. */
  174. static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
  175. unsigned long palette)
  176. {
  177. unsigned long value = 0;
  178. int offset;
  179. /* set gamma values */
  180. for (offset = 0; offset < 256 * 4; offset += 4) {
  181. writel(value, fbi->regs + palette + offset);
  182. value += 0x010101; /* Advance RGB by 1,1,1.*/
  183. }
  184. }
  185. /* sm501fb_check_var
  186. *
  187. * check common variables for both panel and crt
  188. */
  189. static int sm501fb_check_var(struct fb_var_screeninfo *var,
  190. struct fb_info *info)
  191. {
  192. struct sm501fb_par *par = info->par;
  193. struct sm501fb_info *sm = par->info;
  194. unsigned long tmp;
  195. /* check we can fit these values into the registers */
  196. if (var->hsync_len > 255 || var->vsync_len > 255)
  197. return -EINVAL;
  198. if ((var->xres + var->right_margin) >= 4096)
  199. return -EINVAL;
  200. if ((var->yres + var->lower_margin) > 2048)
  201. return -EINVAL;
  202. /* hard limits of device */
  203. if (h_total(var) > 4096 || v_total(var) > 2048)
  204. return -EINVAL;
  205. /* check our line length is going to be 128 bit aligned */
  206. tmp = (var->xres * var->bits_per_pixel) / 8;
  207. if ((tmp & 15) != 0)
  208. return -EINVAL;
  209. /* check the virtual size */
  210. if (var->xres_virtual > 4096 || var->yres_virtual > 2048)
  211. return -EINVAL;
  212. /* can cope with 8,16 or 32bpp */
  213. if (var->bits_per_pixel <= 8)
  214. var->bits_per_pixel = 8;
  215. else if (var->bits_per_pixel <= 16)
  216. var->bits_per_pixel = 16;
  217. else if (var->bits_per_pixel == 24)
  218. var->bits_per_pixel = 32;
  219. /* set r/g/b positions and validate bpp */
  220. switch(var->bits_per_pixel) {
  221. case 8:
  222. var->red.length = var->bits_per_pixel;
  223. var->red.offset = 0;
  224. var->green.length = var->bits_per_pixel;
  225. var->green.offset = 0;
  226. var->blue.length = var->bits_per_pixel;
  227. var->blue.offset = 0;
  228. var->transp.length = 0;
  229. break;
  230. case 16:
  231. if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
  232. var->red.offset = 11;
  233. var->green.offset = 5;
  234. var->blue.offset = 0;
  235. } else {
  236. var->blue.offset = 11;
  237. var->green.offset = 5;
  238. var->red.offset = 0;
  239. }
  240. var->red.length = 5;
  241. var->green.length = 6;
  242. var->blue.length = 5;
  243. var->transp.length = 0;
  244. break;
  245. case 32:
  246. if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
  247. var->transp.offset = 0;
  248. var->red.offset = 8;
  249. var->green.offset = 16;
  250. var->blue.offset = 24;
  251. } else {
  252. var->transp.offset = 24;
  253. var->red.offset = 16;
  254. var->green.offset = 8;
  255. var->blue.offset = 0;
  256. }
  257. var->red.length = 8;
  258. var->green.length = 8;
  259. var->blue.length = 8;
  260. var->transp.length = 0;
  261. break;
  262. default:
  263. return -EINVAL;
  264. }
  265. return 0;
  266. }
  267. /*
  268. * sm501fb_check_var_crt():
  269. *
  270. * check the parameters for the CRT head, and either bring them
  271. * back into range, or return -EINVAL.
  272. */
  273. static int sm501fb_check_var_crt(struct fb_var_screeninfo *var,
  274. struct fb_info *info)
  275. {
  276. return sm501fb_check_var(var, info);
  277. }
  278. /* sm501fb_check_var_pnl():
  279. *
  280. * check the parameters for the CRT head, and either bring them
  281. * back into range, or return -EINVAL.
  282. */
  283. static int sm501fb_check_var_pnl(struct fb_var_screeninfo *var,
  284. struct fb_info *info)
  285. {
  286. return sm501fb_check_var(var, info);
  287. }
  288. /* sm501fb_set_par_common
  289. *
  290. * set common registers for framebuffers
  291. */
  292. static int sm501fb_set_par_common(struct fb_info *info,
  293. struct fb_var_screeninfo *var)
  294. {
  295. struct sm501fb_par *par = info->par;
  296. struct sm501fb_info *fbi = par->info;
  297. unsigned long pixclock; /* pixelclock in Hz */
  298. unsigned long sm501pixclock; /* pixelclock the 501 can achive in Hz */
  299. unsigned int mem_type;
  300. unsigned int clock_type;
  301. unsigned int head_addr;
  302. dev_dbg(fbi->dev, "%s: %dx%d, bpp = %d, virtual %dx%d\n",
  303. __func__, var->xres, var->yres, var->bits_per_pixel,
  304. var->xres_virtual, var->yres_virtual);
  305. switch (par->head) {
  306. case HEAD_CRT:
  307. mem_type = SM501_MEMF_CRT;
  308. clock_type = SM501_CLOCK_V2XCLK;
  309. head_addr = SM501_DC_CRT_FB_ADDR;
  310. break;
  311. case HEAD_PANEL:
  312. mem_type = SM501_MEMF_PANEL;
  313. clock_type = SM501_CLOCK_P2XCLK;
  314. head_addr = SM501_DC_PANEL_FB_ADDR;
  315. break;
  316. default:
  317. mem_type = 0; /* stop compiler warnings */
  318. head_addr = 0;
  319. clock_type = 0;
  320. }
  321. switch (var->bits_per_pixel) {
  322. case 8:
  323. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  324. break;
  325. case 16:
  326. info->fix.visual = FB_VISUAL_DIRECTCOLOR;
  327. break;
  328. case 32:
  329. info->fix.visual = FB_VISUAL_TRUECOLOR;
  330. break;
  331. }
  332. /* allocate fb memory within 501 */
  333. info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
  334. info->fix.smem_len = info->fix.line_length * var->yres_virtual;
  335. dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
  336. info->fix.line_length);
  337. if (sm501_alloc_mem(fbi, &par->screen, mem_type,
  338. info->fix.smem_len)) {
  339. dev_err(fbi->dev, "no memory available\n");
  340. return -ENOMEM;
  341. }
  342. info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
  343. info->screen_base = fbi->fbmem + par->screen.sm_addr;
  344. info->screen_size = info->fix.smem_len;
  345. /* set start of framebuffer to the screen */
  346. writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr);
  347. /* program CRT clock */
  348. pixclock = sm501fb_ps_to_hz(var->pixclock);
  349. sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
  350. pixclock);
  351. /* update fb layer with actual clock used */
  352. var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
  353. dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz) = %lu, "
  354. "sm501pixclock = %lu, error = %ld%%\n",
  355. __func__, var->pixclock, pixclock, sm501pixclock,
  356. ((pixclock - sm501pixclock)*100)/pixclock);
  357. return 0;
  358. }
  359. /* sm501fb_set_par_geometry
  360. *
  361. * set the geometry registers for specified framebuffer.
  362. */
  363. static void sm501fb_set_par_geometry(struct fb_info *info,
  364. struct fb_var_screeninfo *var)
  365. {
  366. struct sm501fb_par *par = info->par;
  367. struct sm501fb_info *fbi = par->info;
  368. void __iomem *base = fbi->regs;
  369. unsigned long reg;
  370. if (par->head == HEAD_CRT)
  371. base += SM501_DC_CRT_H_TOT;
  372. else
  373. base += SM501_DC_PANEL_H_TOT;
  374. /* set framebuffer width and display width */
  375. reg = info->fix.line_length;
  376. reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
  377. writel(reg, fbi->regs + (par->head == HEAD_CRT ?
  378. SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET));
  379. /* program horizontal total */
  380. reg = (h_total(var) - 1) << 16;
  381. reg |= (var->xres - 1);
  382. writel(reg, base + SM501_OFF_DC_H_TOT);
  383. /* program horizontal sync */
  384. reg = var->hsync_len << 16;
  385. reg |= var->xres + var->right_margin - 1;
  386. writel(reg, base + SM501_OFF_DC_H_SYNC);
  387. /* program vertical total */
  388. reg = (v_total(var) - 1) << 16;
  389. reg |= (var->yres - 1);
  390. writel(reg, base + SM501_OFF_DC_V_TOT);
  391. /* program vertical sync */
  392. reg = var->vsync_len << 16;
  393. reg |= var->yres + var->lower_margin - 1;
  394. writel(reg, base + SM501_OFF_DC_V_SYNC);
  395. }
  396. /* sm501fb_pan_crt
  397. *
  398. * pan the CRT display output within an virtual framebuffer
  399. */
  400. static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
  401. struct fb_info *info)
  402. {
  403. struct sm501fb_par *par = info->par;
  404. struct sm501fb_info *fbi = par->info;
  405. unsigned int bytes_pixel = var->bits_per_pixel / 8;
  406. unsigned long reg;
  407. unsigned long xoffs;
  408. xoffs = var->xoffset * bytes_pixel;
  409. reg = readl(fbi->regs + SM501_DC_CRT_CONTROL);
  410. reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
  411. reg |= ((xoffs & 15) / bytes_pixel) << 4;
  412. writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
  413. reg = (par->screen.sm_addr + xoffs +
  414. var->yoffset * info->fix.line_length);
  415. writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
  416. sm501fb_sync_regs(fbi);
  417. return 0;
  418. }
  419. /* sm501fb_pan_pnl
  420. *
  421. * pan the panel display output within an virtual framebuffer
  422. */
  423. static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
  424. struct fb_info *info)
  425. {
  426. struct sm501fb_par *par = info->par;
  427. struct sm501fb_info *fbi = par->info;
  428. unsigned long reg;
  429. reg = var->xoffset | (var->xres_virtual << 16);
  430. writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
  431. reg = var->yoffset | (var->yres_virtual << 16);
  432. writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
  433. sm501fb_sync_regs(fbi);
  434. return 0;
  435. }
  436. /* sm501fb_set_par_crt
  437. *
  438. * Set the CRT video mode from the fb_info structure
  439. */
  440. static int sm501fb_set_par_crt(struct fb_info *info)
  441. {
  442. struct sm501fb_par *par = info->par;
  443. struct sm501fb_info *fbi = par->info;
  444. struct fb_var_screeninfo *var = &info->var;
  445. unsigned long control; /* control register */
  446. int ret;
  447. /* activate new configuration */
  448. dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
  449. /* enable CRT DAC - note 0 is on!*/
  450. sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
  451. control = readl(fbi->regs + SM501_DC_CRT_CONTROL);
  452. control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
  453. SM501_DC_CRT_CONTROL_GAMMA |
  454. SM501_DC_CRT_CONTROL_BLANK |
  455. SM501_DC_CRT_CONTROL_SEL |
  456. SM501_DC_CRT_CONTROL_CP |
  457. SM501_DC_CRT_CONTROL_TVP);
  458. /* set the sync polarities before we check data source */
  459. if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
  460. control |= SM501_DC_CRT_CONTROL_HSP;
  461. if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
  462. control |= SM501_DC_CRT_CONTROL_VSP;
  463. if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
  464. /* the head is displaying panel data... */
  465. sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0);
  466. goto out_update;
  467. }
  468. ret = sm501fb_set_par_common(info, var);
  469. if (ret) {
  470. dev_err(fbi->dev, "failed to set common parameters\n");
  471. return ret;
  472. }
  473. sm501fb_pan_crt(var, info);
  474. sm501fb_set_par_geometry(info, var);
  475. control |= SM501_FIFO_3; /* fill if >3 free slots */
  476. switch(var->bits_per_pixel) {
  477. case 8:
  478. control |= SM501_DC_CRT_CONTROL_8BPP;
  479. break;
  480. case 16:
  481. control |= SM501_DC_CRT_CONTROL_16BPP;
  482. break;
  483. case 32:
  484. control |= SM501_DC_CRT_CONTROL_32BPP;
  485. sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
  486. break;
  487. default:
  488. BUG();
  489. }
  490. control |= SM501_DC_CRT_CONTROL_SEL; /* CRT displays CRT data */
  491. control |= SM501_DC_CRT_CONTROL_TE; /* enable CRT timing */
  492. control |= SM501_DC_CRT_CONTROL_ENABLE; /* enable CRT plane */
  493. out_update:
  494. dev_dbg(fbi->dev, "new control is %08lx\n", control);
  495. writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
  496. sm501fb_sync_regs(fbi);
  497. return 0;
  498. }
  499. static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
  500. {
  501. unsigned long control;
  502. void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
  503. control = readl(ctrl_reg);
  504. if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
  505. /* enable panel power */
  506. control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */
  507. writel(control, ctrl_reg);
  508. sm501fb_sync_regs(fbi);
  509. mdelay(10);
  510. control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
  511. writel(control, ctrl_reg);
  512. sm501fb_sync_regs(fbi);
  513. mdelay(10);
  514. control |= SM501_DC_PANEL_CONTROL_BIAS; /* VBIASEN */
  515. writel(control, ctrl_reg);
  516. sm501fb_sync_regs(fbi);
  517. mdelay(10);
  518. control |= SM501_DC_PANEL_CONTROL_FPEN;
  519. writel(control, ctrl_reg);
  520. } else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
  521. /* disable panel power */
  522. control &= ~SM501_DC_PANEL_CONTROL_FPEN;
  523. writel(control, ctrl_reg);
  524. sm501fb_sync_regs(fbi);
  525. mdelay(10);
  526. control &= ~SM501_DC_PANEL_CONTROL_BIAS;
  527. writel(control, ctrl_reg);
  528. sm501fb_sync_regs(fbi);
  529. mdelay(10);
  530. control &= ~SM501_DC_PANEL_CONTROL_DATA;
  531. writel(control, ctrl_reg);
  532. sm501fb_sync_regs(fbi);
  533. mdelay(10);
  534. control &= ~SM501_DC_PANEL_CONTROL_VDD;
  535. writel(control, ctrl_reg);
  536. sm501fb_sync_regs(fbi);
  537. mdelay(10);
  538. }
  539. sm501fb_sync_regs(fbi);
  540. }
  541. /* sm501fb_set_par_pnl
  542. *
  543. * Set the panel video mode from the fb_info structure
  544. */
  545. static int sm501fb_set_par_pnl(struct fb_info *info)
  546. {
  547. struct sm501fb_par *par = info->par;
  548. struct sm501fb_info *fbi = par->info;
  549. struct fb_var_screeninfo *var = &info->var;
  550. unsigned long control;
  551. unsigned long reg;
  552. int ret;
  553. dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
  554. /* activate this new configuration */
  555. ret = sm501fb_set_par_common(info, var);
  556. if (ret)
  557. return ret;
  558. sm501fb_pan_pnl(var, info);
  559. sm501fb_set_par_geometry(info, var);
  560. /* update control register */
  561. control = readl(fbi->regs + SM501_DC_PANEL_CONTROL);
  562. control &= (SM501_DC_PANEL_CONTROL_GAMMA |
  563. SM501_DC_PANEL_CONTROL_VDD |
  564. SM501_DC_PANEL_CONTROL_DATA |
  565. SM501_DC_PANEL_CONTROL_BIAS |
  566. SM501_DC_PANEL_CONTROL_FPEN |
  567. SM501_DC_PANEL_CONTROL_CP |
  568. SM501_DC_PANEL_CONTROL_CK |
  569. SM501_DC_PANEL_CONTROL_HP |
  570. SM501_DC_PANEL_CONTROL_VP |
  571. SM501_DC_PANEL_CONTROL_HPD |
  572. SM501_DC_PANEL_CONTROL_VPD);
  573. control |= SM501_FIFO_3; /* fill if >3 free slots */
  574. switch(var->bits_per_pixel) {
  575. case 8:
  576. control |= SM501_DC_PANEL_CONTROL_8BPP;
  577. break;
  578. case 16:
  579. control |= SM501_DC_PANEL_CONTROL_16BPP;
  580. break;
  581. case 32:
  582. control |= SM501_DC_PANEL_CONTROL_32BPP;
  583. sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
  584. break;
  585. default:
  586. BUG();
  587. }
  588. writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
  589. /* panel plane top left and bottom right location */
  590. writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
  591. reg = var->xres - 1;
  592. reg |= (var->yres - 1) << 16;
  593. writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
  594. /* program panel control register */
  595. control |= SM501_DC_PANEL_CONTROL_TE; /* enable PANEL timing */
  596. control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */
  597. if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
  598. control |= SM501_DC_PANEL_CONTROL_HSP;
  599. if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
  600. control |= SM501_DC_PANEL_CONTROL_VSP;
  601. writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
  602. sm501fb_sync_regs(fbi);
  603. /* power the panel up */
  604. sm501fb_panel_power(fbi, 1);
  605. return 0;
  606. }
  607. /* chan_to_field
  608. *
  609. * convert a colour value into a field position
  610. *
  611. * from pxafb.c
  612. */
  613. static inline unsigned int chan_to_field(unsigned int chan,
  614. struct fb_bitfield *bf)
  615. {
  616. chan &= 0xffff;
  617. chan >>= 16 - bf->length;
  618. return chan << bf->offset;
  619. }
  620. /* sm501fb_setcolreg
  621. *
  622. * set the colour mapping for modes that support palettised data
  623. */
  624. static int sm501fb_setcolreg(unsigned regno,
  625. unsigned red, unsigned green, unsigned blue,
  626. unsigned transp, struct fb_info *info)
  627. {
  628. struct sm501fb_par *par = info->par;
  629. struct sm501fb_info *fbi = par->info;
  630. void __iomem *base = fbi->regs;
  631. unsigned int val;
  632. if (par->head == HEAD_CRT)
  633. base += SM501_DC_CRT_PALETTE;
  634. else
  635. base += SM501_DC_PANEL_PALETTE;
  636. switch (info->fix.visual) {
  637. case FB_VISUAL_TRUECOLOR:
  638. /* true-colour, use pseuo-palette */
  639. if (regno < 16) {
  640. u32 *pal = par->pseudo_palette;
  641. val = chan_to_field(red, &info->var.red);
  642. val |= chan_to_field(green, &info->var.green);
  643. val |= chan_to_field(blue, &info->var.blue);
  644. pal[regno] = val;
  645. }
  646. break;
  647. case FB_VISUAL_PSEUDOCOLOR:
  648. if (regno < 256) {
  649. val = (red >> 8) << 16;
  650. val |= (green >> 8) << 8;
  651. val |= blue >> 8;
  652. writel(val, base + (regno * 4));
  653. }
  654. break;
  655. default:
  656. return 1; /* unknown type */
  657. }
  658. return 0;
  659. }
  660. /* sm501fb_blank_pnl
  661. *
  662. * Blank or un-blank the panel interface
  663. */
  664. static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
  665. {
  666. struct sm501fb_par *par = info->par;
  667. struct sm501fb_info *fbi = par->info;
  668. dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
  669. switch (blank_mode) {
  670. case FB_BLANK_POWERDOWN:
  671. sm501fb_panel_power(fbi, 0);
  672. break;
  673. case FB_BLANK_UNBLANK:
  674. sm501fb_panel_power(fbi, 1);
  675. break;
  676. case FB_BLANK_NORMAL:
  677. case FB_BLANK_VSYNC_SUSPEND:
  678. case FB_BLANK_HSYNC_SUSPEND:
  679. default:
  680. return 1;
  681. }
  682. return 0;
  683. }
  684. /* sm501fb_blank_crt
  685. *
  686. * Blank or un-blank the crt interface
  687. */
  688. static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
  689. {
  690. struct sm501fb_par *par = info->par;
  691. struct sm501fb_info *fbi = par->info;
  692. unsigned long ctrl;
  693. dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
  694. ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL);
  695. switch (blank_mode) {
  696. case FB_BLANK_POWERDOWN:
  697. ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
  698. sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
  699. case FB_BLANK_NORMAL:
  700. ctrl |= SM501_DC_CRT_CONTROL_BLANK;
  701. break;
  702. case FB_BLANK_UNBLANK:
  703. ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
  704. ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
  705. sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
  706. break;
  707. case FB_BLANK_VSYNC_SUSPEND:
  708. case FB_BLANK_HSYNC_SUSPEND:
  709. default:
  710. return 1;
  711. }
  712. writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
  713. sm501fb_sync_regs(fbi);
  714. return 0;
  715. }
  716. /* sm501fb_cursor
  717. *
  718. * set or change the hardware cursor parameters
  719. */
  720. static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  721. {
  722. struct sm501fb_par *par = info->par;
  723. struct sm501fb_info *fbi = par->info;
  724. void __iomem *base = fbi->regs;
  725. unsigned long hwc_addr;
  726. unsigned long fg, bg;
  727. dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
  728. if (par->head == HEAD_CRT)
  729. base += SM501_DC_CRT_HWC_BASE;
  730. else
  731. base += SM501_DC_PANEL_HWC_BASE;
  732. /* check not being asked to exceed capabilities */
  733. if (cursor->image.width > 64)
  734. return -EINVAL;
  735. if (cursor->image.height > 64)
  736. return -EINVAL;
  737. if (cursor->image.depth > 1)
  738. return -EINVAL;
  739. hwc_addr = readl(base + SM501_OFF_HWC_ADDR);
  740. if (cursor->enable)
  741. writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
  742. else
  743. writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
  744. /* set data */
  745. if (cursor->set & FB_CUR_SETPOS) {
  746. unsigned int x = cursor->image.dx;
  747. unsigned int y = cursor->image.dy;
  748. if (x >= 2048 || y >= 2048 )
  749. return -EINVAL;
  750. dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
  751. //y += cursor->image.height;
  752. writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
  753. }
  754. if (cursor->set & FB_CUR_SETCMAP) {
  755. unsigned int bg_col = cursor->image.bg_color;
  756. unsigned int fg_col = cursor->image.fg_color;
  757. dev_dbg(fbi->dev, "%s: update cmap (%08x,%08x)\n",
  758. __func__, bg_col, fg_col);
  759. bg = ((info->cmap.red[bg_col] & 0xF8) << 8) |
  760. ((info->cmap.green[bg_col] & 0xFC) << 3) |
  761. ((info->cmap.blue[bg_col] & 0xF8) >> 3);
  762. fg = ((info->cmap.red[fg_col] & 0xF8) << 8) |
  763. ((info->cmap.green[fg_col] & 0xFC) << 3) |
  764. ((info->cmap.blue[fg_col] & 0xF8) >> 3);
  765. dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
  766. writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
  767. writel(fg, base + SM501_OFF_HWC_COLOR_3);
  768. }
  769. if (cursor->set & FB_CUR_SETSIZE ||
  770. cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
  771. /* SM501 cursor is a two bpp 64x64 bitmap this routine
  772. * clears it to transparent then combines the cursor
  773. * shape plane with the colour plane to set the
  774. * cursor */
  775. int x, y;
  776. const unsigned char *pcol = cursor->image.data;
  777. const unsigned char *pmsk = cursor->mask;
  778. void __iomem *dst = par->cursor.k_addr;
  779. unsigned char dcol = 0;
  780. unsigned char dmsk = 0;
  781. unsigned int op;
  782. dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
  783. __func__, cursor->image.width, cursor->image.height);
  784. for (op = 0; op < (64*64*2)/8; op+=4)
  785. writel(0x0, dst + op);
  786. for (y = 0; y < cursor->image.height; y++) {
  787. for (x = 0; x < cursor->image.width; x++) {
  788. if ((x % 8) == 0) {
  789. dcol = *pcol++;
  790. dmsk = *pmsk++;
  791. } else {
  792. dcol >>= 1;
  793. dmsk >>= 1;
  794. }
  795. if (dmsk & 1) {
  796. op = (dcol & 1) ? 1 : 3;
  797. op <<= ((x % 4) * 2);
  798. op |= readb(dst + (x / 4));
  799. writeb(op, dst + (x / 4));
  800. }
  801. }
  802. dst += (64*2)/8;
  803. }
  804. }
  805. sm501fb_sync_regs(fbi); /* ensure cursor data flushed */
  806. return 0;
  807. }
  808. /* sm501fb_crtsrc_show
  809. *
  810. * device attribute code to show where the crt output is sourced from
  811. */
  812. static ssize_t sm501fb_crtsrc_show(struct device *dev,
  813. struct device_attribute *attr, char *buf)
  814. {
  815. struct sm501fb_info *info = dev_get_drvdata(dev);
  816. unsigned long ctrl;
  817. ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  818. ctrl &= SM501_DC_CRT_CONTROL_SEL;
  819. return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel");
  820. }
  821. /* sm501fb_crtsrc_show
  822. *
  823. * device attribute code to set where the crt output is sourced from
  824. */
  825. static ssize_t sm501fb_crtsrc_store(struct device *dev,
  826. struct device_attribute *attr,
  827. const char *buf, size_t len)
  828. {
  829. struct sm501fb_info *info = dev_get_drvdata(dev);
  830. enum sm501_controller head;
  831. unsigned long ctrl;
  832. if (len < 1)
  833. return -EINVAL;
  834. if (strnicmp(buf, "crt", 3) == 0)
  835. head = HEAD_CRT;
  836. else if (strnicmp(buf, "panel", 5) == 0)
  837. head = HEAD_PANEL;
  838. else
  839. return -EINVAL;
  840. dev_info(dev, "setting crt source to head %d\n", head);
  841. ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  842. if (head == HEAD_CRT) {
  843. ctrl |= SM501_DC_CRT_CONTROL_SEL;
  844. ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
  845. ctrl |= SM501_DC_CRT_CONTROL_TE;
  846. } else {
  847. ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
  848. ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
  849. ctrl &= ~SM501_DC_CRT_CONTROL_TE;
  850. }
  851. writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  852. sm501fb_sync_regs(info);
  853. return len;
  854. }
  855. /* Prepare the device_attr for registration with sysfs later */
  856. static DEVICE_ATTR(crt_src, 0666, sm501fb_crtsrc_show, sm501fb_crtsrc_store);
  857. /* sm501fb_show_regs
  858. *
  859. * show the primary sm501 registers
  860. */
  861. static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
  862. unsigned int start, unsigned int len)
  863. {
  864. void __iomem *mem = info->regs;
  865. char *buf = ptr;
  866. unsigned int reg;
  867. for (reg = start; reg < (len + start); reg += 4)
  868. ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg));
  869. return ptr - buf;
  870. }
  871. /* sm501fb_debug_show_crt
  872. *
  873. * show the crt control and cursor registers
  874. */
  875. static ssize_t sm501fb_debug_show_crt(struct device *dev,
  876. struct device_attribute *attr, char *buf)
  877. {
  878. struct sm501fb_info *info = dev_get_drvdata(dev);
  879. char *ptr = buf;
  880. ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
  881. ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
  882. return ptr - buf;
  883. }
  884. static DEVICE_ATTR(fbregs_crt, 0444, sm501fb_debug_show_crt, NULL);
  885. /* sm501fb_debug_show_pnl
  886. *
  887. * show the panel control and cursor registers
  888. */
  889. static ssize_t sm501fb_debug_show_pnl(struct device *dev,
  890. struct device_attribute *attr, char *buf)
  891. {
  892. struct sm501fb_info *info = dev_get_drvdata(dev);
  893. char *ptr = buf;
  894. ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
  895. ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
  896. return ptr - buf;
  897. }
  898. static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
  899. /* framebuffer ops */
  900. static struct fb_ops sm501fb_ops_crt = {
  901. .owner = THIS_MODULE,
  902. .fb_check_var = sm501fb_check_var_crt,
  903. .fb_set_par = sm501fb_set_par_crt,
  904. .fb_blank = sm501fb_blank_crt,
  905. .fb_setcolreg = sm501fb_setcolreg,
  906. .fb_pan_display = sm501fb_pan_crt,
  907. .fb_cursor = sm501fb_cursor,
  908. .fb_fillrect = cfb_fillrect,
  909. .fb_copyarea = cfb_copyarea,
  910. .fb_imageblit = cfb_imageblit,
  911. };
  912. static struct fb_ops sm501fb_ops_pnl = {
  913. .owner = THIS_MODULE,
  914. .fb_check_var = sm501fb_check_var_pnl,
  915. .fb_set_par = sm501fb_set_par_pnl,
  916. .fb_pan_display = sm501fb_pan_pnl,
  917. .fb_blank = sm501fb_blank_pnl,
  918. .fb_setcolreg = sm501fb_setcolreg,
  919. .fb_cursor = sm501fb_cursor,
  920. .fb_fillrect = cfb_fillrect,
  921. .fb_copyarea = cfb_copyarea,
  922. .fb_imageblit = cfb_imageblit,
  923. };
  924. /* sm501fb_info_alloc
  925. *
  926. * creates and initialises an sm501fb_info structure
  927. */
  928. static struct sm501fb_info *sm501fb_info_alloc(struct fb_info *fbinfo_crt,
  929. struct fb_info *fbinfo_pnl)
  930. {
  931. struct sm501fb_info *info;
  932. struct sm501fb_par *par;
  933. info = kzalloc(sizeof(struct sm501fb_info), GFP_KERNEL);
  934. if (info) {
  935. /* set the references back */
  936. par = fbinfo_crt->par;
  937. par->info = info;
  938. par->head = HEAD_CRT;
  939. fbinfo_crt->pseudo_palette = &par->pseudo_palette;
  940. par = fbinfo_pnl->par;
  941. par->info = info;
  942. par->head = HEAD_PANEL;
  943. fbinfo_pnl->pseudo_palette = &par->pseudo_palette;
  944. /* store the two fbs into our info */
  945. info->fb[HEAD_CRT] = fbinfo_crt;
  946. info->fb[HEAD_PANEL] = fbinfo_pnl;
  947. }
  948. return info;
  949. }
  950. /* sm501_init_cursor
  951. *
  952. * initialise hw cursor parameters
  953. */
  954. static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
  955. {
  956. struct sm501fb_par *par = fbi->par;
  957. struct sm501fb_info *info = par->info;
  958. int ret;
  959. par->cursor_regs = info->regs + reg_base;
  960. ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024);
  961. if (ret < 0)
  962. return ret;
  963. /* initialise the colour registers */
  964. writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR);
  965. writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
  966. writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
  967. writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
  968. sm501fb_sync_regs(info);
  969. return 0;
  970. }
  971. /* sm501fb_info_start
  972. *
  973. * fills the par structure claiming resources and remapping etc.
  974. */
  975. static int sm501fb_start(struct sm501fb_info *info,
  976. struct platform_device *pdev)
  977. {
  978. struct resource *res;
  979. struct device *dev;
  980. int ret;
  981. info->dev = dev = &pdev->dev;
  982. platform_set_drvdata(pdev, info);
  983. info->irq = ret = platform_get_irq(pdev, 0);
  984. if (ret < 0) {
  985. /* we currently do not use the IRQ */
  986. dev_warn(dev, "no irq for device\n");
  987. }
  988. /* allocate, reserve and remap resources for registers */
  989. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  990. if (res == NULL) {
  991. dev_err(dev, "no resource definition for registers\n");
  992. ret = -ENOENT;
  993. goto err_release;
  994. }
  995. info->regs_res = request_mem_region(res->start,
  996. res->end - res->start,
  997. pdev->name);
  998. if (info->regs_res == NULL) {
  999. dev_err(dev, "cannot claim registers\n");
  1000. ret = -ENXIO;
  1001. goto err_release;
  1002. }
  1003. info->regs = ioremap(res->start, (res->end - res->start)+1);
  1004. if (info->regs == NULL) {
  1005. dev_err(dev, "cannot remap registers\n");
  1006. ret = -ENXIO;
  1007. goto err_regs_res;
  1008. }
  1009. /* allocate, reserve resources for framebuffer */
  1010. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  1011. if (res == NULL) {
  1012. dev_err(dev, "no memory resource defined\n");
  1013. ret = -ENXIO;
  1014. goto err_regs_map;
  1015. }
  1016. info->fbmem_res = request_mem_region(res->start,
  1017. (res->end - res->start)+1,
  1018. pdev->name);
  1019. if (info->fbmem_res == NULL) {
  1020. dev_err(dev, "cannot claim framebuffer\n");
  1021. ret = -ENXIO;
  1022. goto err_regs_map;
  1023. }
  1024. info->fbmem = ioremap(res->start, (res->end - res->start)+1);
  1025. if (info->fbmem == NULL) {
  1026. dev_err(dev, "cannot remap framebuffer\n");
  1027. goto err_mem_res;
  1028. }
  1029. info->fbmem_len = (res->end - res->start)+1;
  1030. /* enable display controller */
  1031. sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
  1032. /* setup cursors */
  1033. sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
  1034. sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
  1035. return 0; /* everything is setup */
  1036. err_mem_res:
  1037. release_resource(info->fbmem_res);
  1038. kfree(info->fbmem_res);
  1039. err_regs_map:
  1040. iounmap(info->regs);
  1041. err_regs_res:
  1042. release_resource(info->regs_res);
  1043. kfree(info->regs_res);
  1044. err_release:
  1045. return ret;
  1046. }
  1047. static void sm501fb_stop(struct sm501fb_info *info)
  1048. {
  1049. /* disable display controller */
  1050. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
  1051. iounmap(info->fbmem);
  1052. release_resource(info->fbmem_res);
  1053. kfree(info->fbmem_res);
  1054. iounmap(info->regs);
  1055. release_resource(info->regs_res);
  1056. kfree(info->regs_res);
  1057. }
  1058. static void sm501fb_info_release(struct sm501fb_info *info)
  1059. {
  1060. kfree(info);
  1061. }
  1062. static int sm501fb_init_fb(struct fb_info *fb,
  1063. enum sm501_controller head,
  1064. const char *fbname)
  1065. {
  1066. struct sm501_platdata_fbsub *pd;
  1067. struct sm501fb_par *par = fb->par;
  1068. struct sm501fb_info *info = par->info;
  1069. unsigned long ctrl;
  1070. unsigned int enable;
  1071. int ret;
  1072. switch (head) {
  1073. case HEAD_CRT:
  1074. pd = info->pdata->fb_crt;
  1075. ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  1076. enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
  1077. /* ensure we set the correct source register */
  1078. if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
  1079. ctrl |= SM501_DC_CRT_CONTROL_SEL;
  1080. writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1081. }
  1082. break;
  1083. case HEAD_PANEL:
  1084. pd = info->pdata->fb_pnl;
  1085. ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL);
  1086. enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
  1087. break;
  1088. default:
  1089. pd = NULL; /* stop compiler warnings */
  1090. ctrl = 0;
  1091. enable = 0;
  1092. BUG();
  1093. }
  1094. dev_info(info->dev, "fb %s %sabled at start\n",
  1095. fbname, enable ? "en" : "dis");
  1096. /* check to see if our routing allows this */
  1097. if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
  1098. ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
  1099. writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1100. enable = 0;
  1101. }
  1102. strlcpy(fb->fix.id, fbname, sizeof(fb->fix.id));
  1103. memcpy(&par->ops,
  1104. (head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
  1105. sizeof(struct fb_ops));
  1106. /* update ops dependant on what we've been passed */
  1107. if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
  1108. par->ops.fb_cursor = NULL;
  1109. fb->fbops = &par->ops;
  1110. fb->flags = FBINFO_FLAG_DEFAULT |
  1111. FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
  1112. /* fixed data */
  1113. fb->fix.type = FB_TYPE_PACKED_PIXELS;
  1114. fb->fix.type_aux = 0;
  1115. fb->fix.xpanstep = 1;
  1116. fb->fix.ypanstep = 1;
  1117. fb->fix.ywrapstep = 0;
  1118. fb->fix.accel = FB_ACCEL_NONE;
  1119. /* screenmode */
  1120. fb->var.nonstd = 0;
  1121. fb->var.activate = FB_ACTIVATE_NOW;
  1122. fb->var.accel_flags = 0;
  1123. fb->var.vmode = FB_VMODE_NONINTERLACED;
  1124. fb->var.bits_per_pixel = 16;
  1125. if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
  1126. /* TODO read the mode from the current display */
  1127. } else {
  1128. if (pd->def_mode) {
  1129. dev_info(info->dev, "using supplied mode\n");
  1130. fb_videomode_to_var(&fb->var, pd->def_mode);
  1131. fb->var.bits_per_pixel = pd->def_bpp ? pd->def_bpp : 8;
  1132. fb->var.xres_virtual = fb->var.xres;
  1133. fb->var.yres_virtual = fb->var.yres;
  1134. } else {
  1135. ret = fb_find_mode(&fb->var, fb,
  1136. NULL, NULL, 0, NULL, 8);
  1137. if (ret == 0 || ret == 4) {
  1138. dev_err(info->dev,
  1139. "failed to get initial mode\n");
  1140. return -EINVAL;
  1141. }
  1142. }
  1143. }
  1144. /* initialise and set the palette */
  1145. fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0);
  1146. fb_set_cmap(&fb->cmap, fb);
  1147. ret = (fb->fbops->fb_check_var)(&fb->var, fb);
  1148. if (ret)
  1149. dev_err(info->dev, "check_var() failed on initial setup?\n");
  1150. /* ensure we've activated our new configuration */
  1151. (fb->fbops->fb_set_par)(fb);
  1152. return 0;
  1153. }
  1154. /* default platform data if none is supplied (ie, PCI device) */
  1155. static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
  1156. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  1157. SM501FB_FLAG_USE_HWCURSOR |
  1158. SM501FB_FLAG_USE_HWACCEL |
  1159. SM501FB_FLAG_DISABLE_AT_EXIT),
  1160. };
  1161. static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
  1162. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  1163. SM501FB_FLAG_USE_HWCURSOR |
  1164. SM501FB_FLAG_USE_HWACCEL |
  1165. SM501FB_FLAG_DISABLE_AT_EXIT),
  1166. };
  1167. static struct sm501_platdata_fb sm501fb_def_pdata = {
  1168. .fb_route = SM501_FB_OWN,
  1169. .fb_crt = &sm501fb_pdata_crt,
  1170. .fb_pnl = &sm501fb_pdata_pnl,
  1171. };
  1172. static char driver_name_crt[] = "sm501fb-crt";
  1173. static char driver_name_pnl[] = "sm501fb-panel";
  1174. static int __init sm501fb_probe(struct platform_device *pdev)
  1175. {
  1176. struct sm501fb_info *info;
  1177. struct device *dev = &pdev->dev;
  1178. struct fb_info *fbinfo_crt;
  1179. struct fb_info *fbinfo_pnl;
  1180. int ret;
  1181. /* allocate our framebuffers */
  1182. fbinfo_crt = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
  1183. if (fbinfo_crt == NULL) {
  1184. dev_err(dev, "cannot allocate crt framebuffer\n");
  1185. return -ENOMEM;
  1186. }
  1187. fbinfo_pnl = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
  1188. if (fbinfo_pnl == NULL) {
  1189. dev_err(dev, "cannot allocate panel framebuffer\n");
  1190. ret = -ENOMEM;
  1191. goto fbinfo_crt_alloc_fail;
  1192. }
  1193. info = sm501fb_info_alloc(fbinfo_crt, fbinfo_pnl);
  1194. if (info == NULL) {
  1195. dev_err(dev, "cannot allocate par\n");
  1196. ret = -ENOMEM;
  1197. goto sm501fb_alloc_fail;
  1198. }
  1199. if (dev->parent->platform_data) {
  1200. struct sm501_platdata *pd = dev->parent->platform_data;
  1201. info->pdata = pd->fb;
  1202. }
  1203. if (info->pdata == NULL) {
  1204. dev_info(dev, "using default configuration data\n");
  1205. info->pdata = &sm501fb_def_pdata;
  1206. }
  1207. /* start the framebuffers */
  1208. ret = sm501fb_start(info, pdev);
  1209. if (ret) {
  1210. dev_err(dev, "cannot initialise SM501\n");
  1211. goto sm501fb_start_fail;
  1212. }
  1213. /* CRT framebuffer setup */
  1214. ret = sm501fb_init_fb(fbinfo_crt, HEAD_CRT, driver_name_crt);
  1215. if (ret) {
  1216. dev_err(dev, "cannot initialise CRT fb\n");
  1217. goto sm501fb_start_fail;
  1218. }
  1219. /* Panel framebuffer setup */
  1220. ret = sm501fb_init_fb(fbinfo_pnl, HEAD_PANEL, driver_name_pnl);
  1221. if (ret) {
  1222. dev_err(dev, "cannot initialise Panel fb\n");
  1223. goto sm501fb_start_fail;
  1224. }
  1225. /* register framebuffers */
  1226. ret = register_framebuffer(fbinfo_crt);
  1227. if (ret < 0) {
  1228. dev_err(dev, "failed to register CRT fb (%d)\n", ret);
  1229. goto register_crt_fail;
  1230. }
  1231. ret = register_framebuffer(fbinfo_pnl);
  1232. if (ret < 0) {
  1233. dev_err(dev, "failed to register panel fb (%d)\n", ret);
  1234. goto register_pnl_fail;
  1235. }
  1236. dev_info(dev, "fb%d: %s frame buffer device\n",
  1237. fbinfo_crt->node, fbinfo_crt->fix.id);
  1238. dev_info(dev, "fb%d: %s frame buffer device\n",
  1239. fbinfo_pnl->node, fbinfo_pnl->fix.id);
  1240. /* create device files */
  1241. ret = device_create_file(dev, &dev_attr_crt_src);
  1242. if (ret)
  1243. goto crtsrc_fail;
  1244. ret = device_create_file(dev, &dev_attr_fbregs_pnl);
  1245. if (ret)
  1246. goto fbregs_pnl_fail;
  1247. ret = device_create_file(dev, &dev_attr_fbregs_crt);
  1248. if (ret)
  1249. goto fbregs_crt_fail;
  1250. /* we registered, return ok */
  1251. return 0;
  1252. fbregs_crt_fail:
  1253. device_remove_file(dev, &dev_attr_fbregs_pnl);
  1254. fbregs_pnl_fail:
  1255. device_remove_file(dev, &dev_attr_crt_src);
  1256. crtsrc_fail:
  1257. unregister_framebuffer(fbinfo_pnl);
  1258. register_pnl_fail:
  1259. unregister_framebuffer(fbinfo_crt);
  1260. register_crt_fail:
  1261. sm501fb_stop(info);
  1262. sm501fb_start_fail:
  1263. sm501fb_info_release(info);
  1264. sm501fb_alloc_fail:
  1265. framebuffer_release(fbinfo_pnl);
  1266. fbinfo_crt_alloc_fail:
  1267. framebuffer_release(fbinfo_crt);
  1268. return ret;
  1269. }
  1270. /*
  1271. * Cleanup
  1272. */
  1273. static int sm501fb_remove(struct platform_device *pdev)
  1274. {
  1275. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1276. struct fb_info *fbinfo_crt = info->fb[0];
  1277. struct fb_info *fbinfo_pnl = info->fb[1];
  1278. device_remove_file(&pdev->dev, &dev_attr_fbregs_crt);
  1279. device_remove_file(&pdev->dev, &dev_attr_fbregs_pnl);
  1280. device_remove_file(&pdev->dev, &dev_attr_crt_src);
  1281. unregister_framebuffer(fbinfo_crt);
  1282. unregister_framebuffer(fbinfo_pnl);
  1283. sm501fb_stop(info);
  1284. sm501fb_info_release(info);
  1285. framebuffer_release(fbinfo_pnl);
  1286. framebuffer_release(fbinfo_crt);
  1287. return 0;
  1288. }
  1289. #ifdef CONFIG_PM
  1290. static int sm501fb_suspend_fb(struct sm501fb_info *info,
  1291. enum sm501_controller head)
  1292. {
  1293. struct fb_info *fbi = info->fb[head];
  1294. struct sm501fb_par *par = fbi->par;
  1295. if (par->screen.size == 0)
  1296. return 0;
  1297. /* backup copies in case chip is powered down over suspend */
  1298. par->store_fb = vmalloc(par->screen.size);
  1299. if (par->store_fb == NULL) {
  1300. dev_err(info->dev, "no memory to store screen\n");
  1301. return -ENOMEM;
  1302. }
  1303. par->store_cursor = vmalloc(par->cursor.size);
  1304. if (par->store_cursor == NULL) {
  1305. dev_err(info->dev, "no memory to store cursor\n");
  1306. goto err_nocursor;
  1307. }
  1308. dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
  1309. dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
  1310. memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
  1311. memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
  1312. /* blank the relevant interface to ensure unit power minimised */
  1313. (par->ops.fb_blank)(FB_BLANK_POWERDOWN, fbi);
  1314. return 0;
  1315. err_nocursor:
  1316. vfree(par->store_fb);
  1317. par->store_fb = NULL;
  1318. return -ENOMEM;
  1319. }
  1320. static void sm501fb_resume_fb(struct sm501fb_info *info,
  1321. enum sm501_controller head)
  1322. {
  1323. struct fb_info *fbi = info->fb[head];
  1324. struct sm501fb_par *par = fbi->par;
  1325. if (par->screen.size == 0)
  1326. return;
  1327. /* re-activate the configuration */
  1328. (par->ops.fb_set_par)(fbi);
  1329. /* restore the data */
  1330. dev_dbg(info->dev, "restoring screen from %p\n", par->store_fb);
  1331. dev_dbg(info->dev, "restoring cursor from %p\n", par->store_cursor);
  1332. if (par->store_fb)
  1333. memcpy_toio(par->screen.k_addr, par->store_fb,
  1334. par->screen.size);
  1335. if (par->store_cursor)
  1336. memcpy_toio(par->cursor.k_addr, par->store_cursor,
  1337. par->cursor.size);
  1338. vfree(par->store_fb);
  1339. vfree(par->store_cursor);
  1340. }
  1341. /* suspend and resume support */
  1342. static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
  1343. {
  1344. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1345. /* store crt control to resume with */
  1346. info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  1347. sm501fb_suspend_fb(info, HEAD_CRT);
  1348. sm501fb_suspend_fb(info, HEAD_PANEL);
  1349. /* turn off the clocks, in case the device is not powered down */
  1350. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
  1351. return 0;
  1352. }
  1353. #define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP | \
  1354. SM501_DC_CRT_CONTROL_SEL)
  1355. static int sm501fb_resume(struct platform_device *pdev)
  1356. {
  1357. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1358. unsigned long crt_ctrl;
  1359. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
  1360. /* restore the items we want to be saved for crt control */
  1361. crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  1362. crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
  1363. crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
  1364. writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1365. sm501fb_resume_fb(info, HEAD_CRT);
  1366. sm501fb_resume_fb(info, HEAD_PANEL);
  1367. return 0;
  1368. }
  1369. #else
  1370. #define sm501fb_suspend NULL
  1371. #define sm501fb_resume NULL
  1372. #endif
  1373. static struct platform_driver sm501fb_driver = {
  1374. .probe = sm501fb_probe,
  1375. .remove = sm501fb_remove,
  1376. .suspend = sm501fb_suspend,
  1377. .resume = sm501fb_resume,
  1378. .driver = {
  1379. .name = "sm501-fb",
  1380. .owner = THIS_MODULE,
  1381. },
  1382. };
  1383. static int __devinit sm501fb_init(void)
  1384. {
  1385. return platform_driver_register(&sm501fb_driver);
  1386. }
  1387. static void __exit sm501fb_cleanup(void)
  1388. {
  1389. platform_driver_unregister(&sm501fb_driver);
  1390. }
  1391. module_init(sm501fb_init);
  1392. module_exit(sm501fb_cleanup);
  1393. MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
  1394. MODULE_DESCRIPTION("SM501 Framebuffer driver");
  1395. MODULE_LICENSE("GPL v2");