p54spi.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734
  1. /*
  2. * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
  3. * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
  4. *
  5. * This driver is a port from stlc45xx:
  6. * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. */
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/firmware.h>
  26. #include <linux/delay.h>
  27. #include <linux/irq.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/gpio.h>
  31. #include <linux/slab.h>
  32. #include "p54spi.h"
  33. #include "p54spi_eeprom.h"
  34. #include "p54.h"
  35. #include "lmac.h"
  36. MODULE_FIRMWARE("3826.arm");
  37. MODULE_ALIAS("stlc45xx");
  38. /*
  39. * gpios should be handled in board files and provided via platform data,
  40. * but because it's currently impossible for p54spi to have a header file
  41. * in include/linux, let's use module paramaters for now
  42. */
  43. static int p54spi_gpio_power = 97;
  44. module_param(p54spi_gpio_power, int, 0444);
  45. MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
  46. static int p54spi_gpio_irq = 87;
  47. module_param(p54spi_gpio_irq, int, 0444);
  48. MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
  49. static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
  50. void *buf, size_t len)
  51. {
  52. struct spi_transfer t[2];
  53. struct spi_message m;
  54. __le16 addr;
  55. /* We first push the address */
  56. addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
  57. spi_message_init(&m);
  58. memset(t, 0, sizeof(t));
  59. t[0].tx_buf = &addr;
  60. t[0].len = sizeof(addr);
  61. spi_message_add_tail(&t[0], &m);
  62. t[1].rx_buf = buf;
  63. t[1].len = len;
  64. spi_message_add_tail(&t[1], &m);
  65. spi_sync(priv->spi, &m);
  66. }
  67. static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
  68. const void *buf, size_t len)
  69. {
  70. struct spi_transfer t[3];
  71. struct spi_message m;
  72. __le16 addr;
  73. /* We first push the address */
  74. addr = cpu_to_le16(address << 8);
  75. spi_message_init(&m);
  76. memset(t, 0, sizeof(t));
  77. t[0].tx_buf = &addr;
  78. t[0].len = sizeof(addr);
  79. spi_message_add_tail(&t[0], &m);
  80. t[1].tx_buf = buf;
  81. t[1].len = len & ~1;
  82. spi_message_add_tail(&t[1], &m);
  83. if (len % 2) {
  84. __le16 last_word;
  85. last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
  86. t[2].tx_buf = &last_word;
  87. t[2].len = sizeof(last_word);
  88. spi_message_add_tail(&t[2], &m);
  89. }
  90. spi_sync(priv->spi, &m);
  91. }
  92. static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
  93. {
  94. __le32 val;
  95. p54spi_spi_read(priv, addr, &val, sizeof(val));
  96. return le32_to_cpu(val);
  97. }
  98. static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
  99. {
  100. p54spi_spi_write(priv, addr, &val, sizeof(val));
  101. }
  102. static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
  103. {
  104. p54spi_spi_write(priv, addr, &val, sizeof(val));
  105. }
  106. static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
  107. {
  108. int i;
  109. for (i = 0; i < 2000; i++) {
  110. u32 buffer = p54spi_read32(priv, reg);
  111. if ((buffer & bits) == bits)
  112. return 1;
  113. }
  114. return 0;
  115. }
  116. static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
  117. const void *buf, size_t len)
  118. {
  119. if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
  120. dev_err(&priv->spi->dev, "spi_write_dma not allowed "
  121. "to DMA write.\n");
  122. return -EAGAIN;
  123. }
  124. p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
  125. cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
  126. p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
  127. p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
  128. p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
  129. return 0;
  130. }
  131. static int p54spi_request_firmware(struct ieee80211_hw *dev)
  132. {
  133. struct p54s_priv *priv = dev->priv;
  134. int ret;
  135. /* FIXME: should driver use it's own struct device? */
  136. ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
  137. if (ret < 0) {
  138. dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
  139. return ret;
  140. }
  141. ret = p54_parse_firmware(dev, priv->firmware);
  142. if (ret) {
  143. release_firmware(priv->firmware);
  144. return ret;
  145. }
  146. return 0;
  147. }
  148. static int p54spi_request_eeprom(struct ieee80211_hw *dev)
  149. {
  150. struct p54s_priv *priv = dev->priv;
  151. const struct firmware *eeprom;
  152. int ret;
  153. /*
  154. * allow users to customize their eeprom.
  155. */
  156. ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
  157. if (ret < 0) {
  158. dev_info(&priv->spi->dev, "loading default eeprom...\n");
  159. ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
  160. sizeof(p54spi_eeprom));
  161. } else {
  162. dev_info(&priv->spi->dev, "loading user eeprom...\n");
  163. ret = p54_parse_eeprom(dev, (void *) eeprom->data,
  164. (int)eeprom->size);
  165. release_firmware(eeprom);
  166. }
  167. return ret;
  168. }
  169. static int p54spi_upload_firmware(struct ieee80211_hw *dev)
  170. {
  171. struct p54s_priv *priv = dev->priv;
  172. unsigned long fw_len, _fw_len;
  173. unsigned int offset = 0;
  174. int err = 0;
  175. u8 *fw;
  176. fw_len = priv->firmware->size;
  177. fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
  178. if (!fw)
  179. return -ENOMEM;
  180. /* stop the device */
  181. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  182. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
  183. SPI_CTRL_STAT_START_HALTED));
  184. msleep(TARGET_BOOT_SLEEP);
  185. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  186. SPI_CTRL_STAT_HOST_OVERRIDE |
  187. SPI_CTRL_STAT_START_HALTED));
  188. msleep(TARGET_BOOT_SLEEP);
  189. while (fw_len > 0) {
  190. _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
  191. err = p54spi_spi_write_dma(priv, cpu_to_le32(
  192. ISL38XX_DEV_FIRMWARE_ADDR + offset),
  193. (fw + offset), _fw_len);
  194. if (err < 0)
  195. goto out;
  196. fw_len -= _fw_len;
  197. offset += _fw_len;
  198. }
  199. BUG_ON(fw_len != 0);
  200. /* enable host interrupts */
  201. p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
  202. cpu_to_le32(SPI_HOST_INTS_DEFAULT));
  203. /* boot the device */
  204. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  205. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
  206. SPI_CTRL_STAT_RAM_BOOT));
  207. msleep(TARGET_BOOT_SLEEP);
  208. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  209. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
  210. msleep(TARGET_BOOT_SLEEP);
  211. out:
  212. kfree(fw);
  213. return err;
  214. }
  215. static void p54spi_power_off(struct p54s_priv *priv)
  216. {
  217. disable_irq(gpio_to_irq(p54spi_gpio_irq));
  218. gpio_set_value(p54spi_gpio_power, 0);
  219. }
  220. static void p54spi_power_on(struct p54s_priv *priv)
  221. {
  222. gpio_set_value(p54spi_gpio_power, 1);
  223. enable_irq(gpio_to_irq(p54spi_gpio_irq));
  224. /*
  225. * need to wait a while before device can be accessed, the lenght
  226. * is just a guess
  227. */
  228. msleep(10);
  229. }
  230. static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
  231. {
  232. p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
  233. }
  234. static int p54spi_wakeup(struct p54s_priv *priv)
  235. {
  236. /* wake the chip */
  237. p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
  238. cpu_to_le32(SPI_TARGET_INT_WAKEUP));
  239. /* And wait for the READY interrupt */
  240. if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
  241. SPI_HOST_INT_READY)) {
  242. dev_err(&priv->spi->dev, "INT_READY timeout\n");
  243. return -EBUSY;
  244. }
  245. p54spi_int_ack(priv, SPI_HOST_INT_READY);
  246. return 0;
  247. }
  248. static inline void p54spi_sleep(struct p54s_priv *priv)
  249. {
  250. p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
  251. cpu_to_le32(SPI_TARGET_INT_SLEEP));
  252. }
  253. static void p54spi_int_ready(struct p54s_priv *priv)
  254. {
  255. p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
  256. SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
  257. switch (priv->fw_state) {
  258. case FW_STATE_BOOTING:
  259. priv->fw_state = FW_STATE_READY;
  260. complete(&priv->fw_comp);
  261. break;
  262. case FW_STATE_RESETTING:
  263. priv->fw_state = FW_STATE_READY;
  264. /* TODO: reinitialize state */
  265. break;
  266. default:
  267. break;
  268. }
  269. }
  270. static int p54spi_rx(struct p54s_priv *priv)
  271. {
  272. struct sk_buff *skb;
  273. u16 len;
  274. u16 rx_head[2];
  275. #define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
  276. if (p54spi_wakeup(priv) < 0)
  277. return -EBUSY;
  278. /* Read data size and first data word in one SPI transaction
  279. * This is workaround for firmware/DMA bug,
  280. * when first data word gets lost under high load.
  281. */
  282. p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
  283. len = rx_head[0];
  284. if (len == 0) {
  285. p54spi_sleep(priv);
  286. dev_err(&priv->spi->dev, "rx request of zero bytes\n");
  287. return 0;
  288. }
  289. /* Firmware may insert up to 4 padding bytes after the lmac header,
  290. * but it does not amend the size of SPI data transfer.
  291. * Such packets has correct data size in header, thus referencing
  292. * past the end of allocated skb. Reserve extra 4 bytes for this case */
  293. skb = dev_alloc_skb(len + 4);
  294. if (!skb) {
  295. p54spi_sleep(priv);
  296. dev_err(&priv->spi->dev, "could not alloc skb");
  297. return -ENOMEM;
  298. }
  299. if (len <= READAHEAD_SZ) {
  300. memcpy(skb_put(skb, len), rx_head + 1, len);
  301. } else {
  302. memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
  303. p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
  304. skb_put(skb, len - READAHEAD_SZ),
  305. len - READAHEAD_SZ);
  306. }
  307. p54spi_sleep(priv);
  308. /* Put additional bytes to compensate for the possible
  309. * alignment-caused truncation */
  310. skb_put(skb, 4);
  311. if (p54_rx(priv->hw, skb) == 0)
  312. dev_kfree_skb(skb);
  313. return 0;
  314. }
  315. static irqreturn_t p54spi_interrupt(int irq, void *config)
  316. {
  317. struct spi_device *spi = config;
  318. struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
  319. ieee80211_queue_work(priv->hw, &priv->work);
  320. return IRQ_HANDLED;
  321. }
  322. static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
  323. {
  324. struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
  325. int ret = 0;
  326. if (p54spi_wakeup(priv) < 0)
  327. return -EBUSY;
  328. ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
  329. if (ret < 0)
  330. goto out;
  331. if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
  332. SPI_HOST_INT_WR_READY)) {
  333. dev_err(&priv->spi->dev, "WR_READY timeout\n");
  334. ret = -EAGAIN;
  335. goto out;
  336. }
  337. p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
  338. if (FREE_AFTER_TX(skb))
  339. p54_free_skb(priv->hw, skb);
  340. out:
  341. p54spi_sleep(priv);
  342. return ret;
  343. }
  344. static int p54spi_wq_tx(struct p54s_priv *priv)
  345. {
  346. struct p54s_tx_info *entry;
  347. struct sk_buff *skb;
  348. struct ieee80211_tx_info *info;
  349. struct p54_tx_info *minfo;
  350. struct p54s_tx_info *dinfo;
  351. unsigned long flags;
  352. int ret = 0;
  353. spin_lock_irqsave(&priv->tx_lock, flags);
  354. while (!list_empty(&priv->tx_pending)) {
  355. entry = list_entry(priv->tx_pending.next,
  356. struct p54s_tx_info, tx_list);
  357. list_del_init(&entry->tx_list);
  358. spin_unlock_irqrestore(&priv->tx_lock, flags);
  359. dinfo = container_of((void *) entry, struct p54s_tx_info,
  360. tx_list);
  361. minfo = container_of((void *) dinfo, struct p54_tx_info,
  362. data);
  363. info = container_of((void *) minfo, struct ieee80211_tx_info,
  364. rate_driver_data);
  365. skb = container_of((void *) info, struct sk_buff, cb);
  366. ret = p54spi_tx_frame(priv, skb);
  367. if (ret < 0) {
  368. p54_free_skb(priv->hw, skb);
  369. return ret;
  370. }
  371. spin_lock_irqsave(&priv->tx_lock, flags);
  372. }
  373. spin_unlock_irqrestore(&priv->tx_lock, flags);
  374. return ret;
  375. }
  376. static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  377. {
  378. struct p54s_priv *priv = dev->priv;
  379. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  380. struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
  381. struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
  382. unsigned long flags;
  383. BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
  384. spin_lock_irqsave(&priv->tx_lock, flags);
  385. list_add_tail(&di->tx_list, &priv->tx_pending);
  386. spin_unlock_irqrestore(&priv->tx_lock, flags);
  387. ieee80211_queue_work(priv->hw, &priv->work);
  388. }
  389. static void p54spi_work(struct work_struct *work)
  390. {
  391. struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
  392. u32 ints;
  393. int ret;
  394. mutex_lock(&priv->mutex);
  395. if (priv->fw_state == FW_STATE_OFF)
  396. goto out;
  397. ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
  398. if (ints & SPI_HOST_INT_READY) {
  399. p54spi_int_ready(priv);
  400. p54spi_int_ack(priv, SPI_HOST_INT_READY);
  401. }
  402. if (priv->fw_state != FW_STATE_READY)
  403. goto out;
  404. if (ints & SPI_HOST_INT_UPDATE) {
  405. p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
  406. ret = p54spi_rx(priv);
  407. if (ret < 0)
  408. goto out;
  409. }
  410. if (ints & SPI_HOST_INT_SW_UPDATE) {
  411. p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
  412. ret = p54spi_rx(priv);
  413. if (ret < 0)
  414. goto out;
  415. }
  416. ret = p54spi_wq_tx(priv);
  417. out:
  418. mutex_unlock(&priv->mutex);
  419. }
  420. static int p54spi_op_start(struct ieee80211_hw *dev)
  421. {
  422. struct p54s_priv *priv = dev->priv;
  423. unsigned long timeout;
  424. int ret = 0;
  425. if (mutex_lock_interruptible(&priv->mutex)) {
  426. ret = -EINTR;
  427. goto out;
  428. }
  429. priv->fw_state = FW_STATE_BOOTING;
  430. p54spi_power_on(priv);
  431. ret = p54spi_upload_firmware(dev);
  432. if (ret < 0) {
  433. p54spi_power_off(priv);
  434. goto out_unlock;
  435. }
  436. mutex_unlock(&priv->mutex);
  437. timeout = msecs_to_jiffies(2000);
  438. timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
  439. timeout);
  440. if (!timeout) {
  441. dev_err(&priv->spi->dev, "firmware boot failed");
  442. p54spi_power_off(priv);
  443. ret = -1;
  444. goto out;
  445. }
  446. if (mutex_lock_interruptible(&priv->mutex)) {
  447. ret = -EINTR;
  448. p54spi_power_off(priv);
  449. goto out;
  450. }
  451. WARN_ON(priv->fw_state != FW_STATE_READY);
  452. out_unlock:
  453. mutex_unlock(&priv->mutex);
  454. out:
  455. return ret;
  456. }
  457. static void p54spi_op_stop(struct ieee80211_hw *dev)
  458. {
  459. struct p54s_priv *priv = dev->priv;
  460. unsigned long flags;
  461. if (mutex_lock_interruptible(&priv->mutex)) {
  462. /* FIXME: how to handle this error? */
  463. return;
  464. }
  465. WARN_ON(priv->fw_state != FW_STATE_READY);
  466. cancel_work_sync(&priv->work);
  467. p54spi_power_off(priv);
  468. spin_lock_irqsave(&priv->tx_lock, flags);
  469. INIT_LIST_HEAD(&priv->tx_pending);
  470. spin_unlock_irqrestore(&priv->tx_lock, flags);
  471. priv->fw_state = FW_STATE_OFF;
  472. mutex_unlock(&priv->mutex);
  473. }
  474. static int __devinit p54spi_probe(struct spi_device *spi)
  475. {
  476. struct p54s_priv *priv = NULL;
  477. struct ieee80211_hw *hw;
  478. int ret = -EINVAL;
  479. hw = p54_init_common(sizeof(*priv));
  480. if (!hw) {
  481. dev_err(&spi->dev, "could not alloc ieee80211_hw");
  482. return -ENOMEM;
  483. }
  484. priv = hw->priv;
  485. priv->hw = hw;
  486. dev_set_drvdata(&spi->dev, priv);
  487. priv->spi = spi;
  488. spi->bits_per_word = 16;
  489. spi->max_speed_hz = 24000000;
  490. ret = spi_setup(spi);
  491. if (ret < 0) {
  492. dev_err(&priv->spi->dev, "spi_setup failed");
  493. goto err_free_common;
  494. }
  495. ret = gpio_request(p54spi_gpio_power, "p54spi power");
  496. if (ret < 0) {
  497. dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
  498. goto err_free_common;
  499. }
  500. ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
  501. if (ret < 0) {
  502. dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
  503. goto err_free_common;
  504. }
  505. gpio_direction_output(p54spi_gpio_power, 0);
  506. gpio_direction_input(p54spi_gpio_irq);
  507. ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
  508. p54spi_interrupt, IRQF_DISABLED, "p54spi",
  509. priv->spi);
  510. if (ret < 0) {
  511. dev_err(&priv->spi->dev, "request_irq() failed");
  512. goto err_free_common;
  513. }
  514. set_irq_type(gpio_to_irq(p54spi_gpio_irq),
  515. IRQ_TYPE_EDGE_RISING);
  516. disable_irq(gpio_to_irq(p54spi_gpio_irq));
  517. INIT_WORK(&priv->work, p54spi_work);
  518. init_completion(&priv->fw_comp);
  519. INIT_LIST_HEAD(&priv->tx_pending);
  520. mutex_init(&priv->mutex);
  521. SET_IEEE80211_DEV(hw, &spi->dev);
  522. priv->common.open = p54spi_op_start;
  523. priv->common.stop = p54spi_op_stop;
  524. priv->common.tx = p54spi_op_tx;
  525. ret = p54spi_request_firmware(hw);
  526. if (ret < 0)
  527. goto err_free_common;
  528. ret = p54spi_request_eeprom(hw);
  529. if (ret)
  530. goto err_free_common;
  531. ret = p54_register_common(hw, &priv->spi->dev);
  532. if (ret)
  533. goto err_free_common;
  534. return 0;
  535. err_free_common:
  536. p54_free_common(priv->hw);
  537. return ret;
  538. }
  539. static int __devexit p54spi_remove(struct spi_device *spi)
  540. {
  541. struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
  542. p54_unregister_common(priv->hw);
  543. free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
  544. gpio_free(p54spi_gpio_power);
  545. gpio_free(p54spi_gpio_irq);
  546. release_firmware(priv->firmware);
  547. mutex_destroy(&priv->mutex);
  548. p54_free_common(priv->hw);
  549. return 0;
  550. }
  551. static struct spi_driver p54spi_driver = {
  552. .driver = {
  553. .name = "p54spi",
  554. .bus = &spi_bus_type,
  555. .owner = THIS_MODULE,
  556. },
  557. .probe = p54spi_probe,
  558. .remove = __devexit_p(p54spi_remove),
  559. };
  560. static int __init p54spi_init(void)
  561. {
  562. int ret;
  563. ret = spi_register_driver(&p54spi_driver);
  564. if (ret < 0) {
  565. printk(KERN_ERR "failed to register SPI driver: %d", ret);
  566. goto out;
  567. }
  568. out:
  569. return ret;
  570. }
  571. static void __exit p54spi_exit(void)
  572. {
  573. spi_unregister_driver(&p54spi_driver);
  574. }
  575. module_init(p54spi_init);
  576. module_exit(p54spi_exit);
  577. MODULE_LICENSE("GPL");
  578. MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
  579. MODULE_ALIAS("spi:cx3110x");
  580. MODULE_ALIAS("spi:p54spi");