mtd.c 16 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2009 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/module.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/rtnetlink.h>
  16. #include "net_driver.h"
  17. #include "spi.h"
  18. #include "efx.h"
  19. #include "nic.h"
  20. #include "mcdi.h"
  21. #include "mcdi_pcol.h"
  22. #define EFX_SPI_VERIFY_BUF_LEN 16
  23. struct efx_mtd_partition {
  24. struct mtd_info mtd;
  25. union {
  26. struct {
  27. bool updating;
  28. u8 nvram_type;
  29. u16 fw_subtype;
  30. } mcdi;
  31. size_t offset;
  32. };
  33. const char *type_name;
  34. char name[IFNAMSIZ + 20];
  35. };
  36. struct efx_mtd_ops {
  37. int (*read)(struct mtd_info *mtd, loff_t start, size_t len,
  38. size_t *retlen, u8 *buffer);
  39. int (*erase)(struct mtd_info *mtd, loff_t start, size_t len);
  40. int (*write)(struct mtd_info *mtd, loff_t start, size_t len,
  41. size_t *retlen, const u8 *buffer);
  42. int (*sync)(struct mtd_info *mtd);
  43. };
  44. struct efx_mtd {
  45. struct list_head node;
  46. struct efx_nic *efx;
  47. const struct efx_spi_device *spi;
  48. const char *name;
  49. const struct efx_mtd_ops *ops;
  50. size_t n_parts;
  51. struct efx_mtd_partition part[0];
  52. };
  53. #define efx_for_each_partition(part, efx_mtd) \
  54. for ((part) = &(efx_mtd)->part[0]; \
  55. (part) != &(efx_mtd)->part[(efx_mtd)->n_parts]; \
  56. (part)++)
  57. #define to_efx_mtd_partition(mtd) \
  58. container_of(mtd, struct efx_mtd_partition, mtd)
  59. static int falcon_mtd_probe(struct efx_nic *efx);
  60. static int siena_mtd_probe(struct efx_nic *efx);
  61. /* SPI utilities */
  62. static int
  63. efx_spi_slow_wait(struct efx_mtd_partition *part, bool uninterruptible)
  64. {
  65. struct efx_mtd *efx_mtd = part->mtd.priv;
  66. const struct efx_spi_device *spi = efx_mtd->spi;
  67. struct efx_nic *efx = efx_mtd->efx;
  68. u8 status;
  69. int rc, i;
  70. /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
  71. for (i = 0; i < 40; i++) {
  72. __set_current_state(uninterruptible ?
  73. TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
  74. schedule_timeout(HZ / 10);
  75. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  76. &status, sizeof(status));
  77. if (rc)
  78. return rc;
  79. if (!(status & SPI_STATUS_NRDY))
  80. return 0;
  81. if (signal_pending(current))
  82. return -EINTR;
  83. }
  84. pr_err("%s: timed out waiting for %s\n", part->name, efx_mtd->name);
  85. return -ETIMEDOUT;
  86. }
  87. static int
  88. efx_spi_unlock(struct efx_nic *efx, const struct efx_spi_device *spi)
  89. {
  90. const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
  91. SPI_STATUS_BP0);
  92. u8 status;
  93. int rc;
  94. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  95. &status, sizeof(status));
  96. if (rc)
  97. return rc;
  98. if (!(status & unlock_mask))
  99. return 0; /* already unlocked */
  100. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  101. if (rc)
  102. return rc;
  103. rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
  104. if (rc)
  105. return rc;
  106. status &= ~unlock_mask;
  107. rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
  108. NULL, sizeof(status));
  109. if (rc)
  110. return rc;
  111. rc = falcon_spi_wait_write(efx, spi);
  112. if (rc)
  113. return rc;
  114. return 0;
  115. }
  116. static int
  117. efx_spi_erase(struct efx_mtd_partition *part, loff_t start, size_t len)
  118. {
  119. struct efx_mtd *efx_mtd = part->mtd.priv;
  120. const struct efx_spi_device *spi = efx_mtd->spi;
  121. struct efx_nic *efx = efx_mtd->efx;
  122. unsigned pos, block_len;
  123. u8 empty[EFX_SPI_VERIFY_BUF_LEN];
  124. u8 buffer[EFX_SPI_VERIFY_BUF_LEN];
  125. int rc;
  126. if (len != spi->erase_size)
  127. return -EINVAL;
  128. if (spi->erase_command == 0)
  129. return -EOPNOTSUPP;
  130. rc = efx_spi_unlock(efx, spi);
  131. if (rc)
  132. return rc;
  133. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  134. if (rc)
  135. return rc;
  136. rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
  137. NULL, 0);
  138. if (rc)
  139. return rc;
  140. rc = efx_spi_slow_wait(part, false);
  141. /* Verify the entire region has been wiped */
  142. memset(empty, 0xff, sizeof(empty));
  143. for (pos = 0; pos < len; pos += block_len) {
  144. block_len = min(len - pos, sizeof(buffer));
  145. rc = falcon_spi_read(efx, spi, start + pos, block_len,
  146. NULL, buffer);
  147. if (rc)
  148. return rc;
  149. if (memcmp(empty, buffer, block_len))
  150. return -EIO;
  151. /* Avoid locking up the system */
  152. cond_resched();
  153. if (signal_pending(current))
  154. return -EINTR;
  155. }
  156. return rc;
  157. }
  158. /* MTD interface */
  159. static int efx_mtd_erase(struct mtd_info *mtd, struct erase_info *erase)
  160. {
  161. struct efx_mtd *efx_mtd = mtd->priv;
  162. int rc;
  163. rc = efx_mtd->ops->erase(mtd, erase->addr, erase->len);
  164. if (rc == 0) {
  165. erase->state = MTD_ERASE_DONE;
  166. } else {
  167. erase->state = MTD_ERASE_FAILED;
  168. erase->fail_addr = 0xffffffff;
  169. }
  170. mtd_erase_callback(erase);
  171. return rc;
  172. }
  173. static void efx_mtd_sync(struct mtd_info *mtd)
  174. {
  175. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  176. struct efx_mtd *efx_mtd = mtd->priv;
  177. int rc;
  178. rc = efx_mtd->ops->sync(mtd);
  179. if (rc)
  180. pr_err("%s: %s sync failed (%d)\n",
  181. part->name, efx_mtd->name, rc);
  182. }
  183. static void efx_mtd_remove_partition(struct efx_mtd_partition *part)
  184. {
  185. int rc;
  186. for (;;) {
  187. rc = del_mtd_device(&part->mtd);
  188. if (rc != -EBUSY)
  189. break;
  190. ssleep(1);
  191. }
  192. WARN_ON(rc);
  193. }
  194. static void efx_mtd_remove_device(struct efx_mtd *efx_mtd)
  195. {
  196. struct efx_mtd_partition *part;
  197. efx_for_each_partition(part, efx_mtd)
  198. efx_mtd_remove_partition(part);
  199. list_del(&efx_mtd->node);
  200. kfree(efx_mtd);
  201. }
  202. static void efx_mtd_rename_device(struct efx_mtd *efx_mtd)
  203. {
  204. struct efx_mtd_partition *part;
  205. efx_for_each_partition(part, efx_mtd)
  206. if (efx_nic_rev(efx_mtd->efx) >= EFX_REV_SIENA_A0)
  207. snprintf(part->name, sizeof(part->name),
  208. "%s %s:%02x", efx_mtd->efx->name,
  209. part->type_name, part->mcdi.fw_subtype);
  210. else
  211. snprintf(part->name, sizeof(part->name),
  212. "%s %s", efx_mtd->efx->name,
  213. part->type_name);
  214. }
  215. static int efx_mtd_probe_device(struct efx_nic *efx, struct efx_mtd *efx_mtd)
  216. {
  217. struct efx_mtd_partition *part;
  218. efx_mtd->efx = efx;
  219. efx_mtd_rename_device(efx_mtd);
  220. efx_for_each_partition(part, efx_mtd) {
  221. part->mtd.writesize = 1;
  222. part->mtd.owner = THIS_MODULE;
  223. part->mtd.priv = efx_mtd;
  224. part->mtd.name = part->name;
  225. part->mtd.erase = efx_mtd_erase;
  226. part->mtd.read = efx_mtd->ops->read;
  227. part->mtd.write = efx_mtd->ops->write;
  228. part->mtd.sync = efx_mtd_sync;
  229. if (add_mtd_device(&part->mtd))
  230. goto fail;
  231. }
  232. list_add(&efx_mtd->node, &efx->mtd_list);
  233. return 0;
  234. fail:
  235. while (part != &efx_mtd->part[0]) {
  236. --part;
  237. efx_mtd_remove_partition(part);
  238. }
  239. /* add_mtd_device() returns 1 if the MTD table is full */
  240. return -ENOMEM;
  241. }
  242. void efx_mtd_remove(struct efx_nic *efx)
  243. {
  244. struct efx_mtd *efx_mtd, *next;
  245. WARN_ON(efx_dev_registered(efx));
  246. list_for_each_entry_safe(efx_mtd, next, &efx->mtd_list, node)
  247. efx_mtd_remove_device(efx_mtd);
  248. }
  249. void efx_mtd_rename(struct efx_nic *efx)
  250. {
  251. struct efx_mtd *efx_mtd;
  252. ASSERT_RTNL();
  253. list_for_each_entry(efx_mtd, &efx->mtd_list, node)
  254. efx_mtd_rename_device(efx_mtd);
  255. }
  256. int efx_mtd_probe(struct efx_nic *efx)
  257. {
  258. if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
  259. return siena_mtd_probe(efx);
  260. else
  261. return falcon_mtd_probe(efx);
  262. }
  263. /* Implementation of MTD operations for Falcon */
  264. static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
  265. size_t len, size_t *retlen, u8 *buffer)
  266. {
  267. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  268. struct efx_mtd *efx_mtd = mtd->priv;
  269. const struct efx_spi_device *spi = efx_mtd->spi;
  270. struct efx_nic *efx = efx_mtd->efx;
  271. int rc;
  272. rc = mutex_lock_interruptible(&efx->spi_lock);
  273. if (rc)
  274. return rc;
  275. rc = falcon_spi_read(efx, spi, part->offset + start, len,
  276. retlen, buffer);
  277. mutex_unlock(&efx->spi_lock);
  278. return rc;
  279. }
  280. static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  281. {
  282. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  283. struct efx_mtd *efx_mtd = mtd->priv;
  284. struct efx_nic *efx = efx_mtd->efx;
  285. int rc;
  286. rc = mutex_lock_interruptible(&efx->spi_lock);
  287. if (rc)
  288. return rc;
  289. rc = efx_spi_erase(part, part->offset + start, len);
  290. mutex_unlock(&efx->spi_lock);
  291. return rc;
  292. }
  293. static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
  294. size_t len, size_t *retlen, const u8 *buffer)
  295. {
  296. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  297. struct efx_mtd *efx_mtd = mtd->priv;
  298. const struct efx_spi_device *spi = efx_mtd->spi;
  299. struct efx_nic *efx = efx_mtd->efx;
  300. int rc;
  301. rc = mutex_lock_interruptible(&efx->spi_lock);
  302. if (rc)
  303. return rc;
  304. rc = falcon_spi_write(efx, spi, part->offset + start, len,
  305. retlen, buffer);
  306. mutex_unlock(&efx->spi_lock);
  307. return rc;
  308. }
  309. static int falcon_mtd_sync(struct mtd_info *mtd)
  310. {
  311. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  312. struct efx_mtd *efx_mtd = mtd->priv;
  313. struct efx_nic *efx = efx_mtd->efx;
  314. int rc;
  315. mutex_lock(&efx->spi_lock);
  316. rc = efx_spi_slow_wait(part, true);
  317. mutex_unlock(&efx->spi_lock);
  318. return rc;
  319. }
  320. static struct efx_mtd_ops falcon_mtd_ops = {
  321. .read = falcon_mtd_read,
  322. .erase = falcon_mtd_erase,
  323. .write = falcon_mtd_write,
  324. .sync = falcon_mtd_sync,
  325. };
  326. static int falcon_mtd_probe(struct efx_nic *efx)
  327. {
  328. struct efx_spi_device *spi = efx->spi_flash;
  329. struct efx_mtd *efx_mtd;
  330. int rc;
  331. ASSERT_RTNL();
  332. if (!spi || spi->size <= FALCON_FLASH_BOOTCODE_START)
  333. return -ENODEV;
  334. efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]),
  335. GFP_KERNEL);
  336. if (!efx_mtd)
  337. return -ENOMEM;
  338. efx_mtd->spi = spi;
  339. efx_mtd->name = "flash";
  340. efx_mtd->ops = &falcon_mtd_ops;
  341. efx_mtd->n_parts = 1;
  342. efx_mtd->part[0].mtd.type = MTD_NORFLASH;
  343. efx_mtd->part[0].mtd.flags = MTD_CAP_NORFLASH;
  344. efx_mtd->part[0].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
  345. efx_mtd->part[0].mtd.erasesize = spi->erase_size;
  346. efx_mtd->part[0].offset = FALCON_FLASH_BOOTCODE_START;
  347. efx_mtd->part[0].type_name = "sfc_flash_bootrom";
  348. rc = efx_mtd_probe_device(efx, efx_mtd);
  349. if (rc)
  350. kfree(efx_mtd);
  351. return rc;
  352. }
  353. /* Implementation of MTD operations for Siena */
  354. static int siena_mtd_read(struct mtd_info *mtd, loff_t start,
  355. size_t len, size_t *retlen, u8 *buffer)
  356. {
  357. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  358. struct efx_mtd *efx_mtd = mtd->priv;
  359. struct efx_nic *efx = efx_mtd->efx;
  360. loff_t offset = start;
  361. loff_t end = min_t(loff_t, start + len, mtd->size);
  362. size_t chunk;
  363. int rc = 0;
  364. while (offset < end) {
  365. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  366. rc = efx_mcdi_nvram_read(efx, part->mcdi.nvram_type, offset,
  367. buffer, chunk);
  368. if (rc)
  369. goto out;
  370. offset += chunk;
  371. buffer += chunk;
  372. }
  373. out:
  374. *retlen = offset - start;
  375. return rc;
  376. }
  377. static int siena_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  378. {
  379. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  380. struct efx_mtd *efx_mtd = mtd->priv;
  381. struct efx_nic *efx = efx_mtd->efx;
  382. loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
  383. loff_t end = min_t(loff_t, start + len, mtd->size);
  384. size_t chunk = part->mtd.erasesize;
  385. int rc = 0;
  386. if (!part->mcdi.updating) {
  387. rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
  388. if (rc)
  389. goto out;
  390. part->mcdi.updating = 1;
  391. }
  392. /* The MCDI interface can in fact do multiple erase blocks at once;
  393. * but erasing may be slow, so we make multiple calls here to avoid
  394. * tripping the MCDI RPC timeout. */
  395. while (offset < end) {
  396. rc = efx_mcdi_nvram_erase(efx, part->mcdi.nvram_type, offset,
  397. chunk);
  398. if (rc)
  399. goto out;
  400. offset += chunk;
  401. }
  402. out:
  403. return rc;
  404. }
  405. static int siena_mtd_write(struct mtd_info *mtd, loff_t start,
  406. size_t len, size_t *retlen, const u8 *buffer)
  407. {
  408. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  409. struct efx_mtd *efx_mtd = mtd->priv;
  410. struct efx_nic *efx = efx_mtd->efx;
  411. loff_t offset = start;
  412. loff_t end = min_t(loff_t, start + len, mtd->size);
  413. size_t chunk;
  414. int rc = 0;
  415. if (!part->mcdi.updating) {
  416. rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
  417. if (rc)
  418. goto out;
  419. part->mcdi.updating = 1;
  420. }
  421. while (offset < end) {
  422. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  423. rc = efx_mcdi_nvram_write(efx, part->mcdi.nvram_type, offset,
  424. buffer, chunk);
  425. if (rc)
  426. goto out;
  427. offset += chunk;
  428. buffer += chunk;
  429. }
  430. out:
  431. *retlen = offset - start;
  432. return rc;
  433. }
  434. static int siena_mtd_sync(struct mtd_info *mtd)
  435. {
  436. struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
  437. struct efx_mtd *efx_mtd = mtd->priv;
  438. struct efx_nic *efx = efx_mtd->efx;
  439. int rc = 0;
  440. if (part->mcdi.updating) {
  441. part->mcdi.updating = 0;
  442. rc = efx_mcdi_nvram_update_finish(efx, part->mcdi.nvram_type);
  443. }
  444. return rc;
  445. }
  446. static struct efx_mtd_ops siena_mtd_ops = {
  447. .read = siena_mtd_read,
  448. .erase = siena_mtd_erase,
  449. .write = siena_mtd_write,
  450. .sync = siena_mtd_sync,
  451. };
  452. struct siena_nvram_type_info {
  453. int port;
  454. const char *name;
  455. };
  456. static struct siena_nvram_type_info siena_nvram_types[] = {
  457. [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
  458. [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
  459. [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
  460. [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
  461. [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
  462. [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
  463. [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
  464. [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
  465. [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
  466. [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
  467. [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
  468. [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
  469. };
  470. static int siena_mtd_probe_partition(struct efx_nic *efx,
  471. struct efx_mtd *efx_mtd,
  472. unsigned int part_id,
  473. unsigned int type)
  474. {
  475. struct efx_mtd_partition *part = &efx_mtd->part[part_id];
  476. struct siena_nvram_type_info *info;
  477. size_t size, erase_size;
  478. bool protected;
  479. int rc;
  480. if (type >= ARRAY_SIZE(siena_nvram_types))
  481. return -ENODEV;
  482. info = &siena_nvram_types[type];
  483. if (info->port != efx_port_num(efx))
  484. return -ENODEV;
  485. rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
  486. if (rc)
  487. return rc;
  488. if (protected)
  489. return -ENODEV; /* hide it */
  490. part->mcdi.nvram_type = type;
  491. part->type_name = info->name;
  492. part->mtd.type = MTD_NORFLASH;
  493. part->mtd.flags = MTD_CAP_NORFLASH;
  494. part->mtd.size = size;
  495. part->mtd.erasesize = erase_size;
  496. return 0;
  497. }
  498. static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
  499. struct efx_mtd *efx_mtd)
  500. {
  501. struct efx_mtd_partition *part;
  502. uint16_t fw_subtype_list[MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN /
  503. sizeof(uint16_t)];
  504. int rc;
  505. rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list);
  506. if (rc)
  507. return rc;
  508. efx_for_each_partition(part, efx_mtd)
  509. part->mcdi.fw_subtype = fw_subtype_list[part->mcdi.nvram_type];
  510. return 0;
  511. }
  512. static int siena_mtd_probe(struct efx_nic *efx)
  513. {
  514. struct efx_mtd *efx_mtd;
  515. int rc = -ENODEV;
  516. u32 nvram_types;
  517. unsigned int type;
  518. ASSERT_RTNL();
  519. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  520. if (rc)
  521. return rc;
  522. efx_mtd = kzalloc(sizeof(*efx_mtd) +
  523. hweight32(nvram_types) * sizeof(efx_mtd->part[0]),
  524. GFP_KERNEL);
  525. if (!efx_mtd)
  526. return -ENOMEM;
  527. efx_mtd->name = "Siena NVRAM manager";
  528. efx_mtd->ops = &siena_mtd_ops;
  529. type = 0;
  530. efx_mtd->n_parts = 0;
  531. while (nvram_types != 0) {
  532. if (nvram_types & 1) {
  533. rc = siena_mtd_probe_partition(efx, efx_mtd,
  534. efx_mtd->n_parts, type);
  535. if (rc == 0)
  536. efx_mtd->n_parts++;
  537. else if (rc != -ENODEV)
  538. goto fail;
  539. }
  540. type++;
  541. nvram_types >>= 1;
  542. }
  543. rc = siena_mtd_get_fw_subtypes(efx, efx_mtd);
  544. if (rc)
  545. goto fail;
  546. rc = efx_mtd_probe_device(efx, efx_mtd);
  547. fail:
  548. if (rc)
  549. kfree(efx_mtd);
  550. return rc;
  551. }