mcdi.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2009 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. /* Software-defined structure to the shared-memory */
  23. #define CMD_NOTIFY_PORT0 0
  24. #define CMD_NOTIFY_PORT1 4
  25. #define CMD_PDU_PORT0 0x008
  26. #define CMD_PDU_PORT1 0x108
  27. #define REBOOT_FLAG_PORT0 0x3f8
  28. #define REBOOT_FLAG_PORT1 0x3fc
  29. #define MCDI_RPC_TIMEOUT 10 /*seconds */
  30. #define MCDI_PDU(efx) \
  31. (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
  32. #define MCDI_DOORBELL(efx) \
  33. (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
  34. #define MCDI_REBOOT_FLAG(efx) \
  35. (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= 0x100);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= 0x100);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned int time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = get_seconds() + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = get_seconds();
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time >= finish)
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. netif_err(efx, hw, efx->net_dev,
  143. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  144. respseq, mcdi->seqno);
  145. rc = EIO;
  146. } else if (error) {
  147. efx_readd(efx, &reg, pdu + 4);
  148. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  149. #define TRANSLATE_ERROR(name) \
  150. case MC_CMD_ERR_ ## name: \
  151. rc = name; \
  152. break
  153. TRANSLATE_ERROR(ENOENT);
  154. TRANSLATE_ERROR(EINTR);
  155. TRANSLATE_ERROR(EACCES);
  156. TRANSLATE_ERROR(EBUSY);
  157. TRANSLATE_ERROR(EINVAL);
  158. TRANSLATE_ERROR(EDEADLK);
  159. TRANSLATE_ERROR(ENOSYS);
  160. TRANSLATE_ERROR(ETIME);
  161. #undef TRANSLATE_ERROR
  162. default:
  163. rc = EIO;
  164. break;
  165. }
  166. } else
  167. rc = 0;
  168. out:
  169. mcdi->resprc = rc;
  170. if (rc)
  171. mcdi->resplen = 0;
  172. /* Return rc=0 like wait_event_timeout() */
  173. return 0;
  174. }
  175. /* Test and clear MC-rebooted flag for this port/function */
  176. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  177. {
  178. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
  179. efx_dword_t reg;
  180. uint32_t value;
  181. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  182. return false;
  183. efx_readd(efx, &reg, addr);
  184. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  185. if (value == 0)
  186. return 0;
  187. EFX_ZERO_DWORD(reg);
  188. efx_writed(efx, &reg, addr);
  189. if (value == MC_STATUS_DWORD_ASSERT)
  190. return -EINTR;
  191. else
  192. return -EIO;
  193. }
  194. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  195. {
  196. /* Wait until the interface becomes QUIESCENT and we win the race
  197. * to mark it RUNNING. */
  198. wait_event(mcdi->wq,
  199. atomic_cmpxchg(&mcdi->state,
  200. MCDI_STATE_QUIESCENT,
  201. MCDI_STATE_RUNNING)
  202. == MCDI_STATE_QUIESCENT);
  203. }
  204. static int efx_mcdi_await_completion(struct efx_nic *efx)
  205. {
  206. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  207. if (wait_event_timeout(
  208. mcdi->wq,
  209. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  210. msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
  211. return -ETIMEDOUT;
  212. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  213. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  214. * completed the request first, then we'll just end up completing the
  215. * request again, which is safe.
  216. *
  217. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  218. * wait_event_timeout() implicitly provides.
  219. */
  220. if (mcdi->mode == MCDI_MODE_POLL)
  221. return efx_mcdi_poll(efx);
  222. return 0;
  223. }
  224. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  225. {
  226. /* If the interface is RUNNING, then move to COMPLETED and wake any
  227. * waiters. If the interface isn't in RUNNING then we've received a
  228. * duplicate completion after we've already transitioned back to
  229. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  230. * have failed the seqno check].
  231. */
  232. if (atomic_cmpxchg(&mcdi->state,
  233. MCDI_STATE_RUNNING,
  234. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  235. wake_up(&mcdi->wq);
  236. return true;
  237. }
  238. return false;
  239. }
  240. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  241. {
  242. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  243. wake_up(&mcdi->wq);
  244. }
  245. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  246. unsigned int datalen, unsigned int errno)
  247. {
  248. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  249. bool wake = false;
  250. spin_lock(&mcdi->iface_lock);
  251. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  252. if (mcdi->credits)
  253. /* The request has been cancelled */
  254. --mcdi->credits;
  255. else
  256. netif_err(efx, hw, efx->net_dev,
  257. "MC response mismatch tx seq 0x%x rx "
  258. "seq 0x%x\n", seqno, mcdi->seqno);
  259. } else {
  260. mcdi->resprc = errno;
  261. mcdi->resplen = datalen;
  262. wake = true;
  263. }
  264. spin_unlock(&mcdi->iface_lock);
  265. if (wake)
  266. efx_mcdi_complete(mcdi);
  267. }
  268. /* Issue the given command by writing the data into the shared memory PDU,
  269. * ring the doorbell and wait for completion. Copyout the result. */
  270. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  271. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  272. size_t *outlen_actual)
  273. {
  274. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  275. int rc;
  276. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  277. efx_mcdi_acquire(mcdi);
  278. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  279. spin_lock_bh(&mcdi->iface_lock);
  280. ++mcdi->seqno;
  281. spin_unlock_bh(&mcdi->iface_lock);
  282. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  283. if (mcdi->mode == MCDI_MODE_POLL)
  284. rc = efx_mcdi_poll(efx);
  285. else
  286. rc = efx_mcdi_await_completion(efx);
  287. if (rc != 0) {
  288. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  289. * and completing a request we've just cancelled, by ensuring
  290. * that the seqno check therein fails.
  291. */
  292. spin_lock_bh(&mcdi->iface_lock);
  293. ++mcdi->seqno;
  294. ++mcdi->credits;
  295. spin_unlock_bh(&mcdi->iface_lock);
  296. netif_err(efx, hw, efx->net_dev,
  297. "MC command 0x%x inlen %d mode %d timed out\n",
  298. cmd, (int)inlen, mcdi->mode);
  299. } else {
  300. size_t resplen;
  301. /* At the very least we need a memory barrier here to ensure
  302. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  303. * a spurious efx_mcdi_ev_cpl() running concurrently by
  304. * acquiring the iface_lock. */
  305. spin_lock_bh(&mcdi->iface_lock);
  306. rc = -mcdi->resprc;
  307. resplen = mcdi->resplen;
  308. spin_unlock_bh(&mcdi->iface_lock);
  309. if (rc == 0) {
  310. efx_mcdi_copyout(efx, outbuf,
  311. min(outlen, mcdi->resplen + 3) & ~0x3);
  312. if (outlen_actual != NULL)
  313. *outlen_actual = resplen;
  314. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  315. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  316. else if (rc == -EIO || rc == -EINTR) {
  317. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  318. -rc);
  319. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  320. } else
  321. netif_err(efx, hw, efx->net_dev,
  322. "MC command 0x%x inlen %d failed rc=%d\n",
  323. cmd, (int)inlen, -rc);
  324. }
  325. efx_mcdi_release(mcdi);
  326. return rc;
  327. }
  328. void efx_mcdi_mode_poll(struct efx_nic *efx)
  329. {
  330. struct efx_mcdi_iface *mcdi;
  331. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  332. return;
  333. mcdi = efx_mcdi(efx);
  334. if (mcdi->mode == MCDI_MODE_POLL)
  335. return;
  336. /* We can switch from event completion to polled completion, because
  337. * mcdi requests are always completed in shared memory. We do this by
  338. * switching the mode to POLL'd then completing the request.
  339. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  340. *
  341. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  342. * which efx_mcdi_complete() provides for us.
  343. */
  344. mcdi->mode = MCDI_MODE_POLL;
  345. efx_mcdi_complete(mcdi);
  346. }
  347. void efx_mcdi_mode_event(struct efx_nic *efx)
  348. {
  349. struct efx_mcdi_iface *mcdi;
  350. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  351. return;
  352. mcdi = efx_mcdi(efx);
  353. if (mcdi->mode == MCDI_MODE_EVENTS)
  354. return;
  355. /* We can't switch from polled to event completion in the middle of a
  356. * request, because the completion method is specified in the request.
  357. * So acquire the interface to serialise the requestors. We don't need
  358. * to acquire the iface_lock to change the mode here, but we do need a
  359. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  360. * efx_mcdi_acquire() provides.
  361. */
  362. efx_mcdi_acquire(mcdi);
  363. mcdi->mode = MCDI_MODE_EVENTS;
  364. efx_mcdi_release(mcdi);
  365. }
  366. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  367. {
  368. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  369. /* If there is an outstanding MCDI request, it has been terminated
  370. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  371. * in polled mode, then do nothing because the MC reboot handler will
  372. * set the header correctly. However, if the mcdi interface is waiting
  373. * for a CMDDONE event it won't receive it [and since all MCDI events
  374. * are sent to the same queue, we can't be racing with
  375. * efx_mcdi_ev_cpl()]
  376. *
  377. * There's a race here with efx_mcdi_rpc(), because we might receive
  378. * a REBOOT event *before* the request has been copied out. In polled
  379. * mode (during startup) this is irrelevent, because efx_mcdi_complete()
  380. * is ignored. In event mode, this condition is just an edge-case of
  381. * receiving a REBOOT event after posting the MCDI request. Did the mc
  382. * reboot before or after the copyout? The best we can do always is
  383. * just return failure.
  384. */
  385. spin_lock(&mcdi->iface_lock);
  386. if (efx_mcdi_complete(mcdi)) {
  387. if (mcdi->mode == MCDI_MODE_EVENTS) {
  388. mcdi->resprc = rc;
  389. mcdi->resplen = 0;
  390. }
  391. } else
  392. /* Nobody was waiting for an MCDI request, so trigger a reset */
  393. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  394. spin_unlock(&mcdi->iface_lock);
  395. }
  396. static unsigned int efx_mcdi_event_link_speed[] = {
  397. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  398. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  399. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  400. };
  401. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  402. {
  403. u32 flags, fcntl, speed, lpa;
  404. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  405. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  406. speed = efx_mcdi_event_link_speed[speed];
  407. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  408. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  409. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  410. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  411. * which is only run after flushing the event queues. Therefore, it
  412. * is safe to modify the link state outside of the mac_lock here.
  413. */
  414. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  415. efx_mcdi_phy_check_fcntl(efx, lpa);
  416. efx_link_status_changed(efx);
  417. }
  418. static const char *sensor_names[] = {
  419. [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
  420. [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
  421. [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
  422. [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
  423. [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
  424. [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
  425. [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
  426. [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
  427. [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
  428. [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
  429. [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
  430. [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
  431. [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
  432. };
  433. static const char *sensor_status_names[] = {
  434. [MC_CMD_SENSOR_STATE_OK] = "OK",
  435. [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
  436. [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
  437. [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
  438. };
  439. static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
  440. {
  441. unsigned int monitor, state, value;
  442. const char *name, *state_txt;
  443. monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
  444. state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
  445. value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
  446. /* Deal gracefully with the board having more drivers than we
  447. * know about, but do not expect new sensor states. */
  448. name = (monitor >= ARRAY_SIZE(sensor_names))
  449. ? "No sensor name available" :
  450. sensor_names[monitor];
  451. EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
  452. state_txt = sensor_status_names[state];
  453. netif_err(efx, hw, efx->net_dev,
  454. "Sensor %d (%s) reports condition '%s' for raw value %d\n",
  455. monitor, name, state_txt, value);
  456. }
  457. /* Called from falcon_process_eventq for MCDI events */
  458. void efx_mcdi_process_event(struct efx_channel *channel,
  459. efx_qword_t *event)
  460. {
  461. struct efx_nic *efx = channel->efx;
  462. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  463. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  464. switch (code) {
  465. case MCDI_EVENT_CODE_BADSSERT:
  466. netif_err(efx, hw, efx->net_dev,
  467. "MC watchdog or assertion failure at 0x%x\n", data);
  468. efx_mcdi_ev_death(efx, EINTR);
  469. break;
  470. case MCDI_EVENT_CODE_PMNOTICE:
  471. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  472. break;
  473. case MCDI_EVENT_CODE_CMDDONE:
  474. efx_mcdi_ev_cpl(efx,
  475. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  476. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  477. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  478. break;
  479. case MCDI_EVENT_CODE_LINKCHANGE:
  480. efx_mcdi_process_link_change(efx, event);
  481. break;
  482. case MCDI_EVENT_CODE_SENSOREVT:
  483. efx_mcdi_sensor_event(efx, event);
  484. break;
  485. case MCDI_EVENT_CODE_SCHEDERR:
  486. netif_info(efx, hw, efx->net_dev,
  487. "MC Scheduler error address=0x%x\n", data);
  488. break;
  489. case MCDI_EVENT_CODE_REBOOT:
  490. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  491. efx_mcdi_ev_death(efx, EIO);
  492. break;
  493. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  494. /* MAC stats are gather lazily. We can ignore this. */
  495. break;
  496. default:
  497. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  498. code);
  499. }
  500. }
  501. /**************************************************************************
  502. *
  503. * Specific request functions
  504. *
  505. **************************************************************************
  506. */
  507. int efx_mcdi_fwver(struct efx_nic *efx, u64 *version, u32 *build)
  508. {
  509. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
  510. size_t outlength;
  511. const __le16 *ver_words;
  512. int rc;
  513. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  514. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  515. outbuf, sizeof(outbuf), &outlength);
  516. if (rc)
  517. goto fail;
  518. if (outlength == MC_CMD_GET_VERSION_V0_OUT_LEN) {
  519. *version = 0;
  520. *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
  521. return 0;
  522. }
  523. if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
  524. rc = -EIO;
  525. goto fail;
  526. }
  527. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  528. *version = (((u64)le16_to_cpu(ver_words[0]) << 48) |
  529. ((u64)le16_to_cpu(ver_words[1]) << 32) |
  530. ((u64)le16_to_cpu(ver_words[2]) << 16) |
  531. le16_to_cpu(ver_words[3]));
  532. *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
  533. return 0;
  534. fail:
  535. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  536. return rc;
  537. }
  538. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  539. bool *was_attached)
  540. {
  541. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  542. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  543. size_t outlen;
  544. int rc;
  545. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  546. driver_operating ? 1 : 0);
  547. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  548. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  549. outbuf, sizeof(outbuf), &outlen);
  550. if (rc)
  551. goto fail;
  552. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  553. rc = -EIO;
  554. goto fail;
  555. }
  556. if (was_attached != NULL)
  557. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  558. return 0;
  559. fail:
  560. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  561. return rc;
  562. }
  563. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  564. u16 *fw_subtype_list)
  565. {
  566. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
  567. size_t outlen;
  568. int port_num = efx_port_num(efx);
  569. int offset;
  570. int rc;
  571. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  572. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  573. outbuf, sizeof(outbuf), &outlen);
  574. if (rc)
  575. goto fail;
  576. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
  577. rc = -EIO;
  578. goto fail;
  579. }
  580. offset = (port_num)
  581. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  582. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  583. if (mac_address)
  584. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  585. if (fw_subtype_list)
  586. memcpy(fw_subtype_list,
  587. outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
  588. MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
  589. return 0;
  590. fail:
  591. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  592. __func__, rc, (int)outlen);
  593. return rc;
  594. }
  595. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  596. {
  597. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  598. u32 dest = 0;
  599. int rc;
  600. if (uart)
  601. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  602. if (evq)
  603. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  604. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  605. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  606. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  607. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  608. NULL, 0, NULL);
  609. if (rc)
  610. goto fail;
  611. return 0;
  612. fail:
  613. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  614. return rc;
  615. }
  616. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  617. {
  618. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  619. size_t outlen;
  620. int rc;
  621. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  622. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  623. outbuf, sizeof(outbuf), &outlen);
  624. if (rc)
  625. goto fail;
  626. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  627. rc = -EIO;
  628. goto fail;
  629. }
  630. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  631. return 0;
  632. fail:
  633. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  634. __func__, rc);
  635. return rc;
  636. }
  637. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  638. size_t *size_out, size_t *erase_size_out,
  639. bool *protected_out)
  640. {
  641. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  642. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  643. size_t outlen;
  644. int rc;
  645. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  646. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  647. outbuf, sizeof(outbuf), &outlen);
  648. if (rc)
  649. goto fail;
  650. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  651. rc = -EIO;
  652. goto fail;
  653. }
  654. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  655. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  656. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  657. (1 << MC_CMD_NVRAM_PROTECTED_LBN));
  658. return 0;
  659. fail:
  660. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  661. return rc;
  662. }
  663. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  664. {
  665. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  666. int rc;
  667. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  668. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  669. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  670. NULL, 0, NULL);
  671. if (rc)
  672. goto fail;
  673. return 0;
  674. fail:
  675. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  676. return rc;
  677. }
  678. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  679. loff_t offset, u8 *buffer, size_t length)
  680. {
  681. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  682. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  683. size_t outlen;
  684. int rc;
  685. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  686. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  687. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  688. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  689. outbuf, sizeof(outbuf), &outlen);
  690. if (rc)
  691. goto fail;
  692. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  693. return 0;
  694. fail:
  695. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  696. return rc;
  697. }
  698. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  699. loff_t offset, const u8 *buffer, size_t length)
  700. {
  701. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  702. int rc;
  703. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  704. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  705. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  706. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  707. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  708. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  709. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  710. NULL, 0, NULL);
  711. if (rc)
  712. goto fail;
  713. return 0;
  714. fail:
  715. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  716. return rc;
  717. }
  718. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  719. loff_t offset, size_t length)
  720. {
  721. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  722. int rc;
  723. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  724. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  725. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  726. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  727. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  728. NULL, 0, NULL);
  729. if (rc)
  730. goto fail;
  731. return 0;
  732. fail:
  733. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  734. return rc;
  735. }
  736. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  737. {
  738. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  739. int rc;
  740. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  741. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  742. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  743. NULL, 0, NULL);
  744. if (rc)
  745. goto fail;
  746. return 0;
  747. fail:
  748. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  749. return rc;
  750. }
  751. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  752. {
  753. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  754. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  755. int rc;
  756. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  757. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  758. outbuf, sizeof(outbuf), NULL);
  759. if (rc)
  760. return rc;
  761. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  762. case MC_CMD_NVRAM_TEST_PASS:
  763. case MC_CMD_NVRAM_TEST_NOTSUPP:
  764. return 0;
  765. default:
  766. return -EIO;
  767. }
  768. }
  769. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  770. {
  771. u32 nvram_types;
  772. unsigned int type;
  773. int rc;
  774. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  775. if (rc)
  776. goto fail1;
  777. type = 0;
  778. while (nvram_types != 0) {
  779. if (nvram_types & 1) {
  780. rc = efx_mcdi_nvram_test(efx, type);
  781. if (rc)
  782. goto fail2;
  783. }
  784. type++;
  785. nvram_types >>= 1;
  786. }
  787. return 0;
  788. fail2:
  789. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  790. __func__, type);
  791. fail1:
  792. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  793. return rc;
  794. }
  795. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  796. {
  797. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  798. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  799. unsigned int flags, index, ofst;
  800. const char *reason;
  801. size_t outlen;
  802. int retry;
  803. int rc;
  804. /* Attempt to read any stored assertion state before we reboot
  805. * the mcfw out of the assertion handler. Retry twice, once
  806. * because a boot-time assertion might cause this command to fail
  807. * with EINTR. And once again because GET_ASSERTS can race with
  808. * MC_CMD_REBOOT running on the other port. */
  809. retry = 2;
  810. do {
  811. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  812. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  813. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  814. outbuf, sizeof(outbuf), &outlen);
  815. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  816. if (rc)
  817. return rc;
  818. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  819. return -EIO;
  820. /* Print out any recorded assertion state */
  821. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  822. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  823. return 0;
  824. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  825. ? "system-level assertion"
  826. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  827. ? "thread-level assertion"
  828. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  829. ? "watchdog reset"
  830. : "unknown assertion";
  831. netif_err(efx, hw, efx->net_dev,
  832. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  833. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  834. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  835. /* Print out the registers */
  836. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  837. for (index = 1; index < 32; index++) {
  838. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  839. MCDI_DWORD2(outbuf, ofst));
  840. ofst += sizeof(efx_dword_t);
  841. }
  842. return 0;
  843. }
  844. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  845. {
  846. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  847. /* Atomically reboot the mcfw out of the assertion handler */
  848. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  849. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  850. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  851. efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  852. NULL, 0, NULL);
  853. }
  854. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  855. {
  856. int rc;
  857. rc = efx_mcdi_read_assertion(efx);
  858. if (rc)
  859. return rc;
  860. efx_mcdi_exit_assertion(efx);
  861. return 0;
  862. }
  863. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  864. {
  865. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  866. int rc;
  867. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  868. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  869. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  870. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  871. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  872. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  873. NULL, 0, NULL);
  874. if (rc)
  875. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  876. __func__, rc);
  877. }
  878. int efx_mcdi_reset_port(struct efx_nic *efx)
  879. {
  880. int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
  881. if (rc)
  882. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  883. __func__, rc);
  884. return rc;
  885. }
  886. int efx_mcdi_reset_mc(struct efx_nic *efx)
  887. {
  888. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  889. int rc;
  890. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  891. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  892. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  893. NULL, 0, NULL);
  894. /* White is black, and up is down */
  895. if (rc == -EIO)
  896. return 0;
  897. if (rc == 0)
  898. rc = -EIO;
  899. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  900. return rc;
  901. }
  902. int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  903. const u8 *mac, int *id_out)
  904. {
  905. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  906. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  907. size_t outlen;
  908. int rc;
  909. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  910. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  911. MC_CMD_FILTER_MODE_SIMPLE);
  912. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  913. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  914. outbuf, sizeof(outbuf), &outlen);
  915. if (rc)
  916. goto fail;
  917. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  918. rc = -EIO;
  919. goto fail;
  920. }
  921. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  922. return 0;
  923. fail:
  924. *id_out = -1;
  925. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  926. return rc;
  927. }
  928. int
  929. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  930. {
  931. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  932. }
  933. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  934. {
  935. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  936. size_t outlen;
  937. int rc;
  938. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  939. outbuf, sizeof(outbuf), &outlen);
  940. if (rc)
  941. goto fail;
  942. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  943. rc = -EIO;
  944. goto fail;
  945. }
  946. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  947. return 0;
  948. fail:
  949. *id_out = -1;
  950. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  951. return rc;
  952. }
  953. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  954. {
  955. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  956. int rc;
  957. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  958. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  959. NULL, 0, NULL);
  960. if (rc)
  961. goto fail;
  962. return 0;
  963. fail:
  964. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  965. return rc;
  966. }
  967. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  968. {
  969. int rc;
  970. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  971. if (rc)
  972. goto fail;
  973. return 0;
  974. fail:
  975. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  976. return rc;
  977. }