cnic.c 121 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723
  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x_reg.h"
  40. #include "bnx2x_fw_defs.h"
  41. #include "bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static void cnic_shutdown_rings(struct cnic_dev *);
  72. static void cnic_init_rings(struct cnic_dev *);
  73. static int cnic_cm_set_pg(struct cnic_sock *);
  74. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  75. {
  76. struct cnic_dev *dev = uinfo->priv;
  77. struct cnic_local *cp = dev->cnic_priv;
  78. if (!capable(CAP_NET_ADMIN))
  79. return -EPERM;
  80. if (cp->uio_dev != -1)
  81. return -EBUSY;
  82. rtnl_lock();
  83. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  84. rtnl_unlock();
  85. return -ENODEV;
  86. }
  87. cp->uio_dev = iminor(inode);
  88. cnic_init_rings(dev);
  89. rtnl_unlock();
  90. return 0;
  91. }
  92. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  93. {
  94. struct cnic_dev *dev = uinfo->priv;
  95. struct cnic_local *cp = dev->cnic_priv;
  96. cnic_shutdown_rings(dev);
  97. cp->uio_dev = -1;
  98. return 0;
  99. }
  100. static inline void cnic_hold(struct cnic_dev *dev)
  101. {
  102. atomic_inc(&dev->ref_count);
  103. }
  104. static inline void cnic_put(struct cnic_dev *dev)
  105. {
  106. atomic_dec(&dev->ref_count);
  107. }
  108. static inline void csk_hold(struct cnic_sock *csk)
  109. {
  110. atomic_inc(&csk->ref_count);
  111. }
  112. static inline void csk_put(struct cnic_sock *csk)
  113. {
  114. atomic_dec(&csk->ref_count);
  115. }
  116. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  117. {
  118. struct cnic_dev *cdev;
  119. read_lock(&cnic_dev_lock);
  120. list_for_each_entry(cdev, &cnic_dev_list, list) {
  121. if (netdev == cdev->netdev) {
  122. cnic_hold(cdev);
  123. read_unlock(&cnic_dev_lock);
  124. return cdev;
  125. }
  126. }
  127. read_unlock(&cnic_dev_lock);
  128. return NULL;
  129. }
  130. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  131. {
  132. atomic_inc(&ulp_ops->ref_count);
  133. }
  134. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  135. {
  136. atomic_dec(&ulp_ops->ref_count);
  137. }
  138. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  139. {
  140. struct cnic_local *cp = dev->cnic_priv;
  141. struct cnic_eth_dev *ethdev = cp->ethdev;
  142. struct drv_ctl_info info;
  143. struct drv_ctl_io *io = &info.data.io;
  144. info.cmd = DRV_CTL_CTX_WR_CMD;
  145. io->cid_addr = cid_addr;
  146. io->offset = off;
  147. io->data = val;
  148. ethdev->drv_ctl(dev->netdev, &info);
  149. }
  150. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  157. io->offset = off;
  158. io->dma_addr = addr;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_l2_ring *ring = &info.data.ring;
  167. if (start)
  168. info.cmd = DRV_CTL_START_L2_CMD;
  169. else
  170. info.cmd = DRV_CTL_STOP_L2_CMD;
  171. ring->cid = cid;
  172. ring->client_id = cl_id;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_io *io = &info.data.io;
  181. info.cmd = DRV_CTL_IO_WR_CMD;
  182. io->offset = off;
  183. io->data = val;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_RD_CMD;
  193. io->offset = off;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. return io->data;
  196. }
  197. static int cnic_in_use(struct cnic_sock *csk)
  198. {
  199. return test_bit(SK_F_INUSE, &csk->flags);
  200. }
  201. static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
  202. {
  203. struct cnic_local *cp = dev->cnic_priv;
  204. struct cnic_eth_dev *ethdev = cp->ethdev;
  205. struct drv_ctl_info info;
  206. info.cmd = DRV_CTL_COMPLETION_CMD;
  207. info.data.comp.comp_count = count;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. }
  210. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  211. {
  212. u32 i;
  213. for (i = 0; i < cp->max_cid_space; i++) {
  214. if (cp->ctx_tbl[i].cid == cid) {
  215. *l5_cid = i;
  216. return 0;
  217. }
  218. }
  219. return -EINVAL;
  220. }
  221. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  222. struct cnic_sock *csk)
  223. {
  224. struct iscsi_path path_req;
  225. char *buf = NULL;
  226. u16 len = 0;
  227. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  228. struct cnic_ulp_ops *ulp_ops;
  229. if (cp->uio_dev == -1)
  230. return -ENODEV;
  231. if (csk) {
  232. len = sizeof(path_req);
  233. buf = (char *) &path_req;
  234. memset(&path_req, 0, len);
  235. msg_type = ISCSI_KEVENT_PATH_REQ;
  236. path_req.handle = (u64) csk->l5_cid;
  237. if (test_bit(SK_F_IPV6, &csk->flags)) {
  238. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  239. sizeof(struct in6_addr));
  240. path_req.ip_addr_len = 16;
  241. } else {
  242. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  243. sizeof(struct in_addr));
  244. path_req.ip_addr_len = 4;
  245. }
  246. path_req.vlan_id = csk->vlan_id;
  247. path_req.pmtu = csk->mtu;
  248. }
  249. rcu_read_lock();
  250. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  251. if (ulp_ops)
  252. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  253. rcu_read_unlock();
  254. return 0;
  255. }
  256. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  257. char *buf, u16 len)
  258. {
  259. int rc = -EINVAL;
  260. switch (msg_type) {
  261. case ISCSI_UEVENT_PATH_UPDATE: {
  262. struct cnic_local *cp;
  263. u32 l5_cid;
  264. struct cnic_sock *csk;
  265. struct iscsi_path *path_resp;
  266. if (len < sizeof(*path_resp))
  267. break;
  268. path_resp = (struct iscsi_path *) buf;
  269. cp = dev->cnic_priv;
  270. l5_cid = (u32) path_resp->handle;
  271. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  272. break;
  273. rcu_read_lock();
  274. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  275. rc = -ENODEV;
  276. rcu_read_unlock();
  277. break;
  278. }
  279. csk = &cp->csk_tbl[l5_cid];
  280. csk_hold(csk);
  281. if (cnic_in_use(csk)) {
  282. memcpy(csk->ha, path_resp->mac_addr, 6);
  283. if (test_bit(SK_F_IPV6, &csk->flags))
  284. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  285. sizeof(struct in6_addr));
  286. else
  287. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  288. sizeof(struct in_addr));
  289. if (is_valid_ether_addr(csk->ha))
  290. cnic_cm_set_pg(csk);
  291. }
  292. csk_put(csk);
  293. rcu_read_unlock();
  294. rc = 0;
  295. }
  296. }
  297. return rc;
  298. }
  299. static int cnic_offld_prep(struct cnic_sock *csk)
  300. {
  301. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  302. return 0;
  303. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  304. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  305. return 0;
  306. }
  307. return 1;
  308. }
  309. static int cnic_close_prep(struct cnic_sock *csk)
  310. {
  311. clear_bit(SK_F_CONNECT_START, &csk->flags);
  312. smp_mb__after_clear_bit();
  313. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  314. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  315. msleep(1);
  316. return 1;
  317. }
  318. return 0;
  319. }
  320. static int cnic_abort_prep(struct cnic_sock *csk)
  321. {
  322. clear_bit(SK_F_CONNECT_START, &csk->flags);
  323. smp_mb__after_clear_bit();
  324. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  325. msleep(1);
  326. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  327. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  328. return 1;
  329. }
  330. return 0;
  331. }
  332. static void cnic_uio_stop(void)
  333. {
  334. struct cnic_dev *dev;
  335. read_lock(&cnic_dev_lock);
  336. list_for_each_entry(dev, &cnic_dev_list, list) {
  337. struct cnic_local *cp = dev->cnic_priv;
  338. if (cp->cnic_uinfo)
  339. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  340. }
  341. read_unlock(&cnic_dev_lock);
  342. }
  343. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  344. {
  345. struct cnic_dev *dev;
  346. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  347. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  348. return -EINVAL;
  349. }
  350. mutex_lock(&cnic_lock);
  351. if (cnic_ulp_tbl[ulp_type]) {
  352. pr_err("%s: Type %d has already been registered\n",
  353. __func__, ulp_type);
  354. mutex_unlock(&cnic_lock);
  355. return -EBUSY;
  356. }
  357. read_lock(&cnic_dev_lock);
  358. list_for_each_entry(dev, &cnic_dev_list, list) {
  359. struct cnic_local *cp = dev->cnic_priv;
  360. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  361. }
  362. read_unlock(&cnic_dev_lock);
  363. atomic_set(&ulp_ops->ref_count, 0);
  364. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  365. mutex_unlock(&cnic_lock);
  366. /* Prevent race conditions with netdev_event */
  367. rtnl_lock();
  368. read_lock(&cnic_dev_lock);
  369. list_for_each_entry(dev, &cnic_dev_list, list) {
  370. struct cnic_local *cp = dev->cnic_priv;
  371. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  372. ulp_ops->cnic_init(dev);
  373. }
  374. read_unlock(&cnic_dev_lock);
  375. rtnl_unlock();
  376. return 0;
  377. }
  378. int cnic_unregister_driver(int ulp_type)
  379. {
  380. struct cnic_dev *dev;
  381. struct cnic_ulp_ops *ulp_ops;
  382. int i = 0;
  383. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  384. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  385. return -EINVAL;
  386. }
  387. mutex_lock(&cnic_lock);
  388. ulp_ops = cnic_ulp_tbl[ulp_type];
  389. if (!ulp_ops) {
  390. pr_err("%s: Type %d has not been registered\n",
  391. __func__, ulp_type);
  392. goto out_unlock;
  393. }
  394. read_lock(&cnic_dev_lock);
  395. list_for_each_entry(dev, &cnic_dev_list, list) {
  396. struct cnic_local *cp = dev->cnic_priv;
  397. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  398. pr_err("%s: Type %d still has devices registered\n",
  399. __func__, ulp_type);
  400. read_unlock(&cnic_dev_lock);
  401. goto out_unlock;
  402. }
  403. }
  404. read_unlock(&cnic_dev_lock);
  405. if (ulp_type == CNIC_ULP_ISCSI)
  406. cnic_uio_stop();
  407. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  408. mutex_unlock(&cnic_lock);
  409. synchronize_rcu();
  410. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  411. msleep(100);
  412. i++;
  413. }
  414. if (atomic_read(&ulp_ops->ref_count) != 0)
  415. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  416. return 0;
  417. out_unlock:
  418. mutex_unlock(&cnic_lock);
  419. return -EINVAL;
  420. }
  421. static int cnic_start_hw(struct cnic_dev *);
  422. static void cnic_stop_hw(struct cnic_dev *);
  423. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  424. void *ulp_ctx)
  425. {
  426. struct cnic_local *cp = dev->cnic_priv;
  427. struct cnic_ulp_ops *ulp_ops;
  428. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  429. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  430. return -EINVAL;
  431. }
  432. mutex_lock(&cnic_lock);
  433. if (cnic_ulp_tbl[ulp_type] == NULL) {
  434. pr_err("%s: Driver with type %d has not been registered\n",
  435. __func__, ulp_type);
  436. mutex_unlock(&cnic_lock);
  437. return -EAGAIN;
  438. }
  439. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  440. pr_err("%s: Type %d has already been registered to this device\n",
  441. __func__, ulp_type);
  442. mutex_unlock(&cnic_lock);
  443. return -EBUSY;
  444. }
  445. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  446. cp->ulp_handle[ulp_type] = ulp_ctx;
  447. ulp_ops = cnic_ulp_tbl[ulp_type];
  448. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  449. cnic_hold(dev);
  450. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  451. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  452. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  453. mutex_unlock(&cnic_lock);
  454. return 0;
  455. }
  456. EXPORT_SYMBOL(cnic_register_driver);
  457. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  458. {
  459. struct cnic_local *cp = dev->cnic_priv;
  460. int i = 0;
  461. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  462. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  463. return -EINVAL;
  464. }
  465. mutex_lock(&cnic_lock);
  466. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  467. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  468. cnic_put(dev);
  469. } else {
  470. pr_err("%s: device not registered to this ulp type %d\n",
  471. __func__, ulp_type);
  472. mutex_unlock(&cnic_lock);
  473. return -EINVAL;
  474. }
  475. mutex_unlock(&cnic_lock);
  476. synchronize_rcu();
  477. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  478. i < 20) {
  479. msleep(100);
  480. i++;
  481. }
  482. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  483. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  484. return 0;
  485. }
  486. EXPORT_SYMBOL(cnic_unregister_driver);
  487. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  488. {
  489. id_tbl->start = start_id;
  490. id_tbl->max = size;
  491. id_tbl->next = 0;
  492. spin_lock_init(&id_tbl->lock);
  493. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  494. if (!id_tbl->table)
  495. return -ENOMEM;
  496. return 0;
  497. }
  498. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  499. {
  500. kfree(id_tbl->table);
  501. id_tbl->table = NULL;
  502. }
  503. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  504. {
  505. int ret = -1;
  506. id -= id_tbl->start;
  507. if (id >= id_tbl->max)
  508. return ret;
  509. spin_lock(&id_tbl->lock);
  510. if (!test_bit(id, id_tbl->table)) {
  511. set_bit(id, id_tbl->table);
  512. ret = 0;
  513. }
  514. spin_unlock(&id_tbl->lock);
  515. return ret;
  516. }
  517. /* Returns -1 if not successful */
  518. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  519. {
  520. u32 id;
  521. spin_lock(&id_tbl->lock);
  522. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  523. if (id >= id_tbl->max) {
  524. id = -1;
  525. if (id_tbl->next != 0) {
  526. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  527. if (id >= id_tbl->next)
  528. id = -1;
  529. }
  530. }
  531. if (id < id_tbl->max) {
  532. set_bit(id, id_tbl->table);
  533. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  534. id += id_tbl->start;
  535. }
  536. spin_unlock(&id_tbl->lock);
  537. return id;
  538. }
  539. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  540. {
  541. if (id == -1)
  542. return;
  543. id -= id_tbl->start;
  544. if (id >= id_tbl->max)
  545. return;
  546. clear_bit(id, id_tbl->table);
  547. }
  548. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  549. {
  550. int i;
  551. if (!dma->pg_arr)
  552. return;
  553. for (i = 0; i < dma->num_pages; i++) {
  554. if (dma->pg_arr[i]) {
  555. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  556. dma->pg_arr[i], dma->pg_map_arr[i]);
  557. dma->pg_arr[i] = NULL;
  558. }
  559. }
  560. if (dma->pgtbl) {
  561. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  562. dma->pgtbl, dma->pgtbl_map);
  563. dma->pgtbl = NULL;
  564. }
  565. kfree(dma->pg_arr);
  566. dma->pg_arr = NULL;
  567. dma->num_pages = 0;
  568. }
  569. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  570. {
  571. int i;
  572. u32 *page_table = dma->pgtbl;
  573. for (i = 0; i < dma->num_pages; i++) {
  574. /* Each entry needs to be in big endian format. */
  575. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  576. page_table++;
  577. *page_table = (u32) dma->pg_map_arr[i];
  578. page_table++;
  579. }
  580. }
  581. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  582. {
  583. int i;
  584. u32 *page_table = dma->pgtbl;
  585. for (i = 0; i < dma->num_pages; i++) {
  586. /* Each entry needs to be in little endian format. */
  587. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  588. page_table++;
  589. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  590. page_table++;
  591. }
  592. }
  593. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  594. int pages, int use_pg_tbl)
  595. {
  596. int i, size;
  597. struct cnic_local *cp = dev->cnic_priv;
  598. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  599. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  600. if (dma->pg_arr == NULL)
  601. return -ENOMEM;
  602. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  603. dma->num_pages = pages;
  604. for (i = 0; i < pages; i++) {
  605. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  606. BCM_PAGE_SIZE,
  607. &dma->pg_map_arr[i],
  608. GFP_ATOMIC);
  609. if (dma->pg_arr[i] == NULL)
  610. goto error;
  611. }
  612. if (!use_pg_tbl)
  613. return 0;
  614. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  615. ~(BCM_PAGE_SIZE - 1);
  616. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  617. &dma->pgtbl_map, GFP_ATOMIC);
  618. if (dma->pgtbl == NULL)
  619. goto error;
  620. cp->setup_pgtbl(dev, dma);
  621. return 0;
  622. error:
  623. cnic_free_dma(dev, dma);
  624. return -ENOMEM;
  625. }
  626. static void cnic_free_context(struct cnic_dev *dev)
  627. {
  628. struct cnic_local *cp = dev->cnic_priv;
  629. int i;
  630. for (i = 0; i < cp->ctx_blks; i++) {
  631. if (cp->ctx_arr[i].ctx) {
  632. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  633. cp->ctx_arr[i].ctx,
  634. cp->ctx_arr[i].mapping);
  635. cp->ctx_arr[i].ctx = NULL;
  636. }
  637. }
  638. }
  639. static void cnic_free_resc(struct cnic_dev *dev)
  640. {
  641. struct cnic_local *cp = dev->cnic_priv;
  642. int i = 0;
  643. if (cp->cnic_uinfo) {
  644. while (cp->uio_dev != -1 && i < 15) {
  645. msleep(100);
  646. i++;
  647. }
  648. uio_unregister_device(cp->cnic_uinfo);
  649. kfree(cp->cnic_uinfo);
  650. cp->cnic_uinfo = NULL;
  651. }
  652. if (cp->l2_buf) {
  653. dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  654. cp->l2_buf, cp->l2_buf_map);
  655. cp->l2_buf = NULL;
  656. }
  657. if (cp->l2_ring) {
  658. dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  659. cp->l2_ring, cp->l2_ring_map);
  660. cp->l2_ring = NULL;
  661. }
  662. cnic_free_context(dev);
  663. kfree(cp->ctx_arr);
  664. cp->ctx_arr = NULL;
  665. cp->ctx_blks = 0;
  666. cnic_free_dma(dev, &cp->gbl_buf_info);
  667. cnic_free_dma(dev, &cp->conn_buf_info);
  668. cnic_free_dma(dev, &cp->kwq_info);
  669. cnic_free_dma(dev, &cp->kwq_16_data_info);
  670. cnic_free_dma(dev, &cp->kcq1.dma);
  671. kfree(cp->iscsi_tbl);
  672. cp->iscsi_tbl = NULL;
  673. kfree(cp->ctx_tbl);
  674. cp->ctx_tbl = NULL;
  675. cnic_free_id_tbl(&cp->cid_tbl);
  676. }
  677. static int cnic_alloc_context(struct cnic_dev *dev)
  678. {
  679. struct cnic_local *cp = dev->cnic_priv;
  680. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  681. int i, k, arr_size;
  682. cp->ctx_blk_size = BCM_PAGE_SIZE;
  683. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  684. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  685. sizeof(struct cnic_ctx);
  686. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  687. if (cp->ctx_arr == NULL)
  688. return -ENOMEM;
  689. k = 0;
  690. for (i = 0; i < 2; i++) {
  691. u32 j, reg, off, lo, hi;
  692. if (i == 0)
  693. off = BNX2_PG_CTX_MAP;
  694. else
  695. off = BNX2_ISCSI_CTX_MAP;
  696. reg = cnic_reg_rd_ind(dev, off);
  697. lo = reg >> 16;
  698. hi = reg & 0xffff;
  699. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  700. cp->ctx_arr[k].cid = j;
  701. }
  702. cp->ctx_blks = k;
  703. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  704. cp->ctx_blks = 0;
  705. return -ENOMEM;
  706. }
  707. for (i = 0; i < cp->ctx_blks; i++) {
  708. cp->ctx_arr[i].ctx =
  709. dma_alloc_coherent(&dev->pcidev->dev,
  710. BCM_PAGE_SIZE,
  711. &cp->ctx_arr[i].mapping,
  712. GFP_KERNEL);
  713. if (cp->ctx_arr[i].ctx == NULL)
  714. return -ENOMEM;
  715. }
  716. }
  717. return 0;
  718. }
  719. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  720. {
  721. int err, i, is_bnx2 = 0;
  722. struct kcqe **kcq;
  723. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  724. is_bnx2 = 1;
  725. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  726. if (err)
  727. return err;
  728. kcq = (struct kcqe **) info->dma.pg_arr;
  729. info->kcq = kcq;
  730. if (is_bnx2)
  731. return 0;
  732. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  733. struct bnx2x_bd_chain_next *next =
  734. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  735. int j = i + 1;
  736. if (j >= KCQ_PAGE_CNT)
  737. j = 0;
  738. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  739. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  740. }
  741. return 0;
  742. }
  743. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  744. {
  745. struct cnic_local *cp = dev->cnic_priv;
  746. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  747. cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  748. &cp->l2_ring_map,
  749. GFP_KERNEL | __GFP_COMP);
  750. if (!cp->l2_ring)
  751. return -ENOMEM;
  752. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  753. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  754. cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  755. &cp->l2_buf_map,
  756. GFP_KERNEL | __GFP_COMP);
  757. if (!cp->l2_buf)
  758. return -ENOMEM;
  759. return 0;
  760. }
  761. static int cnic_alloc_uio(struct cnic_dev *dev) {
  762. struct cnic_local *cp = dev->cnic_priv;
  763. struct uio_info *uinfo;
  764. int ret;
  765. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  766. if (!uinfo)
  767. return -ENOMEM;
  768. uinfo->mem[0].addr = dev->netdev->base_addr;
  769. uinfo->mem[0].internal_addr = dev->regview;
  770. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  771. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  772. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  773. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  774. PAGE_MASK;
  775. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  776. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  777. else
  778. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  779. uinfo->name = "bnx2_cnic";
  780. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  781. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  782. PAGE_MASK;
  783. uinfo->mem[1].size = sizeof(struct host_def_status_block);
  784. uinfo->name = "bnx2x_cnic";
  785. }
  786. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  787. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  788. uinfo->mem[2].size = cp->l2_ring_size;
  789. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  790. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  791. uinfo->mem[3].size = cp->l2_buf_size;
  792. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  793. uinfo->version = CNIC_MODULE_VERSION;
  794. uinfo->irq = UIO_IRQ_CUSTOM;
  795. uinfo->open = cnic_uio_open;
  796. uinfo->release = cnic_uio_close;
  797. uinfo->priv = dev;
  798. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  799. if (ret) {
  800. kfree(uinfo);
  801. return ret;
  802. }
  803. cp->cnic_uinfo = uinfo;
  804. return 0;
  805. }
  806. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  807. {
  808. struct cnic_local *cp = dev->cnic_priv;
  809. int ret;
  810. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  811. if (ret)
  812. goto error;
  813. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  814. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  815. if (ret)
  816. goto error;
  817. ret = cnic_alloc_context(dev);
  818. if (ret)
  819. goto error;
  820. ret = cnic_alloc_l2_rings(dev, 2);
  821. if (ret)
  822. goto error;
  823. ret = cnic_alloc_uio(dev);
  824. if (ret)
  825. goto error;
  826. return 0;
  827. error:
  828. cnic_free_resc(dev);
  829. return ret;
  830. }
  831. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  832. {
  833. struct cnic_local *cp = dev->cnic_priv;
  834. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  835. int total_mem, blks, i;
  836. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  837. blks = total_mem / ctx_blk_size;
  838. if (total_mem % ctx_blk_size)
  839. blks++;
  840. if (blks > cp->ethdev->ctx_tbl_len)
  841. return -ENOMEM;
  842. cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
  843. if (cp->ctx_arr == NULL)
  844. return -ENOMEM;
  845. cp->ctx_blks = blks;
  846. cp->ctx_blk_size = ctx_blk_size;
  847. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  848. cp->ctx_align = 0;
  849. else
  850. cp->ctx_align = ctx_blk_size;
  851. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  852. for (i = 0; i < blks; i++) {
  853. cp->ctx_arr[i].ctx =
  854. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  855. &cp->ctx_arr[i].mapping,
  856. GFP_KERNEL);
  857. if (cp->ctx_arr[i].ctx == NULL)
  858. return -ENOMEM;
  859. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  860. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  861. cnic_free_context(dev);
  862. cp->ctx_blk_size += cp->ctx_align;
  863. i = -1;
  864. continue;
  865. }
  866. }
  867. }
  868. return 0;
  869. }
  870. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  871. {
  872. struct cnic_local *cp = dev->cnic_priv;
  873. struct cnic_eth_dev *ethdev = cp->ethdev;
  874. u32 start_cid = ethdev->starting_cid;
  875. int i, j, n, ret, pages;
  876. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  877. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  878. cp->iscsi_start_cid = start_cid;
  879. if (start_cid < BNX2X_ISCSI_START_CID) {
  880. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  881. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  882. cp->max_cid_space += delta;
  883. }
  884. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  885. GFP_KERNEL);
  886. if (!cp->iscsi_tbl)
  887. goto error;
  888. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  889. cp->max_cid_space, GFP_KERNEL);
  890. if (!cp->ctx_tbl)
  891. goto error;
  892. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  893. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  894. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  895. }
  896. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  897. PAGE_SIZE;
  898. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  899. if (ret)
  900. return -ENOMEM;
  901. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  902. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  903. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  904. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  905. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  906. off;
  907. if ((i % n) == (n - 1))
  908. j++;
  909. }
  910. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  911. if (ret)
  912. goto error;
  913. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  914. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  915. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  916. if (ret)
  917. goto error;
  918. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  919. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  920. if (ret)
  921. goto error;
  922. ret = cnic_alloc_bnx2x_context(dev);
  923. if (ret)
  924. goto error;
  925. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  926. memset(cp->status_blk.bnx2x, 0, sizeof(*cp->status_blk.bnx2x));
  927. cp->l2_rx_ring_size = 15;
  928. ret = cnic_alloc_l2_rings(dev, 4);
  929. if (ret)
  930. goto error;
  931. ret = cnic_alloc_uio(dev);
  932. if (ret)
  933. goto error;
  934. return 0;
  935. error:
  936. cnic_free_resc(dev);
  937. return -ENOMEM;
  938. }
  939. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  940. {
  941. return cp->max_kwq_idx -
  942. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  943. }
  944. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  945. u32 num_wqes)
  946. {
  947. struct cnic_local *cp = dev->cnic_priv;
  948. struct kwqe *prod_qe;
  949. u16 prod, sw_prod, i;
  950. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  951. return -EAGAIN; /* bnx2 is down */
  952. spin_lock_bh(&cp->cnic_ulp_lock);
  953. if (num_wqes > cnic_kwq_avail(cp) &&
  954. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  955. spin_unlock_bh(&cp->cnic_ulp_lock);
  956. return -EAGAIN;
  957. }
  958. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  959. prod = cp->kwq_prod_idx;
  960. sw_prod = prod & MAX_KWQ_IDX;
  961. for (i = 0; i < num_wqes; i++) {
  962. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  963. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  964. prod++;
  965. sw_prod = prod & MAX_KWQ_IDX;
  966. }
  967. cp->kwq_prod_idx = prod;
  968. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  969. spin_unlock_bh(&cp->cnic_ulp_lock);
  970. return 0;
  971. }
  972. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  973. union l5cm_specific_data *l5_data)
  974. {
  975. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  976. dma_addr_t map;
  977. map = ctx->kwqe_data_mapping;
  978. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  979. l5_data->phy_address.hi = (u64) map >> 32;
  980. return ctx->kwqe_data;
  981. }
  982. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  983. u32 type, union l5cm_specific_data *l5_data)
  984. {
  985. struct cnic_local *cp = dev->cnic_priv;
  986. struct l5cm_spe kwqe;
  987. struct kwqe_16 *kwq[1];
  988. int ret;
  989. kwqe.hdr.conn_and_cmd_data =
  990. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  991. BNX2X_HW_CID(cid, cp->func)));
  992. kwqe.hdr.type = cpu_to_le16(type);
  993. kwqe.hdr.reserved = 0;
  994. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  995. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  996. kwq[0] = (struct kwqe_16 *) &kwqe;
  997. spin_lock_bh(&cp->cnic_ulp_lock);
  998. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  999. spin_unlock_bh(&cp->cnic_ulp_lock);
  1000. if (ret == 1)
  1001. return 0;
  1002. return -EBUSY;
  1003. }
  1004. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1005. struct kcqe *cqes[], u32 num_cqes)
  1006. {
  1007. struct cnic_local *cp = dev->cnic_priv;
  1008. struct cnic_ulp_ops *ulp_ops;
  1009. rcu_read_lock();
  1010. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1011. if (likely(ulp_ops)) {
  1012. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1013. cqes, num_cqes);
  1014. }
  1015. rcu_read_unlock();
  1016. }
  1017. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1018. {
  1019. struct cnic_local *cp = dev->cnic_priv;
  1020. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1021. int func = cp->func, pages;
  1022. int hq_bds;
  1023. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1024. cp->num_ccells = req1->num_ccells_per_conn;
  1025. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1026. cp->num_iscsi_tasks;
  1027. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1028. BNX2X_ISCSI_R2TQE_SIZE;
  1029. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1030. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1031. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1032. cp->num_cqs = req1->num_cqs;
  1033. if (!dev->max_iscsi_conn)
  1034. return 0;
  1035. /* init Tstorm RAM */
  1036. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1037. req1->rq_num_wqes);
  1038. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1039. PAGE_SIZE);
  1040. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1041. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1042. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1043. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1044. req1->num_tasks_per_conn);
  1045. /* init Ustorm RAM */
  1046. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1047. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
  1048. req1->rq_buffer_size);
  1049. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1050. PAGE_SIZE);
  1051. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1052. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1053. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1054. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1055. req1->num_tasks_per_conn);
  1056. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1057. req1->rq_num_wqes);
  1058. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1059. req1->cq_num_wqes);
  1060. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1061. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1062. /* init Xstorm RAM */
  1063. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1064. PAGE_SIZE);
  1065. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1066. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1067. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1068. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1069. req1->num_tasks_per_conn);
  1070. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1071. hq_bds);
  1072. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
  1073. req1->num_tasks_per_conn);
  1074. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1075. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1076. /* init Cstorm RAM */
  1077. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1078. PAGE_SIZE);
  1079. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1080. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1081. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1082. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1083. req1->num_tasks_per_conn);
  1084. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1085. req1->cq_num_wqes);
  1086. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1087. hq_bds);
  1088. return 0;
  1089. }
  1090. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1091. {
  1092. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1093. struct cnic_local *cp = dev->cnic_priv;
  1094. int func = cp->func;
  1095. struct iscsi_kcqe kcqe;
  1096. struct kcqe *cqes[1];
  1097. memset(&kcqe, 0, sizeof(kcqe));
  1098. if (!dev->max_iscsi_conn) {
  1099. kcqe.completion_status =
  1100. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1101. goto done;
  1102. }
  1103. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1104. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1105. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1106. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1107. req2->error_bit_map[1]);
  1108. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1109. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1110. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1111. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1112. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1113. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1114. req2->error_bit_map[1]);
  1115. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1116. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1117. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1118. done:
  1119. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1120. cqes[0] = (struct kcqe *) &kcqe;
  1121. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1122. return 0;
  1123. }
  1124. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1125. {
  1126. struct cnic_local *cp = dev->cnic_priv;
  1127. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1128. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1129. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1130. cnic_free_dma(dev, &iscsi->hq_info);
  1131. cnic_free_dma(dev, &iscsi->r2tq_info);
  1132. cnic_free_dma(dev, &iscsi->task_array_info);
  1133. }
  1134. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1135. ctx->cid = 0;
  1136. }
  1137. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1138. {
  1139. u32 cid;
  1140. int ret, pages;
  1141. struct cnic_local *cp = dev->cnic_priv;
  1142. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1143. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1144. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1145. if (cid == -1) {
  1146. ret = -ENOMEM;
  1147. goto error;
  1148. }
  1149. ctx->cid = cid;
  1150. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1151. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1152. if (ret)
  1153. goto error;
  1154. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1155. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1156. if (ret)
  1157. goto error;
  1158. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1159. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1160. if (ret)
  1161. goto error;
  1162. return 0;
  1163. error:
  1164. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1165. return ret;
  1166. }
  1167. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1168. struct regpair *ctx_addr)
  1169. {
  1170. struct cnic_local *cp = dev->cnic_priv;
  1171. struct cnic_eth_dev *ethdev = cp->ethdev;
  1172. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1173. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1174. unsigned long align_off = 0;
  1175. dma_addr_t ctx_map;
  1176. void *ctx;
  1177. if (cp->ctx_align) {
  1178. unsigned long mask = cp->ctx_align - 1;
  1179. if (cp->ctx_arr[blk].mapping & mask)
  1180. align_off = cp->ctx_align -
  1181. (cp->ctx_arr[blk].mapping & mask);
  1182. }
  1183. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1184. (off * BNX2X_CONTEXT_MEM_SIZE);
  1185. ctx = cp->ctx_arr[blk].ctx + align_off +
  1186. (off * BNX2X_CONTEXT_MEM_SIZE);
  1187. if (init)
  1188. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1189. ctx_addr->lo = ctx_map & 0xffffffff;
  1190. ctx_addr->hi = (u64) ctx_map >> 32;
  1191. return ctx;
  1192. }
  1193. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1194. u32 num)
  1195. {
  1196. struct cnic_local *cp = dev->cnic_priv;
  1197. struct iscsi_kwqe_conn_offload1 *req1 =
  1198. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1199. struct iscsi_kwqe_conn_offload2 *req2 =
  1200. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1201. struct iscsi_kwqe_conn_offload3 *req3;
  1202. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1203. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1204. u32 cid = ctx->cid;
  1205. u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
  1206. struct iscsi_context *ictx;
  1207. struct regpair context_addr;
  1208. int i, j, n = 2, n_max;
  1209. ctx->ctx_flags = 0;
  1210. if (!req2->num_additional_wqes)
  1211. return -EINVAL;
  1212. n_max = req2->num_additional_wqes + 2;
  1213. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1214. if (ictx == NULL)
  1215. return -ENOMEM;
  1216. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1217. ictx->xstorm_ag_context.hq_prod = 1;
  1218. ictx->xstorm_st_context.iscsi.first_burst_length =
  1219. ISCSI_DEF_FIRST_BURST_LEN;
  1220. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1221. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1222. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1223. req1->sq_page_table_addr_lo;
  1224. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1225. req1->sq_page_table_addr_hi;
  1226. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1227. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1228. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1229. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1230. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1231. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1232. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1233. iscsi->hq_info.pgtbl[0];
  1234. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1235. iscsi->hq_info.pgtbl[1];
  1236. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1237. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1238. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1239. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1240. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1241. iscsi->r2tq_info.pgtbl[0];
  1242. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1243. iscsi->r2tq_info.pgtbl[1];
  1244. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1245. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1246. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1247. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1248. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1249. BNX2X_ISCSI_PBL_NOT_CACHED;
  1250. ictx->xstorm_st_context.iscsi.flags.flags |=
  1251. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1252. ictx->xstorm_st_context.iscsi.flags.flags |=
  1253. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1254. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1255. /* TSTORM requires the base address of RQ DB & not PTE */
  1256. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1257. req2->rq_page_table_addr_lo & PAGE_MASK;
  1258. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1259. req2->rq_page_table_addr_hi;
  1260. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1261. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1262. ictx->tstorm_st_context.tcp.flags2 |=
  1263. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1264. ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1265. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1266. req2->rq_page_table_addr_lo;
  1267. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1268. req2->rq_page_table_addr_hi;
  1269. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1270. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1271. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1272. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1273. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1274. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1275. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1276. iscsi->r2tq_info.pgtbl[0];
  1277. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1278. iscsi->r2tq_info.pgtbl[1];
  1279. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1280. req1->cq_page_table_addr_lo;
  1281. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1282. req1->cq_page_table_addr_hi;
  1283. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1284. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1285. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1286. ictx->ustorm_st_context.task_pbe_cache_index =
  1287. BNX2X_ISCSI_PBL_NOT_CACHED;
  1288. ictx->ustorm_st_context.task_pdu_cache_index =
  1289. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1290. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1291. if (j == 3) {
  1292. if (n >= n_max)
  1293. break;
  1294. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1295. j = 0;
  1296. }
  1297. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1298. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1299. req3->qp_first_pte[j].hi;
  1300. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1301. req3->qp_first_pte[j].lo;
  1302. }
  1303. ictx->ustorm_st_context.task_pbl_base.lo =
  1304. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1305. ictx->ustorm_st_context.task_pbl_base.hi =
  1306. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1307. ictx->ustorm_st_context.tce_phy_addr.lo =
  1308. iscsi->task_array_info.pgtbl[0];
  1309. ictx->ustorm_st_context.tce_phy_addr.hi =
  1310. iscsi->task_array_info.pgtbl[1];
  1311. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1312. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1313. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1314. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1315. ISCSI_DEF_MAX_BURST_LEN;
  1316. ictx->ustorm_st_context.negotiated_rx |=
  1317. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1318. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1319. ictx->cstorm_st_context.hq_pbl_base.lo =
  1320. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1321. ictx->cstorm_st_context.hq_pbl_base.hi =
  1322. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1323. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1324. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1325. ictx->cstorm_st_context.task_pbl_base.lo =
  1326. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1327. ictx->cstorm_st_context.task_pbl_base.hi =
  1328. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1329. /* CSTORM and USTORM initialization is different, CSTORM requires
  1330. * CQ DB base & not PTE addr */
  1331. ictx->cstorm_st_context.cq_db_base.lo =
  1332. req1->cq_page_table_addr_lo & PAGE_MASK;
  1333. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1334. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1335. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1336. for (i = 0; i < cp->num_cqs; i++) {
  1337. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1338. ISCSI_INITIAL_SN;
  1339. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1340. ISCSI_INITIAL_SN;
  1341. }
  1342. ictx->xstorm_ag_context.cdu_reserved =
  1343. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1344. ISCSI_CONNECTION_TYPE);
  1345. ictx->ustorm_ag_context.cdu_usage =
  1346. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1347. ISCSI_CONNECTION_TYPE);
  1348. return 0;
  1349. }
  1350. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1351. u32 num, int *work)
  1352. {
  1353. struct iscsi_kwqe_conn_offload1 *req1;
  1354. struct iscsi_kwqe_conn_offload2 *req2;
  1355. struct cnic_local *cp = dev->cnic_priv;
  1356. struct iscsi_kcqe kcqe;
  1357. struct kcqe *cqes[1];
  1358. u32 l5_cid;
  1359. int ret;
  1360. if (num < 2) {
  1361. *work = num;
  1362. return -EINVAL;
  1363. }
  1364. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1365. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1366. if ((num - 2) < req2->num_additional_wqes) {
  1367. *work = num;
  1368. return -EINVAL;
  1369. }
  1370. *work = 2 + req2->num_additional_wqes;;
  1371. l5_cid = req1->iscsi_conn_id;
  1372. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1373. return -EINVAL;
  1374. memset(&kcqe, 0, sizeof(kcqe));
  1375. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1376. kcqe.iscsi_conn_id = l5_cid;
  1377. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1378. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1379. atomic_dec(&cp->iscsi_conn);
  1380. ret = 0;
  1381. goto done;
  1382. }
  1383. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1384. if (ret) {
  1385. atomic_dec(&cp->iscsi_conn);
  1386. ret = 0;
  1387. goto done;
  1388. }
  1389. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1390. if (ret < 0) {
  1391. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1392. atomic_dec(&cp->iscsi_conn);
  1393. goto done;
  1394. }
  1395. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1396. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
  1397. cp->func);
  1398. done:
  1399. cqes[0] = (struct kcqe *) &kcqe;
  1400. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1401. return ret;
  1402. }
  1403. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1404. {
  1405. struct cnic_local *cp = dev->cnic_priv;
  1406. struct iscsi_kwqe_conn_update *req =
  1407. (struct iscsi_kwqe_conn_update *) kwqe;
  1408. void *data;
  1409. union l5cm_specific_data l5_data;
  1410. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1411. int ret;
  1412. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1413. return -EINVAL;
  1414. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1415. if (!data)
  1416. return -ENOMEM;
  1417. memcpy(data, kwqe, sizeof(struct kwqe));
  1418. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1419. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1420. return ret;
  1421. }
  1422. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1423. {
  1424. struct cnic_local *cp = dev->cnic_priv;
  1425. struct iscsi_kwqe_conn_destroy *req =
  1426. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1427. union l5cm_specific_data l5_data;
  1428. u32 l5_cid = req->reserved0;
  1429. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1430. int ret = 0;
  1431. struct iscsi_kcqe kcqe;
  1432. struct kcqe *cqes[1];
  1433. if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
  1434. goto skip_cfc_delete;
  1435. while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
  1436. msleep(250);
  1437. init_waitqueue_head(&ctx->waitq);
  1438. ctx->wait_cond = 0;
  1439. memset(&l5_data, 0, sizeof(l5_data));
  1440. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  1441. req->context_id,
  1442. ETH_CONNECTION_TYPE |
  1443. (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
  1444. &l5_data);
  1445. if (ret == 0)
  1446. wait_event(ctx->waitq, ctx->wait_cond);
  1447. skip_cfc_delete:
  1448. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1449. atomic_dec(&cp->iscsi_conn);
  1450. memset(&kcqe, 0, sizeof(kcqe));
  1451. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1452. kcqe.iscsi_conn_id = l5_cid;
  1453. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1454. kcqe.iscsi_conn_context_id = req->context_id;
  1455. cqes[0] = (struct kcqe *) &kcqe;
  1456. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1457. return ret;
  1458. }
  1459. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1460. struct l4_kwq_connect_req1 *kwqe1,
  1461. struct l4_kwq_connect_req3 *kwqe3,
  1462. struct l5cm_active_conn_buffer *conn_buf)
  1463. {
  1464. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1465. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1466. &conn_buf->xstorm_conn_buffer;
  1467. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1468. &conn_buf->tstorm_conn_buffer;
  1469. struct regpair context_addr;
  1470. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1471. struct in6_addr src_ip, dst_ip;
  1472. int i;
  1473. u32 *addrp;
  1474. addrp = (u32 *) &conn_addr->local_ip_addr;
  1475. for (i = 0; i < 4; i++, addrp++)
  1476. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1477. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1478. for (i = 0; i < 4; i++, addrp++)
  1479. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1480. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1481. xstorm_buf->context_addr.hi = context_addr.hi;
  1482. xstorm_buf->context_addr.lo = context_addr.lo;
  1483. xstorm_buf->mss = 0xffff;
  1484. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1485. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1486. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1487. xstorm_buf->pseudo_header_checksum =
  1488. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1489. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1490. tstorm_buf->params |=
  1491. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1492. if (kwqe3->ka_timeout) {
  1493. tstorm_buf->ka_enable = 1;
  1494. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1495. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1496. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1497. }
  1498. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1499. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1500. tstorm_buf->max_rt_time = 0xffffffff;
  1501. }
  1502. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1503. {
  1504. struct cnic_local *cp = dev->cnic_priv;
  1505. int func = CNIC_FUNC(cp);
  1506. u8 *mac = dev->mac_addr;
  1507. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1508. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
  1509. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1510. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
  1511. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1512. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
  1513. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1514. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
  1515. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1516. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
  1517. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1518. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
  1519. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1520. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
  1521. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1522. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1523. mac[4]);
  1524. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1525. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
  1526. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1527. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1528. mac[2]);
  1529. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1530. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
  1531. mac[1]);
  1532. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1533. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
  1534. mac[0]);
  1535. }
  1536. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1537. {
  1538. struct cnic_local *cp = dev->cnic_priv;
  1539. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1540. u16 tstorm_flags = 0;
  1541. if (tcp_ts) {
  1542. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1543. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1544. }
  1545. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1546. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
  1547. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1548. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
  1549. }
  1550. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1551. u32 num, int *work)
  1552. {
  1553. struct cnic_local *cp = dev->cnic_priv;
  1554. struct l4_kwq_connect_req1 *kwqe1 =
  1555. (struct l4_kwq_connect_req1 *) wqes[0];
  1556. struct l4_kwq_connect_req3 *kwqe3;
  1557. struct l5cm_active_conn_buffer *conn_buf;
  1558. struct l5cm_conn_addr_params *conn_addr;
  1559. union l5cm_specific_data l5_data;
  1560. u32 l5_cid = kwqe1->pg_cid;
  1561. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1562. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1563. int ret;
  1564. if (num < 2) {
  1565. *work = num;
  1566. return -EINVAL;
  1567. }
  1568. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1569. *work = 3;
  1570. else
  1571. *work = 2;
  1572. if (num < *work) {
  1573. *work = num;
  1574. return -EINVAL;
  1575. }
  1576. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1577. netdev_err(dev->netdev, "conn_buf size too big\n");
  1578. return -ENOMEM;
  1579. }
  1580. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1581. if (!conn_buf)
  1582. return -ENOMEM;
  1583. memset(conn_buf, 0, sizeof(*conn_buf));
  1584. conn_addr = &conn_buf->conn_addr_buf;
  1585. conn_addr->remote_addr_0 = csk->ha[0];
  1586. conn_addr->remote_addr_1 = csk->ha[1];
  1587. conn_addr->remote_addr_2 = csk->ha[2];
  1588. conn_addr->remote_addr_3 = csk->ha[3];
  1589. conn_addr->remote_addr_4 = csk->ha[4];
  1590. conn_addr->remote_addr_5 = csk->ha[5];
  1591. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1592. struct l4_kwq_connect_req2 *kwqe2 =
  1593. (struct l4_kwq_connect_req2 *) wqes[1];
  1594. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1595. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1596. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1597. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1598. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1599. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1600. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1601. }
  1602. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1603. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1604. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1605. conn_addr->local_tcp_port = kwqe1->src_port;
  1606. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1607. conn_addr->pmtu = kwqe3->pmtu;
  1608. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1609. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1610. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
  1611. cnic_bnx2x_set_tcp_timestamp(dev,
  1612. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1613. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1614. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1615. if (!ret)
  1616. ctx->ctx_flags |= CTX_FL_OFFLD_START;
  1617. return ret;
  1618. }
  1619. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1620. {
  1621. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1622. union l5cm_specific_data l5_data;
  1623. int ret;
  1624. memset(&l5_data, 0, sizeof(l5_data));
  1625. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1626. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1627. return ret;
  1628. }
  1629. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1630. {
  1631. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1632. union l5cm_specific_data l5_data;
  1633. int ret;
  1634. memset(&l5_data, 0, sizeof(l5_data));
  1635. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1636. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1637. return ret;
  1638. }
  1639. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1640. {
  1641. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1642. struct l4_kcq kcqe;
  1643. struct kcqe *cqes[1];
  1644. memset(&kcqe, 0, sizeof(kcqe));
  1645. kcqe.pg_host_opaque = req->host_opaque;
  1646. kcqe.pg_cid = req->host_opaque;
  1647. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1648. cqes[0] = (struct kcqe *) &kcqe;
  1649. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1650. return 0;
  1651. }
  1652. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1653. {
  1654. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1655. struct l4_kcq kcqe;
  1656. struct kcqe *cqes[1];
  1657. memset(&kcqe, 0, sizeof(kcqe));
  1658. kcqe.pg_host_opaque = req->pg_host_opaque;
  1659. kcqe.pg_cid = req->pg_cid;
  1660. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1661. cqes[0] = (struct kcqe *) &kcqe;
  1662. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1663. return 0;
  1664. }
  1665. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1666. u32 num_wqes)
  1667. {
  1668. int i, work, ret;
  1669. u32 opcode;
  1670. struct kwqe *kwqe;
  1671. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1672. return -EAGAIN; /* bnx2 is down */
  1673. for (i = 0; i < num_wqes; ) {
  1674. kwqe = wqes[i];
  1675. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1676. work = 1;
  1677. switch (opcode) {
  1678. case ISCSI_KWQE_OPCODE_INIT1:
  1679. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1680. break;
  1681. case ISCSI_KWQE_OPCODE_INIT2:
  1682. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1683. break;
  1684. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1685. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1686. num_wqes - i, &work);
  1687. break;
  1688. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1689. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1690. break;
  1691. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1692. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1693. break;
  1694. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1695. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1696. &work);
  1697. break;
  1698. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1699. ret = cnic_bnx2x_close(dev, kwqe);
  1700. break;
  1701. case L4_KWQE_OPCODE_VALUE_RESET:
  1702. ret = cnic_bnx2x_reset(dev, kwqe);
  1703. break;
  1704. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1705. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1706. break;
  1707. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1708. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1709. break;
  1710. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1711. ret = 0;
  1712. break;
  1713. default:
  1714. ret = 0;
  1715. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1716. opcode);
  1717. break;
  1718. }
  1719. if (ret < 0)
  1720. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1721. opcode);
  1722. i += work;
  1723. }
  1724. return 0;
  1725. }
  1726. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1727. {
  1728. struct cnic_local *cp = dev->cnic_priv;
  1729. int i, j;
  1730. i = 0;
  1731. j = 1;
  1732. while (num_cqes) {
  1733. struct cnic_ulp_ops *ulp_ops;
  1734. int ulp_type;
  1735. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1736. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1737. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1738. cnic_kwq_completion(dev, 1);
  1739. while (j < num_cqes) {
  1740. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1741. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1742. break;
  1743. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1744. cnic_kwq_completion(dev, 1);
  1745. j++;
  1746. }
  1747. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1748. ulp_type = CNIC_ULP_RDMA;
  1749. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1750. ulp_type = CNIC_ULP_ISCSI;
  1751. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1752. ulp_type = CNIC_ULP_L4;
  1753. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1754. goto end;
  1755. else {
  1756. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1757. kcqe_op_flag);
  1758. goto end;
  1759. }
  1760. rcu_read_lock();
  1761. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1762. if (likely(ulp_ops)) {
  1763. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1764. cp->completed_kcq + i, j);
  1765. }
  1766. rcu_read_unlock();
  1767. end:
  1768. num_cqes -= j;
  1769. i += j;
  1770. j = 1;
  1771. }
  1772. }
  1773. static u16 cnic_bnx2_next_idx(u16 idx)
  1774. {
  1775. return idx + 1;
  1776. }
  1777. static u16 cnic_bnx2_hw_idx(u16 idx)
  1778. {
  1779. return idx;
  1780. }
  1781. static u16 cnic_bnx2x_next_idx(u16 idx)
  1782. {
  1783. idx++;
  1784. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1785. idx++;
  1786. return idx;
  1787. }
  1788. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1789. {
  1790. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1791. idx++;
  1792. return idx;
  1793. }
  1794. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1795. {
  1796. struct cnic_local *cp = dev->cnic_priv;
  1797. u16 i, ri, hw_prod, last;
  1798. struct kcqe *kcqe;
  1799. int kcqe_cnt = 0, last_cnt = 0;
  1800. i = ri = last = info->sw_prod_idx;
  1801. ri &= MAX_KCQ_IDX;
  1802. hw_prod = *info->hw_prod_idx_ptr;
  1803. hw_prod = cp->hw_idx(hw_prod);
  1804. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1805. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1806. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1807. i = cp->next_idx(i);
  1808. ri = i & MAX_KCQ_IDX;
  1809. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1810. last_cnt = kcqe_cnt;
  1811. last = i;
  1812. }
  1813. }
  1814. info->sw_prod_idx = last;
  1815. return last_cnt;
  1816. }
  1817. static int cnic_l2_completion(struct cnic_local *cp)
  1818. {
  1819. u16 hw_cons, sw_cons;
  1820. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1821. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  1822. u32 cmd;
  1823. int comp = 0;
  1824. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1825. return 0;
  1826. hw_cons = *cp->rx_cons_ptr;
  1827. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1828. hw_cons++;
  1829. sw_cons = cp->rx_cons;
  1830. while (sw_cons != hw_cons) {
  1831. u8 cqe_fp_flags;
  1832. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1833. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1834. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1835. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1836. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1837. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1838. cmd == RAMROD_CMD_ID_ETH_HALT)
  1839. comp++;
  1840. }
  1841. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1842. }
  1843. return comp;
  1844. }
  1845. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1846. {
  1847. u16 rx_cons = *cp->rx_cons_ptr;
  1848. u16 tx_cons = *cp->tx_cons_ptr;
  1849. int comp = 0;
  1850. if (!test_bit(CNIC_F_CNIC_UP, &cp->dev->flags))
  1851. return;
  1852. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1853. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1854. comp = cnic_l2_completion(cp);
  1855. cp->tx_cons = tx_cons;
  1856. cp->rx_cons = rx_cons;
  1857. uio_event_notify(cp->cnic_uinfo);
  1858. }
  1859. if (comp)
  1860. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1861. }
  1862. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1863. {
  1864. struct cnic_local *cp = dev->cnic_priv;
  1865. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1866. int kcqe_cnt;
  1867. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1868. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1869. service_kcqes(dev, kcqe_cnt);
  1870. /* Tell compiler that status_blk fields can change. */
  1871. barrier();
  1872. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1873. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1874. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1875. } else
  1876. break;
  1877. }
  1878. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1879. cnic_chk_pkt_rings(cp);
  1880. return status_idx;
  1881. }
  1882. static int cnic_service_bnx2(void *data, void *status_blk)
  1883. {
  1884. struct cnic_dev *dev = data;
  1885. struct cnic_local *cp = dev->cnic_priv;
  1886. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1887. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1888. return status_idx;
  1889. return cnic_service_bnx2_queues(dev);
  1890. }
  1891. static void cnic_service_bnx2_msix(unsigned long data)
  1892. {
  1893. struct cnic_dev *dev = (struct cnic_dev *) data;
  1894. struct cnic_local *cp = dev->cnic_priv;
  1895. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1896. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1897. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1898. }
  1899. static void cnic_doirq(struct cnic_dev *dev)
  1900. {
  1901. struct cnic_local *cp = dev->cnic_priv;
  1902. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1903. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1904. prefetch(cp->status_blk.gen);
  1905. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1906. tasklet_schedule(&cp->cnic_irq_task);
  1907. }
  1908. }
  1909. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1910. {
  1911. struct cnic_dev *dev = dev_instance;
  1912. struct cnic_local *cp = dev->cnic_priv;
  1913. if (cp->ack_int)
  1914. cp->ack_int(dev);
  1915. cnic_doirq(dev);
  1916. return IRQ_HANDLED;
  1917. }
  1918. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1919. u16 index, u8 op, u8 update)
  1920. {
  1921. struct cnic_local *cp = dev->cnic_priv;
  1922. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1923. COMMAND_REG_INT_ACK);
  1924. struct igu_ack_register igu_ack;
  1925. igu_ack.status_block_index = index;
  1926. igu_ack.sb_id_and_flags =
  1927. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1928. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1929. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1930. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1931. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1932. }
  1933. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1934. {
  1935. struct cnic_local *cp = dev->cnic_priv;
  1936. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
  1937. IGU_INT_DISABLE, 0);
  1938. }
  1939. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  1940. {
  1941. u32 last_status = *info->status_idx_ptr;
  1942. int kcqe_cnt;
  1943. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  1944. service_kcqes(dev, kcqe_cnt);
  1945. /* Tell compiler that sblk fields can change. */
  1946. barrier();
  1947. if (last_status == *info->status_idx_ptr)
  1948. break;
  1949. last_status = *info->status_idx_ptr;
  1950. }
  1951. return last_status;
  1952. }
  1953. static void cnic_service_bnx2x_bh(unsigned long data)
  1954. {
  1955. struct cnic_dev *dev = (struct cnic_dev *) data;
  1956. struct cnic_local *cp = dev->cnic_priv;
  1957. u32 status_idx;
  1958. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1959. return;
  1960. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  1961. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  1962. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
  1963. status_idx, IGU_INT_ENABLE, 1);
  1964. }
  1965. static int cnic_service_bnx2x(void *data, void *status_blk)
  1966. {
  1967. struct cnic_dev *dev = data;
  1968. struct cnic_local *cp = dev->cnic_priv;
  1969. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  1970. cnic_doirq(dev);
  1971. cnic_chk_pkt_rings(cp);
  1972. return 0;
  1973. }
  1974. static void cnic_ulp_stop(struct cnic_dev *dev)
  1975. {
  1976. struct cnic_local *cp = dev->cnic_priv;
  1977. int if_type;
  1978. if (cp->cnic_uinfo)
  1979. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  1980. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1981. struct cnic_ulp_ops *ulp_ops;
  1982. mutex_lock(&cnic_lock);
  1983. ulp_ops = cp->ulp_ops[if_type];
  1984. if (!ulp_ops) {
  1985. mutex_unlock(&cnic_lock);
  1986. continue;
  1987. }
  1988. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1989. mutex_unlock(&cnic_lock);
  1990. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1991. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  1992. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1993. }
  1994. }
  1995. static void cnic_ulp_start(struct cnic_dev *dev)
  1996. {
  1997. struct cnic_local *cp = dev->cnic_priv;
  1998. int if_type;
  1999. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2000. struct cnic_ulp_ops *ulp_ops;
  2001. mutex_lock(&cnic_lock);
  2002. ulp_ops = cp->ulp_ops[if_type];
  2003. if (!ulp_ops || !ulp_ops->cnic_start) {
  2004. mutex_unlock(&cnic_lock);
  2005. continue;
  2006. }
  2007. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2008. mutex_unlock(&cnic_lock);
  2009. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2010. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2011. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2012. }
  2013. }
  2014. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2015. {
  2016. struct cnic_dev *dev = data;
  2017. switch (info->cmd) {
  2018. case CNIC_CTL_STOP_CMD:
  2019. cnic_hold(dev);
  2020. cnic_ulp_stop(dev);
  2021. cnic_stop_hw(dev);
  2022. cnic_put(dev);
  2023. break;
  2024. case CNIC_CTL_START_CMD:
  2025. cnic_hold(dev);
  2026. if (!cnic_start_hw(dev))
  2027. cnic_ulp_start(dev);
  2028. cnic_put(dev);
  2029. break;
  2030. case CNIC_CTL_COMPLETION_CMD: {
  2031. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2032. u32 l5_cid;
  2033. struct cnic_local *cp = dev->cnic_priv;
  2034. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2035. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2036. ctx->wait_cond = 1;
  2037. wake_up(&ctx->waitq);
  2038. }
  2039. break;
  2040. }
  2041. default:
  2042. return -EINVAL;
  2043. }
  2044. return 0;
  2045. }
  2046. static void cnic_ulp_init(struct cnic_dev *dev)
  2047. {
  2048. int i;
  2049. struct cnic_local *cp = dev->cnic_priv;
  2050. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2051. struct cnic_ulp_ops *ulp_ops;
  2052. mutex_lock(&cnic_lock);
  2053. ulp_ops = cnic_ulp_tbl[i];
  2054. if (!ulp_ops || !ulp_ops->cnic_init) {
  2055. mutex_unlock(&cnic_lock);
  2056. continue;
  2057. }
  2058. ulp_get(ulp_ops);
  2059. mutex_unlock(&cnic_lock);
  2060. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2061. ulp_ops->cnic_init(dev);
  2062. ulp_put(ulp_ops);
  2063. }
  2064. }
  2065. static void cnic_ulp_exit(struct cnic_dev *dev)
  2066. {
  2067. int i;
  2068. struct cnic_local *cp = dev->cnic_priv;
  2069. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2070. struct cnic_ulp_ops *ulp_ops;
  2071. mutex_lock(&cnic_lock);
  2072. ulp_ops = cnic_ulp_tbl[i];
  2073. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2074. mutex_unlock(&cnic_lock);
  2075. continue;
  2076. }
  2077. ulp_get(ulp_ops);
  2078. mutex_unlock(&cnic_lock);
  2079. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2080. ulp_ops->cnic_exit(dev);
  2081. ulp_put(ulp_ops);
  2082. }
  2083. }
  2084. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2085. {
  2086. struct cnic_dev *dev = csk->dev;
  2087. struct l4_kwq_offload_pg *l4kwqe;
  2088. struct kwqe *wqes[1];
  2089. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2090. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2091. wqes[0] = (struct kwqe *) l4kwqe;
  2092. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2093. l4kwqe->flags =
  2094. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2095. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2096. l4kwqe->da0 = csk->ha[0];
  2097. l4kwqe->da1 = csk->ha[1];
  2098. l4kwqe->da2 = csk->ha[2];
  2099. l4kwqe->da3 = csk->ha[3];
  2100. l4kwqe->da4 = csk->ha[4];
  2101. l4kwqe->da5 = csk->ha[5];
  2102. l4kwqe->sa0 = dev->mac_addr[0];
  2103. l4kwqe->sa1 = dev->mac_addr[1];
  2104. l4kwqe->sa2 = dev->mac_addr[2];
  2105. l4kwqe->sa3 = dev->mac_addr[3];
  2106. l4kwqe->sa4 = dev->mac_addr[4];
  2107. l4kwqe->sa5 = dev->mac_addr[5];
  2108. l4kwqe->etype = ETH_P_IP;
  2109. l4kwqe->ipid_start = DEF_IPID_START;
  2110. l4kwqe->host_opaque = csk->l5_cid;
  2111. if (csk->vlan_id) {
  2112. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2113. l4kwqe->vlan_tag = csk->vlan_id;
  2114. l4kwqe->l2hdr_nbytes += 4;
  2115. }
  2116. return dev->submit_kwqes(dev, wqes, 1);
  2117. }
  2118. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2119. {
  2120. struct cnic_dev *dev = csk->dev;
  2121. struct l4_kwq_update_pg *l4kwqe;
  2122. struct kwqe *wqes[1];
  2123. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2124. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2125. wqes[0] = (struct kwqe *) l4kwqe;
  2126. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2127. l4kwqe->flags =
  2128. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2129. l4kwqe->pg_cid = csk->pg_cid;
  2130. l4kwqe->da0 = csk->ha[0];
  2131. l4kwqe->da1 = csk->ha[1];
  2132. l4kwqe->da2 = csk->ha[2];
  2133. l4kwqe->da3 = csk->ha[3];
  2134. l4kwqe->da4 = csk->ha[4];
  2135. l4kwqe->da5 = csk->ha[5];
  2136. l4kwqe->pg_host_opaque = csk->l5_cid;
  2137. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2138. return dev->submit_kwqes(dev, wqes, 1);
  2139. }
  2140. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2141. {
  2142. struct cnic_dev *dev = csk->dev;
  2143. struct l4_kwq_upload *l4kwqe;
  2144. struct kwqe *wqes[1];
  2145. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2146. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2147. wqes[0] = (struct kwqe *) l4kwqe;
  2148. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2149. l4kwqe->flags =
  2150. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2151. l4kwqe->cid = csk->pg_cid;
  2152. return dev->submit_kwqes(dev, wqes, 1);
  2153. }
  2154. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2155. {
  2156. struct cnic_dev *dev = csk->dev;
  2157. struct l4_kwq_connect_req1 *l4kwqe1;
  2158. struct l4_kwq_connect_req2 *l4kwqe2;
  2159. struct l4_kwq_connect_req3 *l4kwqe3;
  2160. struct kwqe *wqes[3];
  2161. u8 tcp_flags = 0;
  2162. int num_wqes = 2;
  2163. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2164. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2165. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2166. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2167. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2168. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2169. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2170. l4kwqe3->flags =
  2171. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2172. l4kwqe3->ka_timeout = csk->ka_timeout;
  2173. l4kwqe3->ka_interval = csk->ka_interval;
  2174. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2175. l4kwqe3->tos = csk->tos;
  2176. l4kwqe3->ttl = csk->ttl;
  2177. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2178. l4kwqe3->pmtu = csk->mtu;
  2179. l4kwqe3->rcv_buf = csk->rcv_buf;
  2180. l4kwqe3->snd_buf = csk->snd_buf;
  2181. l4kwqe3->seed = csk->seed;
  2182. wqes[0] = (struct kwqe *) l4kwqe1;
  2183. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2184. wqes[1] = (struct kwqe *) l4kwqe2;
  2185. wqes[2] = (struct kwqe *) l4kwqe3;
  2186. num_wqes = 3;
  2187. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2188. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2189. l4kwqe2->flags =
  2190. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2191. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2192. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2193. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2194. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2195. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2196. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2197. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2198. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2199. sizeof(struct tcphdr);
  2200. } else {
  2201. wqes[1] = (struct kwqe *) l4kwqe3;
  2202. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2203. sizeof(struct tcphdr);
  2204. }
  2205. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2206. l4kwqe1->flags =
  2207. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2208. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2209. l4kwqe1->cid = csk->cid;
  2210. l4kwqe1->pg_cid = csk->pg_cid;
  2211. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2212. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2213. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2214. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2215. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2216. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2217. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2218. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2219. if (csk->tcp_flags & SK_TCP_NAGLE)
  2220. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2221. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2222. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2223. if (csk->tcp_flags & SK_TCP_SACK)
  2224. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2225. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2226. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2227. l4kwqe1->tcp_flags = tcp_flags;
  2228. return dev->submit_kwqes(dev, wqes, num_wqes);
  2229. }
  2230. static int cnic_cm_close_req(struct cnic_sock *csk)
  2231. {
  2232. struct cnic_dev *dev = csk->dev;
  2233. struct l4_kwq_close_req *l4kwqe;
  2234. struct kwqe *wqes[1];
  2235. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2236. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2237. wqes[0] = (struct kwqe *) l4kwqe;
  2238. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2239. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2240. l4kwqe->cid = csk->cid;
  2241. return dev->submit_kwqes(dev, wqes, 1);
  2242. }
  2243. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2244. {
  2245. struct cnic_dev *dev = csk->dev;
  2246. struct l4_kwq_reset_req *l4kwqe;
  2247. struct kwqe *wqes[1];
  2248. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2249. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2250. wqes[0] = (struct kwqe *) l4kwqe;
  2251. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2252. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2253. l4kwqe->cid = csk->cid;
  2254. return dev->submit_kwqes(dev, wqes, 1);
  2255. }
  2256. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2257. u32 l5_cid, struct cnic_sock **csk, void *context)
  2258. {
  2259. struct cnic_local *cp = dev->cnic_priv;
  2260. struct cnic_sock *csk1;
  2261. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2262. return -EINVAL;
  2263. csk1 = &cp->csk_tbl[l5_cid];
  2264. if (atomic_read(&csk1->ref_count))
  2265. return -EAGAIN;
  2266. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2267. return -EBUSY;
  2268. csk1->dev = dev;
  2269. csk1->cid = cid;
  2270. csk1->l5_cid = l5_cid;
  2271. csk1->ulp_type = ulp_type;
  2272. csk1->context = context;
  2273. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2274. csk1->ka_interval = DEF_KA_INTERVAL;
  2275. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2276. csk1->tos = DEF_TOS;
  2277. csk1->ttl = DEF_TTL;
  2278. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2279. csk1->rcv_buf = DEF_RCV_BUF;
  2280. csk1->snd_buf = DEF_SND_BUF;
  2281. csk1->seed = DEF_SEED;
  2282. *csk = csk1;
  2283. return 0;
  2284. }
  2285. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2286. {
  2287. if (csk->src_port) {
  2288. struct cnic_dev *dev = csk->dev;
  2289. struct cnic_local *cp = dev->cnic_priv;
  2290. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2291. csk->src_port = 0;
  2292. }
  2293. }
  2294. static void cnic_close_conn(struct cnic_sock *csk)
  2295. {
  2296. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2297. cnic_cm_upload_pg(csk);
  2298. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2299. }
  2300. cnic_cm_cleanup(csk);
  2301. }
  2302. static int cnic_cm_destroy(struct cnic_sock *csk)
  2303. {
  2304. if (!cnic_in_use(csk))
  2305. return -EINVAL;
  2306. csk_hold(csk);
  2307. clear_bit(SK_F_INUSE, &csk->flags);
  2308. smp_mb__after_clear_bit();
  2309. while (atomic_read(&csk->ref_count) != 1)
  2310. msleep(1);
  2311. cnic_cm_cleanup(csk);
  2312. csk->flags = 0;
  2313. csk_put(csk);
  2314. return 0;
  2315. }
  2316. static inline u16 cnic_get_vlan(struct net_device *dev,
  2317. struct net_device **vlan_dev)
  2318. {
  2319. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2320. *vlan_dev = vlan_dev_real_dev(dev);
  2321. return vlan_dev_vlan_id(dev);
  2322. }
  2323. *vlan_dev = dev;
  2324. return 0;
  2325. }
  2326. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2327. struct dst_entry **dst)
  2328. {
  2329. #if defined(CONFIG_INET)
  2330. struct flowi fl;
  2331. int err;
  2332. struct rtable *rt;
  2333. memset(&fl, 0, sizeof(fl));
  2334. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2335. err = ip_route_output_key(&init_net, &rt, &fl);
  2336. if (!err)
  2337. *dst = &rt->dst;
  2338. return err;
  2339. #else
  2340. return -ENETUNREACH;
  2341. #endif
  2342. }
  2343. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2344. struct dst_entry **dst)
  2345. {
  2346. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2347. struct flowi fl;
  2348. memset(&fl, 0, sizeof(fl));
  2349. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2350. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2351. fl.oif = dst_addr->sin6_scope_id;
  2352. *dst = ip6_route_output(&init_net, NULL, &fl);
  2353. if (*dst)
  2354. return 0;
  2355. #endif
  2356. return -ENETUNREACH;
  2357. }
  2358. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2359. int ulp_type)
  2360. {
  2361. struct cnic_dev *dev = NULL;
  2362. struct dst_entry *dst;
  2363. struct net_device *netdev = NULL;
  2364. int err = -ENETUNREACH;
  2365. if (dst_addr->sin_family == AF_INET)
  2366. err = cnic_get_v4_route(dst_addr, &dst);
  2367. else if (dst_addr->sin_family == AF_INET6) {
  2368. struct sockaddr_in6 *dst_addr6 =
  2369. (struct sockaddr_in6 *) dst_addr;
  2370. err = cnic_get_v6_route(dst_addr6, &dst);
  2371. } else
  2372. return NULL;
  2373. if (err)
  2374. return NULL;
  2375. if (!dst->dev)
  2376. goto done;
  2377. cnic_get_vlan(dst->dev, &netdev);
  2378. dev = cnic_from_netdev(netdev);
  2379. done:
  2380. dst_release(dst);
  2381. if (dev)
  2382. cnic_put(dev);
  2383. return dev;
  2384. }
  2385. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2386. {
  2387. struct cnic_dev *dev = csk->dev;
  2388. struct cnic_local *cp = dev->cnic_priv;
  2389. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2390. }
  2391. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2392. {
  2393. struct cnic_dev *dev = csk->dev;
  2394. struct cnic_local *cp = dev->cnic_priv;
  2395. int is_v6, rc = 0;
  2396. struct dst_entry *dst = NULL;
  2397. struct net_device *realdev;
  2398. u32 local_port;
  2399. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2400. saddr->remote.v6.sin6_family == AF_INET6)
  2401. is_v6 = 1;
  2402. else if (saddr->local.v4.sin_family == AF_INET &&
  2403. saddr->remote.v4.sin_family == AF_INET)
  2404. is_v6 = 0;
  2405. else
  2406. return -EINVAL;
  2407. clear_bit(SK_F_IPV6, &csk->flags);
  2408. if (is_v6) {
  2409. set_bit(SK_F_IPV6, &csk->flags);
  2410. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2411. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2412. sizeof(struct in6_addr));
  2413. csk->dst_port = saddr->remote.v6.sin6_port;
  2414. local_port = saddr->local.v6.sin6_port;
  2415. } else {
  2416. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2417. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2418. csk->dst_port = saddr->remote.v4.sin_port;
  2419. local_port = saddr->local.v4.sin_port;
  2420. }
  2421. csk->vlan_id = 0;
  2422. csk->mtu = dev->netdev->mtu;
  2423. if (dst && dst->dev) {
  2424. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2425. if (realdev == dev->netdev) {
  2426. csk->vlan_id = vlan;
  2427. csk->mtu = dst_mtu(dst);
  2428. }
  2429. }
  2430. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2431. local_port < CNIC_LOCAL_PORT_MAX) {
  2432. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2433. local_port = 0;
  2434. } else
  2435. local_port = 0;
  2436. if (!local_port) {
  2437. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2438. if (local_port == -1) {
  2439. rc = -ENOMEM;
  2440. goto err_out;
  2441. }
  2442. }
  2443. csk->src_port = local_port;
  2444. err_out:
  2445. dst_release(dst);
  2446. return rc;
  2447. }
  2448. static void cnic_init_csk_state(struct cnic_sock *csk)
  2449. {
  2450. csk->state = 0;
  2451. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2452. clear_bit(SK_F_CLOSING, &csk->flags);
  2453. }
  2454. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2455. {
  2456. int err = 0;
  2457. if (!cnic_in_use(csk))
  2458. return -EINVAL;
  2459. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2460. return -EINVAL;
  2461. cnic_init_csk_state(csk);
  2462. err = cnic_get_route(csk, saddr);
  2463. if (err)
  2464. goto err_out;
  2465. err = cnic_resolve_addr(csk, saddr);
  2466. if (!err)
  2467. return 0;
  2468. err_out:
  2469. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2470. return err;
  2471. }
  2472. static int cnic_cm_abort(struct cnic_sock *csk)
  2473. {
  2474. struct cnic_local *cp = csk->dev->cnic_priv;
  2475. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2476. if (!cnic_in_use(csk))
  2477. return -EINVAL;
  2478. if (cnic_abort_prep(csk))
  2479. return cnic_cm_abort_req(csk);
  2480. /* Getting here means that we haven't started connect, or
  2481. * connect was not successful.
  2482. */
  2483. cp->close_conn(csk, opcode);
  2484. if (csk->state != opcode)
  2485. return -EALREADY;
  2486. return 0;
  2487. }
  2488. static int cnic_cm_close(struct cnic_sock *csk)
  2489. {
  2490. if (!cnic_in_use(csk))
  2491. return -EINVAL;
  2492. if (cnic_close_prep(csk)) {
  2493. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2494. return cnic_cm_close_req(csk);
  2495. } else {
  2496. return -EALREADY;
  2497. }
  2498. return 0;
  2499. }
  2500. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2501. u8 opcode)
  2502. {
  2503. struct cnic_ulp_ops *ulp_ops;
  2504. int ulp_type = csk->ulp_type;
  2505. rcu_read_lock();
  2506. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2507. if (ulp_ops) {
  2508. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2509. ulp_ops->cm_connect_complete(csk);
  2510. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2511. ulp_ops->cm_close_complete(csk);
  2512. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2513. ulp_ops->cm_remote_abort(csk);
  2514. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2515. ulp_ops->cm_abort_complete(csk);
  2516. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2517. ulp_ops->cm_remote_close(csk);
  2518. }
  2519. rcu_read_unlock();
  2520. }
  2521. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2522. {
  2523. if (cnic_offld_prep(csk)) {
  2524. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2525. cnic_cm_update_pg(csk);
  2526. else
  2527. cnic_cm_offload_pg(csk);
  2528. }
  2529. return 0;
  2530. }
  2531. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2532. {
  2533. struct cnic_local *cp = dev->cnic_priv;
  2534. u32 l5_cid = kcqe->pg_host_opaque;
  2535. u8 opcode = kcqe->op_code;
  2536. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2537. csk_hold(csk);
  2538. if (!cnic_in_use(csk))
  2539. goto done;
  2540. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2541. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2542. goto done;
  2543. }
  2544. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2545. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2546. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2547. cnic_cm_upcall(cp, csk,
  2548. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2549. goto done;
  2550. }
  2551. csk->pg_cid = kcqe->pg_cid;
  2552. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2553. cnic_cm_conn_req(csk);
  2554. done:
  2555. csk_put(csk);
  2556. }
  2557. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2558. {
  2559. struct cnic_local *cp = dev->cnic_priv;
  2560. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2561. u8 opcode = l4kcqe->op_code;
  2562. u32 l5_cid;
  2563. struct cnic_sock *csk;
  2564. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2565. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2566. cnic_cm_process_offld_pg(dev, l4kcqe);
  2567. return;
  2568. }
  2569. l5_cid = l4kcqe->conn_id;
  2570. if (opcode & 0x80)
  2571. l5_cid = l4kcqe->cid;
  2572. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2573. return;
  2574. csk = &cp->csk_tbl[l5_cid];
  2575. csk_hold(csk);
  2576. if (!cnic_in_use(csk)) {
  2577. csk_put(csk);
  2578. return;
  2579. }
  2580. switch (opcode) {
  2581. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2582. if (l4kcqe->status != 0) {
  2583. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2584. cnic_cm_upcall(cp, csk,
  2585. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2586. }
  2587. break;
  2588. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2589. if (l4kcqe->status == 0)
  2590. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2591. smp_mb__before_clear_bit();
  2592. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2593. cnic_cm_upcall(cp, csk, opcode);
  2594. break;
  2595. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2596. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2597. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2598. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2599. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2600. cp->close_conn(csk, opcode);
  2601. break;
  2602. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2603. cnic_cm_upcall(cp, csk, opcode);
  2604. break;
  2605. }
  2606. csk_put(csk);
  2607. }
  2608. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2609. {
  2610. struct cnic_dev *dev = data;
  2611. int i;
  2612. for (i = 0; i < num; i++)
  2613. cnic_cm_process_kcqe(dev, kcqe[i]);
  2614. }
  2615. static struct cnic_ulp_ops cm_ulp_ops = {
  2616. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2617. };
  2618. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2619. {
  2620. struct cnic_local *cp = dev->cnic_priv;
  2621. kfree(cp->csk_tbl);
  2622. cp->csk_tbl = NULL;
  2623. cnic_free_id_tbl(&cp->csk_port_tbl);
  2624. }
  2625. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2626. {
  2627. struct cnic_local *cp = dev->cnic_priv;
  2628. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2629. GFP_KERNEL);
  2630. if (!cp->csk_tbl)
  2631. return -ENOMEM;
  2632. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2633. CNIC_LOCAL_PORT_MIN)) {
  2634. cnic_cm_free_mem(dev);
  2635. return -ENOMEM;
  2636. }
  2637. return 0;
  2638. }
  2639. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2640. {
  2641. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2642. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2643. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2644. csk->state = opcode;
  2645. }
  2646. /* 1. If event opcode matches the expected event in csk->state
  2647. * 2. If the expected event is CLOSE_COMP, we accept any event
  2648. * 3. If the expected event is 0, meaning the connection was never
  2649. * never established, we accept the opcode from cm_abort.
  2650. */
  2651. if (opcode == csk->state || csk->state == 0 ||
  2652. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2653. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2654. if (csk->state == 0)
  2655. csk->state = opcode;
  2656. return 1;
  2657. }
  2658. }
  2659. return 0;
  2660. }
  2661. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2662. {
  2663. struct cnic_dev *dev = csk->dev;
  2664. struct cnic_local *cp = dev->cnic_priv;
  2665. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2666. cnic_cm_upcall(cp, csk, opcode);
  2667. return;
  2668. }
  2669. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2670. cnic_close_conn(csk);
  2671. csk->state = opcode;
  2672. cnic_cm_upcall(cp, csk, opcode);
  2673. }
  2674. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2675. {
  2676. }
  2677. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2678. {
  2679. u32 seed;
  2680. get_random_bytes(&seed, 4);
  2681. cnic_ctx_wr(dev, 45, 0, seed);
  2682. return 0;
  2683. }
  2684. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2685. {
  2686. struct cnic_dev *dev = csk->dev;
  2687. struct cnic_local *cp = dev->cnic_priv;
  2688. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2689. union l5cm_specific_data l5_data;
  2690. u32 cmd = 0;
  2691. int close_complete = 0;
  2692. switch (opcode) {
  2693. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2694. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2695. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2696. if (cnic_ready_to_close(csk, opcode)) {
  2697. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2698. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2699. else
  2700. close_complete = 1;
  2701. }
  2702. break;
  2703. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2704. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2705. break;
  2706. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2707. close_complete = 1;
  2708. break;
  2709. }
  2710. if (cmd) {
  2711. memset(&l5_data, 0, sizeof(l5_data));
  2712. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2713. &l5_data);
  2714. } else if (close_complete) {
  2715. ctx->timestamp = jiffies;
  2716. cnic_close_conn(csk);
  2717. cnic_cm_upcall(cp, csk, csk->state);
  2718. }
  2719. }
  2720. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2721. {
  2722. }
  2723. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2724. {
  2725. struct cnic_local *cp = dev->cnic_priv;
  2726. int func = CNIC_FUNC(cp);
  2727. cnic_init_bnx2x_mac(dev);
  2728. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2729. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2730. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
  2731. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2732. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
  2733. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2734. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
  2735. DEF_MAX_DA_COUNT);
  2736. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2737. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
  2738. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2739. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
  2740. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2741. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
  2742. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2743. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
  2744. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
  2745. DEF_MAX_CWND);
  2746. return 0;
  2747. }
  2748. static int cnic_cm_open(struct cnic_dev *dev)
  2749. {
  2750. struct cnic_local *cp = dev->cnic_priv;
  2751. int err;
  2752. err = cnic_cm_alloc_mem(dev);
  2753. if (err)
  2754. return err;
  2755. err = cp->start_cm(dev);
  2756. if (err)
  2757. goto err_out;
  2758. dev->cm_create = cnic_cm_create;
  2759. dev->cm_destroy = cnic_cm_destroy;
  2760. dev->cm_connect = cnic_cm_connect;
  2761. dev->cm_abort = cnic_cm_abort;
  2762. dev->cm_close = cnic_cm_close;
  2763. dev->cm_select_dev = cnic_cm_select_dev;
  2764. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2765. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2766. return 0;
  2767. err_out:
  2768. cnic_cm_free_mem(dev);
  2769. return err;
  2770. }
  2771. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2772. {
  2773. struct cnic_local *cp = dev->cnic_priv;
  2774. int i;
  2775. cp->stop_cm(dev);
  2776. if (!cp->csk_tbl)
  2777. return 0;
  2778. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2779. struct cnic_sock *csk = &cp->csk_tbl[i];
  2780. clear_bit(SK_F_INUSE, &csk->flags);
  2781. cnic_cm_cleanup(csk);
  2782. }
  2783. cnic_cm_free_mem(dev);
  2784. return 0;
  2785. }
  2786. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2787. {
  2788. u32 cid_addr;
  2789. int i;
  2790. cid_addr = GET_CID_ADDR(cid);
  2791. for (i = 0; i < CTX_SIZE; i += 4)
  2792. cnic_ctx_wr(dev, cid_addr, i, 0);
  2793. }
  2794. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2795. {
  2796. struct cnic_local *cp = dev->cnic_priv;
  2797. int ret = 0, i;
  2798. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2799. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2800. return 0;
  2801. for (i = 0; i < cp->ctx_blks; i++) {
  2802. int j;
  2803. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2804. u32 val;
  2805. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2806. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2807. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2808. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2809. (u64) cp->ctx_arr[i].mapping >> 32);
  2810. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2811. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2812. for (j = 0; j < 10; j++) {
  2813. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2814. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2815. break;
  2816. udelay(5);
  2817. }
  2818. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2819. ret = -EBUSY;
  2820. break;
  2821. }
  2822. }
  2823. return ret;
  2824. }
  2825. static void cnic_free_irq(struct cnic_dev *dev)
  2826. {
  2827. struct cnic_local *cp = dev->cnic_priv;
  2828. struct cnic_eth_dev *ethdev = cp->ethdev;
  2829. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2830. cp->disable_int_sync(dev);
  2831. tasklet_disable(&cp->cnic_irq_task);
  2832. free_irq(ethdev->irq_arr[0].vector, dev);
  2833. }
  2834. }
  2835. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2836. {
  2837. struct cnic_local *cp = dev->cnic_priv;
  2838. struct cnic_eth_dev *ethdev = cp->ethdev;
  2839. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2840. int err, i = 0;
  2841. int sblk_num = cp->status_blk_num;
  2842. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2843. BNX2_HC_SB_CONFIG_1;
  2844. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2845. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2846. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2847. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2848. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  2849. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2850. (unsigned long) dev);
  2851. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  2852. "cnic", dev);
  2853. if (err) {
  2854. tasklet_disable(&cp->cnic_irq_task);
  2855. return err;
  2856. }
  2857. while (cp->status_blk.bnx2->status_completion_producer_index &&
  2858. i < 10) {
  2859. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2860. 1 << (11 + sblk_num));
  2861. udelay(10);
  2862. i++;
  2863. barrier();
  2864. }
  2865. if (cp->status_blk.bnx2->status_completion_producer_index) {
  2866. cnic_free_irq(dev);
  2867. goto failed;
  2868. }
  2869. } else {
  2870. struct status_block *sblk = cp->status_blk.gen;
  2871. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2872. int i = 0;
  2873. while (sblk->status_completion_producer_index && i < 10) {
  2874. CNIC_WR(dev, BNX2_HC_COMMAND,
  2875. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2876. udelay(10);
  2877. i++;
  2878. barrier();
  2879. }
  2880. if (sblk->status_completion_producer_index)
  2881. goto failed;
  2882. }
  2883. return 0;
  2884. failed:
  2885. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  2886. return -EBUSY;
  2887. }
  2888. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2889. {
  2890. struct cnic_local *cp = dev->cnic_priv;
  2891. struct cnic_eth_dev *ethdev = cp->ethdev;
  2892. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2893. return;
  2894. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2895. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2896. }
  2897. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2898. {
  2899. struct cnic_local *cp = dev->cnic_priv;
  2900. struct cnic_eth_dev *ethdev = cp->ethdev;
  2901. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2902. return;
  2903. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2904. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2905. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2906. synchronize_irq(ethdev->irq_arr[0].vector);
  2907. }
  2908. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  2909. {
  2910. struct cnic_local *cp = dev->cnic_priv;
  2911. struct cnic_eth_dev *ethdev = cp->ethdev;
  2912. u32 cid_addr, tx_cid, sb_id;
  2913. u32 val, offset0, offset1, offset2, offset3;
  2914. int i;
  2915. struct tx_bd *txbd;
  2916. dma_addr_t buf_map;
  2917. struct status_block *s_blk = cp->status_blk.gen;
  2918. sb_id = cp->status_blk_num;
  2919. tx_cid = 20;
  2920. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  2921. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2922. struct status_block_msix *sblk = cp->status_blk.bnx2;
  2923. tx_cid = TX_TSS_CID + sb_id - 1;
  2924. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  2925. (TX_TSS_CID << 7));
  2926. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  2927. }
  2928. cp->tx_cons = *cp->tx_cons_ptr;
  2929. cid_addr = GET_CID_ADDR(tx_cid);
  2930. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  2931. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  2932. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  2933. cnic_ctx_wr(dev, cid_addr2, i, 0);
  2934. offset0 = BNX2_L2CTX_TYPE_XI;
  2935. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2936. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2937. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2938. } else {
  2939. cnic_init_context(dev, tx_cid);
  2940. cnic_init_context(dev, tx_cid + 1);
  2941. offset0 = BNX2_L2CTX_TYPE;
  2942. offset1 = BNX2_L2CTX_CMD_TYPE;
  2943. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2944. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2945. }
  2946. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2947. cnic_ctx_wr(dev, cid_addr, offset0, val);
  2948. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2949. cnic_ctx_wr(dev, cid_addr, offset1, val);
  2950. txbd = (struct tx_bd *) cp->l2_ring;
  2951. buf_map = cp->l2_buf_map;
  2952. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  2953. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  2954. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2955. }
  2956. val = (u64) cp->l2_ring_map >> 32;
  2957. cnic_ctx_wr(dev, cid_addr, offset2, val);
  2958. txbd->tx_bd_haddr_hi = val;
  2959. val = (u64) cp->l2_ring_map & 0xffffffff;
  2960. cnic_ctx_wr(dev, cid_addr, offset3, val);
  2961. txbd->tx_bd_haddr_lo = val;
  2962. }
  2963. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  2964. {
  2965. struct cnic_local *cp = dev->cnic_priv;
  2966. struct cnic_eth_dev *ethdev = cp->ethdev;
  2967. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  2968. int i;
  2969. struct rx_bd *rxbd;
  2970. struct status_block *s_blk = cp->status_blk.gen;
  2971. sb_id = cp->status_blk_num;
  2972. cnic_init_context(dev, 2);
  2973. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  2974. coal_reg = BNX2_HC_COMMAND;
  2975. coal_val = CNIC_RD(dev, coal_reg);
  2976. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2977. struct status_block_msix *sblk = cp->status_blk.bnx2;
  2978. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  2979. coal_reg = BNX2_HC_COALESCE_NOW;
  2980. coal_val = 1 << (11 + sb_id);
  2981. }
  2982. i = 0;
  2983. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  2984. CNIC_WR(dev, coal_reg, coal_val);
  2985. udelay(10);
  2986. i++;
  2987. barrier();
  2988. }
  2989. cp->rx_cons = *cp->rx_cons_ptr;
  2990. cid_addr = GET_CID_ADDR(2);
  2991. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  2992. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  2993. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  2994. if (sb_id == 0)
  2995. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  2996. else
  2997. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  2998. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  2999. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  3000. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3001. dma_addr_t buf_map;
  3002. int n = (i % cp->l2_rx_ring_size) + 1;
  3003. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3004. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3005. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3006. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3007. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3008. }
  3009. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3010. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3011. rxbd->rx_bd_haddr_hi = val;
  3012. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3013. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3014. rxbd->rx_bd_haddr_lo = val;
  3015. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3016. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3017. }
  3018. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3019. {
  3020. struct kwqe *wqes[1], l2kwqe;
  3021. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3022. wqes[0] = &l2kwqe;
  3023. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3024. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3025. KWQE_OPCODE_SHIFT) | 2;
  3026. dev->submit_kwqes(dev, wqes, 1);
  3027. }
  3028. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3029. {
  3030. struct cnic_local *cp = dev->cnic_priv;
  3031. u32 val;
  3032. val = cp->func << 2;
  3033. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3034. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3035. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3036. dev->mac_addr[0] = (u8) (val >> 8);
  3037. dev->mac_addr[1] = (u8) val;
  3038. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3039. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3040. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3041. dev->mac_addr[2] = (u8) (val >> 24);
  3042. dev->mac_addr[3] = (u8) (val >> 16);
  3043. dev->mac_addr[4] = (u8) (val >> 8);
  3044. dev->mac_addr[5] = (u8) val;
  3045. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3046. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3047. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3048. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3049. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3050. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3051. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3052. }
  3053. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3054. {
  3055. struct cnic_local *cp = dev->cnic_priv;
  3056. struct cnic_eth_dev *ethdev = cp->ethdev;
  3057. struct status_block *sblk = cp->status_blk.gen;
  3058. u32 val, kcq_cid_addr, kwq_cid_addr;
  3059. int err;
  3060. cnic_set_bnx2_mac(dev);
  3061. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3062. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3063. if (BCM_PAGE_BITS > 12)
  3064. val |= (12 - 8) << 4;
  3065. else
  3066. val |= (BCM_PAGE_BITS - 8) << 4;
  3067. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3068. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3069. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3070. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3071. err = cnic_setup_5709_context(dev, 1);
  3072. if (err)
  3073. return err;
  3074. cnic_init_context(dev, KWQ_CID);
  3075. cnic_init_context(dev, KCQ_CID);
  3076. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3077. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3078. cp->max_kwq_idx = MAX_KWQ_IDX;
  3079. cp->kwq_prod_idx = 0;
  3080. cp->kwq_con_idx = 0;
  3081. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3082. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3083. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3084. else
  3085. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3086. /* Initialize the kernel work queue context. */
  3087. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3088. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3089. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3090. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3091. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3092. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3093. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3094. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3095. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3096. val = (u32) cp->kwq_info.pgtbl_map;
  3097. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3098. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3099. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3100. cp->kcq1.sw_prod_idx = 0;
  3101. cp->kcq1.hw_prod_idx_ptr =
  3102. (u16 *) &sblk->status_completion_producer_index;
  3103. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3104. /* Initialize the kernel complete queue context. */
  3105. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3106. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3107. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3108. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3109. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3110. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3111. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3112. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3113. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3114. val = (u32) cp->kcq1.dma.pgtbl_map;
  3115. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3116. cp->int_num = 0;
  3117. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3118. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3119. u32 sb_id = cp->status_blk_num;
  3120. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3121. cp->kcq1.hw_prod_idx_ptr =
  3122. (u16 *) &msblk->status_completion_producer_index;
  3123. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3124. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3125. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3126. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3127. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3128. }
  3129. /* Enable Commnad Scheduler notification when we write to the
  3130. * host producer index of the kernel contexts. */
  3131. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3132. /* Enable Command Scheduler notification when we write to either
  3133. * the Send Queue or Receive Queue producer indexes of the kernel
  3134. * bypass contexts. */
  3135. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3136. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3137. /* Notify COM when the driver post an application buffer. */
  3138. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3139. /* Set the CP and COM doorbells. These two processors polls the
  3140. * doorbell for a non zero value before running. This must be done
  3141. * after setting up the kernel queue contexts. */
  3142. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3143. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3144. cnic_init_bnx2_tx_ring(dev);
  3145. cnic_init_bnx2_rx_ring(dev);
  3146. err = cnic_init_bnx2_irq(dev);
  3147. if (err) {
  3148. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3149. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3150. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3151. return err;
  3152. }
  3153. return 0;
  3154. }
  3155. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3156. {
  3157. struct cnic_local *cp = dev->cnic_priv;
  3158. struct cnic_eth_dev *ethdev = cp->ethdev;
  3159. u32 start_offset = ethdev->ctx_tbl_offset;
  3160. int i;
  3161. for (i = 0; i < cp->ctx_blks; i++) {
  3162. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3163. dma_addr_t map = ctx->mapping;
  3164. if (cp->ctx_align) {
  3165. unsigned long mask = cp->ctx_align - 1;
  3166. map = (map + mask) & ~mask;
  3167. }
  3168. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3169. }
  3170. }
  3171. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3172. {
  3173. struct cnic_local *cp = dev->cnic_priv;
  3174. struct cnic_eth_dev *ethdev = cp->ethdev;
  3175. int err = 0;
  3176. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3177. (unsigned long) dev);
  3178. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3179. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  3180. "cnic", dev);
  3181. if (err)
  3182. tasklet_disable(&cp->cnic_irq_task);
  3183. }
  3184. return err;
  3185. }
  3186. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3187. {
  3188. struct cnic_local *cp = dev->cnic_priv;
  3189. u8 sb_id = cp->status_blk_num;
  3190. int port = CNIC_PORT(cp);
  3191. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3192. CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
  3193. HC_INDEX_C_ISCSI_EQ_CONS),
  3194. 64 / 12);
  3195. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3196. CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
  3197. HC_INDEX_C_ISCSI_EQ_CONS), 0);
  3198. }
  3199. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3200. {
  3201. }
  3202. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
  3203. {
  3204. struct cnic_local *cp = dev->cnic_priv;
  3205. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3206. struct eth_context *context;
  3207. struct regpair context_addr;
  3208. dma_addr_t buf_map;
  3209. int func = CNIC_FUNC(cp);
  3210. int port = CNIC_PORT(cp);
  3211. int i;
  3212. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3213. u32 val;
  3214. memset(txbd, 0, BCM_PAGE_SIZE);
  3215. buf_map = cp->l2_buf_map;
  3216. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3217. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3218. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3219. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3220. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3221. reg_bd->addr_hi = start_bd->addr_hi;
  3222. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3223. start_bd->nbytes = cpu_to_le16(0x10);
  3224. start_bd->nbd = cpu_to_le16(3);
  3225. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3226. start_bd->general_data = (UNICAST_ADDRESS <<
  3227. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3228. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3229. }
  3230. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
  3231. val = (u64) cp->l2_ring_map >> 32;
  3232. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3233. context->xstorm_st_context.tx_bd_page_base_hi = val;
  3234. val = (u64) cp->l2_ring_map & 0xffffffff;
  3235. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3236. context->xstorm_st_context.tx_bd_page_base_lo = val;
  3237. context->cstorm_st_context.sb_index_number =
  3238. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
  3239. context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
  3240. if (cli < MAX_X_STAT_COUNTER_ID)
  3241. context->xstorm_st_context.statistics_data = cli |
  3242. XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE;
  3243. context->xstorm_ag_context.cdu_reserved =
  3244. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3245. CDU_REGION_NUMBER_XCM_AG,
  3246. ETH_CONNECTION_TYPE);
  3247. /* reset xstorm per client statistics */
  3248. if (cli < MAX_X_STAT_COUNTER_ID) {
  3249. val = BAR_XSTRORM_INTMEM +
  3250. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3251. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3252. CNIC_WR(dev, val + i * 4, 0);
  3253. }
  3254. cp->tx_cons_ptr =
  3255. &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
  3256. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
  3257. }
  3258. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
  3259. {
  3260. struct cnic_local *cp = dev->cnic_priv;
  3261. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3262. BCM_PAGE_SIZE);
  3263. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3264. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3265. struct eth_context *context;
  3266. struct regpair context_addr;
  3267. int i;
  3268. int port = CNIC_PORT(cp);
  3269. int func = CNIC_FUNC(cp);
  3270. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3271. u32 val;
  3272. struct tstorm_eth_client_config tstorm_client = {0};
  3273. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3274. dma_addr_t buf_map;
  3275. int n = (i % cp->l2_rx_ring_size) + 1;
  3276. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3277. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3278. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3279. }
  3280. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
  3281. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3282. rxbd->addr_hi = cpu_to_le32(val);
  3283. context->ustorm_st_context.common.bd_page_base_hi = val;
  3284. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3285. rxbd->addr_lo = cpu_to_le32(val);
  3286. context->ustorm_st_context.common.bd_page_base_lo = val;
  3287. context->ustorm_st_context.common.sb_index_numbers =
  3288. BNX2X_ISCSI_RX_SB_INDEX_NUM;
  3289. context->ustorm_st_context.common.clientId = cli;
  3290. context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
  3291. if (cli < MAX_U_STAT_COUNTER_ID) {
  3292. context->ustorm_st_context.common.flags =
  3293. USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
  3294. context->ustorm_st_context.common.statistics_counter_id = cli;
  3295. }
  3296. context->ustorm_st_context.common.mc_alignment_log_size = 0;
  3297. context->ustorm_st_context.common.bd_buff_size =
  3298. cp->l2_single_buf_size;
  3299. context->ustorm_ag_context.cdu_usage =
  3300. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3301. CDU_REGION_NUMBER_UCM_AG,
  3302. ETH_CONNECTION_TYPE);
  3303. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3304. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3305. rxcqe->addr_hi = cpu_to_le32(val);
  3306. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3307. USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
  3308. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3309. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
  3310. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3311. rxcqe->addr_lo = cpu_to_le32(val);
  3312. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3313. USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
  3314. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3315. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
  3316. /* client tstorm info */
  3317. tstorm_client.mtu = cp->l2_single_buf_size - 14;
  3318. tstorm_client.config_flags = TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE;
  3319. if (cli < MAX_T_STAT_COUNTER_ID) {
  3320. tstorm_client.config_flags |=
  3321. TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
  3322. tstorm_client.statistics_counter_id = cli;
  3323. }
  3324. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3325. TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
  3326. ((u32 *)&tstorm_client)[0]);
  3327. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3328. TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
  3329. ((u32 *)&tstorm_client)[1]);
  3330. /* reset tstorm per client statistics */
  3331. if (cli < MAX_T_STAT_COUNTER_ID) {
  3332. val = BAR_TSTRORM_INTMEM +
  3333. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3334. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3335. CNIC_WR(dev, val + i * 4, 0);
  3336. }
  3337. /* reset ustorm per client statistics */
  3338. if (cli < MAX_U_STAT_COUNTER_ID) {
  3339. val = BAR_USTRORM_INTMEM +
  3340. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3341. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3342. CNIC_WR(dev, val + i * 4, 0);
  3343. }
  3344. cp->rx_cons_ptr =
  3345. &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
  3346. HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
  3347. }
  3348. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3349. {
  3350. struct cnic_local *cp = dev->cnic_priv;
  3351. u32 base, addr, val;
  3352. int port = CNIC_PORT(cp);
  3353. dev->max_iscsi_conn = 0;
  3354. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3355. if (base < 0xa0000 || base >= 0xc0000)
  3356. return;
  3357. addr = BNX2X_SHMEM_ADDR(base,
  3358. dev_info.port_hw_config[port].iscsi_mac_upper);
  3359. val = CNIC_RD(dev, addr);
  3360. dev->mac_addr[0] = (u8) (val >> 8);
  3361. dev->mac_addr[1] = (u8) val;
  3362. addr = BNX2X_SHMEM_ADDR(base,
  3363. dev_info.port_hw_config[port].iscsi_mac_lower);
  3364. val = CNIC_RD(dev, addr);
  3365. dev->mac_addr[2] = (u8) (val >> 24);
  3366. dev->mac_addr[3] = (u8) (val >> 16);
  3367. dev->mac_addr[4] = (u8) (val >> 8);
  3368. dev->mac_addr[5] = (u8) val;
  3369. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3370. val = CNIC_RD(dev, addr);
  3371. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3372. u16 val16;
  3373. addr = BNX2X_SHMEM_ADDR(base,
  3374. drv_lic_key[port].max_iscsi_init_conn);
  3375. val16 = CNIC_RD16(dev, addr);
  3376. if (val16)
  3377. val16 ^= 0x1e1e;
  3378. dev->max_iscsi_conn = val16;
  3379. }
  3380. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3381. int func = CNIC_FUNC(cp);
  3382. addr = BNX2X_SHMEM_ADDR(base,
  3383. mf_cfg.func_mf_config[func].e1hov_tag);
  3384. val = CNIC_RD(dev, addr);
  3385. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3386. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3387. addr = BNX2X_SHMEM_ADDR(base,
  3388. mf_cfg.func_mf_config[func].config);
  3389. val = CNIC_RD(dev, addr);
  3390. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3391. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3392. dev->max_iscsi_conn = 0;
  3393. }
  3394. }
  3395. }
  3396. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3397. {
  3398. struct cnic_local *cp = dev->cnic_priv;
  3399. int func = CNIC_FUNC(cp), ret, i;
  3400. int port = CNIC_PORT(cp);
  3401. u16 eq_idx;
  3402. u8 sb_id = cp->status_blk_num;
  3403. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3404. cp->iscsi_start_cid);
  3405. if (ret)
  3406. return -ENOMEM;
  3407. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3408. CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
  3409. cp->kcq1.sw_prod_idx = 0;
  3410. cp->kcq1.hw_prod_idx_ptr =
  3411. &cp->status_blk.bnx2x->c_status_block.index_values[
  3412. HC_INDEX_C_ISCSI_EQ_CONS];
  3413. cp->kcq1.status_idx_ptr =
  3414. &cp->status_blk.bnx2x->c_status_block.status_block_index;
  3415. cnic_get_bnx2x_iscsi_info(dev);
  3416. /* Only 1 EQ */
  3417. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3418. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3419. CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
  3420. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3421. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
  3422. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3423. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3424. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
  3425. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3426. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3427. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
  3428. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3429. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3430. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
  3431. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3432. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3433. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
  3434. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3435. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
  3436. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3437. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
  3438. HC_INDEX_C_ISCSI_EQ_CONS);
  3439. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3440. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3441. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
  3442. cp->conn_buf_info.pgtbl[2 * i]);
  3443. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3444. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
  3445. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3446. }
  3447. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3448. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
  3449. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3450. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3451. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
  3452. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3453. cnic_setup_bnx2x_context(dev);
  3454. eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
  3455. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3456. offsetof(struct cstorm_status_block_c,
  3457. index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
  3458. if (eq_idx != 0) {
  3459. netdev_err(dev->netdev, "EQ cons index %x != 0\n", eq_idx);
  3460. return -EBUSY;
  3461. }
  3462. ret = cnic_init_bnx2x_irq(dev);
  3463. if (ret)
  3464. return ret;
  3465. cnic_init_bnx2x_tx_ring(dev);
  3466. cnic_init_bnx2x_rx_ring(dev);
  3467. return 0;
  3468. }
  3469. static void cnic_init_rings(struct cnic_dev *dev)
  3470. {
  3471. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3472. cnic_init_bnx2_tx_ring(dev);
  3473. cnic_init_bnx2_rx_ring(dev);
  3474. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3475. struct cnic_local *cp = dev->cnic_priv;
  3476. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3477. union l5cm_specific_data l5_data;
  3478. struct ustorm_eth_rx_producers rx_prods = {0};
  3479. u32 off, i;
  3480. rx_prods.bd_prod = 0;
  3481. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3482. barrier();
  3483. off = BAR_USTRORM_INTMEM +
  3484. USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
  3485. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3486. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3487. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3488. cnic_init_bnx2x_tx_ring(dev);
  3489. cnic_init_bnx2x_rx_ring(dev);
  3490. l5_data.phy_address.lo = cli;
  3491. l5_data.phy_address.hi = 0;
  3492. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3493. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3494. i = 0;
  3495. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3496. ++i < 10)
  3497. msleep(1);
  3498. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3499. netdev_err(dev->netdev,
  3500. "iSCSI CLIENT_SETUP did not complete\n");
  3501. cnic_kwq_completion(dev, 1);
  3502. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3503. }
  3504. }
  3505. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3506. {
  3507. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3508. cnic_shutdown_bnx2_rx_ring(dev);
  3509. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3510. struct cnic_local *cp = dev->cnic_priv;
  3511. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3512. union l5cm_specific_data l5_data;
  3513. int i;
  3514. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3515. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3516. l5_data.phy_address.lo = cli;
  3517. l5_data.phy_address.hi = 0;
  3518. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3519. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3520. i = 0;
  3521. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3522. ++i < 10)
  3523. msleep(1);
  3524. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3525. netdev_err(dev->netdev,
  3526. "iSCSI CLIENT_HALT did not complete\n");
  3527. cnic_kwq_completion(dev, 1);
  3528. memset(&l5_data, 0, sizeof(l5_data));
  3529. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  3530. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE |
  3531. (1 << SPE_HDR_COMMON_RAMROD_SHIFT), &l5_data);
  3532. msleep(10);
  3533. }
  3534. }
  3535. static int cnic_register_netdev(struct cnic_dev *dev)
  3536. {
  3537. struct cnic_local *cp = dev->cnic_priv;
  3538. struct cnic_eth_dev *ethdev = cp->ethdev;
  3539. int err;
  3540. if (!ethdev)
  3541. return -ENODEV;
  3542. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3543. return 0;
  3544. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3545. if (err)
  3546. netdev_err(dev->netdev, "register_cnic failed\n");
  3547. return err;
  3548. }
  3549. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3550. {
  3551. struct cnic_local *cp = dev->cnic_priv;
  3552. struct cnic_eth_dev *ethdev = cp->ethdev;
  3553. if (!ethdev)
  3554. return;
  3555. ethdev->drv_unregister_cnic(dev->netdev);
  3556. }
  3557. static int cnic_start_hw(struct cnic_dev *dev)
  3558. {
  3559. struct cnic_local *cp = dev->cnic_priv;
  3560. struct cnic_eth_dev *ethdev = cp->ethdev;
  3561. int err;
  3562. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3563. return -EALREADY;
  3564. dev->regview = ethdev->io_base;
  3565. cp->chip_id = ethdev->chip_id;
  3566. pci_dev_get(dev->pcidev);
  3567. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3568. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3569. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3570. err = cp->alloc_resc(dev);
  3571. if (err) {
  3572. netdev_err(dev->netdev, "allocate resource failure\n");
  3573. goto err1;
  3574. }
  3575. err = cp->start_hw(dev);
  3576. if (err)
  3577. goto err1;
  3578. err = cnic_cm_open(dev);
  3579. if (err)
  3580. goto err1;
  3581. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3582. cp->enable_int(dev);
  3583. return 0;
  3584. err1:
  3585. cp->free_resc(dev);
  3586. pci_dev_put(dev->pcidev);
  3587. return err;
  3588. }
  3589. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3590. {
  3591. cnic_disable_bnx2_int_sync(dev);
  3592. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3593. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3594. cnic_init_context(dev, KWQ_CID);
  3595. cnic_init_context(dev, KCQ_CID);
  3596. cnic_setup_5709_context(dev, 0);
  3597. cnic_free_irq(dev);
  3598. cnic_free_resc(dev);
  3599. }
  3600. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3601. {
  3602. struct cnic_local *cp = dev->cnic_priv;
  3603. u8 sb_id = cp->status_blk_num;
  3604. int port = CNIC_PORT(cp);
  3605. cnic_free_irq(dev);
  3606. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3607. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3608. offsetof(struct cstorm_status_block_c,
  3609. index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
  3610. 0);
  3611. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3612. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->func, 0), 0);
  3613. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3614. cnic_free_resc(dev);
  3615. }
  3616. static void cnic_stop_hw(struct cnic_dev *dev)
  3617. {
  3618. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3619. struct cnic_local *cp = dev->cnic_priv;
  3620. int i = 0;
  3621. /* Need to wait for the ring shutdown event to complete
  3622. * before clearing the CNIC_UP flag.
  3623. */
  3624. while (cp->uio_dev != -1 && i < 15) {
  3625. msleep(100);
  3626. i++;
  3627. }
  3628. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3629. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3630. synchronize_rcu();
  3631. cnic_cm_shutdown(dev);
  3632. cp->stop_hw(dev);
  3633. pci_dev_put(dev->pcidev);
  3634. }
  3635. }
  3636. static void cnic_free_dev(struct cnic_dev *dev)
  3637. {
  3638. int i = 0;
  3639. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3640. msleep(100);
  3641. i++;
  3642. }
  3643. if (atomic_read(&dev->ref_count) != 0)
  3644. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3645. netdev_info(dev->netdev, "Removed CNIC device\n");
  3646. dev_put(dev->netdev);
  3647. kfree(dev);
  3648. }
  3649. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3650. struct pci_dev *pdev)
  3651. {
  3652. struct cnic_dev *cdev;
  3653. struct cnic_local *cp;
  3654. int alloc_size;
  3655. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3656. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3657. if (cdev == NULL) {
  3658. netdev_err(dev, "allocate dev struct failure\n");
  3659. return NULL;
  3660. }
  3661. cdev->netdev = dev;
  3662. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3663. cdev->register_device = cnic_register_device;
  3664. cdev->unregister_device = cnic_unregister_device;
  3665. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3666. cp = cdev->cnic_priv;
  3667. cp->dev = cdev;
  3668. cp->uio_dev = -1;
  3669. cp->l2_single_buf_size = 0x400;
  3670. cp->l2_rx_ring_size = 3;
  3671. spin_lock_init(&cp->cnic_ulp_lock);
  3672. netdev_info(dev, "Added CNIC device\n");
  3673. return cdev;
  3674. }
  3675. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3676. {
  3677. struct pci_dev *pdev;
  3678. struct cnic_dev *cdev;
  3679. struct cnic_local *cp;
  3680. struct cnic_eth_dev *ethdev = NULL;
  3681. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3682. probe = symbol_get(bnx2_cnic_probe);
  3683. if (probe) {
  3684. ethdev = (*probe)(dev);
  3685. symbol_put(bnx2_cnic_probe);
  3686. }
  3687. if (!ethdev)
  3688. return NULL;
  3689. pdev = ethdev->pdev;
  3690. if (!pdev)
  3691. return NULL;
  3692. dev_hold(dev);
  3693. pci_dev_get(pdev);
  3694. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3695. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3696. u8 rev;
  3697. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3698. if (rev < 0x10) {
  3699. pci_dev_put(pdev);
  3700. goto cnic_err;
  3701. }
  3702. }
  3703. pci_dev_put(pdev);
  3704. cdev = cnic_alloc_dev(dev, pdev);
  3705. if (cdev == NULL)
  3706. goto cnic_err;
  3707. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3708. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3709. cp = cdev->cnic_priv;
  3710. cp->ethdev = ethdev;
  3711. cdev->pcidev = pdev;
  3712. cp->cnic_ops = &cnic_bnx2_ops;
  3713. cp->start_hw = cnic_start_bnx2_hw;
  3714. cp->stop_hw = cnic_stop_bnx2_hw;
  3715. cp->setup_pgtbl = cnic_setup_page_tbl;
  3716. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3717. cp->free_resc = cnic_free_resc;
  3718. cp->start_cm = cnic_cm_init_bnx2_hw;
  3719. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3720. cp->enable_int = cnic_enable_bnx2_int;
  3721. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3722. cp->close_conn = cnic_close_bnx2_conn;
  3723. cp->next_idx = cnic_bnx2_next_idx;
  3724. cp->hw_idx = cnic_bnx2_hw_idx;
  3725. return cdev;
  3726. cnic_err:
  3727. dev_put(dev);
  3728. return NULL;
  3729. }
  3730. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3731. {
  3732. struct pci_dev *pdev;
  3733. struct cnic_dev *cdev;
  3734. struct cnic_local *cp;
  3735. struct cnic_eth_dev *ethdev = NULL;
  3736. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3737. probe = symbol_get(bnx2x_cnic_probe);
  3738. if (probe) {
  3739. ethdev = (*probe)(dev);
  3740. symbol_put(bnx2x_cnic_probe);
  3741. }
  3742. if (!ethdev)
  3743. return NULL;
  3744. pdev = ethdev->pdev;
  3745. if (!pdev)
  3746. return NULL;
  3747. dev_hold(dev);
  3748. cdev = cnic_alloc_dev(dev, pdev);
  3749. if (cdev == NULL) {
  3750. dev_put(dev);
  3751. return NULL;
  3752. }
  3753. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3754. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3755. cp = cdev->cnic_priv;
  3756. cp->ethdev = ethdev;
  3757. cdev->pcidev = pdev;
  3758. cp->cnic_ops = &cnic_bnx2x_ops;
  3759. cp->start_hw = cnic_start_bnx2x_hw;
  3760. cp->stop_hw = cnic_stop_bnx2x_hw;
  3761. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3762. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3763. cp->free_resc = cnic_free_resc;
  3764. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3765. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3766. cp->enable_int = cnic_enable_bnx2x_int;
  3767. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3768. cp->ack_int = cnic_ack_bnx2x_msix;
  3769. cp->close_conn = cnic_close_bnx2x_conn;
  3770. cp->next_idx = cnic_bnx2x_next_idx;
  3771. cp->hw_idx = cnic_bnx2x_hw_idx;
  3772. return cdev;
  3773. }
  3774. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3775. {
  3776. struct ethtool_drvinfo drvinfo;
  3777. struct cnic_dev *cdev = NULL;
  3778. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3779. memset(&drvinfo, 0, sizeof(drvinfo));
  3780. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3781. if (!strcmp(drvinfo.driver, "bnx2"))
  3782. cdev = init_bnx2_cnic(dev);
  3783. if (!strcmp(drvinfo.driver, "bnx2x"))
  3784. cdev = init_bnx2x_cnic(dev);
  3785. if (cdev) {
  3786. write_lock(&cnic_dev_lock);
  3787. list_add(&cdev->list, &cnic_dev_list);
  3788. write_unlock(&cnic_dev_lock);
  3789. }
  3790. }
  3791. return cdev;
  3792. }
  3793. /**
  3794. * netdev event handler
  3795. */
  3796. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3797. void *ptr)
  3798. {
  3799. struct net_device *netdev = ptr;
  3800. struct cnic_dev *dev;
  3801. int if_type;
  3802. int new_dev = 0;
  3803. dev = cnic_from_netdev(netdev);
  3804. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3805. /* Check for the hot-plug device */
  3806. dev = is_cnic_dev(netdev);
  3807. if (dev) {
  3808. new_dev = 1;
  3809. cnic_hold(dev);
  3810. }
  3811. }
  3812. if (dev) {
  3813. struct cnic_local *cp = dev->cnic_priv;
  3814. if (new_dev)
  3815. cnic_ulp_init(dev);
  3816. else if (event == NETDEV_UNREGISTER)
  3817. cnic_ulp_exit(dev);
  3818. if (event == NETDEV_UP) {
  3819. if (cnic_register_netdev(dev) != 0) {
  3820. cnic_put(dev);
  3821. goto done;
  3822. }
  3823. if (!cnic_start_hw(dev))
  3824. cnic_ulp_start(dev);
  3825. }
  3826. rcu_read_lock();
  3827. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3828. struct cnic_ulp_ops *ulp_ops;
  3829. void *ctx;
  3830. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3831. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3832. continue;
  3833. ctx = cp->ulp_handle[if_type];
  3834. ulp_ops->indicate_netevent(ctx, event);
  3835. }
  3836. rcu_read_unlock();
  3837. if (event == NETDEV_GOING_DOWN) {
  3838. cnic_ulp_stop(dev);
  3839. cnic_stop_hw(dev);
  3840. cnic_unregister_netdev(dev);
  3841. } else if (event == NETDEV_UNREGISTER) {
  3842. write_lock(&cnic_dev_lock);
  3843. list_del_init(&dev->list);
  3844. write_unlock(&cnic_dev_lock);
  3845. cnic_put(dev);
  3846. cnic_free_dev(dev);
  3847. goto done;
  3848. }
  3849. cnic_put(dev);
  3850. }
  3851. done:
  3852. return NOTIFY_DONE;
  3853. }
  3854. static struct notifier_block cnic_netdev_notifier = {
  3855. .notifier_call = cnic_netdev_event
  3856. };
  3857. static void cnic_release(void)
  3858. {
  3859. struct cnic_dev *dev;
  3860. while (!list_empty(&cnic_dev_list)) {
  3861. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3862. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3863. cnic_ulp_stop(dev);
  3864. cnic_stop_hw(dev);
  3865. }
  3866. cnic_ulp_exit(dev);
  3867. cnic_unregister_netdev(dev);
  3868. list_del_init(&dev->list);
  3869. cnic_free_dev(dev);
  3870. }
  3871. }
  3872. static int __init cnic_init(void)
  3873. {
  3874. int rc = 0;
  3875. pr_info("%s", version);
  3876. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3877. if (rc) {
  3878. cnic_release();
  3879. return rc;
  3880. }
  3881. return 0;
  3882. }
  3883. static void __exit cnic_exit(void)
  3884. {
  3885. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3886. cnic_release();
  3887. }
  3888. module_init(cnic_init);
  3889. module_exit(cnic_exit);