s3c2410_wdt.c 13 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@redhat.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. * Changelog:
  26. * 05-Oct-2004 BJD Added semaphore init to stop crashes on open
  27. * Fixed tmr_count / wdt_count confusion
  28. * Added configurable debug
  29. *
  30. * 11-Jan-2005 BJD Fixed divide-by-2 in timeout code
  31. *
  32. * 25-Jan-2005 DA Added suspend/resume support
  33. * Replaced reboot notifier with .shutdown method
  34. *
  35. * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
  36. */
  37. #include <linux/module.h>
  38. #include <linux/moduleparam.h>
  39. #include <linux/types.h>
  40. #include <linux/timer.h>
  41. #include <linux/miscdevice.h>
  42. #include <linux/watchdog.h>
  43. #include <linux/fs.h>
  44. #include <linux/init.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/clk.h>
  48. #include <linux/uaccess.h>
  49. #include <linux/io.h>
  50. #include <asm/arch/map.h>
  51. #undef S3C_VA_WATCHDOG
  52. #define S3C_VA_WATCHDOG (0)
  53. #include <asm/plat-s3c/regs-watchdog.h>
  54. #define PFX "s3c2410-wdt: "
  55. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  56. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  57. static int nowayout = WATCHDOG_NOWAYOUT;
  58. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  59. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  60. static int soft_noboot;
  61. static int debug;
  62. module_param(tmr_margin, int, 0);
  63. module_param(tmr_atboot, int, 0);
  64. module_param(nowayout, int, 0);
  65. module_param(soft_noboot, int, 0);
  66. module_param(debug, int, 0);
  67. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
  68. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  69. MODULE_PARM_DESC(tmr_atboot,
  70. "Watchdog is started at boot time if set to 1, default="
  71. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  72. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  73. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  74. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default depends on ONLY_TESTING)");
  75. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
  76. typedef enum close_state {
  77. CLOSE_STATE_NOT,
  78. CLOSE_STATE_ALLOW = 0x4021
  79. } close_state_t;
  80. static unsigned long open_lock;
  81. static struct device *wdt_dev; /* platform device attached to */
  82. static struct resource *wdt_mem;
  83. static struct resource *wdt_irq;
  84. static struct clk *wdt_clock;
  85. static void __iomem *wdt_base;
  86. static unsigned int wdt_count;
  87. static close_state_t allow_close;
  88. static DEFINE_SPINLOCK(wdt_lock);
  89. /* watchdog control routines */
  90. #define DBG(msg...) do { \
  91. if (debug) \
  92. printk(KERN_INFO msg); \
  93. } while (0)
  94. /* functions */
  95. static void s3c2410wdt_keepalive(void)
  96. {
  97. spin_lock(&wdt_lock);
  98. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  99. spin_unlock(&wdt_lock);
  100. }
  101. static void __s3c2410wdt_stop(void)
  102. {
  103. unsigned long wtcon;
  104. wtcon = readl(wdt_base + S3C2410_WTCON);
  105. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  106. writel(wtcon, wdt_base + S3C2410_WTCON);
  107. }
  108. static void s3c2410wdt_stop(void)
  109. {
  110. spin_lock(&wdt_lock);
  111. __s3c2410wdt_stop();
  112. spin_unlock(&wdt_lock);
  113. }
  114. static void s3c2410wdt_start(void)
  115. {
  116. unsigned long wtcon;
  117. spin_lock(&wdt_lock);
  118. __s3c2410wdt_stop();
  119. wtcon = readl(wdt_base + S3C2410_WTCON);
  120. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  121. if (soft_noboot) {
  122. wtcon |= S3C2410_WTCON_INTEN;
  123. wtcon &= ~S3C2410_WTCON_RSTEN;
  124. } else {
  125. wtcon &= ~S3C2410_WTCON_INTEN;
  126. wtcon |= S3C2410_WTCON_RSTEN;
  127. }
  128. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  129. __func__, wdt_count, wtcon);
  130. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  131. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  132. writel(wtcon, wdt_base + S3C2410_WTCON);
  133. spin_unlock(&wdt_lock);
  134. return 0;
  135. }
  136. static int s3c2410wdt_set_heartbeat(int timeout)
  137. {
  138. unsigned int freq = clk_get_rate(wdt_clock);
  139. unsigned int count;
  140. unsigned int divisor = 1;
  141. unsigned long wtcon;
  142. if (timeout < 1)
  143. return -EINVAL;
  144. freq /= 128;
  145. count = timeout * freq;
  146. DBG("%s: count=%d, timeout=%d, freq=%d\n",
  147. __func__, count, timeout, freq);
  148. /* if the count is bigger than the watchdog register,
  149. then work out what we need to do (and if) we can
  150. actually make this value
  151. */
  152. if (count >= 0x10000) {
  153. for (divisor = 1; divisor <= 0x100; divisor++) {
  154. if ((count / divisor) < 0x10000)
  155. break;
  156. }
  157. if ((count / divisor) >= 0x10000) {
  158. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  159. return -EINVAL;
  160. }
  161. }
  162. tmr_margin = timeout;
  163. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  164. __func__, timeout, divisor, count, count/divisor);
  165. count /= divisor;
  166. wdt_count = count;
  167. /* update the pre-scaler */
  168. wtcon = readl(wdt_base + S3C2410_WTCON);
  169. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  170. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  171. writel(count, wdt_base + S3C2410_WTDAT);
  172. writel(wtcon, wdt_base + S3C2410_WTCON);
  173. return 0;
  174. }
  175. /*
  176. * /dev/watchdog handling
  177. */
  178. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  179. {
  180. if (test_and_set_bit(0, &open_lock))
  181. return -EBUSY;
  182. if (nowayout)
  183. __module_get(THIS_MODULE);
  184. allow_close = CLOSE_STATE_NOT;
  185. /* start the timer */
  186. s3c2410wdt_start();
  187. return nonseekable_open(inode, file);
  188. }
  189. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  190. {
  191. /*
  192. * Shut off the timer.
  193. * Lock it in if it's a module and we set nowayout
  194. */
  195. if (allow_close == CLOSE_STATE_ALLOW)
  196. s3c2410wdt_stop();
  197. else {
  198. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  199. s3c2410wdt_keepalive();
  200. }
  201. allow_close = CLOSE_STATE_NOT;
  202. clear_bit(0, &open_lock);
  203. return 0;
  204. }
  205. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  206. size_t len, loff_t *ppos)
  207. {
  208. /*
  209. * Refresh the timer.
  210. */
  211. if (len) {
  212. if (!nowayout) {
  213. size_t i;
  214. /* In case it was set long ago */
  215. allow_close = CLOSE_STATE_NOT;
  216. for (i = 0; i != len; i++) {
  217. char c;
  218. if (get_user(c, data + i))
  219. return -EFAULT;
  220. if (c == 'V')
  221. allow_close = CLOSE_STATE_ALLOW;
  222. }
  223. }
  224. s3c2410wdt_keepalive();
  225. }
  226. return len;
  227. }
  228. #define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE
  229. static const struct watchdog_info s3c2410_wdt_ident = {
  230. .options = OPTIONS,
  231. .firmware_version = 0,
  232. .identity = "S3C2410 Watchdog",
  233. };
  234. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  235. unsigned long arg)
  236. {
  237. void __user *argp = (void __user *)arg;
  238. int __user *p = argp;
  239. int new_margin;
  240. switch (cmd) {
  241. case WDIOC_GETSUPPORT:
  242. return copy_to_user(argp, &s3c2410_wdt_ident,
  243. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  244. case WDIOC_GETSTATUS:
  245. case WDIOC_GETBOOTSTATUS:
  246. return put_user(0, p);
  247. case WDIOC_KEEPALIVE:
  248. s3c2410wdt_keepalive();
  249. return 0;
  250. case WDIOC_SETTIMEOUT:
  251. if (get_user(new_margin, p))
  252. return -EFAULT;
  253. if (s3c2410wdt_set_heartbeat(new_margin))
  254. return -EINVAL;
  255. s3c2410wdt_keepalive();
  256. return put_user(tmr_margin, p);
  257. case WDIOC_GETTIMEOUT:
  258. return put_user(tmr_margin, p);
  259. default:
  260. return -ENOTTY;
  261. }
  262. }
  263. /* kernel interface */
  264. static const struct file_operations s3c2410wdt_fops = {
  265. .owner = THIS_MODULE,
  266. .llseek = no_llseek,
  267. .write = s3c2410wdt_write,
  268. .unlocked_ioctl = s3c2410wdt_ioctl,
  269. .open = s3c2410wdt_open,
  270. .release = s3c2410wdt_release,
  271. };
  272. static struct miscdevice s3c2410wdt_miscdev = {
  273. .minor = WATCHDOG_MINOR,
  274. .name = "watchdog",
  275. .fops = &s3c2410wdt_fops,
  276. };
  277. /* interrupt handler code */
  278. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  279. {
  280. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  281. s3c2410wdt_keepalive();
  282. return IRQ_HANDLED;
  283. }
  284. /* device interface */
  285. static int s3c2410wdt_probe(struct platform_device *pdev)
  286. {
  287. struct resource *res;
  288. struct device *dev;
  289. unsigned int wtcon;
  290. int started = 0;
  291. int ret;
  292. int size;
  293. DBG("%s: probe=%p\n", __func__, pdev);
  294. dev = &pdev->dev;
  295. wdt_dev = &pdev->dev;
  296. /* get the memory region for the watchdog timer */
  297. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  298. if (res == NULL) {
  299. dev_err(dev, "no memory resource specified\n");
  300. return -ENOENT;
  301. }
  302. size = (res->end-res->start)+1;
  303. wdt_mem = request_mem_region(res->start, size, pdev->name);
  304. if (wdt_mem == NULL) {
  305. dev_err(dev, "failed to get memory region\n");
  306. ret = -ENOENT;
  307. goto err_req;
  308. }
  309. wdt_base = ioremap(res->start, size);
  310. if (wdt_base == 0) {
  311. dev_err(dev, "failed to ioremap() region\n");
  312. ret = -EINVAL;
  313. goto err_req;
  314. }
  315. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  316. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  317. if (wdt_irq == NULL) {
  318. dev_err(dev, "no irq resource specified\n");
  319. ret = -ENOENT;
  320. goto err_map;
  321. }
  322. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  323. if (ret != 0) {
  324. dev_err(dev, "failed to install irq (%d)\n", ret);
  325. goto err_map;
  326. }
  327. wdt_clock = clk_get(&pdev->dev, "watchdog");
  328. if (IS_ERR(wdt_clock)) {
  329. dev_err(dev, "failed to find watchdog clock source\n");
  330. ret = PTR_ERR(wdt_clock);
  331. goto err_irq;
  332. }
  333. clk_enable(wdt_clock);
  334. /* see if we can actually set the requested timer margin, and if
  335. * not, try the default value */
  336. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  337. started = s3c2410wdt_set_heartbeat(
  338. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  339. if (started == 0)
  340. dev_info(dev,
  341. "tmr_margin value out of range, default %d used\n",
  342. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  343. else
  344. dev_info(dev, "default timer value is out of range, cannot start\n");
  345. }
  346. ret = misc_register(&s3c2410wdt_miscdev);
  347. if (ret) {
  348. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  349. WATCHDOG_MINOR, ret);
  350. goto err_clk;
  351. }
  352. if (tmr_atboot && started == 0) {
  353. dev_info(dev, "starting watchdog timer\n");
  354. s3c2410wdt_start();
  355. } else if (!tmr_atboot) {
  356. /* if we're not enabling the watchdog, then ensure it is
  357. * disabled if it has been left running from the bootloader
  358. * or other source */
  359. s3c2410wdt_stop();
  360. }
  361. /* print out a statement of readiness */
  362. wtcon = readl(wdt_base + S3C2410_WTCON);
  363. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  364. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  365. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  366. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  367. return 0;
  368. err_clk:
  369. clk_disable(wdt_clock);
  370. clk_put(wdt_clock);
  371. err_irq:
  372. free_irq(wdt_irq->start, pdev);
  373. err_map:
  374. iounmap(wdt_base);
  375. err_req:
  376. release_resource(wdt_mem);
  377. kfree(wdt_mem);
  378. return ret;
  379. }
  380. static int s3c2410wdt_remove(struct platform_device *dev)
  381. {
  382. release_resource(wdt_mem);
  383. kfree(wdt_mem);
  384. wdt_mem = NULL;
  385. free_irq(wdt_irq->start, dev);
  386. wdt_irq = NULL;
  387. clk_disable(wdt_clock);
  388. clk_put(wdt_clock);
  389. wdt_clock = NULL;
  390. iounmap(wdt_base);
  391. misc_deregister(&s3c2410wdt_miscdev);
  392. return 0;
  393. }
  394. static void s3c2410wdt_shutdown(struct platform_device *dev)
  395. {
  396. s3c2410wdt_stop();
  397. }
  398. #ifdef CONFIG_PM
  399. static unsigned long wtcon_save;
  400. static unsigned long wtdat_save;
  401. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  402. {
  403. /* Save watchdog state, and turn it off. */
  404. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  405. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  406. /* Note that WTCNT doesn't need to be saved. */
  407. s3c2410wdt_stop();
  408. return 0;
  409. }
  410. static int s3c2410wdt_resume(struct platform_device *dev)
  411. {
  412. /* Restore watchdog state. */
  413. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  414. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  415. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  416. printk(KERN_INFO PFX "watchdog %sabled\n",
  417. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  418. return 0;
  419. }
  420. #else
  421. #define s3c2410wdt_suspend NULL
  422. #define s3c2410wdt_resume NULL
  423. #endif /* CONFIG_PM */
  424. static struct platform_driver s3c2410wdt_driver = {
  425. .probe = s3c2410wdt_probe,
  426. .remove = s3c2410wdt_remove,
  427. .shutdown = s3c2410wdt_shutdown,
  428. .suspend = s3c2410wdt_suspend,
  429. .resume = s3c2410wdt_resume,
  430. .driver = {
  431. .owner = THIS_MODULE,
  432. .name = "s3c2410-wdt",
  433. },
  434. };
  435. static char banner[] __initdata =
  436. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  437. static int __init watchdog_init(void)
  438. {
  439. printk(banner);
  440. return platform_driver_register(&s3c2410wdt_driver);
  441. }
  442. static void __exit watchdog_exit(void)
  443. {
  444. platform_driver_unregister(&s3c2410wdt_driver);
  445. }
  446. module_init(watchdog_init);
  447. module_exit(watchdog_exit);
  448. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  449. "Dimitry Andric <dimitry.andric@tomtom.com>");
  450. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  451. MODULE_LICENSE("GPL");
  452. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  453. MODULE_ALIAS("platform:s3c2410-wdt");