netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. if (recv_ctx->rds_rings == NULL)
  163. goto skip_rds;
  164. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  165. rds_ring = &recv_ctx->rds_rings[ring];
  166. vfree(rds_ring->rx_buf_arr);
  167. rds_ring->rx_buf_arr = NULL;
  168. }
  169. kfree(recv_ctx->rds_rings);
  170. skip_rds:
  171. if (recv_ctx->sds_rings == NULL)
  172. goto skip_sds;
  173. for(ring = 0; ring < adapter->max_sds_rings; ring++)
  174. recv_ctx->sds_rings[ring].consumer = 0;
  175. skip_sds:
  176. if (adapter->tx_ring == NULL)
  177. return;
  178. tx_ring = adapter->tx_ring;
  179. vfree(tx_ring->cmd_buf_arr);
  180. }
  181. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  182. {
  183. struct netxen_recv_context *recv_ctx;
  184. struct nx_host_rds_ring *rds_ring;
  185. struct nx_host_sds_ring *sds_ring;
  186. struct nx_host_tx_ring *tx_ring;
  187. struct netxen_rx_buffer *rx_buf;
  188. int ring, i, size;
  189. struct netxen_cmd_buffer *cmd_buf_arr;
  190. struct net_device *netdev = adapter->netdev;
  191. struct pci_dev *pdev = adapter->pdev;
  192. size = sizeof(struct nx_host_tx_ring);
  193. tx_ring = kzalloc(size, GFP_KERNEL);
  194. if (tx_ring == NULL) {
  195. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  196. netdev->name);
  197. return -ENOMEM;
  198. }
  199. adapter->tx_ring = tx_ring;
  200. tx_ring->num_desc = adapter->num_txd;
  201. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  202. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  203. if (cmd_buf_arr == NULL) {
  204. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  205. netdev->name);
  206. return -ENOMEM;
  207. }
  208. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  209. tx_ring->cmd_buf_arr = cmd_buf_arr;
  210. recv_ctx = &adapter->recv_ctx;
  211. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  212. rds_ring = kzalloc(size, GFP_KERNEL);
  213. if (rds_ring == NULL) {
  214. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  215. netdev->name);
  216. return -ENOMEM;
  217. }
  218. recv_ctx->rds_rings = rds_ring;
  219. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  220. rds_ring = &recv_ctx->rds_rings[ring];
  221. switch (ring) {
  222. case RCV_RING_NORMAL:
  223. rds_ring->num_desc = adapter->num_rxd;
  224. if (adapter->ahw.cut_through) {
  225. rds_ring->dma_size =
  226. NX_CT_DEFAULT_RX_BUF_LEN;
  227. rds_ring->skb_size =
  228. NX_CT_DEFAULT_RX_BUF_LEN;
  229. } else {
  230. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  231. rds_ring->dma_size =
  232. NX_P3_RX_BUF_MAX_LEN;
  233. else
  234. rds_ring->dma_size =
  235. NX_P2_RX_BUF_MAX_LEN;
  236. rds_ring->skb_size =
  237. rds_ring->dma_size + NET_IP_ALIGN;
  238. }
  239. break;
  240. case RCV_RING_JUMBO:
  241. rds_ring->num_desc = adapter->num_jumbo_rxd;
  242. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  243. rds_ring->dma_size =
  244. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  245. else
  246. rds_ring->dma_size =
  247. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  248. rds_ring->skb_size =
  249. rds_ring->dma_size + NET_IP_ALIGN;
  250. break;
  251. case RCV_RING_LRO:
  252. rds_ring->num_desc = adapter->num_lro_rxd;
  253. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  254. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  255. break;
  256. }
  257. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  258. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  259. if (rds_ring->rx_buf_arr == NULL) {
  260. printk(KERN_ERR "%s: Failed to allocate "
  261. "rx buffer ring %d\n",
  262. netdev->name, ring);
  263. /* free whatever was already allocated */
  264. goto err_out;
  265. }
  266. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  267. INIT_LIST_HEAD(&rds_ring->free_list);
  268. /*
  269. * Now go through all of them, set reference handles
  270. * and put them in the queues.
  271. */
  272. rx_buf = rds_ring->rx_buf_arr;
  273. for (i = 0; i < rds_ring->num_desc; i++) {
  274. list_add_tail(&rx_buf->list,
  275. &rds_ring->free_list);
  276. rx_buf->ref_handle = i;
  277. rx_buf->state = NETXEN_BUFFER_FREE;
  278. rx_buf++;
  279. }
  280. spin_lock_init(&rds_ring->lock);
  281. }
  282. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  283. sds_ring = &recv_ctx->sds_rings[ring];
  284. sds_ring->irq = adapter->msix_entries[ring].vector;
  285. sds_ring->adapter = adapter;
  286. sds_ring->num_desc = adapter->num_rxd;
  287. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  288. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  289. }
  290. return 0;
  291. err_out:
  292. netxen_free_sw_resources(adapter);
  293. return -ENOMEM;
  294. }
  295. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  296. {
  297. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  298. adapter->set_multi = netxen_p2_nic_set_multi;
  299. switch (adapter->ahw.port_type) {
  300. case NETXEN_NIC_GBE:
  301. adapter->enable_phy_interrupts =
  302. netxen_niu_gbe_enable_phy_interrupts;
  303. adapter->disable_phy_interrupts =
  304. netxen_niu_gbe_disable_phy_interrupts;
  305. adapter->set_mtu = netxen_nic_set_mtu_gb;
  306. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  307. adapter->phy_read = netxen_niu_gbe_phy_read;
  308. adapter->phy_write = netxen_niu_gbe_phy_write;
  309. adapter->init_port = netxen_niu_gbe_init_port;
  310. adapter->stop_port = netxen_niu_disable_gbe_port;
  311. break;
  312. case NETXEN_NIC_XGBE:
  313. adapter->enable_phy_interrupts =
  314. netxen_niu_xgbe_enable_phy_interrupts;
  315. adapter->disable_phy_interrupts =
  316. netxen_niu_xgbe_disable_phy_interrupts;
  317. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  318. adapter->init_port = netxen_niu_xg_init_port;
  319. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  320. adapter->stop_port = netxen_niu_disable_xg_port;
  321. break;
  322. default:
  323. break;
  324. }
  325. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  326. adapter->set_mtu = nx_fw_cmd_set_mtu;
  327. adapter->set_promisc = netxen_p3_nic_set_promisc;
  328. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  329. adapter->set_multi = netxen_p3_nic_set_multi;
  330. }
  331. }
  332. /*
  333. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  334. * address to external PCI CRB address.
  335. */
  336. static u32 netxen_decode_crb_addr(u32 addr)
  337. {
  338. int i;
  339. u32 base_addr, offset, pci_base;
  340. crb_addr_transform_setup();
  341. pci_base = NETXEN_ADDR_ERROR;
  342. base_addr = addr & 0xfff00000;
  343. offset = addr & 0x000fffff;
  344. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  345. if (crb_addr_xform[i] == base_addr) {
  346. pci_base = i << 20;
  347. break;
  348. }
  349. }
  350. if (pci_base == NETXEN_ADDR_ERROR)
  351. return pci_base;
  352. else
  353. return (pci_base + offset);
  354. }
  355. static long rom_max_timeout = 100;
  356. static long rom_lock_timeout = 10000;
  357. static int rom_lock(struct netxen_adapter *adapter)
  358. {
  359. int iter;
  360. u32 done = 0;
  361. int timeout = 0;
  362. while (!done) {
  363. /* acquire semaphore2 from PCI HW block */
  364. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  365. if (done == 1)
  366. break;
  367. if (timeout >= rom_lock_timeout)
  368. return -EIO;
  369. timeout++;
  370. /*
  371. * Yield CPU
  372. */
  373. if (!in_atomic())
  374. schedule();
  375. else {
  376. for (iter = 0; iter < 20; iter++)
  377. cpu_relax(); /*This a nop instr on i386 */
  378. }
  379. }
  380. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  381. return 0;
  382. }
  383. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  384. {
  385. long timeout = 0;
  386. long done = 0;
  387. cond_resched();
  388. while (done == 0) {
  389. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  390. done &= 2;
  391. timeout++;
  392. if (timeout >= rom_max_timeout) {
  393. printk("Timeout reached waiting for rom done");
  394. return -EIO;
  395. }
  396. }
  397. return 0;
  398. }
  399. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  400. {
  401. /* release semaphore2 */
  402. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  403. }
  404. static int do_rom_fast_read(struct netxen_adapter *adapter,
  405. int addr, int *valp)
  406. {
  407. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  408. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  409. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  410. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  411. if (netxen_wait_rom_done(adapter)) {
  412. printk("Error waiting for rom done\n");
  413. return -EIO;
  414. }
  415. /* reset abyte_cnt and dummy_byte_cnt */
  416. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  417. udelay(10);
  418. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  419. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  420. return 0;
  421. }
  422. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  423. u8 *bytes, size_t size)
  424. {
  425. int addridx;
  426. int ret = 0;
  427. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  428. int v;
  429. ret = do_rom_fast_read(adapter, addridx, &v);
  430. if (ret != 0)
  431. break;
  432. *(__le32 *)bytes = cpu_to_le32(v);
  433. bytes += 4;
  434. }
  435. return ret;
  436. }
  437. int
  438. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  439. u8 *bytes, size_t size)
  440. {
  441. int ret;
  442. ret = rom_lock(adapter);
  443. if (ret < 0)
  444. return ret;
  445. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  446. netxen_rom_unlock(adapter);
  447. return ret;
  448. }
  449. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  450. {
  451. int ret;
  452. if (rom_lock(adapter) != 0)
  453. return -EIO;
  454. ret = do_rom_fast_read(adapter, addr, valp);
  455. netxen_rom_unlock(adapter);
  456. return ret;
  457. }
  458. #define NETXEN_BOARDTYPE 0x4008
  459. #define NETXEN_BOARDNUM 0x400c
  460. #define NETXEN_CHIPNUM 0x4010
  461. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  462. {
  463. int addr, val;
  464. int i, n, init_delay = 0;
  465. struct crb_addr_pair *buf;
  466. unsigned offset;
  467. u32 off;
  468. /* resetall */
  469. rom_lock(adapter);
  470. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  471. netxen_rom_unlock(adapter);
  472. if (verbose) {
  473. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  474. printk("P2 ROM board type: 0x%08x\n", val);
  475. else
  476. printk("Could not read board type\n");
  477. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  478. printk("P2 ROM board num: 0x%08x\n", val);
  479. else
  480. printk("Could not read board number\n");
  481. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  482. printk("P2 ROM chip num: 0x%08x\n", val);
  483. else
  484. printk("Could not read chip number\n");
  485. }
  486. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  487. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  488. (n != 0xcafecafe) ||
  489. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  490. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  491. "n: %08x\n", netxen_nic_driver_name, n);
  492. return -EIO;
  493. }
  494. offset = n & 0xffffU;
  495. n = (n >> 16) & 0xffffU;
  496. } else {
  497. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  498. !(n & 0x80000000)) {
  499. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  500. "n: %08x\n", netxen_nic_driver_name, n);
  501. return -EIO;
  502. }
  503. offset = 1;
  504. n &= ~0x80000000;
  505. }
  506. if (n < 1024) {
  507. if (verbose)
  508. printk(KERN_DEBUG "%s: %d CRB init values found"
  509. " in ROM.\n", netxen_nic_driver_name, n);
  510. } else {
  511. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  512. " initialized.\n", __func__, n);
  513. return -EIO;
  514. }
  515. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  516. if (buf == NULL) {
  517. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  518. netxen_nic_driver_name);
  519. return -ENOMEM;
  520. }
  521. for (i = 0; i < n; i++) {
  522. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  523. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  524. kfree(buf);
  525. return -EIO;
  526. }
  527. buf[i].addr = addr;
  528. buf[i].data = val;
  529. if (verbose)
  530. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  531. netxen_nic_driver_name,
  532. (u32)netxen_decode_crb_addr(addr), val);
  533. }
  534. for (i = 0; i < n; i++) {
  535. off = netxen_decode_crb_addr(buf[i].addr);
  536. if (off == NETXEN_ADDR_ERROR) {
  537. printk(KERN_ERR"CRB init value out of range %x\n",
  538. buf[i].addr);
  539. continue;
  540. }
  541. off += NETXEN_PCI_CRBSPACE;
  542. /* skipping cold reboot MAGIC */
  543. if (off == NETXEN_CAM_RAM(0x1fc))
  544. continue;
  545. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  546. /* do not reset PCI */
  547. if (off == (ROMUSB_GLB + 0xbc))
  548. continue;
  549. if (off == (ROMUSB_GLB + 0xa8))
  550. continue;
  551. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  552. continue;
  553. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  554. continue;
  555. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  556. continue;
  557. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  558. buf[i].data = 0x1020;
  559. /* skip the function enable register */
  560. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  561. continue;
  562. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  563. continue;
  564. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  565. continue;
  566. }
  567. if (off == NETXEN_ADDR_ERROR) {
  568. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  569. netxen_nic_driver_name, buf[i].addr);
  570. continue;
  571. }
  572. init_delay = 1;
  573. /* After writing this register, HW needs time for CRB */
  574. /* to quiet down (else crb_window returns 0xffffffff) */
  575. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  576. init_delay = 1000;
  577. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  578. /* hold xdma in reset also */
  579. buf[i].data = NETXEN_NIC_XDMA_RESET;
  580. buf[i].data = 0x8000ff;
  581. }
  582. }
  583. NXWR32(adapter, off, buf[i].data);
  584. msleep(init_delay);
  585. }
  586. kfree(buf);
  587. /* disable_peg_cache_all */
  588. /* unreset_net_cache */
  589. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  590. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  591. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  592. }
  593. /* p2dn replyCount */
  594. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  595. /* disable_peg_cache 0 */
  596. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  597. /* disable_peg_cache 1 */
  598. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  599. /* peg_clr_all */
  600. /* peg_clr 0 */
  601. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  602. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  603. /* peg_clr 1 */
  604. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  605. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  606. /* peg_clr 2 */
  607. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  608. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  609. /* peg_clr 3 */
  610. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  611. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  612. return 0;
  613. }
  614. int
  615. netxen_need_fw_reset(struct netxen_adapter *adapter)
  616. {
  617. u32 count, old_count;
  618. u32 val, version, major, minor, build;
  619. int i, timeout;
  620. u8 fw_type;
  621. /* NX2031 firmware doesn't support heartbit */
  622. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  623. return 1;
  624. /* last attempt had failed */
  625. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  626. return 1;
  627. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  628. for (i = 0; i < 10; i++) {
  629. timeout = msleep_interruptible(200);
  630. if (timeout) {
  631. NXWR32(adapter, CRB_CMDPEG_STATE,
  632. PHAN_INITIALIZE_FAILED);
  633. return -EINTR;
  634. }
  635. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  636. if (count != old_count)
  637. break;
  638. }
  639. /* firmware is dead */
  640. if (count == old_count)
  641. return 1;
  642. /* check if we have got newer or different file firmware */
  643. if (adapter->fw) {
  644. const struct firmware *fw = adapter->fw;
  645. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  646. version = NETXEN_DECODE_VERSION(val);
  647. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  648. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  649. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  650. if (version > NETXEN_VERSION_CODE(major, minor, build))
  651. return 1;
  652. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  653. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  654. fw_type = (val & 0x4) ?
  655. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  656. if (adapter->fw_type != fw_type)
  657. return 1;
  658. }
  659. }
  660. return 0;
  661. }
  662. static char *fw_name[] = {
  663. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  664. };
  665. int
  666. netxen_load_firmware(struct netxen_adapter *adapter)
  667. {
  668. u64 *ptr64;
  669. u32 i, flashaddr, size;
  670. const struct firmware *fw = adapter->fw;
  671. struct pci_dev *pdev = adapter->pdev;
  672. dev_info(&pdev->dev, "loading firmware from %s\n",
  673. fw_name[adapter->fw_type]);
  674. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  675. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  676. if (fw) {
  677. __le64 data;
  678. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  679. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  680. flashaddr = NETXEN_BOOTLD_START;
  681. for (i = 0; i < size; i++) {
  682. data = cpu_to_le64(ptr64[i]);
  683. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  684. flashaddr += 8;
  685. }
  686. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  687. size = (__force u32)cpu_to_le32(size) / 8;
  688. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  689. flashaddr = NETXEN_IMAGE_START;
  690. for (i = 0; i < size; i++) {
  691. data = cpu_to_le64(ptr64[i]);
  692. if (adapter->pci_mem_write(adapter,
  693. flashaddr, &data, 8))
  694. return -EIO;
  695. flashaddr += 8;
  696. }
  697. } else {
  698. u32 data;
  699. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  700. flashaddr = NETXEN_BOOTLD_START;
  701. for (i = 0; i < size; i++) {
  702. if (netxen_rom_fast_read(adapter,
  703. flashaddr, (int *)&data) != 0)
  704. return -EIO;
  705. if (adapter->pci_mem_write(adapter,
  706. flashaddr, &data, 4))
  707. return -EIO;
  708. flashaddr += 4;
  709. }
  710. }
  711. msleep(1);
  712. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  713. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  714. else {
  715. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  716. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  717. }
  718. return 0;
  719. }
  720. static int
  721. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  722. {
  723. __le32 val;
  724. u32 ver, min_ver, bios;
  725. struct pci_dev *pdev = adapter->pdev;
  726. const struct firmware *fw = adapter->fw;
  727. if (fw->size < NX_FW_MIN_SIZE)
  728. return -EINVAL;
  729. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  730. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  731. return -EINVAL;
  732. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  733. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  734. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  735. else
  736. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  737. ver = NETXEN_DECODE_VERSION(val);
  738. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  739. dev_err(&pdev->dev,
  740. "%s: firmware version %d.%d.%d unsupported\n",
  741. fwname, _major(ver), _minor(ver), _build(ver));
  742. return -EINVAL;
  743. }
  744. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  745. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  746. if ((__force u32)val != bios) {
  747. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  748. fwname);
  749. return -EINVAL;
  750. }
  751. /* check if flashed firmware is newer */
  752. if (netxen_rom_fast_read(adapter,
  753. NX_FW_VERSION_OFFSET, (int *)&val))
  754. return -EIO;
  755. val = NETXEN_DECODE_VERSION(val);
  756. if (val > ver) {
  757. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  758. fwname);
  759. return -EINVAL;
  760. }
  761. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  762. return 0;
  763. }
  764. static int
  765. netxen_p3_has_mn(struct netxen_adapter *adapter)
  766. {
  767. u32 capability, flashed_ver;
  768. capability = 0;
  769. netxen_rom_fast_read(adapter,
  770. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  771. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  772. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  773. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  774. if (capability & NX_PEG_TUNE_MN_PRESENT)
  775. return 1;
  776. }
  777. return 0;
  778. }
  779. void netxen_request_firmware(struct netxen_adapter *adapter)
  780. {
  781. u8 fw_type;
  782. struct pci_dev *pdev = adapter->pdev;
  783. int rc = 0;
  784. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  785. fw_type = NX_P2_MN_ROMIMAGE;
  786. goto request_fw;
  787. }
  788. fw_type = netxen_p3_has_mn(adapter) ?
  789. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  790. request_fw:
  791. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  792. if (rc != 0) {
  793. if (fw_type == NX_P3_MN_ROMIMAGE) {
  794. msleep(1);
  795. fw_type = NX_P3_CT_ROMIMAGE;
  796. goto request_fw;
  797. }
  798. fw_type = NX_FLASH_ROMIMAGE;
  799. adapter->fw = NULL;
  800. goto done;
  801. }
  802. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  803. if (rc != 0) {
  804. release_firmware(adapter->fw);
  805. if (fw_type == NX_P3_MN_ROMIMAGE) {
  806. msleep(1);
  807. fw_type = NX_P3_CT_ROMIMAGE;
  808. goto request_fw;
  809. }
  810. fw_type = NX_FLASH_ROMIMAGE;
  811. adapter->fw = NULL;
  812. goto done;
  813. }
  814. done:
  815. adapter->fw_type = fw_type;
  816. }
  817. void
  818. netxen_release_firmware(struct netxen_adapter *adapter)
  819. {
  820. if (adapter->fw)
  821. release_firmware(adapter->fw);
  822. }
  823. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  824. {
  825. u64 addr;
  826. u32 hi, lo;
  827. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  828. return 0;
  829. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  830. NETXEN_HOST_DUMMY_DMA_SIZE,
  831. &adapter->dummy_dma.phys_addr);
  832. if (adapter->dummy_dma.addr == NULL) {
  833. dev_err(&adapter->pdev->dev,
  834. "ERROR: Could not allocate dummy DMA memory\n");
  835. return -ENOMEM;
  836. }
  837. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  838. hi = (addr >> 32) & 0xffffffff;
  839. lo = addr & 0xffffffff;
  840. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  841. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  842. return 0;
  843. }
  844. /*
  845. * NetXen DMA watchdog control:
  846. *
  847. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  848. * Bit 1 : disable_request => 1 req disable dma watchdog
  849. * Bit 2 : enable_request => 1 req enable dma watchdog
  850. * Bit 3-31 : unused
  851. */
  852. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  853. {
  854. int i = 100;
  855. u32 ctrl;
  856. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  857. return;
  858. if (!adapter->dummy_dma.addr)
  859. return;
  860. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  861. if ((ctrl & 0x1) != 0) {
  862. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  863. while ((ctrl & 0x1) != 0) {
  864. msleep(50);
  865. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  866. if (--i == 0)
  867. break;
  868. };
  869. }
  870. if (i) {
  871. pci_free_consistent(adapter->pdev,
  872. NETXEN_HOST_DUMMY_DMA_SIZE,
  873. adapter->dummy_dma.addr,
  874. adapter->dummy_dma.phys_addr);
  875. adapter->dummy_dma.addr = NULL;
  876. } else
  877. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  878. }
  879. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  880. {
  881. u32 val = 0;
  882. int retries = 60;
  883. if (pegtune_val)
  884. return 0;
  885. do {
  886. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  887. switch (val) {
  888. case PHAN_INITIALIZE_COMPLETE:
  889. case PHAN_INITIALIZE_ACK:
  890. return 0;
  891. case PHAN_INITIALIZE_FAILED:
  892. goto out_err;
  893. default:
  894. break;
  895. }
  896. msleep(500);
  897. } while (--retries);
  898. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  899. out_err:
  900. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  901. return -EIO;
  902. }
  903. static int
  904. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  905. {
  906. u32 val = 0;
  907. int retries = 2000;
  908. do {
  909. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  910. if (val == PHAN_PEG_RCV_INITIALIZED)
  911. return 0;
  912. msleep(10);
  913. } while (--retries);
  914. if (!retries) {
  915. printk(KERN_ERR "Receive Peg initialization not "
  916. "complete, state: 0x%x.\n", val);
  917. return -EIO;
  918. }
  919. return 0;
  920. }
  921. int netxen_init_firmware(struct netxen_adapter *adapter)
  922. {
  923. int err;
  924. err = netxen_receive_peg_ready(adapter);
  925. if (err)
  926. return err;
  927. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  928. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  929. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  930. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  931. return err;
  932. }
  933. static void
  934. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  935. {
  936. u32 cable_OUI;
  937. u16 cable_len;
  938. u16 link_speed;
  939. u8 link_status, module, duplex, autoneg;
  940. struct net_device *netdev = adapter->netdev;
  941. adapter->has_link_events = 1;
  942. cable_OUI = msg->body[1] & 0xffffffff;
  943. cable_len = (msg->body[1] >> 32) & 0xffff;
  944. link_speed = (msg->body[1] >> 48) & 0xffff;
  945. link_status = msg->body[2] & 0xff;
  946. duplex = (msg->body[2] >> 16) & 0xff;
  947. autoneg = (msg->body[2] >> 24) & 0xff;
  948. module = (msg->body[2] >> 8) & 0xff;
  949. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  950. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  951. netdev->name, cable_OUI, cable_len);
  952. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  953. printk(KERN_INFO "%s: unsupported cable length %d\n",
  954. netdev->name, cable_len);
  955. }
  956. netxen_advert_link_change(adapter, link_status);
  957. /* update link parameters */
  958. if (duplex == LINKEVENT_FULL_DUPLEX)
  959. adapter->link_duplex = DUPLEX_FULL;
  960. else
  961. adapter->link_duplex = DUPLEX_HALF;
  962. adapter->module_type = module;
  963. adapter->link_autoneg = autoneg;
  964. adapter->link_speed = link_speed;
  965. }
  966. static void
  967. netxen_handle_fw_message(int desc_cnt, int index,
  968. struct nx_host_sds_ring *sds_ring)
  969. {
  970. nx_fw_msg_t msg;
  971. struct status_desc *desc;
  972. int i = 0, opcode;
  973. while (desc_cnt > 0 && i < 8) {
  974. desc = &sds_ring->desc_head[index];
  975. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  976. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  977. index = get_next_index(index, sds_ring->num_desc);
  978. desc_cnt--;
  979. }
  980. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  981. switch (opcode) {
  982. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  983. netxen_handle_linkevent(sds_ring->adapter, &msg);
  984. break;
  985. default:
  986. break;
  987. }
  988. }
  989. static int
  990. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  991. struct nx_host_rds_ring *rds_ring,
  992. struct netxen_rx_buffer *buffer)
  993. {
  994. struct sk_buff *skb;
  995. dma_addr_t dma;
  996. struct pci_dev *pdev = adapter->pdev;
  997. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  998. if (!buffer->skb)
  999. return 1;
  1000. skb = buffer->skb;
  1001. if (!adapter->ahw.cut_through)
  1002. skb_reserve(skb, 2);
  1003. dma = pci_map_single(pdev, skb->data,
  1004. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1005. if (pci_dma_mapping_error(pdev, dma)) {
  1006. dev_kfree_skb_any(skb);
  1007. buffer->skb = NULL;
  1008. return 1;
  1009. }
  1010. buffer->skb = skb;
  1011. buffer->dma = dma;
  1012. buffer->state = NETXEN_BUFFER_BUSY;
  1013. return 0;
  1014. }
  1015. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1016. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1017. {
  1018. struct netxen_rx_buffer *buffer;
  1019. struct sk_buff *skb;
  1020. buffer = &rds_ring->rx_buf_arr[index];
  1021. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1022. PCI_DMA_FROMDEVICE);
  1023. skb = buffer->skb;
  1024. if (!skb)
  1025. goto no_skb;
  1026. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1027. adapter->stats.csummed++;
  1028. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1029. } else
  1030. skb->ip_summed = CHECKSUM_NONE;
  1031. skb->dev = adapter->netdev;
  1032. buffer->skb = NULL;
  1033. no_skb:
  1034. buffer->state = NETXEN_BUFFER_FREE;
  1035. return skb;
  1036. }
  1037. static struct netxen_rx_buffer *
  1038. netxen_process_rcv(struct netxen_adapter *adapter,
  1039. struct nx_host_sds_ring *sds_ring,
  1040. int ring, u64 sts_data0)
  1041. {
  1042. struct net_device *netdev = adapter->netdev;
  1043. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1044. struct netxen_rx_buffer *buffer;
  1045. struct sk_buff *skb;
  1046. struct nx_host_rds_ring *rds_ring;
  1047. int index, length, cksum, pkt_offset;
  1048. if (unlikely(ring >= adapter->max_rds_rings))
  1049. return NULL;
  1050. rds_ring = &recv_ctx->rds_rings[ring];
  1051. index = netxen_get_sts_refhandle(sts_data0);
  1052. if (unlikely(index >= rds_ring->num_desc))
  1053. return NULL;
  1054. buffer = &rds_ring->rx_buf_arr[index];
  1055. length = netxen_get_sts_totallength(sts_data0);
  1056. cksum = netxen_get_sts_status(sts_data0);
  1057. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1058. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1059. if (!skb)
  1060. return buffer;
  1061. if (length > rds_ring->skb_size)
  1062. skb_put(skb, rds_ring->skb_size);
  1063. else
  1064. skb_put(skb, length);
  1065. if (pkt_offset)
  1066. skb_pull(skb, pkt_offset);
  1067. skb->protocol = eth_type_trans(skb, netdev);
  1068. napi_gro_receive(&sds_ring->napi, skb);
  1069. adapter->stats.no_rcv++;
  1070. adapter->stats.rxbytes += length;
  1071. return buffer;
  1072. }
  1073. #define TCP_HDR_SIZE 20
  1074. #define TCP_TS_OPTION_SIZE 12
  1075. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1076. static struct netxen_rx_buffer *
  1077. netxen_process_lro(struct netxen_adapter *adapter,
  1078. struct nx_host_sds_ring *sds_ring,
  1079. int ring, u64 sts_data0, u64 sts_data1)
  1080. {
  1081. struct net_device *netdev = adapter->netdev;
  1082. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1083. struct netxen_rx_buffer *buffer;
  1084. struct sk_buff *skb;
  1085. struct nx_host_rds_ring *rds_ring;
  1086. struct iphdr *iph;
  1087. struct tcphdr *th;
  1088. bool push, timestamp;
  1089. int l2_hdr_offset, l4_hdr_offset;
  1090. int index;
  1091. u16 lro_length, length, data_offset;
  1092. u32 seq_number;
  1093. if (unlikely(ring > adapter->max_rds_rings))
  1094. return NULL;
  1095. rds_ring = &recv_ctx->rds_rings[ring];
  1096. index = netxen_get_lro_sts_refhandle(sts_data0);
  1097. if (unlikely(index > rds_ring->num_desc))
  1098. return NULL;
  1099. buffer = &rds_ring->rx_buf_arr[index];
  1100. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1101. lro_length = netxen_get_lro_sts_length(sts_data0);
  1102. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1103. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1104. push = netxen_get_lro_sts_push_flag(sts_data0);
  1105. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1106. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1107. if (!skb)
  1108. return buffer;
  1109. if (timestamp)
  1110. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1111. else
  1112. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1113. skb_put(skb, lro_length + data_offset);
  1114. skb->truesize = (skb->len + sizeof(struct sk_buff) +
  1115. ((unsigned long)skb->data - (unsigned long)skb->head));
  1116. skb_pull(skb, l2_hdr_offset);
  1117. skb->protocol = eth_type_trans(skb, netdev);
  1118. iph = (struct iphdr *)skb->data;
  1119. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1120. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1121. iph->tot_len = htons(length);
  1122. iph->check = 0;
  1123. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1124. th->psh = push;
  1125. th->seq = htonl(seq_number);
  1126. netif_receive_skb(skb);
  1127. return buffer;
  1128. }
  1129. #define netxen_merge_rx_buffers(list, head) \
  1130. do { list_splice_tail_init(list, head); } while (0);
  1131. int
  1132. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1133. {
  1134. struct netxen_adapter *adapter = sds_ring->adapter;
  1135. struct list_head *cur;
  1136. struct status_desc *desc;
  1137. struct netxen_rx_buffer *rxbuf;
  1138. u32 consumer = sds_ring->consumer;
  1139. int count = 0;
  1140. u64 sts_data0, sts_data1;
  1141. int opcode, ring = 0, desc_cnt;
  1142. while (count < max) {
  1143. desc = &sds_ring->desc_head[consumer];
  1144. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1145. if (!(sts_data0 & STATUS_OWNER_HOST))
  1146. break;
  1147. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1148. opcode = netxen_get_sts_opcode(sts_data0);
  1149. switch (opcode) {
  1150. case NETXEN_NIC_RXPKT_DESC:
  1151. case NETXEN_OLD_RXPKT_DESC:
  1152. case NETXEN_NIC_SYN_OFFLOAD:
  1153. ring = netxen_get_sts_type(sts_data0);
  1154. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1155. ring, sts_data0);
  1156. break;
  1157. case NETXEN_NIC_LRO_DESC:
  1158. ring = netxen_get_lro_sts_type(sts_data0);
  1159. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1160. rxbuf = netxen_process_lro(adapter, sds_ring,
  1161. ring, sts_data0, sts_data1);
  1162. break;
  1163. case NETXEN_NIC_RESPONSE_DESC:
  1164. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1165. default:
  1166. goto skip;
  1167. }
  1168. WARN_ON(desc_cnt > 1);
  1169. if (rxbuf)
  1170. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1171. skip:
  1172. for (; desc_cnt > 0; desc_cnt--) {
  1173. desc = &sds_ring->desc_head[consumer];
  1174. desc->status_desc_data[0] =
  1175. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1176. consumer = get_next_index(consumer, sds_ring->num_desc);
  1177. }
  1178. count++;
  1179. }
  1180. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1181. struct nx_host_rds_ring *rds_ring =
  1182. &adapter->recv_ctx.rds_rings[ring];
  1183. if (!list_empty(&sds_ring->free_list[ring])) {
  1184. list_for_each(cur, &sds_ring->free_list[ring]) {
  1185. rxbuf = list_entry(cur,
  1186. struct netxen_rx_buffer, list);
  1187. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1188. }
  1189. spin_lock(&rds_ring->lock);
  1190. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1191. &rds_ring->free_list);
  1192. spin_unlock(&rds_ring->lock);
  1193. }
  1194. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1195. }
  1196. if (count) {
  1197. sds_ring->consumer = consumer;
  1198. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1199. }
  1200. return count;
  1201. }
  1202. /* Process Command status ring */
  1203. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1204. {
  1205. u32 sw_consumer, hw_consumer;
  1206. int count = 0, i;
  1207. struct netxen_cmd_buffer *buffer;
  1208. struct pci_dev *pdev = adapter->pdev;
  1209. struct net_device *netdev = adapter->netdev;
  1210. struct netxen_skb_frag *frag;
  1211. int done = 0;
  1212. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1213. if (!spin_trylock(&adapter->tx_clean_lock))
  1214. return 1;
  1215. sw_consumer = tx_ring->sw_consumer;
  1216. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1217. while (sw_consumer != hw_consumer) {
  1218. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1219. if (buffer->skb) {
  1220. frag = &buffer->frag_array[0];
  1221. pci_unmap_single(pdev, frag->dma, frag->length,
  1222. PCI_DMA_TODEVICE);
  1223. frag->dma = 0ULL;
  1224. for (i = 1; i < buffer->frag_count; i++) {
  1225. frag++; /* Get the next frag */
  1226. pci_unmap_page(pdev, frag->dma, frag->length,
  1227. PCI_DMA_TODEVICE);
  1228. frag->dma = 0ULL;
  1229. }
  1230. adapter->stats.xmitfinished++;
  1231. dev_kfree_skb_any(buffer->skb);
  1232. buffer->skb = NULL;
  1233. }
  1234. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1235. if (++count >= MAX_STATUS_HANDLE)
  1236. break;
  1237. }
  1238. if (count && netif_running(netdev)) {
  1239. tx_ring->sw_consumer = sw_consumer;
  1240. smp_mb();
  1241. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1242. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1243. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1244. netif_wake_queue(netdev);
  1245. __netif_tx_unlock(tx_ring->txq);
  1246. }
  1247. }
  1248. /*
  1249. * If everything is freed up to consumer then check if the ring is full
  1250. * If the ring is full then check if more needs to be freed and
  1251. * schedule the call back again.
  1252. *
  1253. * This happens when there are 2 CPUs. One could be freeing and the
  1254. * other filling it. If the ring is full when we get out of here and
  1255. * the card has already interrupted the host then the host can miss the
  1256. * interrupt.
  1257. *
  1258. * There is still a possible race condition and the host could miss an
  1259. * interrupt. The card has to take care of this.
  1260. */
  1261. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1262. done = (sw_consumer == hw_consumer);
  1263. spin_unlock(&adapter->tx_clean_lock);
  1264. return (done);
  1265. }
  1266. void
  1267. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1268. struct nx_host_rds_ring *rds_ring)
  1269. {
  1270. struct rcv_desc *pdesc;
  1271. struct netxen_rx_buffer *buffer;
  1272. int producer, count = 0;
  1273. netxen_ctx_msg msg = 0;
  1274. struct list_head *head;
  1275. producer = rds_ring->producer;
  1276. spin_lock(&rds_ring->lock);
  1277. head = &rds_ring->free_list;
  1278. while (!list_empty(head)) {
  1279. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1280. if (!buffer->skb) {
  1281. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1282. break;
  1283. }
  1284. count++;
  1285. list_del(&buffer->list);
  1286. /* make a rcv descriptor */
  1287. pdesc = &rds_ring->desc_head[producer];
  1288. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1289. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1290. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1291. producer = get_next_index(producer, rds_ring->num_desc);
  1292. }
  1293. spin_unlock(&rds_ring->lock);
  1294. if (count) {
  1295. rds_ring->producer = producer;
  1296. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1297. (producer-1) & (rds_ring->num_desc-1));
  1298. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1299. /*
  1300. * Write a doorbell msg to tell phanmon of change in
  1301. * receive ring producer
  1302. * Only for firmware version < 4.0.0
  1303. */
  1304. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1305. netxen_set_msg_privid(msg);
  1306. netxen_set_msg_count(msg,
  1307. ((producer - 1) &
  1308. (rds_ring->num_desc - 1)));
  1309. netxen_set_msg_ctxid(msg, adapter->portnum);
  1310. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1311. writel(msg,
  1312. DB_NORMALIZE(adapter,
  1313. NETXEN_RCV_PRODUCER_OFFSET));
  1314. }
  1315. }
  1316. }
  1317. static void
  1318. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1319. struct nx_host_rds_ring *rds_ring)
  1320. {
  1321. struct rcv_desc *pdesc;
  1322. struct netxen_rx_buffer *buffer;
  1323. int producer, count = 0;
  1324. struct list_head *head;
  1325. producer = rds_ring->producer;
  1326. if (!spin_trylock(&rds_ring->lock))
  1327. return;
  1328. head = &rds_ring->free_list;
  1329. while (!list_empty(head)) {
  1330. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1331. if (!buffer->skb) {
  1332. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1333. break;
  1334. }
  1335. count++;
  1336. list_del(&buffer->list);
  1337. /* make a rcv descriptor */
  1338. pdesc = &rds_ring->desc_head[producer];
  1339. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1340. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1341. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1342. producer = get_next_index(producer, rds_ring->num_desc);
  1343. }
  1344. if (count) {
  1345. rds_ring->producer = producer;
  1346. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1347. (producer - 1) & (rds_ring->num_desc - 1));
  1348. }
  1349. spin_unlock(&rds_ring->lock);
  1350. }
  1351. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1352. {
  1353. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1354. return;
  1355. }