main.c 36 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494
  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
  21. #define IEEE80211_ACTION_CAT_HT 7
  22. #define IEEE80211_ACTION_HT_TXCHWIDTH 0
  23. static char *dev_info = "ath9k";
  24. MODULE_AUTHOR("Atheros Communications");
  25. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27. MODULE_LICENSE("Dual BSD/GPL");
  28. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  29. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  31. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  32. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  33. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  34. { 0 }
  35. };
  36. static int ath_get_channel(struct ath_softc *sc,
  37. struct ieee80211_channel *chan)
  38. {
  39. int i;
  40. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  41. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  42. return i;
  43. }
  44. return -1;
  45. }
  46. static u32 ath_get_extchanmode(struct ath_softc *sc,
  47. struct ieee80211_channel *chan)
  48. {
  49. u32 chanmode = 0;
  50. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  51. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  52. switch (chan->band) {
  53. case IEEE80211_BAND_2GHZ:
  54. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  55. (tx_chan_width == ATH9K_HT_MACMODE_20))
  56. chanmode = CHANNEL_G_HT20;
  57. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  58. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  59. chanmode = CHANNEL_G_HT40PLUS;
  60. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  61. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  62. chanmode = CHANNEL_G_HT40MINUS;
  63. break;
  64. case IEEE80211_BAND_5GHZ:
  65. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  66. (tx_chan_width == ATH9K_HT_MACMODE_20))
  67. chanmode = CHANNEL_A_HT20;
  68. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  69. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  70. chanmode = CHANNEL_A_HT40PLUS;
  71. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  72. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  73. chanmode = CHANNEL_A_HT40MINUS;
  74. break;
  75. default:
  76. break;
  77. }
  78. return chanmode;
  79. }
  80. static int ath_setkey_tkip(struct ath_softc *sc,
  81. struct ieee80211_key_conf *key,
  82. struct ath9k_keyval *hk,
  83. const u8 *addr)
  84. {
  85. u8 *key_rxmic = NULL;
  86. u8 *key_txmic = NULL;
  87. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  88. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  89. if (addr == NULL) {
  90. /* Group key installation */
  91. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  92. return ath_keyset(sc, key->keyidx, hk, addr);
  93. }
  94. if (!sc->sc_splitmic) {
  95. /*
  96. * data key goes at first index,
  97. * the hal handles the MIC keys at index+64.
  98. */
  99. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  100. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  101. return ath_keyset(sc, key->keyidx, hk, addr);
  102. }
  103. /*
  104. * TX key goes at first index, RX key at +32.
  105. * The hal handles the MIC keys at index+64.
  106. */
  107. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  108. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  109. /* Txmic entry failed. No need to proceed further */
  110. DPRINTF(sc, ATH_DBG_KEYCACHE,
  111. "%s Setting TX MIC Key Failed\n", __func__);
  112. return 0;
  113. }
  114. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  115. /* XXX delete tx key on failure? */
  116. return ath_keyset(sc, key->keyidx+32, hk, addr);
  117. }
  118. static int ath_key_config(struct ath_softc *sc,
  119. const u8 *addr,
  120. struct ieee80211_key_conf *key)
  121. {
  122. struct ieee80211_vif *vif;
  123. struct ath9k_keyval hk;
  124. const u8 *mac = NULL;
  125. int ret = 0;
  126. enum ieee80211_if_types opmode;
  127. memset(&hk, 0, sizeof(hk));
  128. switch (key->alg) {
  129. case ALG_WEP:
  130. hk.kv_type = ATH9K_CIPHER_WEP;
  131. break;
  132. case ALG_TKIP:
  133. hk.kv_type = ATH9K_CIPHER_TKIP;
  134. break;
  135. case ALG_CCMP:
  136. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  137. break;
  138. default:
  139. return -EINVAL;
  140. }
  141. hk.kv_len = key->keylen;
  142. memcpy(hk.kv_val, key->key, key->keylen);
  143. if (!sc->sc_vaps[0])
  144. return -EIO;
  145. vif = sc->sc_vaps[0]->av_if_data;
  146. opmode = vif->type;
  147. /*
  148. * Strategy:
  149. * For _M_STA mc tx, we will not setup a key at all since we never
  150. * tx mc.
  151. * _M_STA mc rx, we will use the keyID.
  152. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  153. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  154. * peer node. BUT we will plumb a cleartext key so that we can do
  155. * perSta default key table lookup in software.
  156. */
  157. if (is_broadcast_ether_addr(addr)) {
  158. switch (opmode) {
  159. case IEEE80211_IF_TYPE_STA:
  160. /* default key: could be group WPA key
  161. * or could be static WEP key */
  162. mac = NULL;
  163. break;
  164. case IEEE80211_IF_TYPE_IBSS:
  165. break;
  166. case IEEE80211_IF_TYPE_AP:
  167. break;
  168. default:
  169. ASSERT(0);
  170. break;
  171. }
  172. } else {
  173. mac = addr;
  174. }
  175. if (key->alg == ALG_TKIP)
  176. ret = ath_setkey_tkip(sc, key, &hk, mac);
  177. else
  178. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  179. if (!ret)
  180. return -EIO;
  181. if (mac)
  182. sc->sc_keytype = hk.kv_type;
  183. return 0;
  184. }
  185. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  186. {
  187. #define ATH_MAX_NUM_KEYS 4
  188. int freeslot;
  189. freeslot = (key->keyidx >= ATH_MAX_NUM_KEYS) ? 1 : 0;
  190. ath_key_reset(sc, key->keyidx, freeslot);
  191. #undef ATH_MAX_NUM_KEYS
  192. }
  193. static void setup_ht_cap(struct ieee80211_ht_info *ht_info)
  194. {
  195. /* Until mac80211 includes these fields */
  196. #define IEEE80211_HT_CAP_DSSSCCK40 0x1000
  197. #define IEEE80211_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  198. #define IEEE80211_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  199. ht_info->ht_supported = 1;
  200. ht_info->cap = (u16)IEEE80211_HT_CAP_SUP_WIDTH
  201. |(u16)IEEE80211_HT_CAP_MIMO_PS
  202. |(u16)IEEE80211_HT_CAP_SGI_40
  203. |(u16)IEEE80211_HT_CAP_DSSSCCK40;
  204. ht_info->ampdu_factor = IEEE80211_HT_CAP_MAXRXAMPDU_65536;
  205. ht_info->ampdu_density = IEEE80211_HT_CAP_MPDUDENSITY_8;
  206. /* setup supported mcs set */
  207. memset(ht_info->supp_mcs_set, 0, 16);
  208. ht_info->supp_mcs_set[0] = 0xff;
  209. ht_info->supp_mcs_set[1] = 0xff;
  210. ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
  211. }
  212. static int ath_rate2idx(struct ath_softc *sc, int rate)
  213. {
  214. int i = 0, cur_band, n_rates;
  215. struct ieee80211_hw *hw = sc->hw;
  216. cur_band = hw->conf.channel->band;
  217. n_rates = sc->sbands[cur_band].n_bitrates;
  218. for (i = 0; i < n_rates; i++) {
  219. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  220. break;
  221. }
  222. /*
  223. * NB:mac80211 validates rx rate index against the supported legacy rate
  224. * index only (should be done against ht rates also), return the highest
  225. * legacy rate index for rx rate which does not match any one of the
  226. * supported basic and extended rates to make mac80211 happy.
  227. * The following hack will be cleaned up once the issue with
  228. * the rx rate index validation in mac80211 is fixed.
  229. */
  230. if (i == n_rates)
  231. return n_rates - 1;
  232. return i;
  233. }
  234. static void ath9k_rx_prepare(struct ath_softc *sc,
  235. struct sk_buff *skb,
  236. struct ath_recv_status *status,
  237. struct ieee80211_rx_status *rx_status)
  238. {
  239. struct ieee80211_hw *hw = sc->hw;
  240. struct ieee80211_channel *curchan = hw->conf.channel;
  241. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  242. rx_status->mactime = status->tsf;
  243. rx_status->band = curchan->band;
  244. rx_status->freq = curchan->center_freq;
  245. rx_status->noise = ATH_DEFAULT_NOISE_FLOOR;
  246. rx_status->signal = rx_status->noise + status->rssi;
  247. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  248. rx_status->antenna = status->antenna;
  249. rx_status->qual = status->rssi * 100 / 64;
  250. if (status->flags & ATH_RX_MIC_ERROR)
  251. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  252. if (status->flags & ATH_RX_FCS_ERROR)
  253. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  254. rx_status->flag |= RX_FLAG_TSFT;
  255. }
  256. static u8 parse_mpdudensity(u8 mpdudensity)
  257. {
  258. /*
  259. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  260. * 0 for no restriction
  261. * 1 for 1/4 us
  262. * 2 for 1/2 us
  263. * 3 for 1 us
  264. * 4 for 2 us
  265. * 5 for 4 us
  266. * 6 for 8 us
  267. * 7 for 16 us
  268. */
  269. switch (mpdudensity) {
  270. case 0:
  271. return 0;
  272. case 1:
  273. case 2:
  274. case 3:
  275. /* Our lower layer calculations limit our precision to
  276. 1 microsecond */
  277. return 1;
  278. case 4:
  279. return 2;
  280. case 5:
  281. return 4;
  282. case 6:
  283. return 8;
  284. case 7:
  285. return 16;
  286. default:
  287. return 0;
  288. }
  289. }
  290. static int ath9k_start(struct ieee80211_hw *hw)
  291. {
  292. struct ath_softc *sc = hw->priv;
  293. struct ieee80211_channel *curchan = hw->conf.channel;
  294. int error = 0, pos;
  295. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  296. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  297. /* setup initial channel */
  298. pos = ath_get_channel(sc, curchan);
  299. if (pos == -1) {
  300. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  301. return -EINVAL;
  302. }
  303. sc->sc_ah->ah_channels[pos].chanmode =
  304. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  305. /* open ath_dev */
  306. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  307. if (error) {
  308. DPRINTF(sc, ATH_DBG_FATAL,
  309. "%s: Unable to complete ath_open\n", __func__);
  310. return error;
  311. }
  312. ieee80211_wake_queues(hw);
  313. return 0;
  314. }
  315. static int ath9k_tx(struct ieee80211_hw *hw,
  316. struct sk_buff *skb)
  317. {
  318. struct ath_softc *sc = hw->priv;
  319. int hdrlen, padsize;
  320. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  321. /*
  322. * As a temporary workaround, assign seq# here; this will likely need
  323. * to be cleaned up to work better with Beacon transmission and virtual
  324. * BSSes.
  325. */
  326. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  327. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  328. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  329. sc->seq_no += 0x10;
  330. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  331. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  332. }
  333. /* Add the padding after the header if this is not already done */
  334. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  335. if (hdrlen & 3) {
  336. padsize = hdrlen % 4;
  337. if (skb_headroom(skb) < padsize)
  338. return -1;
  339. skb_push(skb, padsize);
  340. memmove(skb->data, skb->data + padsize, hdrlen);
  341. }
  342. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  343. __func__,
  344. skb);
  345. if (ath_tx_start(sc, skb) != 0) {
  346. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  347. dev_kfree_skb_any(skb);
  348. /* FIXME: Check for proper return value from ATH_DEV */
  349. return 0;
  350. }
  351. return 0;
  352. }
  353. static void ath9k_stop(struct ieee80211_hw *hw)
  354. {
  355. struct ath_softc *sc = hw->priv;
  356. int error;
  357. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  358. error = ath_suspend(sc);
  359. if (error)
  360. DPRINTF(sc, ATH_DBG_CONFIG,
  361. "%s: Device is no longer present\n", __func__);
  362. ieee80211_stop_queues(hw);
  363. }
  364. static int ath9k_add_interface(struct ieee80211_hw *hw,
  365. struct ieee80211_if_init_conf *conf)
  366. {
  367. struct ath_softc *sc = hw->priv;
  368. int error, ic_opmode = 0;
  369. /* Support only vap for now */
  370. if (sc->sc_nvaps)
  371. return -ENOBUFS;
  372. switch (conf->type) {
  373. case IEEE80211_IF_TYPE_STA:
  374. ic_opmode = ATH9K_M_STA;
  375. break;
  376. case IEEE80211_IF_TYPE_IBSS:
  377. ic_opmode = ATH9K_M_IBSS;
  378. break;
  379. default:
  380. DPRINTF(sc, ATH_DBG_FATAL,
  381. "%s: Only STA and IBSS are supported currently\n",
  382. __func__);
  383. return -EOPNOTSUPP;
  384. }
  385. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  386. __func__,
  387. ic_opmode);
  388. error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
  389. if (error) {
  390. DPRINTF(sc, ATH_DBG_FATAL,
  391. "%s: Unable to attach vap, error: %d\n",
  392. __func__, error);
  393. return error;
  394. }
  395. return 0;
  396. }
  397. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  398. struct ieee80211_if_init_conf *conf)
  399. {
  400. struct ath_softc *sc = hw->priv;
  401. struct ath_vap *avp;
  402. int error;
  403. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  404. avp = sc->sc_vaps[0];
  405. if (avp == NULL) {
  406. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  407. __func__);
  408. return;
  409. }
  410. #ifdef CONFIG_SLOW_ANT_DIV
  411. ath_slow_ant_div_stop(&sc->sc_antdiv);
  412. #endif
  413. /* Update ratectrl */
  414. ath_rate_newstate(sc, avp);
  415. /* Reclaim beacon resources */
  416. if (sc->sc_opmode == ATH9K_M_HOSTAP || sc->sc_opmode == ATH9K_M_IBSS) {
  417. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  418. ath_beacon_return(sc, avp);
  419. }
  420. /* Set interrupt mask */
  421. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  422. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
  423. sc->sc_beacons = 0;
  424. error = ath_vap_detach(sc, 0);
  425. if (error)
  426. DPRINTF(sc, ATH_DBG_FATAL,
  427. "%s: Unable to detach vap, error: %d\n",
  428. __func__, error);
  429. }
  430. static int ath9k_config(struct ieee80211_hw *hw,
  431. struct ieee80211_conf *conf)
  432. {
  433. struct ath_softc *sc = hw->priv;
  434. struct ieee80211_channel *curchan = hw->conf.channel;
  435. int pos;
  436. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  437. __func__,
  438. curchan->center_freq);
  439. pos = ath_get_channel(sc, curchan);
  440. if (pos == -1) {
  441. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  442. return -EINVAL;
  443. }
  444. sc->sc_ah->ah_channels[pos].chanmode =
  445. (curchan->band == IEEE80211_BAND_2GHZ) ?
  446. CHANNEL_G : CHANNEL_A;
  447. if (sc->sc_curaid && hw->conf.ht_conf.ht_supported)
  448. sc->sc_ah->ah_channels[pos].chanmode =
  449. ath_get_extchanmode(sc, curchan);
  450. sc->sc_config.txpowlimit = 2 * conf->power_level;
  451. /* set h/w channel */
  452. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  453. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  454. __func__);
  455. return 0;
  456. }
  457. static int ath9k_config_interface(struct ieee80211_hw *hw,
  458. struct ieee80211_vif *vif,
  459. struct ieee80211_if_conf *conf)
  460. {
  461. struct ath_softc *sc = hw->priv;
  462. struct ath_vap *avp;
  463. u32 rfilt = 0;
  464. int error, i;
  465. DECLARE_MAC_BUF(mac);
  466. avp = sc->sc_vaps[0];
  467. if (avp == NULL) {
  468. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  469. __func__);
  470. return -EINVAL;
  471. }
  472. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  473. !is_zero_ether_addr(conf->bssid)) {
  474. switch (vif->type) {
  475. case IEEE80211_IF_TYPE_STA:
  476. case IEEE80211_IF_TYPE_IBSS:
  477. /* Update ratectrl about the new state */
  478. ath_rate_newstate(sc, avp);
  479. /* Set rx filter */
  480. rfilt = ath_calcrxfilter(sc);
  481. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  482. /* Set BSSID */
  483. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  484. sc->sc_curaid = 0;
  485. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  486. sc->sc_curaid);
  487. /* Set aggregation protection mode parameters */
  488. sc->sc_config.ath_aggr_prot = 0;
  489. /*
  490. * Reset our TSF so that its value is lower than the
  491. * beacon that we are trying to catch.
  492. * Only then hw will update its TSF register with the
  493. * new beacon. Reset the TSF before setting the BSSID
  494. * to avoid allowing in any frames that would update
  495. * our TSF only to have us clear it
  496. * immediately thereafter.
  497. */
  498. ath9k_hw_reset_tsf(sc->sc_ah);
  499. /* Disable BMISS interrupt when we're not associated */
  500. ath9k_hw_set_interrupts(sc->sc_ah,
  501. sc->sc_imask &
  502. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  503. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  504. DPRINTF(sc, ATH_DBG_CONFIG,
  505. "%s: RX filter 0x%x bssid %s aid 0x%x\n",
  506. __func__, rfilt,
  507. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  508. /* need to reconfigure the beacon */
  509. sc->sc_beacons = 0;
  510. break;
  511. default:
  512. break;
  513. }
  514. }
  515. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  516. (vif->type == IEEE80211_IF_TYPE_IBSS)) {
  517. /*
  518. * Allocate and setup the beacon frame.
  519. *
  520. * Stop any previous beacon DMA. This may be
  521. * necessary, for example, when an ibss merge
  522. * causes reconfiguration; we may be called
  523. * with beacon transmission active.
  524. */
  525. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  526. error = ath_beacon_alloc(sc, 0);
  527. if (error != 0)
  528. return error;
  529. ath_beacon_sync(sc, 0);
  530. }
  531. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  532. if ((avp->av_opmode != IEEE80211_IF_TYPE_STA)) {
  533. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  534. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  535. ath9k_hw_keysetmac(sc->sc_ah,
  536. (u16)i,
  537. sc->sc_curbssid);
  538. }
  539. /* Only legacy IBSS for now */
  540. if (vif->type == IEEE80211_IF_TYPE_IBSS)
  541. ath_update_chainmask(sc, 0);
  542. return 0;
  543. }
  544. #define SUPPORTED_FILTERS \
  545. (FIF_PROMISC_IN_BSS | \
  546. FIF_ALLMULTI | \
  547. FIF_CONTROL | \
  548. FIF_OTHER_BSS | \
  549. FIF_BCN_PRBRESP_PROMISC | \
  550. FIF_FCSFAIL)
  551. /* Accept unicast, bcast and mcast frames */
  552. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  553. unsigned int changed_flags,
  554. unsigned int *total_flags,
  555. int mc_count,
  556. struct dev_mc_list *mclist)
  557. {
  558. struct ath_softc *sc = hw->priv;
  559. changed_flags &= SUPPORTED_FILTERS;
  560. *total_flags &= SUPPORTED_FILTERS;
  561. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  562. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  563. ath_scan_start(sc);
  564. else
  565. ath_scan_end(sc);
  566. }
  567. }
  568. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  569. struct ieee80211_vif *vif,
  570. enum sta_notify_cmd cmd,
  571. const u8 *addr)
  572. {
  573. struct ath_softc *sc = hw->priv;
  574. struct ath_node *an;
  575. unsigned long flags;
  576. DECLARE_MAC_BUF(mac);
  577. spin_lock_irqsave(&sc->node_lock, flags);
  578. an = ath_node_find(sc, (u8 *) addr);
  579. spin_unlock_irqrestore(&sc->node_lock, flags);
  580. switch (cmd) {
  581. case STA_NOTIFY_ADD:
  582. spin_lock_irqsave(&sc->node_lock, flags);
  583. if (!an) {
  584. ath_node_attach(sc, (u8 *)addr, 0);
  585. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n",
  586. __func__,
  587. print_mac(mac, addr));
  588. } else {
  589. ath_node_get(sc, (u8 *)addr);
  590. }
  591. spin_unlock_irqrestore(&sc->node_lock, flags);
  592. break;
  593. case STA_NOTIFY_REMOVE:
  594. if (!an)
  595. DPRINTF(sc, ATH_DBG_FATAL,
  596. "%s: Removal of a non-existent node\n",
  597. __func__);
  598. else {
  599. ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
  600. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n",
  601. __func__,
  602. print_mac(mac, addr));
  603. }
  604. break;
  605. default:
  606. break;
  607. }
  608. }
  609. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  610. u16 queue,
  611. const struct ieee80211_tx_queue_params *params)
  612. {
  613. struct ath_softc *sc = hw->priv;
  614. struct ath9k_tx_queue_info qi;
  615. int ret = 0, qnum;
  616. if (queue >= WME_NUM_AC)
  617. return 0;
  618. qi.tqi_aifs = params->aifs;
  619. qi.tqi_cwmin = params->cw_min;
  620. qi.tqi_cwmax = params->cw_max;
  621. qi.tqi_burstTime = params->txop;
  622. qnum = ath_get_hal_qnum(queue, sc);
  623. DPRINTF(sc, ATH_DBG_CONFIG,
  624. "%s: Configure tx [queue/halq] [%d/%d], "
  625. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  626. __func__,
  627. queue,
  628. qnum,
  629. params->aifs,
  630. params->cw_min,
  631. params->cw_max,
  632. params->txop);
  633. ret = ath_txq_update(sc, qnum, &qi);
  634. if (ret)
  635. DPRINTF(sc, ATH_DBG_FATAL,
  636. "%s: TXQ Update failed\n", __func__);
  637. return ret;
  638. }
  639. static int ath9k_set_key(struct ieee80211_hw *hw,
  640. enum set_key_cmd cmd,
  641. const u8 *local_addr,
  642. const u8 *addr,
  643. struct ieee80211_key_conf *key)
  644. {
  645. struct ath_softc *sc = hw->priv;
  646. int ret = 0;
  647. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  648. switch (cmd) {
  649. case SET_KEY:
  650. ret = ath_key_config(sc, addr, key);
  651. if (!ret) {
  652. set_bit(key->keyidx, sc->sc_keymap);
  653. key->hw_key_idx = key->keyidx;
  654. /* push IV and Michael MIC generation to stack */
  655. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  656. if (key->alg == ALG_TKIP)
  657. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  658. }
  659. break;
  660. case DISABLE_KEY:
  661. ath_key_delete(sc, key);
  662. clear_bit(key->keyidx, sc->sc_keymap);
  663. sc->sc_keytype = ATH9K_CIPHER_CLR;
  664. break;
  665. default:
  666. ret = -EINVAL;
  667. }
  668. return ret;
  669. }
  670. static void ath9k_ht_conf(struct ath_softc *sc,
  671. struct ieee80211_bss_conf *bss_conf)
  672. {
  673. #define IEEE80211_HT_CAP_40MHZ_INTOLERANT BIT(14)
  674. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  675. if (bss_conf->assoc_ht) {
  676. ht_info->ext_chan_offset =
  677. bss_conf->ht_bss_conf->bss_cap &
  678. IEEE80211_HT_IE_CHA_SEC_OFFSET;
  679. if (!(bss_conf->ht_conf->cap &
  680. IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
  681. (bss_conf->ht_bss_conf->bss_cap &
  682. IEEE80211_HT_IE_CHA_WIDTH))
  683. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  684. else
  685. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  686. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  687. ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
  688. bss_conf->ht_conf->ampdu_factor);
  689. ht_info->mpdudensity =
  690. parse_mpdudensity(bss_conf->ht_conf->ampdu_density);
  691. }
  692. #undef IEEE80211_HT_CAP_40MHZ_INTOLERANT
  693. }
  694. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  695. struct ieee80211_bss_conf *bss_conf)
  696. {
  697. struct ieee80211_hw *hw = sc->hw;
  698. struct ieee80211_channel *curchan = hw->conf.channel;
  699. struct ath_vap *avp;
  700. int pos;
  701. DECLARE_MAC_BUF(mac);
  702. if (bss_conf->assoc) {
  703. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  704. __func__,
  705. bss_conf->aid);
  706. avp = sc->sc_vaps[0];
  707. if (avp == NULL) {
  708. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  709. __func__);
  710. return;
  711. }
  712. /* New association, store aid */
  713. if (avp->av_opmode == ATH9K_M_STA) {
  714. sc->sc_curaid = bss_conf->aid;
  715. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  716. sc->sc_curaid);
  717. }
  718. /* Configure the beacon */
  719. ath_beacon_config(sc, 0);
  720. sc->sc_beacons = 1;
  721. /* Reset rssi stats */
  722. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  723. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  724. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  725. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  726. /* Update chainmask */
  727. ath_update_chainmask(sc, bss_conf->assoc_ht);
  728. DPRINTF(sc, ATH_DBG_CONFIG,
  729. "%s: bssid %s aid 0x%x\n",
  730. __func__,
  731. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  732. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  733. __func__,
  734. curchan->center_freq);
  735. pos = ath_get_channel(sc, curchan);
  736. if (pos == -1) {
  737. DPRINTF(sc, ATH_DBG_FATAL,
  738. "%s: Invalid channel\n", __func__);
  739. return;
  740. }
  741. if (hw->conf.ht_conf.ht_supported)
  742. sc->sc_ah->ah_channels[pos].chanmode =
  743. ath_get_extchanmode(sc, curchan);
  744. else
  745. sc->sc_ah->ah_channels[pos].chanmode =
  746. (curchan->band == IEEE80211_BAND_2GHZ) ?
  747. CHANNEL_G : CHANNEL_A;
  748. /* set h/w channel */
  749. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  750. DPRINTF(sc, ATH_DBG_FATAL,
  751. "%s: Unable to set channel\n",
  752. __func__);
  753. ath_rate_newstate(sc, avp);
  754. /* Update ratectrl about the new state */
  755. ath_rc_node_update(hw, avp->rc_node);
  756. } else {
  757. DPRINTF(sc, ATH_DBG_CONFIG,
  758. "%s: Bss Info DISSOC\n", __func__);
  759. sc->sc_curaid = 0;
  760. }
  761. }
  762. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  763. struct ieee80211_vif *vif,
  764. struct ieee80211_bss_conf *bss_conf,
  765. u32 changed)
  766. {
  767. struct ath_softc *sc = hw->priv;
  768. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  769. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  770. __func__,
  771. bss_conf->use_short_preamble);
  772. if (bss_conf->use_short_preamble)
  773. sc->sc_flags |= ATH_PREAMBLE_SHORT;
  774. else
  775. sc->sc_flags &= ~ATH_PREAMBLE_SHORT;
  776. }
  777. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  778. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  779. __func__,
  780. bss_conf->use_cts_prot);
  781. if (bss_conf->use_cts_prot &&
  782. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  783. sc->sc_flags |= ATH_PROTECT_ENABLE;
  784. else
  785. sc->sc_flags &= ~ATH_PROTECT_ENABLE;
  786. }
  787. if (changed & BSS_CHANGED_HT) {
  788. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
  789. __func__,
  790. bss_conf->assoc_ht);
  791. ath9k_ht_conf(sc, bss_conf);
  792. }
  793. if (changed & BSS_CHANGED_ASSOC) {
  794. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  795. __func__,
  796. bss_conf->assoc);
  797. ath9k_bss_assoc_info(sc, bss_conf);
  798. }
  799. }
  800. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  801. {
  802. u64 tsf;
  803. struct ath_softc *sc = hw->priv;
  804. struct ath_hal *ah = sc->sc_ah;
  805. tsf = ath9k_hw_gettsf64(ah);
  806. return tsf;
  807. }
  808. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  809. {
  810. struct ath_softc *sc = hw->priv;
  811. struct ath_hal *ah = sc->sc_ah;
  812. ath9k_hw_reset_tsf(ah);
  813. }
  814. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  815. enum ieee80211_ampdu_mlme_action action,
  816. const u8 *addr,
  817. u16 tid,
  818. u16 *ssn)
  819. {
  820. struct ath_softc *sc = hw->priv;
  821. int ret = 0;
  822. switch (action) {
  823. case IEEE80211_AMPDU_RX_START:
  824. ret = ath_rx_aggr_start(sc, addr, tid, ssn);
  825. if (ret < 0)
  826. DPRINTF(sc, ATH_DBG_FATAL,
  827. "%s: Unable to start RX aggregation\n",
  828. __func__);
  829. break;
  830. case IEEE80211_AMPDU_RX_STOP:
  831. ret = ath_rx_aggr_stop(sc, addr, tid);
  832. if (ret < 0)
  833. DPRINTF(sc, ATH_DBG_FATAL,
  834. "%s: Unable to stop RX aggregation\n",
  835. __func__);
  836. break;
  837. case IEEE80211_AMPDU_TX_START:
  838. ret = ath_tx_aggr_start(sc, addr, tid, ssn);
  839. if (ret < 0)
  840. DPRINTF(sc, ATH_DBG_FATAL,
  841. "%s: Unable to start TX aggregation\n",
  842. __func__);
  843. else
  844. ieee80211_start_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
  845. break;
  846. case IEEE80211_AMPDU_TX_STOP:
  847. ret = ath_tx_aggr_stop(sc, addr, tid);
  848. if (ret < 0)
  849. DPRINTF(sc, ATH_DBG_FATAL,
  850. "%s: Unable to stop TX aggregation\n",
  851. __func__);
  852. ieee80211_stop_tx_ba_cb_irqsafe(hw, (u8 *)addr, tid);
  853. break;
  854. default:
  855. DPRINTF(sc, ATH_DBG_FATAL,
  856. "%s: Unknown AMPDU action\n", __func__);
  857. }
  858. return ret;
  859. }
  860. static struct ieee80211_ops ath9k_ops = {
  861. .tx = ath9k_tx,
  862. .start = ath9k_start,
  863. .stop = ath9k_stop,
  864. .add_interface = ath9k_add_interface,
  865. .remove_interface = ath9k_remove_interface,
  866. .config = ath9k_config,
  867. .config_interface = ath9k_config_interface,
  868. .configure_filter = ath9k_configure_filter,
  869. .get_stats = NULL,
  870. .sta_notify = ath9k_sta_notify,
  871. .conf_tx = ath9k_conf_tx,
  872. .get_tx_stats = NULL,
  873. .bss_info_changed = ath9k_bss_info_changed,
  874. .set_tim = NULL,
  875. .set_key = ath9k_set_key,
  876. .hw_scan = NULL,
  877. .get_tkip_seq = NULL,
  878. .set_rts_threshold = NULL,
  879. .set_frag_threshold = NULL,
  880. .set_retry_limit = NULL,
  881. .get_tsf = ath9k_get_tsf,
  882. .reset_tsf = ath9k_reset_tsf,
  883. .tx_last_beacon = NULL,
  884. .ampdu_action = ath9k_ampdu_action
  885. };
  886. void ath_get_beaconconfig(struct ath_softc *sc,
  887. int if_id,
  888. struct ath_beacon_config *conf)
  889. {
  890. struct ieee80211_hw *hw = sc->hw;
  891. /* fill in beacon config data */
  892. conf->beacon_interval = hw->conf.beacon_int;
  893. conf->listen_interval = 100;
  894. conf->dtim_count = 1;
  895. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  896. }
  897. int ath_update_beacon(struct ath_softc *sc,
  898. int if_id,
  899. struct ath_beacon_offset *bo,
  900. struct sk_buff *skb,
  901. int mcast)
  902. {
  903. return 0;
  904. }
  905. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  906. struct ath_xmit_status *tx_status, struct ath_node *an)
  907. {
  908. struct ieee80211_hw *hw = sc->hw;
  909. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  910. DPRINTF(sc, ATH_DBG_XMIT,
  911. "%s: TX complete: skb: %p\n", __func__, skb);
  912. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  913. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  914. /* free driver's private data area of tx_info */
  915. if (tx_info->driver_data[0] != NULL)
  916. kfree(tx_info->driver_data[0]);
  917. tx_info->driver_data[0] = NULL;
  918. }
  919. if (tx_status->flags & ATH_TX_BAR) {
  920. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  921. tx_status->flags &= ~ATH_TX_BAR;
  922. }
  923. if (tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY)) {
  924. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  925. /* Frame was not ACKed, but an ACK was expected */
  926. tx_info->status.excessive_retries = 1;
  927. }
  928. } else {
  929. /* Frame was ACKed */
  930. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  931. }
  932. tx_info->status.retry_count = tx_status->retries;
  933. ieee80211_tx_status(hw, skb);
  934. if (an)
  935. ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
  936. }
  937. int ath__rx_indicate(struct ath_softc *sc,
  938. struct sk_buff *skb,
  939. struct ath_recv_status *status,
  940. u16 keyix)
  941. {
  942. struct ieee80211_hw *hw = sc->hw;
  943. struct ath_node *an = NULL;
  944. struct ieee80211_rx_status rx_status;
  945. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  946. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  947. int padsize;
  948. enum ATH_RX_TYPE st;
  949. /* see if any padding is done by the hw and remove it */
  950. if (hdrlen & 3) {
  951. padsize = hdrlen % 4;
  952. memmove(skb->data + padsize, skb->data, hdrlen);
  953. skb_pull(skb, padsize);
  954. }
  955. /* remove FCS before passing up to protocol stack */
  956. skb_trim(skb, (skb->len - FCS_LEN));
  957. /* Prepare rx status */
  958. ath9k_rx_prepare(sc, skb, status, &rx_status);
  959. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  960. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  961. rx_status.flag |= RX_FLAG_DECRYPTED;
  962. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  963. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  964. && skb->len >= hdrlen + 4) {
  965. keyix = skb->data[hdrlen + 3] >> 6;
  966. if (test_bit(keyix, sc->sc_keymap))
  967. rx_status.flag |= RX_FLAG_DECRYPTED;
  968. }
  969. spin_lock_bh(&sc->node_lock);
  970. an = ath_node_find(sc, hdr->addr2);
  971. spin_unlock_bh(&sc->node_lock);
  972. if (an) {
  973. ath_rx_input(sc, an,
  974. hw->conf.ht_conf.ht_supported,
  975. skb, status, &st);
  976. }
  977. if (!an || (st != ATH_RX_CONSUMED))
  978. __ieee80211_rx(hw, skb, &rx_status);
  979. return 0;
  980. }
  981. int ath_rx_subframe(struct ath_node *an,
  982. struct sk_buff *skb,
  983. struct ath_recv_status *status)
  984. {
  985. struct ath_softc *sc = an->an_sc;
  986. struct ieee80211_hw *hw = sc->hw;
  987. struct ieee80211_rx_status rx_status;
  988. /* Prepare rx status */
  989. ath9k_rx_prepare(sc, skb, status, &rx_status);
  990. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  991. rx_status.flag |= RX_FLAG_DECRYPTED;
  992. __ieee80211_rx(hw, skb, &rx_status);
  993. return 0;
  994. }
  995. enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc)
  996. {
  997. return sc->sc_ht_info.tx_chan_width;
  998. }
  999. static int ath_detach(struct ath_softc *sc)
  1000. {
  1001. struct ieee80211_hw *hw = sc->hw;
  1002. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  1003. /* Unregister hw */
  1004. ieee80211_unregister_hw(hw);
  1005. /* unregister Rate control */
  1006. ath_rate_control_unregister();
  1007. /* tx/rx cleanup */
  1008. ath_rx_cleanup(sc);
  1009. ath_tx_cleanup(sc);
  1010. /* Deinit */
  1011. ath_deinit(sc);
  1012. return 0;
  1013. }
  1014. static int ath_attach(u16 devid,
  1015. struct ath_softc *sc)
  1016. {
  1017. struct ieee80211_hw *hw = sc->hw;
  1018. int error = 0;
  1019. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  1020. error = ath_init(devid, sc);
  1021. if (error != 0)
  1022. return error;
  1023. /* Init nodes */
  1024. INIT_LIST_HEAD(&sc->node_list);
  1025. spin_lock_init(&sc->node_lock);
  1026. /* get mac address from hardware and set in mac80211 */
  1027. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  1028. /* setup channels and rates */
  1029. sc->sbands[IEEE80211_BAND_2GHZ].channels =
  1030. sc->channels[IEEE80211_BAND_2GHZ];
  1031. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  1032. sc->rates[IEEE80211_BAND_2GHZ];
  1033. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  1034. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  1035. /* Setup HT capabilities for 2.4Ghz*/
  1036. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
  1037. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1038. &sc->sbands[IEEE80211_BAND_2GHZ];
  1039. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
  1040. sc->sbands[IEEE80211_BAND_5GHZ].channels =
  1041. sc->channels[IEEE80211_BAND_5GHZ];
  1042. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  1043. sc->rates[IEEE80211_BAND_5GHZ];
  1044. sc->sbands[IEEE80211_BAND_5GHZ].band =
  1045. IEEE80211_BAND_5GHZ;
  1046. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  1047. /* Setup HT capabilities for 5Ghz*/
  1048. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
  1049. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1050. &sc->sbands[IEEE80211_BAND_5GHZ];
  1051. }
  1052. /* FIXME: Have to figure out proper hw init values later */
  1053. hw->queues = 4;
  1054. hw->ampdu_queues = 1;
  1055. /* Register rate control */
  1056. hw->rate_control_algorithm = "ath9k_rate_control";
  1057. error = ath_rate_control_register();
  1058. if (error != 0) {
  1059. DPRINTF(sc, ATH_DBG_FATAL,
  1060. "%s: Unable to register rate control "
  1061. "algorithm:%d\n", __func__, error);
  1062. ath_rate_control_unregister();
  1063. goto bad;
  1064. }
  1065. error = ieee80211_register_hw(hw);
  1066. if (error != 0) {
  1067. ath_rate_control_unregister();
  1068. goto bad;
  1069. }
  1070. /* initialize tx/rx engine */
  1071. error = ath_tx_init(sc, ATH_TXBUF);
  1072. if (error != 0)
  1073. goto bad1;
  1074. error = ath_rx_init(sc, ATH_RXBUF);
  1075. if (error != 0)
  1076. goto bad1;
  1077. return 0;
  1078. bad1:
  1079. ath_detach(sc);
  1080. bad:
  1081. return error;
  1082. }
  1083. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1084. {
  1085. void __iomem *mem;
  1086. struct ath_softc *sc;
  1087. struct ieee80211_hw *hw;
  1088. const char *athname;
  1089. u8 csz;
  1090. u32 val;
  1091. int ret = 0;
  1092. if (pci_enable_device(pdev))
  1093. return -EIO;
  1094. /* XXX 32-bit addressing only */
  1095. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1096. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1097. ret = -ENODEV;
  1098. goto bad;
  1099. }
  1100. /*
  1101. * Cache line size is used to size and align various
  1102. * structures used to communicate with the hardware.
  1103. */
  1104. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1105. if (csz == 0) {
  1106. /*
  1107. * Linux 2.4.18 (at least) writes the cache line size
  1108. * register as a 16-bit wide register which is wrong.
  1109. * We must have this setup properly for rx buffer
  1110. * DMA to work so force a reasonable value here if it
  1111. * comes up zero.
  1112. */
  1113. csz = L1_CACHE_BYTES / sizeof(u32);
  1114. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1115. }
  1116. /*
  1117. * The default setting of latency timer yields poor results,
  1118. * set it to the value used by other systems. It may be worth
  1119. * tweaking this setting more.
  1120. */
  1121. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1122. pci_set_master(pdev);
  1123. /*
  1124. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1125. * PCI Tx retries from interfering with C3 CPU state.
  1126. */
  1127. pci_read_config_dword(pdev, 0x40, &val);
  1128. if ((val & 0x0000ff00) != 0)
  1129. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1130. ret = pci_request_region(pdev, 0, "ath9k");
  1131. if (ret) {
  1132. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1133. ret = -ENODEV;
  1134. goto bad;
  1135. }
  1136. mem = pci_iomap(pdev, 0, 0);
  1137. if (!mem) {
  1138. printk(KERN_ERR "PCI memory map error\n") ;
  1139. ret = -EIO;
  1140. goto bad1;
  1141. }
  1142. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1143. if (hw == NULL) {
  1144. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1145. goto bad2;
  1146. }
  1147. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1148. IEEE80211_HW_NOISE_DBM;
  1149. SET_IEEE80211_DEV(hw, &pdev->dev);
  1150. pci_set_drvdata(pdev, hw);
  1151. sc = hw->priv;
  1152. sc->hw = hw;
  1153. sc->pdev = pdev;
  1154. sc->mem = mem;
  1155. if (ath_attach(id->device, sc) != 0) {
  1156. ret = -ENODEV;
  1157. goto bad3;
  1158. }
  1159. /* setup interrupt service routine */
  1160. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1161. printk(KERN_ERR "%s: request_irq failed\n",
  1162. wiphy_name(hw->wiphy));
  1163. ret = -EIO;
  1164. goto bad4;
  1165. }
  1166. athname = ath9k_hw_probe(id->vendor, id->device);
  1167. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1168. wiphy_name(hw->wiphy),
  1169. athname ? athname : "Atheros ???",
  1170. (unsigned long)mem, pdev->irq);
  1171. return 0;
  1172. bad4:
  1173. ath_detach(sc);
  1174. bad3:
  1175. ieee80211_free_hw(hw);
  1176. bad2:
  1177. pci_iounmap(pdev, mem);
  1178. bad1:
  1179. pci_release_region(pdev, 0);
  1180. bad:
  1181. pci_disable_device(pdev);
  1182. return ret;
  1183. }
  1184. static void ath_pci_remove(struct pci_dev *pdev)
  1185. {
  1186. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1187. struct ath_softc *sc = hw->priv;
  1188. if (pdev->irq)
  1189. free_irq(pdev->irq, sc);
  1190. ath_detach(sc);
  1191. pci_iounmap(pdev, sc->mem);
  1192. pci_release_region(pdev, 0);
  1193. pci_disable_device(pdev);
  1194. ieee80211_free_hw(hw);
  1195. }
  1196. #ifdef CONFIG_PM
  1197. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1198. {
  1199. pci_save_state(pdev);
  1200. pci_disable_device(pdev);
  1201. pci_set_power_state(pdev, 3);
  1202. return 0;
  1203. }
  1204. static int ath_pci_resume(struct pci_dev *pdev)
  1205. {
  1206. u32 val;
  1207. int err;
  1208. err = pci_enable_device(pdev);
  1209. if (err)
  1210. return err;
  1211. pci_restore_state(pdev);
  1212. /*
  1213. * Suspend/Resume resets the PCI configuration space, so we have to
  1214. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1215. * PCI Tx retries from interfering with C3 CPU state
  1216. */
  1217. pci_read_config_dword(pdev, 0x40, &val);
  1218. if ((val & 0x0000ff00) != 0)
  1219. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1220. return 0;
  1221. }
  1222. #endif /* CONFIG_PM */
  1223. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1224. static struct pci_driver ath_pci_driver = {
  1225. .name = "ath9k",
  1226. .id_table = ath_pci_id_table,
  1227. .probe = ath_pci_probe,
  1228. .remove = ath_pci_remove,
  1229. #ifdef CONFIG_PM
  1230. .suspend = ath_pci_suspend,
  1231. .resume = ath_pci_resume,
  1232. #endif /* CONFIG_PM */
  1233. };
  1234. static int __init init_ath_pci(void)
  1235. {
  1236. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1237. if (pci_register_driver(&ath_pci_driver) < 0) {
  1238. printk(KERN_ERR
  1239. "ath_pci: No devices found, driver not installed.\n");
  1240. pci_unregister_driver(&ath_pci_driver);
  1241. return -ENODEV;
  1242. }
  1243. return 0;
  1244. }
  1245. module_init(init_ath_pci);
  1246. static void __exit exit_ath_pci(void)
  1247. {
  1248. pci_unregister_driver(&ath_pci_driver);
  1249. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1250. }
  1251. module_exit(exit_ath_pci);