ezbrd.c 18 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf518/boards/ezbrd.c
  3. * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
  4. * Author: Bryan Wu <cooloney@kernel.org>
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2008 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/irq.h>
  39. #include <linux/interrupt.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/reboot.h>
  43. #include <asm/portmux.h>
  44. #include <asm/dpmc.h>
  45. #include <asm/bfin_sdh.h>
  46. #include <linux/spi/ad7877.h>
  47. #include <net/dsa.h>
  48. /*
  49. * Name the Board for the /proc/cpuinfo
  50. */
  51. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  52. /*
  53. * Driver needs to know address, irq and flag pin.
  54. */
  55. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  56. static struct mtd_partition ezbrd_partitions[] = {
  57. {
  58. .name = "bootloader(nor)",
  59. .size = 0x40000,
  60. .offset = 0,
  61. }, {
  62. .name = "linux kernel(nor)",
  63. .size = 0x1C0000,
  64. .offset = MTDPART_OFS_APPEND,
  65. }, {
  66. .name = "file system(nor)",
  67. .size = MTDPART_SIZ_FULL,
  68. .offset = MTDPART_OFS_APPEND,
  69. }
  70. };
  71. static struct physmap_flash_data ezbrd_flash_data = {
  72. .width = 2,
  73. .parts = ezbrd_partitions,
  74. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  75. };
  76. static struct resource ezbrd_flash_resource = {
  77. .start = 0x20000000,
  78. .end = 0x203fffff,
  79. .flags = IORESOURCE_MEM,
  80. };
  81. static struct platform_device ezbrd_flash_device = {
  82. .name = "physmap-flash",
  83. .id = 0,
  84. .dev = {
  85. .platform_data = &ezbrd_flash_data,
  86. },
  87. .num_resources = 1,
  88. .resource = &ezbrd_flash_resource,
  89. };
  90. #endif
  91. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  92. static struct platform_device rtc_device = {
  93. .name = "rtc-bfin",
  94. .id = -1,
  95. };
  96. #endif
  97. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  98. static struct platform_device bfin_mii_bus = {
  99. .name = "bfin_mii_bus",
  100. };
  101. static struct platform_device bfin_mac_device = {
  102. .name = "bfin_mac",
  103. .dev.platform_data = &bfin_mii_bus,
  104. };
  105. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  106. static struct dsa_platform_data ksz8893m_switch_data = {
  107. .mii_bus = &bfin_mii_bus.dev,
  108. .netdev = &bfin_mac_device.dev,
  109. .port_names[0] = NULL,
  110. .port_names[1] = "eth%d",
  111. .port_names[2] = "eth%d",
  112. .port_names[3] = "cpu",
  113. };
  114. static struct platform_device ksz8893m_switch_device = {
  115. .name = "dsa",
  116. .id = 0,
  117. .num_resources = 0,
  118. .dev.platform_data = &ksz8893m_switch_data,
  119. };
  120. #endif
  121. #endif
  122. #if defined(CONFIG_MTD_M25P80) \
  123. || defined(CONFIG_MTD_M25P80_MODULE)
  124. static struct mtd_partition bfin_spi_flash_partitions[] = {
  125. {
  126. .name = "bootloader(spi)",
  127. .size = 0x00040000,
  128. .offset = 0,
  129. .mask_flags = MTD_CAP_ROM
  130. }, {
  131. .name = "linux kernel(spi)",
  132. .size = MTDPART_SIZ_FULL,
  133. .offset = MTDPART_OFS_APPEND,
  134. }
  135. };
  136. static struct flash_platform_data bfin_spi_flash_data = {
  137. .name = "m25p80",
  138. .parts = bfin_spi_flash_partitions,
  139. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  140. .type = "m25p16",
  141. };
  142. /* SPI flash chip (m25p64) */
  143. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  144. .enable_dma = 0, /* use dma transfer with this chip*/
  145. .bits_per_word = 8,
  146. };
  147. #endif
  148. #if defined(CONFIG_SPI_ADC_BF533) \
  149. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  150. /* SPI ADC chip */
  151. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  152. .enable_dma = 1, /* use dma transfer with this chip*/
  153. .bits_per_word = 16,
  154. };
  155. #endif
  156. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  157. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  158. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  159. /* SPI SWITCH CHIP */
  160. static struct bfin5xx_spi_chip spi_switch_info = {
  161. .enable_dma = 0,
  162. .bits_per_word = 8,
  163. };
  164. #endif
  165. #endif
  166. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  167. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  168. .enable_dma = 1,
  169. .bits_per_word = 8,
  170. };
  171. #endif
  172. #if defined(CONFIG_PBX)
  173. static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
  174. .ctl_reg = 0x4, /* send zero */
  175. .enable_dma = 0,
  176. .bits_per_word = 8,
  177. .cs_change_per_word = 1,
  178. };
  179. #endif
  180. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  181. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  182. .enable_dma = 0,
  183. .bits_per_word = 16,
  184. };
  185. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  186. .model = 7877,
  187. .vref_delay_usecs = 50, /* internal, no capacitor */
  188. .x_plate_ohms = 419,
  189. .y_plate_ohms = 486,
  190. .pressure_max = 1000,
  191. .pressure_min = 0,
  192. .stopacq_polarity = 1,
  193. .first_conversion_delay = 3,
  194. .acquisition_time = 1,
  195. .averaging = 1,
  196. .pen_down_acc_interval = 1,
  197. };
  198. #endif
  199. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  200. && defined(CONFIG_SND_SOC_WM8731_SPI)
  201. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  202. .enable_dma = 0,
  203. .bits_per_word = 16,
  204. };
  205. #endif
  206. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  207. static struct bfin5xx_spi_chip spidev_chip_info = {
  208. .enable_dma = 0,
  209. .bits_per_word = 8,
  210. };
  211. #endif
  212. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  213. #if defined(CONFIG_MTD_M25P80) \
  214. || defined(CONFIG_MTD_M25P80_MODULE)
  215. {
  216. /* the modalias must be the same as spi device driver name */
  217. .modalias = "m25p80", /* Name of spi_driver for this device */
  218. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  219. .bus_num = 0, /* Framework bus number */
  220. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  221. .platform_data = &bfin_spi_flash_data,
  222. .controller_data = &spi_flash_chip_info,
  223. .mode = SPI_MODE_3,
  224. },
  225. #endif
  226. #if defined(CONFIG_SPI_ADC_BF533) \
  227. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  228. {
  229. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  230. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  231. .bus_num = 0, /* Framework bus number */
  232. .chip_select = 1, /* Framework chip select. */
  233. .platform_data = NULL, /* No spi_driver specific config */
  234. .controller_data = &spi_adc_chip_info,
  235. },
  236. #endif
  237. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  238. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  239. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  240. {
  241. .modalias = "ksz8893m",
  242. .max_speed_hz = 5000000,
  243. .bus_num = 0,
  244. .chip_select = 1,
  245. .platform_data = NULL,
  246. .controller_data = &spi_switch_info,
  247. .mode = SPI_MODE_3,
  248. },
  249. #endif
  250. #endif
  251. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  252. {
  253. .modalias = "spi_mmc_dummy",
  254. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  255. .bus_num = 0,
  256. .chip_select = 0,
  257. .platform_data = NULL,
  258. .controller_data = &spi_mmc_chip_info,
  259. .mode = SPI_MODE_3,
  260. },
  261. {
  262. .modalias = "spi_mmc",
  263. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  264. .bus_num = 0,
  265. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  266. .platform_data = NULL,
  267. .controller_data = &spi_mmc_chip_info,
  268. .mode = SPI_MODE_3,
  269. },
  270. #endif
  271. #if defined(CONFIG_PBX)
  272. {
  273. .modalias = "fxs-spi",
  274. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  275. .bus_num = 0,
  276. .chip_select = 8 - CONFIG_J11_JUMPER,
  277. .controller_data = &spi_si3xxx_chip_info,
  278. .mode = SPI_MODE_3,
  279. },
  280. {
  281. .modalias = "fxo-spi",
  282. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  283. .bus_num = 0,
  284. .chip_select = 8 - CONFIG_J19_JUMPER,
  285. .controller_data = &spi_si3xxx_chip_info,
  286. .mode = SPI_MODE_3,
  287. },
  288. #endif
  289. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  290. {
  291. .modalias = "ad7877",
  292. .platform_data = &bfin_ad7877_ts_info,
  293. .irq = IRQ_PF8,
  294. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  295. .bus_num = 0,
  296. .chip_select = 2,
  297. .controller_data = &spi_ad7877_chip_info,
  298. },
  299. #endif
  300. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  301. && defined(CONFIG_SND_SOC_WM8731_SPI)
  302. {
  303. .modalias = "wm8731",
  304. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  305. .bus_num = 0,
  306. .chip_select = 5,
  307. .controller_data = &spi_wm8731_chip_info,
  308. .mode = SPI_MODE_0,
  309. },
  310. #endif
  311. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  312. {
  313. .modalias = "spidev",
  314. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  315. .bus_num = 0,
  316. .chip_select = 1,
  317. .controller_data = &spidev_chip_info,
  318. },
  319. #endif
  320. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  321. {
  322. .modalias = "bfin-lq035q1-spi",
  323. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  324. .bus_num = 0,
  325. .chip_select = 1,
  326. .controller_data = &lq035q1_spi_chip_info,
  327. .mode = SPI_CPHA | SPI_CPOL,
  328. },
  329. #endif
  330. };
  331. /* SPI controller data */
  332. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  333. /* SPI (0) */
  334. static struct bfin5xx_spi_master bfin_spi0_info = {
  335. .num_chipselect = 5,
  336. .enable_dma = 1, /* master has the ability to do dma transfer */
  337. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  338. };
  339. static struct resource bfin_spi0_resource[] = {
  340. [0] = {
  341. .start = SPI0_REGBASE,
  342. .end = SPI0_REGBASE + 0xFF,
  343. .flags = IORESOURCE_MEM,
  344. },
  345. [1] = {
  346. .start = CH_SPI0,
  347. .end = CH_SPI0,
  348. .flags = IORESOURCE_IRQ,
  349. },
  350. };
  351. static struct platform_device bfin_spi0_device = {
  352. .name = "bfin-spi",
  353. .id = 0, /* Bus number */
  354. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  355. .resource = bfin_spi0_resource,
  356. .dev = {
  357. .platform_data = &bfin_spi0_info, /* Passed to driver */
  358. },
  359. };
  360. /* SPI (1) */
  361. static struct bfin5xx_spi_master bfin_spi1_info = {
  362. .num_chipselect = 5,
  363. .enable_dma = 1, /* master has the ability to do dma transfer */
  364. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  365. };
  366. static struct resource bfin_spi1_resource[] = {
  367. [0] = {
  368. .start = SPI1_REGBASE,
  369. .end = SPI1_REGBASE + 0xFF,
  370. .flags = IORESOURCE_MEM,
  371. },
  372. [1] = {
  373. .start = CH_SPI1,
  374. .end = CH_SPI1,
  375. .flags = IORESOURCE_IRQ,
  376. },
  377. };
  378. static struct platform_device bfin_spi1_device = {
  379. .name = "bfin-spi",
  380. .id = 1, /* Bus number */
  381. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  382. .resource = bfin_spi1_resource,
  383. .dev = {
  384. .platform_data = &bfin_spi1_info, /* Passed to driver */
  385. },
  386. };
  387. #endif /* spi master and devices */
  388. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  389. static struct resource bfin_uart_resources[] = {
  390. #ifdef CONFIG_SERIAL_BFIN_UART0
  391. {
  392. .start = 0xFFC00400,
  393. .end = 0xFFC004FF,
  394. .flags = IORESOURCE_MEM,
  395. },
  396. #endif
  397. #ifdef CONFIG_SERIAL_BFIN_UART1
  398. {
  399. .start = 0xFFC02000,
  400. .end = 0xFFC020FF,
  401. .flags = IORESOURCE_MEM,
  402. },
  403. #endif
  404. };
  405. static struct platform_device bfin_uart_device = {
  406. .name = "bfin-uart",
  407. .id = 1,
  408. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  409. .resource = bfin_uart_resources,
  410. };
  411. #endif
  412. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  413. #ifdef CONFIG_BFIN_SIR0
  414. static struct resource bfin_sir0_resources[] = {
  415. {
  416. .start = 0xFFC00400,
  417. .end = 0xFFC004FF,
  418. .flags = IORESOURCE_MEM,
  419. },
  420. {
  421. .start = IRQ_UART0_RX,
  422. .end = IRQ_UART0_RX+1,
  423. .flags = IORESOURCE_IRQ,
  424. },
  425. {
  426. .start = CH_UART0_RX,
  427. .end = CH_UART0_RX+1,
  428. .flags = IORESOURCE_DMA,
  429. },
  430. };
  431. static struct platform_device bfin_sir0_device = {
  432. .name = "bfin_sir",
  433. .id = 0,
  434. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  435. .resource = bfin_sir0_resources,
  436. };
  437. #endif
  438. #ifdef CONFIG_BFIN_SIR1
  439. static struct resource bfin_sir1_resources[] = {
  440. {
  441. .start = 0xFFC02000,
  442. .end = 0xFFC020FF,
  443. .flags = IORESOURCE_MEM,
  444. },
  445. {
  446. .start = IRQ_UART1_RX,
  447. .end = IRQ_UART1_RX+1,
  448. .flags = IORESOURCE_IRQ,
  449. },
  450. {
  451. .start = CH_UART1_RX,
  452. .end = CH_UART1_RX+1,
  453. .flags = IORESOURCE_DMA,
  454. },
  455. };
  456. static struct platform_device bfin_sir1_device = {
  457. .name = "bfin_sir",
  458. .id = 1,
  459. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  460. .resource = bfin_sir1_resources,
  461. };
  462. #endif
  463. #endif
  464. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  465. static struct resource bfin_twi0_resource[] = {
  466. [0] = {
  467. .start = TWI0_REGBASE,
  468. .end = TWI0_REGBASE,
  469. .flags = IORESOURCE_MEM,
  470. },
  471. [1] = {
  472. .start = IRQ_TWI,
  473. .end = IRQ_TWI,
  474. .flags = IORESOURCE_IRQ,
  475. },
  476. };
  477. static struct platform_device i2c_bfin_twi_device = {
  478. .name = "i2c-bfin-twi",
  479. .id = 0,
  480. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  481. .resource = bfin_twi0_resource,
  482. };
  483. #endif
  484. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  485. #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
  486. {
  487. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  488. },
  489. #endif
  490. #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
  491. {
  492. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  493. .irq = IRQ_PF8,
  494. },
  495. #endif
  496. };
  497. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  498. static struct platform_device bfin_sport0_uart_device = {
  499. .name = "bfin-sport-uart",
  500. .id = 0,
  501. };
  502. static struct platform_device bfin_sport1_uart_device = {
  503. .name = "bfin-sport-uart",
  504. .id = 1,
  505. };
  506. #endif
  507. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  508. #include <linux/input.h>
  509. #include <linux/gpio_keys.h>
  510. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  511. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  512. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  513. };
  514. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  515. .buttons = bfin_gpio_keys_table,
  516. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  517. };
  518. static struct platform_device bfin_device_gpiokeys = {
  519. .name = "gpio-keys",
  520. .dev = {
  521. .platform_data = &bfin_gpio_keys_data,
  522. },
  523. };
  524. #endif
  525. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  526. static struct bfin_sd_host bfin_sdh_data = {
  527. .dma_chan = CH_RSI,
  528. .irq_int0 = IRQ_RSI_INT0,
  529. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  530. };
  531. static struct platform_device bf51x_sdh_device = {
  532. .name = "bfin-sdh",
  533. .id = 0,
  534. .dev = {
  535. .platform_data = &bfin_sdh_data,
  536. },
  537. };
  538. #endif
  539. static struct resource bfin_gpios_resources = {
  540. .start = 0,
  541. .end = MAX_BLACKFIN_GPIOS - 1,
  542. .flags = IORESOURCE_IRQ,
  543. };
  544. static struct platform_device bfin_gpios_device = {
  545. .name = "simple-gpio",
  546. .id = -1,
  547. .num_resources = 1,
  548. .resource = &bfin_gpios_resources,
  549. };
  550. static const unsigned int cclk_vlev_datasheet[] =
  551. {
  552. VRPAIR(VLEV_100, 400000000),
  553. VRPAIR(VLEV_105, 426000000),
  554. VRPAIR(VLEV_110, 500000000),
  555. VRPAIR(VLEV_115, 533000000),
  556. VRPAIR(VLEV_120, 600000000),
  557. };
  558. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  559. .tuple_tab = cclk_vlev_datasheet,
  560. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  561. .vr_settling_time = 25 /* us */,
  562. };
  563. static struct platform_device bfin_dpmc = {
  564. .name = "bfin dpmc",
  565. .dev = {
  566. .platform_data = &bfin_dmpc_vreg_data,
  567. },
  568. };
  569. static struct platform_device *stamp_devices[] __initdata = {
  570. &bfin_dpmc,
  571. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  572. &rtc_device,
  573. #endif
  574. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  575. &bfin_mii_bus,
  576. &bfin_mac_device,
  577. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  578. &ksz8893m_switch_device,
  579. #endif
  580. #endif
  581. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  582. &bfin_spi0_device,
  583. &bfin_spi1_device,
  584. #endif
  585. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  586. &bfin_uart_device,
  587. #endif
  588. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  589. #ifdef CONFIG_BFIN_SIR0
  590. &bfin_sir0_device,
  591. #endif
  592. #ifdef CONFIG_BFIN_SIR1
  593. &bfin_sir1_device,
  594. #endif
  595. #endif
  596. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  597. &i2c_bfin_twi_device,
  598. #endif
  599. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  600. &bfin_sport0_uart_device,
  601. &bfin_sport1_uart_device,
  602. #endif
  603. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  604. &bfin_device_gpiokeys,
  605. #endif
  606. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  607. &bf51x_sdh_device,
  608. #endif
  609. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  610. &ezbrd_flash_device,
  611. #endif
  612. &bfin_gpios_device,
  613. };
  614. static int __init ezbrd_init(void)
  615. {
  616. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  617. i2c_register_board_info(0, bfin_i2c_board_info,
  618. ARRAY_SIZE(bfin_i2c_board_info));
  619. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  620. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  621. return 0;
  622. }
  623. arch_initcall(ezbrd_init);
  624. void native_machine_restart(char *cmd)
  625. {
  626. /* workaround reboot hang when booting from SPI */
  627. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  628. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  629. }
  630. void bfin_get_ether_addr(char *addr)
  631. {
  632. /* the MAC is stored in OTP memory page 0xDF */
  633. u32 ret;
  634. u64 otp_mac;
  635. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  636. ret = otp_read(0xDF, 0x00, &otp_mac);
  637. if (!(ret & 0x1)) {
  638. char *otp_mac_p = (char *)&otp_mac;
  639. for (ret = 0; ret < 6; ++ret)
  640. addr[ret] = otp_mac_p[5 - ret];
  641. }
  642. }
  643. EXPORT_SYMBOL(bfin_get_ether_addr);