qla_mr.c 93 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t __iomem *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. uint32_t __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state > pci_channel_io_frozen) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "error_state is greater than pci_channel_io_frozen, "
  53. "exiting.\n");
  54. return QLA_FUNCTION_TIMEOUT;
  55. }
  56. if (vha->device_flags & DFLG_DEV_FAILED) {
  57. ql_log(ql_log_warn, vha, 0x115f,
  58. "Device in failed state, exiting.\n");
  59. return QLA_FUNCTION_TIMEOUT;
  60. }
  61. reg = ha->iobase;
  62. io_lock_on = base_vha->flags.init_done;
  63. rval = QLA_SUCCESS;
  64. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  65. if (ha->flags.pci_channel_io_perm_failure) {
  66. ql_log(ql_log_warn, vha, 0x1175,
  67. "Perm failure on EEH timeout MBX, exiting.\n");
  68. return QLA_FUNCTION_TIMEOUT;
  69. }
  70. if (ha->flags.isp82xx_fw_hung) {
  71. /* Setting Link-Down error */
  72. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  73. ql_log(ql_log_warn, vha, 0x1176,
  74. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  75. rval = QLA_FUNCTION_FAILED;
  76. goto premature_exit;
  77. }
  78. /*
  79. * Wait for active mailbox commands to finish by waiting at most tov
  80. * seconds. This is to serialize actual issuing of mailbox cmds during
  81. * non ISP abort time.
  82. */
  83. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  84. /* Timeout occurred. Return error. */
  85. ql_log(ql_log_warn, vha, 0x1177,
  86. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  87. mcp->mb[0]);
  88. return QLA_FUNCTION_TIMEOUT;
  89. }
  90. ha->flags.mbox_busy = 1;
  91. /* Save mailbox command for debug */
  92. ha->mcp32 = mcp;
  93. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  94. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. /* Load mailbox registers. */
  97. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (mboxes & BIT_0)
  103. WRT_REG_DWORD(optr, *iptr);
  104. mboxes >>= 1;
  105. optr++;
  106. iptr++;
  107. }
  108. /* Issue set host interrupt command to send cmd out. */
  109. ha->flags.mbox_int = 0;
  110. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  111. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  112. (uint8_t *)mcp->mb, 16);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  114. ((uint8_t *)mcp->mb + 0x10), 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  116. ((uint8_t *)mcp->mb + 0x20), 8);
  117. /* Unlock mbx registers and wait for interrupt */
  118. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  119. "Going to unlock irq & waiting for interrupts. "
  120. "jiffies=%lx.\n", jiffies);
  121. /* Wait for mbx cmd completion until timeout */
  122. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  123. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  124. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  125. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  127. } else {
  128. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  129. "Cmd=%x Polling Mode.\n", command);
  130. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  131. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  132. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  133. while (!ha->flags.mbox_int) {
  134. if (time_after(jiffies, wait_time))
  135. break;
  136. /* Check for pending interrupts. */
  137. qla2x00_poll(ha->rsp_q_map[0]);
  138. if (!ha->flags.mbox_int &&
  139. !(IS_QLA2200(ha) &&
  140. command == MBC_LOAD_RISC_RAM_EXTENDED))
  141. usleep_range(10000, 11000);
  142. } /* while */
  143. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  144. "Waited %d sec.\n",
  145. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  146. }
  147. /* Check whether we timed out */
  148. if (ha->flags.mbox_int) {
  149. uint32_t *iptr2;
  150. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  151. "Cmd=%x completed.\n", command);
  152. /* Got interrupt. Clear the flag. */
  153. ha->flags.mbox_int = 0;
  154. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  155. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  156. rval = QLA_FUNCTION_FAILED;
  157. /* Load return mailbox registers. */
  158. iptr2 = mcp->mb;
  159. iptr = (uint32_t *)&ha->mailbox_out32[0];
  160. mboxes = mcp->in_mb;
  161. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  162. if (mboxes & BIT_0)
  163. *iptr2 = *iptr;
  164. mboxes >>= 1;
  165. iptr2++;
  166. iptr++;
  167. }
  168. } else {
  169. rval = QLA_FUNCTION_TIMEOUT;
  170. }
  171. ha->flags.mbox_busy = 0;
  172. /* Clean up */
  173. ha->mcp32 = NULL;
  174. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  175. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  176. "checking for additional resp interrupt.\n");
  177. /* polling mode for non isp_abort commands. */
  178. qla2x00_poll(ha->rsp_q_map[0]);
  179. }
  180. if (rval == QLA_FUNCTION_TIMEOUT &&
  181. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  182. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  183. ha->flags.eeh_busy) {
  184. /* not in dpc. schedule it for dpc to take over. */
  185. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  186. "Timeout, schedule isp_abort_needed.\n");
  187. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  188. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  189. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  190. ql_log(ql_log_info, base_vha, 0x115e,
  191. "Mailbox cmd timeout occurred, cmd=0x%x, "
  192. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  193. "abort.\n", command, mcp->mb[0],
  194. ha->flags.eeh_busy);
  195. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  196. qla2xxx_wake_dpc(vha);
  197. }
  198. } else if (!abort_active) {
  199. /* call abort directly since we are in the DPC thread */
  200. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  201. "Timeout, calling abort_isp.\n");
  202. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  203. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  204. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  205. ql_log(ql_log_info, base_vha, 0x1161,
  206. "Mailbox cmd timeout occurred, cmd=0x%x, "
  207. "mb[0]=0x%x. Scheduling ISP abort ",
  208. command, mcp->mb[0]);
  209. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  210. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  211. if (ha->isp_ops->abort_isp(vha)) {
  212. /* Failed. retry later. */
  213. set_bit(ISP_ABORT_NEEDED,
  214. &vha->dpc_flags);
  215. }
  216. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  217. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  218. "Finished abort_isp.\n");
  219. }
  220. }
  221. }
  222. premature_exit:
  223. /* Allow next mbx cmd to come in. */
  224. complete(&ha->mbx_cmd_comp);
  225. if (rval) {
  226. ql_log(ql_log_warn, base_vha, 0x1163,
  227. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  228. "mb[3]=%x, cmd=%x ****.\n",
  229. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  230. } else {
  231. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  232. }
  233. return rval;
  234. }
  235. /*
  236. * qlafx00_driver_shutdown
  237. * Indicate a driver shutdown to firmware.
  238. *
  239. * Input:
  240. * ha = adapter block pointer.
  241. *
  242. * Returns:
  243. * local function return status code.
  244. *
  245. * Context:
  246. * Kernel context.
  247. */
  248. int
  249. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  250. {
  251. int rval;
  252. struct mbx_cmd_32 mc;
  253. struct mbx_cmd_32 *mcp = &mc;
  254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  255. "Entered %s.\n", __func__);
  256. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  257. mcp->out_mb = MBX_0;
  258. mcp->in_mb = MBX_0;
  259. if (tmo)
  260. mcp->tov = tmo;
  261. else
  262. mcp->tov = MBX_TOV_SECONDS;
  263. mcp->flags = 0;
  264. rval = qlafx00_mailbox_command(vha, mcp);
  265. if (rval != QLA_SUCCESS) {
  266. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  267. "Failed=%x.\n", rval);
  268. } else {
  269. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  270. "Done %s.\n", __func__);
  271. }
  272. return rval;
  273. }
  274. /*
  275. * qlafx00_get_firmware_state
  276. * Get adapter firmware state.
  277. *
  278. * Input:
  279. * ha = adapter block pointer.
  280. * TARGET_QUEUE_LOCK must be released.
  281. * ADAPTER_STATE_LOCK must be released.
  282. *
  283. * Returns:
  284. * qla7xxx local function return status code.
  285. *
  286. * Context:
  287. * Kernel context.
  288. */
  289. static int
  290. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  291. {
  292. int rval;
  293. struct mbx_cmd_32 mc;
  294. struct mbx_cmd_32 *mcp = &mc;
  295. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  296. "Entered %s.\n", __func__);
  297. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  298. mcp->out_mb = MBX_0;
  299. mcp->in_mb = MBX_1|MBX_0;
  300. mcp->tov = MBX_TOV_SECONDS;
  301. mcp->flags = 0;
  302. rval = qlafx00_mailbox_command(vha, mcp);
  303. /* Return firmware states. */
  304. states[0] = mcp->mb[1];
  305. if (rval != QLA_SUCCESS) {
  306. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  307. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  308. } else {
  309. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  310. "Done %s.\n", __func__);
  311. }
  312. return rval;
  313. }
  314. /*
  315. * qlafx00_init_firmware
  316. * Initialize adapter firmware.
  317. *
  318. * Input:
  319. * ha = adapter block pointer.
  320. * dptr = Initialization control block pointer.
  321. * size = size of initialization control block.
  322. * TARGET_QUEUE_LOCK must be released.
  323. * ADAPTER_STATE_LOCK must be released.
  324. *
  325. * Returns:
  326. * qlafx00 local function return status code.
  327. *
  328. * Context:
  329. * Kernel context.
  330. */
  331. int
  332. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  333. {
  334. int rval;
  335. struct mbx_cmd_32 mc;
  336. struct mbx_cmd_32 *mcp = &mc;
  337. struct qla_hw_data *ha = vha->hw;
  338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  339. "Entered %s.\n", __func__);
  340. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  341. mcp->mb[1] = 0;
  342. mcp->mb[2] = MSD(ha->init_cb_dma);
  343. mcp->mb[3] = LSD(ha->init_cb_dma);
  344. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  345. mcp->in_mb = MBX_0;
  346. mcp->buf_size = size;
  347. mcp->flags = MBX_DMA_OUT;
  348. mcp->tov = MBX_TOV_SECONDS;
  349. rval = qlafx00_mailbox_command(vha, mcp);
  350. if (rval != QLA_SUCCESS) {
  351. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  352. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  353. } else {
  354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  355. "Done %s.\n", __func__);
  356. }
  357. return rval;
  358. }
  359. /*
  360. * qlafx00_mbx_reg_test
  361. */
  362. static int
  363. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  364. {
  365. int rval;
  366. struct mbx_cmd_32 mc;
  367. struct mbx_cmd_32 *mcp = &mc;
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  369. "Entered %s.\n", __func__);
  370. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  371. mcp->mb[1] = 0xAAAA;
  372. mcp->mb[2] = 0x5555;
  373. mcp->mb[3] = 0xAA55;
  374. mcp->mb[4] = 0x55AA;
  375. mcp->mb[5] = 0xA5A5;
  376. mcp->mb[6] = 0x5A5A;
  377. mcp->mb[7] = 0x2525;
  378. mcp->mb[8] = 0xBBBB;
  379. mcp->mb[9] = 0x6666;
  380. mcp->mb[10] = 0xBB66;
  381. mcp->mb[11] = 0x66BB;
  382. mcp->mb[12] = 0xB6B6;
  383. mcp->mb[13] = 0x6B6B;
  384. mcp->mb[14] = 0x3636;
  385. mcp->mb[15] = 0xCCCC;
  386. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  387. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  388. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->buf_size = 0;
  391. mcp->flags = MBX_DMA_OUT;
  392. mcp->tov = MBX_TOV_SECONDS;
  393. rval = qlafx00_mailbox_command(vha, mcp);
  394. if (rval == QLA_SUCCESS) {
  395. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  396. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  397. rval = QLA_FUNCTION_FAILED;
  398. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  399. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  400. rval = QLA_FUNCTION_FAILED;
  401. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  402. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  403. rval = QLA_FUNCTION_FAILED;
  404. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  405. mcp->mb[31] != 0xCCCC)
  406. rval = QLA_FUNCTION_FAILED;
  407. }
  408. if (rval != QLA_SUCCESS) {
  409. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  411. } else {
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  413. "Done %s.\n", __func__);
  414. }
  415. return rval;
  416. }
  417. /**
  418. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  419. * @ha: HA context
  420. *
  421. * Returns 0 on success.
  422. */
  423. int
  424. qlafx00_pci_config(scsi_qla_host_t *vha)
  425. {
  426. uint16_t w;
  427. struct qla_hw_data *ha = vha->hw;
  428. pci_set_master(ha->pdev);
  429. pci_try_set_mwi(ha->pdev);
  430. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  431. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  432. w &= ~PCI_COMMAND_INTX_DISABLE;
  433. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  434. /* PCIe -- adjust Maximum Read Request Size (2048). */
  435. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  436. pcie_set_readrq(ha->pdev, 2048);
  437. ha->chip_revision = ha->pdev->revision;
  438. return QLA_SUCCESS;
  439. }
  440. /**
  441. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  442. * @ha: HA context
  443. *
  444. */
  445. static inline void
  446. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  447. {
  448. unsigned long flags = 0;
  449. struct qla_hw_data *ha = vha->hw;
  450. int i, core;
  451. uint32_t cnt;
  452. /* Set all 4 cores in reset */
  453. for (i = 0; i < 4; i++) {
  454. QLAFX00_SET_HBA_SOC_REG(ha,
  455. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  456. }
  457. /* Set all 4 core Clock gating control */
  458. for (i = 0; i < 4; i++) {
  459. QLAFX00_SET_HBA_SOC_REG(ha,
  460. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  461. }
  462. /* Reset all units in Fabric */
  463. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x11F0101));
  464. /* Reset all interrupt control registers */
  465. for (i = 0; i < 115; i++) {
  466. QLAFX00_SET_HBA_SOC_REG(ha,
  467. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  468. }
  469. /* Reset Timers control registers. per core */
  470. for (core = 0; core < 4; core++)
  471. for (i = 0; i < 8; i++)
  472. QLAFX00_SET_HBA_SOC_REG(ha,
  473. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  474. /* Reset per core IRQ ack register */
  475. for (core = 0; core < 4; core++)
  476. QLAFX00_SET_HBA_SOC_REG(ha,
  477. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  478. /* Set Fabric control and config to defaults */
  479. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  480. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  481. spin_lock_irqsave(&ha->hardware_lock, flags);
  482. /* Kick in Fabric units */
  483. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  484. /* Kick in Core0 to start boot process */
  485. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  486. /* Wait 10secs for soft-reset to complete. */
  487. for (cnt = 10; cnt; cnt--) {
  488. msleep(1000);
  489. barrier();
  490. }
  491. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  492. }
  493. /**
  494. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  495. * @ha: HA context
  496. *
  497. * Returns 0 on success.
  498. */
  499. void
  500. qlafx00_soft_reset(scsi_qla_host_t *vha)
  501. {
  502. struct qla_hw_data *ha = vha->hw;
  503. if (unlikely(pci_channel_offline(ha->pdev) &&
  504. ha->flags.pci_channel_io_perm_failure))
  505. return;
  506. ha->isp_ops->disable_intrs(ha);
  507. qlafx00_soc_cpu_reset(vha);
  508. ha->isp_ops->enable_intrs(ha);
  509. }
  510. /**
  511. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  512. * @ha: HA context
  513. *
  514. * Returns 0 on success.
  515. */
  516. int
  517. qlafx00_chip_diag(scsi_qla_host_t *vha)
  518. {
  519. int rval = 0;
  520. struct qla_hw_data *ha = vha->hw;
  521. struct req_que *req = ha->req_q_map[0];
  522. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  523. rval = qlafx00_mbx_reg_test(vha);
  524. if (rval) {
  525. ql_log(ql_log_warn, vha, 0x1165,
  526. "Failed mailbox send register test\n");
  527. } else {
  528. /* Flag a successful rval */
  529. rval = QLA_SUCCESS;
  530. }
  531. return rval;
  532. }
  533. void
  534. qlafx00_config_rings(struct scsi_qla_host *vha)
  535. {
  536. struct qla_hw_data *ha = vha->hw;
  537. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  538. struct init_cb_fx *icb;
  539. struct req_que *req = ha->req_q_map[0];
  540. struct rsp_que *rsp = ha->rsp_q_map[0];
  541. /* Setup ring parameters in initialization control block. */
  542. icb = (struct init_cb_fx *)ha->init_cb;
  543. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  544. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  545. icb->request_q_length = cpu_to_le16(req->length);
  546. icb->response_q_length = cpu_to_le16(rsp->length);
  547. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  548. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  549. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  550. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  551. WRT_REG_DWORD(&reg->req_q_in, 0);
  552. WRT_REG_DWORD(&reg->req_q_out, 0);
  553. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  554. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  555. /* PCI posting */
  556. RD_REG_DWORD(&reg->rsp_q_out);
  557. }
  558. char *
  559. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  560. {
  561. struct qla_hw_data *ha = vha->hw;
  562. int pcie_reg;
  563. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  564. if (pcie_reg) {
  565. strcpy(str, "PCIe iSA");
  566. return str;
  567. }
  568. return str;
  569. }
  570. char *
  571. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str)
  572. {
  573. struct qla_hw_data *ha = vha->hw;
  574. sprintf(str, "%s", ha->mr.fw_version);
  575. return str;
  576. }
  577. void
  578. qlafx00_enable_intrs(struct qla_hw_data *ha)
  579. {
  580. unsigned long flags = 0;
  581. spin_lock_irqsave(&ha->hardware_lock, flags);
  582. ha->interrupts_on = 1;
  583. QLAFX00_ENABLE_ICNTRL_REG(ha);
  584. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  585. }
  586. void
  587. qlafx00_disable_intrs(struct qla_hw_data *ha)
  588. {
  589. unsigned long flags = 0;
  590. spin_lock_irqsave(&ha->hardware_lock, flags);
  591. ha->interrupts_on = 0;
  592. QLAFX00_DISABLE_ICNTRL_REG(ha);
  593. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  594. }
  595. static void
  596. qlafx00_tmf_iocb_timeout(void *data)
  597. {
  598. srb_t *sp = (srb_t *)data;
  599. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  600. tmf->u.tmf.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  601. complete(&tmf->u.tmf.comp);
  602. }
  603. static void
  604. qlafx00_tmf_sp_done(void *data, void *ptr, int res)
  605. {
  606. srb_t *sp = (srb_t *)ptr;
  607. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  608. complete(&tmf->u.tmf.comp);
  609. }
  610. static int
  611. qlafx00_async_tm_cmd(fc_port_t *fcport, uint32_t flags,
  612. uint32_t lun, uint32_t tag)
  613. {
  614. scsi_qla_host_t *vha = fcport->vha;
  615. struct srb_iocb *tm_iocb;
  616. srb_t *sp;
  617. int rval = QLA_FUNCTION_FAILED;
  618. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  619. if (!sp)
  620. goto done;
  621. tm_iocb = &sp->u.iocb_cmd;
  622. sp->type = SRB_TM_CMD;
  623. sp->name = "tmf";
  624. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
  625. tm_iocb->u.tmf.flags = flags;
  626. tm_iocb->u.tmf.lun = lun;
  627. tm_iocb->u.tmf.data = tag;
  628. sp->done = qlafx00_tmf_sp_done;
  629. tm_iocb->timeout = qlafx00_tmf_iocb_timeout;
  630. init_completion(&tm_iocb->u.tmf.comp);
  631. rval = qla2x00_start_sp(sp);
  632. if (rval != QLA_SUCCESS)
  633. goto done_free_sp;
  634. ql_dbg(ql_dbg_async, vha, 0x507b,
  635. "Task management command issued target_id=%x\n",
  636. fcport->tgt_id);
  637. wait_for_completion(&tm_iocb->u.tmf.comp);
  638. rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
  639. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  640. done_free_sp:
  641. sp->free(vha, sp);
  642. done:
  643. return rval;
  644. }
  645. int
  646. qlafx00_abort_target(fc_port_t *fcport, unsigned int l, int tag)
  647. {
  648. return qlafx00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  649. }
  650. int
  651. qlafx00_lun_reset(fc_port_t *fcport, unsigned int l, int tag)
  652. {
  653. return qlafx00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  654. }
  655. int
  656. qlafx00_loop_reset(scsi_qla_host_t *vha)
  657. {
  658. int ret;
  659. struct fc_port *fcport;
  660. struct qla_hw_data *ha = vha->hw;
  661. if (ql2xtargetreset) {
  662. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  663. if (fcport->port_type != FCT_TARGET)
  664. continue;
  665. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  666. if (ret != QLA_SUCCESS) {
  667. ql_dbg(ql_dbg_taskm, vha, 0x803d,
  668. "Bus Reset failed: Reset=%d "
  669. "d_id=%x.\n", ret, fcport->d_id.b24);
  670. }
  671. }
  672. }
  673. return QLA_SUCCESS;
  674. }
  675. int
  676. qlafx00_iospace_config(struct qla_hw_data *ha)
  677. {
  678. if (pci_request_selected_regions(ha->pdev, ha->bars,
  679. QLA2XXX_DRIVER_NAME)) {
  680. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  681. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  682. pci_name(ha->pdev));
  683. goto iospace_error_exit;
  684. }
  685. /* Use MMIO operations for all accesses. */
  686. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  687. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  688. "Invalid pci I/O region size (%s).\n",
  689. pci_name(ha->pdev));
  690. goto iospace_error_exit;
  691. }
  692. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  693. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  694. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  695. pci_name(ha->pdev));
  696. goto iospace_error_exit;
  697. }
  698. ha->cregbase =
  699. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  700. if (!ha->cregbase) {
  701. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  702. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  703. goto iospace_error_exit;
  704. }
  705. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  706. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  707. "region #2 not an MMIO resource (%s), aborting\n",
  708. pci_name(ha->pdev));
  709. goto iospace_error_exit;
  710. }
  711. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  712. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  713. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  714. pci_name(ha->pdev));
  715. goto iospace_error_exit;
  716. }
  717. ha->iobase =
  718. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  719. if (!ha->iobase) {
  720. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  721. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  722. goto iospace_error_exit;
  723. }
  724. /* Determine queue resources */
  725. ha->max_req_queues = ha->max_rsp_queues = 1;
  726. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  727. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  728. ha->bars, ha->cregbase, ha->iobase);
  729. return 0;
  730. iospace_error_exit:
  731. return -ENOMEM;
  732. }
  733. static void
  734. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  735. {
  736. struct qla_hw_data *ha = vha->hw;
  737. struct req_que *req = ha->req_q_map[0];
  738. struct rsp_que *rsp = ha->rsp_q_map[0];
  739. req->length_fx00 = req->length;
  740. req->ring_fx00 = req->ring;
  741. req->dma_fx00 = req->dma;
  742. rsp->length_fx00 = rsp->length;
  743. rsp->ring_fx00 = rsp->ring;
  744. rsp->dma_fx00 = rsp->dma;
  745. ql_dbg(ql_dbg_init, vha, 0x012d,
  746. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  747. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  748. req->length_fx00, (u64)req->dma_fx00);
  749. ql_dbg(ql_dbg_init, vha, 0x012e,
  750. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  751. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  752. rsp->length_fx00, (u64)rsp->dma_fx00);
  753. }
  754. static int
  755. qlafx00_config_queues(struct scsi_qla_host *vha)
  756. {
  757. struct qla_hw_data *ha = vha->hw;
  758. struct req_que *req = ha->req_q_map[0];
  759. struct rsp_que *rsp = ha->rsp_q_map[0];
  760. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  761. req->length = ha->req_que_len;
  762. req->ring = (void *)ha->iobase + ha->req_que_off;
  763. req->dma = bar2_hdl + ha->req_que_off;
  764. if ((!req->ring) || (req->length == 0)) {
  765. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  766. "Unable to allocate memory for req_ring\n");
  767. return QLA_FUNCTION_FAILED;
  768. }
  769. ql_dbg(ql_dbg_init, vha, 0x0130,
  770. "req: %p req_ring pointer %p req len 0x%x "
  771. "req off 0x%x\n, req->dma: 0x%llx",
  772. req, req->ring, req->length,
  773. ha->req_que_off, (u64)req->dma);
  774. rsp->length = ha->rsp_que_len;
  775. rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
  776. rsp->dma = bar2_hdl + ha->rsp_que_off;
  777. if ((!rsp->ring) || (rsp->length == 0)) {
  778. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  779. "Unable to allocate memory for rsp_ring\n");
  780. return QLA_FUNCTION_FAILED;
  781. }
  782. ql_dbg(ql_dbg_init, vha, 0x0132,
  783. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  784. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  785. rsp, rsp->ring, rsp->length,
  786. ha->rsp_que_off, (u64)rsp->dma);
  787. return QLA_SUCCESS;
  788. }
  789. static int
  790. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  791. {
  792. int rval = 0;
  793. unsigned long wtime;
  794. uint16_t wait_time; /* Wait time */
  795. struct qla_hw_data *ha = vha->hw;
  796. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  797. uint32_t aenmbx, aenmbx7 = 0;
  798. uint32_t pseudo_aen;
  799. uint32_t state[5];
  800. bool done = false;
  801. /* 30 seconds wait - Adjust if required */
  802. wait_time = 30;
  803. pseudo_aen = RD_REG_DWORD(&reg->pseudoaen);
  804. if (pseudo_aen == 1) {
  805. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  806. ha->mbx_intr_code = MSW(aenmbx7);
  807. ha->rqstq_intr_code = LSW(aenmbx7);
  808. rval = qlafx00_driver_shutdown(vha, 10);
  809. if (rval != QLA_SUCCESS)
  810. qlafx00_soft_reset(vha);
  811. }
  812. /* wait time before firmware ready */
  813. wtime = jiffies + (wait_time * HZ);
  814. do {
  815. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  816. barrier();
  817. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  818. "aenmbx: 0x%x\n", aenmbx);
  819. switch (aenmbx) {
  820. case MBA_FW_NOT_STARTED:
  821. case MBA_FW_STARTING:
  822. break;
  823. case MBA_SYSTEM_ERR:
  824. case MBA_REQ_TRANSFER_ERR:
  825. case MBA_RSP_TRANSFER_ERR:
  826. case MBA_FW_INIT_FAILURE:
  827. qlafx00_soft_reset(vha);
  828. break;
  829. case MBA_FW_RESTART_CMPLT:
  830. /* Set the mbx and rqstq intr code */
  831. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  832. ha->mbx_intr_code = MSW(aenmbx7);
  833. ha->rqstq_intr_code = LSW(aenmbx7);
  834. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  835. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  836. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  837. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  838. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  839. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  840. ql_dbg(ql_dbg_init, vha, 0x0134,
  841. "f/w returned mbx_intr_code: 0x%x, "
  842. "rqstq_intr_code: 0x%x\n",
  843. ha->mbx_intr_code, ha->rqstq_intr_code);
  844. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  845. rval = QLA_SUCCESS;
  846. done = true;
  847. break;
  848. default:
  849. /* If fw is apparently not ready. In order to continue,
  850. * we might need to issue Mbox cmd, but the problem is
  851. * that the DoorBell vector values that come with the
  852. * 8060 AEN are most likely gone by now (and thus no
  853. * bell would be rung on the fw side when mbox cmd is
  854. * issued). We have to therefore grab the 8060 AEN
  855. * shadow regs (filled in by FW when the last 8060
  856. * AEN was being posted).
  857. * Do the following to determine what is needed in
  858. * order to get the FW ready:
  859. * 1. reload the 8060 AEN values from the shadow regs
  860. * 2. clear int status to get rid of possible pending
  861. * interrupts
  862. * 3. issue Get FW State Mbox cmd to determine fw state
  863. * Set the mbx and rqstq intr code from Shadow Regs
  864. */
  865. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  866. ha->mbx_intr_code = MSW(aenmbx7);
  867. ha->rqstq_intr_code = LSW(aenmbx7);
  868. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  869. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  870. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  871. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  872. ql_dbg(ql_dbg_init, vha, 0x0135,
  873. "f/w returned mbx_intr_code: 0x%x, "
  874. "rqstq_intr_code: 0x%x\n",
  875. ha->mbx_intr_code, ha->rqstq_intr_code);
  876. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  877. /* Get the FW state */
  878. rval = qlafx00_get_firmware_state(vha, state);
  879. if (rval != QLA_SUCCESS) {
  880. /* Retry if timer has not expired */
  881. break;
  882. }
  883. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  884. /* Firmware is waiting to be
  885. * initialized by driver
  886. */
  887. rval = QLA_SUCCESS;
  888. done = true;
  889. break;
  890. }
  891. /* Issue driver shutdown and wait until f/w recovers.
  892. * Driver should continue to poll until 8060 AEN is
  893. * received indicating firmware recovery.
  894. */
  895. ql_dbg(ql_dbg_init, vha, 0x0136,
  896. "Sending Driver shutdown fw_state 0x%x\n",
  897. state[0]);
  898. rval = qlafx00_driver_shutdown(vha, 10);
  899. if (rval != QLA_SUCCESS) {
  900. rval = QLA_FUNCTION_FAILED;
  901. break;
  902. }
  903. msleep(500);
  904. wtime = jiffies + (wait_time * HZ);
  905. break;
  906. }
  907. if (!done) {
  908. if (time_after_eq(jiffies, wtime)) {
  909. ql_dbg(ql_dbg_init, vha, 0x0137,
  910. "Init f/w failed: aen[7]: 0x%x\n",
  911. RD_REG_DWORD(&reg->aenmailbox7));
  912. rval = QLA_FUNCTION_FAILED;
  913. done = true;
  914. break;
  915. }
  916. /* Delay for a while */
  917. msleep(500);
  918. }
  919. } while (!done);
  920. if (rval)
  921. ql_dbg(ql_dbg_init, vha, 0x0138,
  922. "%s **** FAILED ****.\n", __func__);
  923. else
  924. ql_dbg(ql_dbg_init, vha, 0x0139,
  925. "%s **** SUCCESS ****.\n", __func__);
  926. return rval;
  927. }
  928. /*
  929. * qlafx00_fw_ready() - Waits for firmware ready.
  930. * @ha: HA context
  931. *
  932. * Returns 0 on success.
  933. */
  934. int
  935. qlafx00_fw_ready(scsi_qla_host_t *vha)
  936. {
  937. int rval;
  938. unsigned long wtime;
  939. uint16_t wait_time; /* Wait time if loop is coming ready */
  940. uint32_t state[5];
  941. rval = QLA_SUCCESS;
  942. wait_time = 10;
  943. /* wait time before firmware ready */
  944. wtime = jiffies + (wait_time * HZ);
  945. /* Wait for ISP to finish init */
  946. if (!vha->flags.init_done)
  947. ql_dbg(ql_dbg_init, vha, 0x013a,
  948. "Waiting for init to complete...\n");
  949. do {
  950. rval = qlafx00_get_firmware_state(vha, state);
  951. if (rval == QLA_SUCCESS) {
  952. if (state[0] == FSTATE_FX00_INITIALIZED) {
  953. ql_dbg(ql_dbg_init, vha, 0x013b,
  954. "fw_state=%x\n", state[0]);
  955. rval = QLA_SUCCESS;
  956. break;
  957. }
  958. }
  959. rval = QLA_FUNCTION_FAILED;
  960. if (time_after_eq(jiffies, wtime))
  961. break;
  962. /* Delay for a while */
  963. msleep(500);
  964. ql_dbg(ql_dbg_init, vha, 0x013c,
  965. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  966. } while (1);
  967. if (rval)
  968. ql_dbg(ql_dbg_init, vha, 0x013d,
  969. "Firmware ready **** FAILED ****.\n");
  970. else
  971. ql_dbg(ql_dbg_init, vha, 0x013e,
  972. "Firmware ready **** SUCCESS ****.\n");
  973. return rval;
  974. }
  975. static int
  976. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  977. struct list_head *new_fcports)
  978. {
  979. int rval;
  980. uint16_t tgt_id;
  981. fc_port_t *fcport, *new_fcport;
  982. int found;
  983. struct qla_hw_data *ha = vha->hw;
  984. rval = QLA_SUCCESS;
  985. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  986. return QLA_FUNCTION_FAILED;
  987. if ((atomic_read(&vha->loop_down_timer) ||
  988. STATE_TRANSITION(vha))) {
  989. atomic_set(&vha->loop_down_timer, 0);
  990. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  991. return QLA_FUNCTION_FAILED;
  992. }
  993. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  994. "Listing Target bit map...\n");
  995. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  996. 0x2089, (uint8_t *)ha->gid_list, 32);
  997. /* Allocate temporary rmtport for any new rmtports discovered. */
  998. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  999. if (new_fcport == NULL)
  1000. return QLA_MEMORY_ALLOC_FAILED;
  1001. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  1002. QLAFX00_TGT_NODE_LIST_SIZE) {
  1003. /* Send get target node info */
  1004. new_fcport->tgt_id = tgt_id;
  1005. rval = qlafx00_fx_disc(vha, new_fcport,
  1006. FXDISC_GET_TGT_NODE_INFO);
  1007. if (rval != QLA_SUCCESS) {
  1008. ql_log(ql_log_warn, vha, 0x208a,
  1009. "Target info scan failed -- assuming zero-entry "
  1010. "result...\n");
  1011. continue;
  1012. }
  1013. /* Locate matching device in database. */
  1014. found = 0;
  1015. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1016. if (memcmp(new_fcport->port_name,
  1017. fcport->port_name, WWN_SIZE))
  1018. continue;
  1019. found++;
  1020. /*
  1021. * If tgt_id is same and state FCS_ONLINE, nothing
  1022. * changed.
  1023. */
  1024. if (fcport->tgt_id == new_fcport->tgt_id &&
  1025. atomic_read(&fcport->state) == FCS_ONLINE)
  1026. break;
  1027. /*
  1028. * Tgt ID changed or device was marked to be updated.
  1029. */
  1030. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1031. "TGT-ID Change(%s): Present tgt id: "
  1032. "0x%x state: 0x%x "
  1033. "wwnn = %llx wwpn = %llx.\n",
  1034. __func__, fcport->tgt_id,
  1035. atomic_read(&fcport->state),
  1036. (unsigned long long)wwn_to_u64(fcport->node_name),
  1037. (unsigned long long)wwn_to_u64(fcport->port_name));
  1038. ql_log(ql_log_info, vha, 0x208c,
  1039. "TGT-ID Announce(%s): Discovered tgt "
  1040. "id 0x%x wwnn = %llx "
  1041. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1042. (unsigned long long)
  1043. wwn_to_u64(new_fcport->node_name),
  1044. (unsigned long long)
  1045. wwn_to_u64(new_fcport->port_name));
  1046. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1047. fcport->old_tgt_id = fcport->tgt_id;
  1048. fcport->tgt_id = new_fcport->tgt_id;
  1049. ql_log(ql_log_info, vha, 0x208d,
  1050. "TGT-ID: New fcport Added: %p\n", fcport);
  1051. qla2x00_update_fcport(vha, fcport);
  1052. } else {
  1053. ql_log(ql_log_info, vha, 0x208e,
  1054. " Existing TGT-ID %x did not get "
  1055. " offline event from firmware.\n",
  1056. fcport->old_tgt_id);
  1057. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1058. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1059. kfree(new_fcport);
  1060. return rval;
  1061. }
  1062. break;
  1063. }
  1064. if (found)
  1065. continue;
  1066. /* If device was not in our fcports list, then add it. */
  1067. list_add_tail(&new_fcport->list, new_fcports);
  1068. /* Allocate a new replacement fcport. */
  1069. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1070. if (new_fcport == NULL)
  1071. return QLA_MEMORY_ALLOC_FAILED;
  1072. }
  1073. kfree(new_fcport);
  1074. return rval;
  1075. }
  1076. /*
  1077. * qlafx00_configure_all_targets
  1078. * Setup target devices with node ID's.
  1079. *
  1080. * Input:
  1081. * ha = adapter block pointer.
  1082. *
  1083. * Returns:
  1084. * 0 = success.
  1085. * BIT_0 = error
  1086. */
  1087. static int
  1088. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1089. {
  1090. int rval;
  1091. fc_port_t *fcport, *rmptemp;
  1092. LIST_HEAD(new_fcports);
  1093. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1094. FXDISC_GET_TGT_NODE_LIST);
  1095. if (rval != QLA_SUCCESS) {
  1096. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1097. return rval;
  1098. }
  1099. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1100. if (rval != QLA_SUCCESS) {
  1101. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1102. return rval;
  1103. }
  1104. /*
  1105. * Delete all previous devices marked lost.
  1106. */
  1107. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1108. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1109. break;
  1110. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1111. if (fcport->port_type != FCT_INITIATOR)
  1112. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1113. }
  1114. }
  1115. /*
  1116. * Add the new devices to our devices list.
  1117. */
  1118. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1119. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1120. break;
  1121. qla2x00_update_fcport(vha, fcport);
  1122. list_move_tail(&fcport->list, &vha->vp_fcports);
  1123. ql_log(ql_log_info, vha, 0x208f,
  1124. "Attach new target id 0x%x wwnn = %llx "
  1125. "wwpn = %llx.\n",
  1126. fcport->tgt_id,
  1127. (unsigned long long)wwn_to_u64(fcport->node_name),
  1128. (unsigned long long)wwn_to_u64(fcport->port_name));
  1129. }
  1130. /* Free all new device structures not processed. */
  1131. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1132. list_del(&fcport->list);
  1133. kfree(fcport);
  1134. }
  1135. return rval;
  1136. }
  1137. /*
  1138. * qlafx00_configure_devices
  1139. * Updates Fibre Channel Device Database with what is actually on loop.
  1140. *
  1141. * Input:
  1142. * ha = adapter block pointer.
  1143. *
  1144. * Returns:
  1145. * 0 = success.
  1146. * 1 = error.
  1147. * 2 = database was full and device was not configured.
  1148. */
  1149. int
  1150. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1151. {
  1152. int rval;
  1153. unsigned long flags, save_flags;
  1154. rval = QLA_SUCCESS;
  1155. save_flags = flags = vha->dpc_flags;
  1156. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1157. "Configure devices -- dpc flags =0x%lx\n", flags);
  1158. rval = qlafx00_configure_all_targets(vha);
  1159. if (rval == QLA_SUCCESS) {
  1160. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1161. rval = QLA_FUNCTION_FAILED;
  1162. } else {
  1163. atomic_set(&vha->loop_state, LOOP_READY);
  1164. ql_log(ql_log_info, vha, 0x2091,
  1165. "Device Ready\n");
  1166. }
  1167. }
  1168. if (rval) {
  1169. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1170. "%s *** FAILED ***.\n", __func__);
  1171. } else {
  1172. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1173. "%s: exiting normally.\n", __func__);
  1174. }
  1175. return rval;
  1176. }
  1177. static void
  1178. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
  1179. {
  1180. struct qla_hw_data *ha = vha->hw;
  1181. fc_port_t *fcport;
  1182. vha->flags.online = 0;
  1183. ha->mr.fw_hbt_en = 0;
  1184. if (!critemp) {
  1185. ha->flags.chip_reset_done = 0;
  1186. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1187. vha->qla_stats.total_isp_aborts++;
  1188. ql_log(ql_log_info, vha, 0x013f,
  1189. "Performing ISP error recovery - ha = %p.\n", ha);
  1190. ha->isp_ops->reset_chip(vha);
  1191. }
  1192. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1193. atomic_set(&vha->loop_state, LOOP_DOWN);
  1194. atomic_set(&vha->loop_down_timer,
  1195. QLAFX00_LOOP_DOWN_TIME);
  1196. } else {
  1197. if (!atomic_read(&vha->loop_down_timer))
  1198. atomic_set(&vha->loop_down_timer,
  1199. QLAFX00_LOOP_DOWN_TIME);
  1200. }
  1201. /* Clear all async request states across all VPs. */
  1202. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1203. fcport->flags = 0;
  1204. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1205. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1206. }
  1207. if (!ha->flags.eeh_busy) {
  1208. if (critemp) {
  1209. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  1210. } else {
  1211. /* Requeue all commands in outstanding command list. */
  1212. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1213. }
  1214. }
  1215. qla2x00_free_irqs(vha);
  1216. if (critemp)
  1217. set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
  1218. else
  1219. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1220. /* Clear the Interrupts */
  1221. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1222. ql_log(ql_log_info, vha, 0x0140,
  1223. "%s Done done - ha=%p.\n", __func__, ha);
  1224. }
  1225. /**
  1226. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1227. * @ha: HA context
  1228. *
  1229. * Beginning of request ring has initialization control block already built
  1230. * by nvram config routine.
  1231. *
  1232. * Returns 0 on success.
  1233. */
  1234. void
  1235. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1236. {
  1237. uint16_t cnt;
  1238. response_t *pkt;
  1239. rsp->ring_ptr = rsp->ring;
  1240. rsp->ring_index = 0;
  1241. rsp->status_srb = NULL;
  1242. pkt = rsp->ring_ptr;
  1243. for (cnt = 0; cnt < rsp->length; cnt++) {
  1244. pkt->signature = RESPONSE_PROCESSED;
  1245. WRT_REG_DWORD((void __iomem *)&pkt->signature,
  1246. RESPONSE_PROCESSED);
  1247. pkt++;
  1248. }
  1249. }
  1250. int
  1251. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1252. {
  1253. uint32_t status = QLA_FUNCTION_FAILED;
  1254. struct qla_hw_data *ha = vha->hw;
  1255. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1256. uint32_t aenmbx7;
  1257. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1258. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1259. ha->mbx_intr_code = MSW(aenmbx7);
  1260. ha->rqstq_intr_code = LSW(aenmbx7);
  1261. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1262. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1263. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1264. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1265. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1266. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1267. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1268. ha->mbx_intr_code, ha->rqstq_intr_code,
  1269. ha->req_que_off, ha->rsp_que_len);
  1270. /* Clear the Interrupts */
  1271. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1272. status = qla2x00_init_rings(vha);
  1273. if (!status) {
  1274. vha->flags.online = 1;
  1275. /* if no cable then assume it's good */
  1276. if ((vha->device_flags & DFLG_NO_CABLE))
  1277. status = 0;
  1278. /* Register system information */
  1279. if (qlafx00_fx_disc(vha,
  1280. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1281. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1282. "failed to register host info\n");
  1283. }
  1284. scsi_unblock_requests(vha->host);
  1285. return status;
  1286. }
  1287. void
  1288. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1289. {
  1290. struct qla_hw_data *ha = vha->hw;
  1291. uint32_t fw_heart_beat;
  1292. uint32_t aenmbx0;
  1293. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1294. uint32_t tempc;
  1295. /* Check firmware health */
  1296. if (ha->mr.fw_hbt_cnt)
  1297. ha->mr.fw_hbt_cnt--;
  1298. else {
  1299. if ((!ha->flags.mr_reset_hdlr_active) &&
  1300. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1301. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1302. (ha->mr.fw_hbt_en)) {
  1303. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1304. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1305. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1306. ha->mr.fw_hbt_miss_cnt = 0;
  1307. } else {
  1308. ha->mr.fw_hbt_miss_cnt++;
  1309. if (ha->mr.fw_hbt_miss_cnt ==
  1310. QLAFX00_HEARTBEAT_MISS_CNT) {
  1311. set_bit(ISP_ABORT_NEEDED,
  1312. &vha->dpc_flags);
  1313. qla2xxx_wake_dpc(vha);
  1314. ha->mr.fw_hbt_miss_cnt = 0;
  1315. }
  1316. }
  1317. }
  1318. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1319. }
  1320. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1321. /* Reset recovery to be performed in timer routine */
  1322. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1323. if (ha->mr.fw_reset_timer_exp) {
  1324. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1325. qla2xxx_wake_dpc(vha);
  1326. ha->mr.fw_reset_timer_exp = 0;
  1327. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1328. /* Wake up DPC to rescan the targets */
  1329. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1330. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1331. qla2xxx_wake_dpc(vha);
  1332. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1333. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1334. (!ha->mr.fw_hbt_en)) {
  1335. ha->mr.fw_hbt_en = 1;
  1336. } else if (!ha->mr.fw_reset_timer_tick) {
  1337. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1338. ha->mr.fw_reset_timer_exp = 1;
  1339. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1340. } else if (aenmbx0 == 0xFFFFFFFF) {
  1341. uint32_t data0, data1;
  1342. data0 = QLAFX00_RD_REG(ha,
  1343. QLAFX00_BAR1_BASE_ADDR_REG);
  1344. data1 = QLAFX00_RD_REG(ha,
  1345. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1346. data0 &= 0xffff0000;
  1347. data1 &= 0x0000ffff;
  1348. QLAFX00_WR_REG(ha,
  1349. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1350. (data0 | data1));
  1351. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1352. ha->mr.fw_reset_timer_tick =
  1353. QLAFX00_MAX_RESET_INTERVAL;
  1354. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1355. ha->mr.fw_reset_timer_tick =
  1356. QLAFX00_MAX_RESET_INTERVAL;
  1357. }
  1358. ha->mr.old_aenmbx0_state = aenmbx0;
  1359. ha->mr.fw_reset_timer_tick--;
  1360. }
  1361. if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
  1362. /*
  1363. * Critical temperature recovery to be
  1364. * performed in timer routine
  1365. */
  1366. if (ha->mr.fw_critemp_timer_tick == 0) {
  1367. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1368. ql_log(ql_dbg_timer, vha, 0x6012,
  1369. "ISPFx00(%s): Critical temp timer, "
  1370. "current SOC temperature: %d\n",
  1371. __func__, tempc);
  1372. if (tempc < ha->mr.critical_temperature) {
  1373. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1374. clear_bit(FX00_CRITEMP_RECOVERY,
  1375. &vha->dpc_flags);
  1376. qla2xxx_wake_dpc(vha);
  1377. }
  1378. ha->mr.fw_critemp_timer_tick =
  1379. QLAFX00_CRITEMP_INTERVAL;
  1380. } else {
  1381. ha->mr.fw_critemp_timer_tick--;
  1382. }
  1383. }
  1384. }
  1385. /*
  1386. * qlfx00a_reset_initialize
  1387. * Re-initialize after a iSA device reset.
  1388. *
  1389. * Input:
  1390. * ha = adapter block pointer.
  1391. *
  1392. * Returns:
  1393. * 0 = success
  1394. */
  1395. int
  1396. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1397. {
  1398. struct qla_hw_data *ha = vha->hw;
  1399. if (vha->device_flags & DFLG_DEV_FAILED) {
  1400. ql_dbg(ql_dbg_init, vha, 0x0142,
  1401. "Device in failed state\n");
  1402. return QLA_SUCCESS;
  1403. }
  1404. ha->flags.mr_reset_hdlr_active = 1;
  1405. if (vha->flags.online) {
  1406. scsi_block_requests(vha->host);
  1407. qlafx00_abort_isp_cleanup(vha, false);
  1408. }
  1409. ql_log(ql_log_info, vha, 0x0143,
  1410. "(%s): succeeded.\n", __func__);
  1411. ha->flags.mr_reset_hdlr_active = 0;
  1412. return QLA_SUCCESS;
  1413. }
  1414. /*
  1415. * qlafx00_abort_isp
  1416. * Resets ISP and aborts all outstanding commands.
  1417. *
  1418. * Input:
  1419. * ha = adapter block pointer.
  1420. *
  1421. * Returns:
  1422. * 0 = success
  1423. */
  1424. int
  1425. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1426. {
  1427. struct qla_hw_data *ha = vha->hw;
  1428. if (vha->flags.online) {
  1429. if (unlikely(pci_channel_offline(ha->pdev) &&
  1430. ha->flags.pci_channel_io_perm_failure)) {
  1431. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1432. return QLA_SUCCESS;
  1433. }
  1434. scsi_block_requests(vha->host);
  1435. qlafx00_abort_isp_cleanup(vha, false);
  1436. } else {
  1437. scsi_block_requests(vha->host);
  1438. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1439. vha->qla_stats.total_isp_aborts++;
  1440. ha->isp_ops->reset_chip(vha);
  1441. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1442. /* Clear the Interrupts */
  1443. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1444. }
  1445. ql_log(ql_log_info, vha, 0x0145,
  1446. "(%s): succeeded.\n", __func__);
  1447. return QLA_SUCCESS;
  1448. }
  1449. static inline fc_port_t*
  1450. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1451. {
  1452. fc_port_t *fcport;
  1453. /* Check for matching device in remote port list. */
  1454. fcport = NULL;
  1455. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1456. if (fcport->tgt_id == tgt_id) {
  1457. ql_dbg(ql_dbg_async, vha, 0x5072,
  1458. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1459. "and Remote TGT_ID: 0x%x\n",
  1460. fcport, fcport->tgt_id, tgt_id);
  1461. break;
  1462. }
  1463. }
  1464. return fcport;
  1465. }
  1466. static void
  1467. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1468. {
  1469. fc_port_t *fcport;
  1470. ql_log(ql_log_info, vha, 0x5073,
  1471. "Detach TGT-ID: 0x%x\n", tgt_id);
  1472. fcport = qlafx00_get_fcport(vha, tgt_id);
  1473. if (!fcport)
  1474. return;
  1475. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1476. return;
  1477. }
  1478. int
  1479. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1480. {
  1481. int rval = 0;
  1482. uint32_t aen_code, aen_data;
  1483. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1484. aen_data = evt->u.aenfx.evtcode;
  1485. switch (evt->u.aenfx.evtcode) {
  1486. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* FW shutdown pending */
  1487. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1488. rval = qlafx00_driver_shutdown(vha, 10);
  1489. break;
  1490. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1491. if (evt->u.aenfx.mbx[1] == 0) {
  1492. if (evt->u.aenfx.mbx[2] == 1) {
  1493. if (!vha->flags.fw_tgt_reported)
  1494. vha->flags.fw_tgt_reported = 1;
  1495. atomic_set(&vha->loop_down_timer, 0);
  1496. atomic_set(&vha->loop_state, LOOP_UP);
  1497. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1498. qla2xxx_wake_dpc(vha);
  1499. } else if (evt->u.aenfx.mbx[2] == 2) {
  1500. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1501. }
  1502. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1503. if (evt->u.aenfx.mbx[2] == 1) {
  1504. if (!vha->flags.fw_tgt_reported)
  1505. vha->flags.fw_tgt_reported = 1;
  1506. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1507. } else if (evt->u.aenfx.mbx[2] == 2) {
  1508. vha->device_flags |= DFLG_NO_CABLE;
  1509. qla2x00_mark_all_devices_lost(vha, 1);
  1510. }
  1511. }
  1512. break;
  1513. case QLAFX00_MBA_LINK_UP:
  1514. aen_code = FCH_EVT_LINKUP;
  1515. aen_data = 0;
  1516. break;
  1517. case QLAFX00_MBA_LINK_DOWN:
  1518. aen_code = FCH_EVT_LINKDOWN;
  1519. aen_data = 0;
  1520. break;
  1521. case QLAFX00_MBA_TEMP_OVER:
  1522. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  1523. ql_log(ql_log_info, vha, 0x5082,
  1524. "Process critical temperature event "
  1525. "aenmb[0]: %x\n",
  1526. evt->u.aenfx.evtcode);
  1527. scsi_block_requests(vha->host);
  1528. qlafx00_abort_isp_cleanup(vha, true);
  1529. scsi_unblock_requests(vha->host);
  1530. break;
  1531. }
  1532. fc_host_post_event(vha->host, fc_get_event_number(),
  1533. aen_code, aen_data);
  1534. return rval;
  1535. }
  1536. static void
  1537. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1538. {
  1539. u64 port_name = 0, node_name = 0;
  1540. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1541. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1542. fc_host_node_name(vha->host) = node_name;
  1543. fc_host_port_name(vha->host) = port_name;
  1544. if (!pinfo->port_type)
  1545. vha->hw->current_topology = ISP_CFG_F;
  1546. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1547. atomic_set(&vha->loop_state, LOOP_READY);
  1548. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1549. atomic_set(&vha->loop_state, LOOP_DOWN);
  1550. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1551. }
  1552. static void
  1553. qla2x00_fxdisc_iocb_timeout(void *data)
  1554. {
  1555. srb_t *sp = (srb_t *)data;
  1556. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1557. complete(&lio->u.fxiocb.fxiocb_comp);
  1558. }
  1559. static void
  1560. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1561. {
  1562. srb_t *sp = (srb_t *)ptr;
  1563. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1564. complete(&lio->u.fxiocb.fxiocb_comp);
  1565. }
  1566. int
  1567. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1568. {
  1569. srb_t *sp;
  1570. struct srb_iocb *fdisc;
  1571. int rval = QLA_FUNCTION_FAILED;
  1572. struct qla_hw_data *ha = vha->hw;
  1573. struct host_system_info *phost_info;
  1574. struct register_host_info *preg_hsi;
  1575. struct new_utsname *p_sysid = NULL;
  1576. struct timeval tv;
  1577. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1578. if (!sp)
  1579. goto done;
  1580. fdisc = &sp->u.iocb_cmd;
  1581. switch (fx_type) {
  1582. case FXDISC_GET_CONFIG_INFO:
  1583. fdisc->u.fxiocb.flags =
  1584. SRB_FXDISC_RESP_DMA_VALID;
  1585. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1586. break;
  1587. case FXDISC_GET_PORT_INFO:
  1588. fdisc->u.fxiocb.flags =
  1589. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1590. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1591. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1592. break;
  1593. case FXDISC_GET_TGT_NODE_INFO:
  1594. fdisc->u.fxiocb.flags =
  1595. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1596. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1597. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1598. break;
  1599. case FXDISC_GET_TGT_NODE_LIST:
  1600. fdisc->u.fxiocb.flags =
  1601. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1602. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1603. break;
  1604. case FXDISC_REG_HOST_INFO:
  1605. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1606. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1607. p_sysid = utsname();
  1608. if (!p_sysid) {
  1609. ql_log(ql_log_warn, vha, 0x303c,
  1610. "Not able to get the system informtion\n");
  1611. goto done_free_sp;
  1612. }
  1613. break;
  1614. default:
  1615. break;
  1616. }
  1617. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1618. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1619. fdisc->u.fxiocb.req_len,
  1620. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1621. if (!fdisc->u.fxiocb.req_addr)
  1622. goto done_free_sp;
  1623. if (fx_type == FXDISC_REG_HOST_INFO) {
  1624. preg_hsi = (struct register_host_info *)
  1625. fdisc->u.fxiocb.req_addr;
  1626. phost_info = &preg_hsi->hsi;
  1627. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1628. phost_info->os_type = OS_TYPE_LINUX;
  1629. strncpy(phost_info->sysname,
  1630. p_sysid->sysname, SYSNAME_LENGTH);
  1631. strncpy(phost_info->nodename,
  1632. p_sysid->nodename, NODENAME_LENGTH);
  1633. strncpy(phost_info->release,
  1634. p_sysid->release, RELEASE_LENGTH);
  1635. strncpy(phost_info->version,
  1636. p_sysid->version, VERSION_LENGTH);
  1637. strncpy(phost_info->machine,
  1638. p_sysid->machine, MACHINE_LENGTH);
  1639. strncpy(phost_info->domainname,
  1640. p_sysid->domainname, DOMNAME_LENGTH);
  1641. strncpy(phost_info->hostdriver,
  1642. QLA2XXX_VERSION, VERSION_LENGTH);
  1643. do_gettimeofday(&tv);
  1644. preg_hsi->utc = (uint64_t)tv.tv_sec;
  1645. ql_dbg(ql_dbg_init, vha, 0x0149,
  1646. "ISP%04X: Host registration with firmware\n",
  1647. ha->pdev->device);
  1648. ql_dbg(ql_dbg_init, vha, 0x014a,
  1649. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1650. phost_info->os_type,
  1651. phost_info->sysname,
  1652. phost_info->nodename);
  1653. ql_dbg(ql_dbg_init, vha, 0x014b,
  1654. "release = '%s', version = '%s'\n",
  1655. phost_info->release,
  1656. phost_info->version);
  1657. ql_dbg(ql_dbg_init, vha, 0x014c,
  1658. "machine = '%s' "
  1659. "domainname = '%s', hostdriver = '%s'\n",
  1660. phost_info->machine,
  1661. phost_info->domainname,
  1662. phost_info->hostdriver);
  1663. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1664. (uint8_t *)phost_info,
  1665. sizeof(struct host_system_info));
  1666. }
  1667. }
  1668. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1669. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1670. fdisc->u.fxiocb.rsp_len,
  1671. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1672. if (!fdisc->u.fxiocb.rsp_addr)
  1673. goto done_unmap_req;
  1674. }
  1675. sp->type = SRB_FXIOCB_DCMD;
  1676. sp->name = "fxdisc";
  1677. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1678. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1679. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1680. sp->done = qla2x00_fxdisc_sp_done;
  1681. rval = qla2x00_start_sp(sp);
  1682. if (rval != QLA_SUCCESS)
  1683. goto done_unmap_dma;
  1684. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1685. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1686. struct config_info_data *pinfo =
  1687. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1688. memcpy(&vha->hw->mr.product_name, pinfo->product_name,
  1689. sizeof(vha->hw->mr.product_name));
  1690. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1691. sizeof(vha->hw->mr.symbolic_name));
  1692. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1693. sizeof(vha->hw->mr.serial_num));
  1694. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1695. sizeof(vha->hw->mr.hw_version));
  1696. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1697. sizeof(vha->hw->mr.fw_version));
  1698. strim(vha->hw->mr.fw_version);
  1699. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1700. sizeof(vha->hw->mr.uboot_version));
  1701. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1702. sizeof(vha->hw->mr.fru_serial_num));
  1703. vha->hw->mr.critical_temperature = pinfo->nominal_temp_value;
  1704. ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
  1705. QLAFX00_EXTENDED_IO_EN_MASK) != 0;
  1706. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1707. struct port_info_data *pinfo =
  1708. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1709. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1710. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1711. vha->d_id.b.domain = pinfo->port_id[0];
  1712. vha->d_id.b.area = pinfo->port_id[1];
  1713. vha->d_id.b.al_pa = pinfo->port_id[2];
  1714. qlafx00_update_host_attr(vha, pinfo);
  1715. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1716. (uint8_t *)pinfo, 16);
  1717. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1718. struct qlafx00_tgt_node_info *pinfo =
  1719. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1720. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1721. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1722. fcport->port_type = FCT_TARGET;
  1723. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1724. (uint8_t *)pinfo, 16);
  1725. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1726. struct qlafx00_tgt_node_info *pinfo =
  1727. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1728. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1729. (uint8_t *)pinfo, 16);
  1730. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1731. }
  1732. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1733. done_unmap_dma:
  1734. if (fdisc->u.fxiocb.rsp_addr)
  1735. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1736. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1737. done_unmap_req:
  1738. if (fdisc->u.fxiocb.req_addr)
  1739. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1740. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1741. done_free_sp:
  1742. sp->free(vha, sp);
  1743. done:
  1744. return rval;
  1745. }
  1746. static void
  1747. qlafx00_abort_iocb_timeout(void *data)
  1748. {
  1749. srb_t *sp = (srb_t *)data;
  1750. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1751. abt->u.abt.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  1752. complete(&abt->u.abt.comp);
  1753. }
  1754. static void
  1755. qlafx00_abort_sp_done(void *data, void *ptr, int res)
  1756. {
  1757. srb_t *sp = (srb_t *)ptr;
  1758. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1759. complete(&abt->u.abt.comp);
  1760. }
  1761. static int
  1762. qlafx00_async_abt_cmd(srb_t *cmd_sp)
  1763. {
  1764. scsi_qla_host_t *vha = cmd_sp->fcport->vha;
  1765. fc_port_t *fcport = cmd_sp->fcport;
  1766. struct srb_iocb *abt_iocb;
  1767. srb_t *sp;
  1768. int rval = QLA_FUNCTION_FAILED;
  1769. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1770. if (!sp)
  1771. goto done;
  1772. abt_iocb = &sp->u.iocb_cmd;
  1773. sp->type = SRB_ABT_CMD;
  1774. sp->name = "abort";
  1775. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1776. abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
  1777. sp->done = qlafx00_abort_sp_done;
  1778. abt_iocb->timeout = qlafx00_abort_iocb_timeout;
  1779. init_completion(&abt_iocb->u.abt.comp);
  1780. rval = qla2x00_start_sp(sp);
  1781. if (rval != QLA_SUCCESS)
  1782. goto done_free_sp;
  1783. ql_dbg(ql_dbg_async, vha, 0x507c,
  1784. "Abort command issued - hdl=%x, target_id=%x\n",
  1785. cmd_sp->handle, fcport->tgt_id);
  1786. wait_for_completion(&abt_iocb->u.abt.comp);
  1787. rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
  1788. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  1789. done_free_sp:
  1790. sp->free(vha, sp);
  1791. done:
  1792. return rval;
  1793. }
  1794. int
  1795. qlafx00_abort_command(srb_t *sp)
  1796. {
  1797. unsigned long flags = 0;
  1798. uint32_t handle;
  1799. fc_port_t *fcport = sp->fcport;
  1800. struct scsi_qla_host *vha = fcport->vha;
  1801. struct qla_hw_data *ha = vha->hw;
  1802. struct req_que *req = vha->req;
  1803. spin_lock_irqsave(&ha->hardware_lock, flags);
  1804. for (handle = 1; handle < DEFAULT_OUTSTANDING_COMMANDS; handle++) {
  1805. if (req->outstanding_cmds[handle] == sp)
  1806. break;
  1807. }
  1808. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1809. if (handle == DEFAULT_OUTSTANDING_COMMANDS) {
  1810. /* Command not found. */
  1811. return QLA_FUNCTION_FAILED;
  1812. }
  1813. return qlafx00_async_abt_cmd(sp);
  1814. }
  1815. /*
  1816. * qlafx00_initialize_adapter
  1817. * Initialize board.
  1818. *
  1819. * Input:
  1820. * ha = adapter block pointer.
  1821. *
  1822. * Returns:
  1823. * 0 = success
  1824. */
  1825. int
  1826. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1827. {
  1828. int rval;
  1829. struct qla_hw_data *ha = vha->hw;
  1830. uint32_t tempc;
  1831. /* Clear adapter flags. */
  1832. vha->flags.online = 0;
  1833. ha->flags.chip_reset_done = 0;
  1834. vha->flags.reset_active = 0;
  1835. ha->flags.pci_channel_io_perm_failure = 0;
  1836. ha->flags.eeh_busy = 0;
  1837. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1838. atomic_set(&vha->loop_state, LOOP_DOWN);
  1839. vha->device_flags = DFLG_NO_CABLE;
  1840. vha->dpc_flags = 0;
  1841. vha->flags.management_server_logged_in = 0;
  1842. vha->marker_needed = 0;
  1843. ha->isp_abort_cnt = 0;
  1844. ha->beacon_blink_led = 0;
  1845. set_bit(0, ha->req_qid_map);
  1846. set_bit(0, ha->rsp_qid_map);
  1847. ql_dbg(ql_dbg_init, vha, 0x0147,
  1848. "Configuring PCI space...\n");
  1849. rval = ha->isp_ops->pci_config(vha);
  1850. if (rval) {
  1851. ql_log(ql_log_warn, vha, 0x0148,
  1852. "Unable to configure PCI space.\n");
  1853. return rval;
  1854. }
  1855. rval = qlafx00_init_fw_ready(vha);
  1856. if (rval != QLA_SUCCESS)
  1857. return rval;
  1858. qlafx00_save_queue_ptrs(vha);
  1859. rval = qlafx00_config_queues(vha);
  1860. if (rval != QLA_SUCCESS)
  1861. return rval;
  1862. /*
  1863. * Allocate the array of outstanding commands
  1864. * now that we know the firmware resources.
  1865. */
  1866. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1867. if (rval != QLA_SUCCESS)
  1868. return rval;
  1869. rval = qla2x00_init_rings(vha);
  1870. ha->flags.chip_reset_done = 1;
  1871. tempc = QLAFX00_GET_TEMPERATURE(ha);
  1872. ql_dbg(ql_dbg_init, vha, 0x0152,
  1873. "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
  1874. __func__, tempc);
  1875. return rval;
  1876. }
  1877. uint32_t
  1878. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1879. char *buf)
  1880. {
  1881. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1882. int rval = QLA_FUNCTION_FAILED;
  1883. uint32_t state[1];
  1884. if (qla2x00_reset_active(vha))
  1885. ql_log(ql_log_warn, vha, 0x70ce,
  1886. "ISP reset active.\n");
  1887. else if (!vha->hw->flags.eeh_busy) {
  1888. rval = qlafx00_get_firmware_state(vha, state);
  1889. }
  1890. if (rval != QLA_SUCCESS)
  1891. memset(state, -1, sizeof(state));
  1892. return state[0];
  1893. }
  1894. void
  1895. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1896. {
  1897. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1898. (shost_priv(shost)))->hw;
  1899. u32 speed = FC_PORTSPEED_UNKNOWN;
  1900. switch (ha->link_data_rate) {
  1901. case QLAFX00_PORT_SPEED_2G:
  1902. speed = FC_PORTSPEED_2GBIT;
  1903. break;
  1904. case QLAFX00_PORT_SPEED_4G:
  1905. speed = FC_PORTSPEED_4GBIT;
  1906. break;
  1907. case QLAFX00_PORT_SPEED_8G:
  1908. speed = FC_PORTSPEED_8GBIT;
  1909. break;
  1910. case QLAFX00_PORT_SPEED_10G:
  1911. speed = FC_PORTSPEED_10GBIT;
  1912. break;
  1913. }
  1914. fc_host_speed(shost) = speed;
  1915. }
  1916. /** QLAFX00 specific ISR implementation functions */
  1917. static inline void
  1918. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1919. uint32_t sense_len, struct rsp_que *rsp, int res)
  1920. {
  1921. struct scsi_qla_host *vha = sp->fcport->vha;
  1922. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1923. uint32_t track_sense_len;
  1924. SET_FW_SENSE_LEN(sp, sense_len);
  1925. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1926. sense_len = SCSI_SENSE_BUFFERSIZE;
  1927. SET_CMD_SENSE_LEN(sp, sense_len);
  1928. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1929. track_sense_len = sense_len;
  1930. if (sense_len > par_sense_len)
  1931. sense_len = par_sense_len;
  1932. memcpy(cp->sense_buffer, sense_data, sense_len);
  1933. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1934. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1935. track_sense_len -= sense_len;
  1936. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1937. ql_dbg(ql_dbg_io, vha, 0x304d,
  1938. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1939. sense_len, par_sense_len, track_sense_len);
  1940. if (GET_FW_SENSE_LEN(sp) > 0) {
  1941. rsp->status_srb = sp;
  1942. cp->result = res;
  1943. }
  1944. if (sense_len) {
  1945. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1946. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1947. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1948. cp);
  1949. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1950. cp->sense_buffer, sense_len);
  1951. }
  1952. }
  1953. static void
  1954. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1955. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1956. __le16 sstatus, __le16 cpstatus)
  1957. {
  1958. struct srb_iocb *tmf;
  1959. tmf = &sp->u.iocb_cmd;
  1960. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1961. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1962. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1963. tmf->u.tmf.comp_status = cpstatus;
  1964. sp->done(vha, sp, 0);
  1965. }
  1966. static void
  1967. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1968. struct abort_iocb_entry_fx00 *pkt)
  1969. {
  1970. const char func[] = "ABT_IOCB";
  1971. srb_t *sp;
  1972. struct srb_iocb *abt;
  1973. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1974. if (!sp)
  1975. return;
  1976. abt = &sp->u.iocb_cmd;
  1977. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1978. sp->done(vha, sp, 0);
  1979. }
  1980. static void
  1981. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1982. struct ioctl_iocb_entry_fx00 *pkt)
  1983. {
  1984. const char func[] = "IOSB_IOCB";
  1985. srb_t *sp;
  1986. struct fc_bsg_job *bsg_job;
  1987. struct srb_iocb *iocb_job;
  1988. int res;
  1989. struct qla_mt_iocb_rsp_fx00 fstatus;
  1990. uint8_t *fw_sts_ptr;
  1991. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1992. if (!sp)
  1993. return;
  1994. if (sp->type == SRB_FXIOCB_DCMD) {
  1995. iocb_job = &sp->u.iocb_cmd;
  1996. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1997. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1998. iocb_job->u.fxiocb.result = pkt->status;
  1999. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  2000. iocb_job->u.fxiocb.req_data =
  2001. pkt->dataword_r;
  2002. } else {
  2003. bsg_job = sp->u.bsg_job;
  2004. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  2005. fstatus.reserved_1 = pkt->reserved_0;
  2006. fstatus.func_type = pkt->comp_func_num;
  2007. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  2008. fstatus.ioctl_data = pkt->dataword_r;
  2009. fstatus.adapid = pkt->adapid;
  2010. fstatus.adapid_hi = pkt->adapid_hi;
  2011. fstatus.reserved_2 = pkt->reserved_1;
  2012. fstatus.res_count = pkt->residuallen;
  2013. fstatus.status = pkt->status;
  2014. fstatus.seq_number = pkt->seq_no;
  2015. memcpy(fstatus.reserved_3,
  2016. pkt->reserved_2, 20 * sizeof(uint8_t));
  2017. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  2018. sizeof(struct fc_bsg_reply);
  2019. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  2020. sizeof(struct qla_mt_iocb_rsp_fx00));
  2021. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  2022. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  2023. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2024. sp->fcport->vha, 0x5080,
  2025. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  2026. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2027. sp->fcport->vha, 0x5074,
  2028. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  2029. res = bsg_job->reply->result = DID_OK << 16;
  2030. bsg_job->reply->reply_payload_rcv_len =
  2031. bsg_job->reply_payload.payload_len;
  2032. }
  2033. sp->done(vha, sp, res);
  2034. }
  2035. /**
  2036. * qlafx00_status_entry() - Process a Status IOCB entry.
  2037. * @ha: SCSI driver HA context
  2038. * @pkt: Entry pointer
  2039. */
  2040. static void
  2041. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  2042. {
  2043. srb_t *sp;
  2044. fc_port_t *fcport;
  2045. struct scsi_cmnd *cp;
  2046. struct sts_entry_fx00 *sts;
  2047. __le16 comp_status;
  2048. __le16 scsi_status;
  2049. uint16_t ox_id;
  2050. __le16 lscsi_status;
  2051. int32_t resid;
  2052. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  2053. fw_resid_len;
  2054. uint8_t *rsp_info = NULL, *sense_data = NULL;
  2055. struct qla_hw_data *ha = vha->hw;
  2056. uint32_t hindex, handle;
  2057. uint16_t que;
  2058. struct req_que *req;
  2059. int logit = 1;
  2060. int res = 0;
  2061. sts = (struct sts_entry_fx00 *) pkt;
  2062. comp_status = sts->comp_status;
  2063. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  2064. hindex = sts->handle;
  2065. handle = LSW(hindex);
  2066. que = MSW(hindex);
  2067. req = ha->req_q_map[que];
  2068. /* Validate handle. */
  2069. if (handle < req->num_outstanding_cmds)
  2070. sp = req->outstanding_cmds[handle];
  2071. else
  2072. sp = NULL;
  2073. if (sp == NULL) {
  2074. ql_dbg(ql_dbg_io, vha, 0x3034,
  2075. "Invalid status handle (0x%x).\n", handle);
  2076. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2077. qla2xxx_wake_dpc(vha);
  2078. return;
  2079. }
  2080. if (sp->type == SRB_TM_CMD) {
  2081. req->outstanding_cmds[handle] = NULL;
  2082. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  2083. scsi_status, comp_status);
  2084. return;
  2085. }
  2086. /* Fast path completion. */
  2087. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2088. qla2x00_do_host_ramp_up(vha);
  2089. qla2x00_process_completed_request(vha, req, handle);
  2090. return;
  2091. }
  2092. req->outstanding_cmds[handle] = NULL;
  2093. cp = GET_CMD_SP(sp);
  2094. if (cp == NULL) {
  2095. ql_dbg(ql_dbg_io, vha, 0x3048,
  2096. "Command already returned (0x%x/%p).\n",
  2097. handle, sp);
  2098. return;
  2099. }
  2100. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2101. fcport = sp->fcport;
  2102. ox_id = 0;
  2103. sense_len = par_sense_len = rsp_info_len = resid_len =
  2104. fw_resid_len = 0;
  2105. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2106. sense_len = sts->sense_len;
  2107. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2108. | (uint16_t)SS_RESIDUAL_OVER)))
  2109. resid_len = le32_to_cpu(sts->residual_len);
  2110. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2111. fw_resid_len = le32_to_cpu(sts->residual_len);
  2112. rsp_info = sense_data = sts->data;
  2113. par_sense_len = sizeof(sts->data);
  2114. /* Check for overrun. */
  2115. if (comp_status == CS_COMPLETE &&
  2116. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2117. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2118. /*
  2119. * Based on Host and scsi status generate status code for Linux
  2120. */
  2121. switch (le16_to_cpu(comp_status)) {
  2122. case CS_COMPLETE:
  2123. case CS_QUEUE_FULL:
  2124. if (scsi_status == 0) {
  2125. res = DID_OK << 16;
  2126. break;
  2127. }
  2128. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2129. | (uint16_t)SS_RESIDUAL_OVER))) {
  2130. resid = resid_len;
  2131. scsi_set_resid(cp, resid);
  2132. if (!lscsi_status &&
  2133. ((unsigned)(scsi_bufflen(cp) - resid) <
  2134. cp->underflow)) {
  2135. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2136. "Mid-layer underflow "
  2137. "detected (0x%x of 0x%x bytes).\n",
  2138. resid, scsi_bufflen(cp));
  2139. res = DID_ERROR << 16;
  2140. break;
  2141. }
  2142. }
  2143. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2144. if (lscsi_status ==
  2145. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2146. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2147. "QUEUE FULL detected.\n");
  2148. break;
  2149. }
  2150. logit = 0;
  2151. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2152. break;
  2153. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2154. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2155. break;
  2156. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2157. rsp, res);
  2158. break;
  2159. case CS_DATA_UNDERRUN:
  2160. /* Use F/W calculated residual length. */
  2161. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2162. resid = fw_resid_len;
  2163. else
  2164. resid = resid_len;
  2165. scsi_set_resid(cp, resid);
  2166. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2167. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2168. && fw_resid_len != resid_len) {
  2169. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2170. "Dropped frame(s) detected "
  2171. "(0x%x of 0x%x bytes).\n",
  2172. resid, scsi_bufflen(cp));
  2173. res = DID_ERROR << 16 |
  2174. le16_to_cpu(lscsi_status);
  2175. goto check_scsi_status;
  2176. }
  2177. if (!lscsi_status &&
  2178. ((unsigned)(scsi_bufflen(cp) - resid) <
  2179. cp->underflow)) {
  2180. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2181. "Mid-layer underflow "
  2182. "detected (0x%x of 0x%x bytes, "
  2183. "cp->underflow: 0x%x).\n",
  2184. resid, scsi_bufflen(cp), cp->underflow);
  2185. res = DID_ERROR << 16;
  2186. break;
  2187. }
  2188. } else if (lscsi_status !=
  2189. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2190. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2191. /*
  2192. * scsi status of task set and busy are considered
  2193. * to be task not completed.
  2194. */
  2195. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2196. "Dropped frame(s) detected (0x%x "
  2197. "of 0x%x bytes).\n", resid,
  2198. scsi_bufflen(cp));
  2199. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2200. goto check_scsi_status;
  2201. } else {
  2202. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2203. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2204. scsi_status, lscsi_status);
  2205. }
  2206. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2207. logit = 0;
  2208. check_scsi_status:
  2209. /*
  2210. * Check to see if SCSI Status is non zero. If so report SCSI
  2211. * Status.
  2212. */
  2213. if (lscsi_status != 0) {
  2214. if (lscsi_status ==
  2215. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2216. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2217. "QUEUE FULL detected.\n");
  2218. logit = 1;
  2219. break;
  2220. }
  2221. if (lscsi_status !=
  2222. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2223. break;
  2224. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2225. if (!(scsi_status &
  2226. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2227. break;
  2228. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2229. sense_len, rsp, res);
  2230. }
  2231. break;
  2232. case CS_PORT_LOGGED_OUT:
  2233. case CS_PORT_CONFIG_CHG:
  2234. case CS_PORT_BUSY:
  2235. case CS_INCOMPLETE:
  2236. case CS_PORT_UNAVAILABLE:
  2237. case CS_TIMEOUT:
  2238. case CS_RESET:
  2239. /*
  2240. * We are going to have the fc class block the rport
  2241. * while we try to recover so instruct the mid layer
  2242. * to requeue until the class decides how to handle this.
  2243. */
  2244. res = DID_TRANSPORT_DISRUPTED << 16;
  2245. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2246. "Port down status: port-state=0x%x.\n",
  2247. atomic_read(&fcport->state));
  2248. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2249. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2250. break;
  2251. case CS_ABORTED:
  2252. res = DID_RESET << 16;
  2253. break;
  2254. default:
  2255. res = DID_ERROR << 16;
  2256. break;
  2257. }
  2258. if (logit)
  2259. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2260. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  2261. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2262. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2263. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2264. comp_status, scsi_status, res, vha->host_no,
  2265. cp->device->id, cp->device->lun, fcport->tgt_id,
  2266. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2267. rsp_info_len, resid_len, fw_resid_len, sense_len,
  2268. par_sense_len, rsp_info_len);
  2269. if (!res)
  2270. qla2x00_do_host_ramp_up(vha);
  2271. if (rsp->status_srb == NULL)
  2272. sp->done(ha, sp, res);
  2273. }
  2274. /**
  2275. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2276. * @ha: SCSI driver HA context
  2277. * @pkt: Entry pointer
  2278. *
  2279. * Extended sense data.
  2280. */
  2281. static void
  2282. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2283. {
  2284. uint8_t sense_sz = 0;
  2285. struct qla_hw_data *ha = rsp->hw;
  2286. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2287. srb_t *sp = rsp->status_srb;
  2288. struct scsi_cmnd *cp;
  2289. uint32_t sense_len;
  2290. uint8_t *sense_ptr;
  2291. if (!sp) {
  2292. ql_dbg(ql_dbg_io, vha, 0x3037,
  2293. "no SP, sp = %p\n", sp);
  2294. return;
  2295. }
  2296. if (!GET_FW_SENSE_LEN(sp)) {
  2297. ql_dbg(ql_dbg_io, vha, 0x304b,
  2298. "no fw sense data, sp = %p\n", sp);
  2299. return;
  2300. }
  2301. cp = GET_CMD_SP(sp);
  2302. if (cp == NULL) {
  2303. ql_log(ql_log_warn, vha, 0x303b,
  2304. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2305. rsp->status_srb = NULL;
  2306. return;
  2307. }
  2308. if (!GET_CMD_SENSE_LEN(sp)) {
  2309. ql_dbg(ql_dbg_io, vha, 0x304c,
  2310. "no sense data, sp = %p\n", sp);
  2311. } else {
  2312. sense_len = GET_CMD_SENSE_LEN(sp);
  2313. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2314. ql_dbg(ql_dbg_io, vha, 0x304f,
  2315. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2316. sp, sense_len, sense_ptr);
  2317. if (sense_len > sizeof(pkt->data))
  2318. sense_sz = sizeof(pkt->data);
  2319. else
  2320. sense_sz = sense_len;
  2321. /* Move sense data. */
  2322. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2323. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2324. memcpy(sense_ptr, pkt->data, sense_sz);
  2325. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2326. sense_ptr, sense_sz);
  2327. sense_len -= sense_sz;
  2328. sense_ptr += sense_sz;
  2329. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2330. SET_CMD_SENSE_LEN(sp, sense_len);
  2331. }
  2332. sense_len = GET_FW_SENSE_LEN(sp);
  2333. sense_len = (sense_len > sizeof(pkt->data)) ?
  2334. (sense_len - sizeof(pkt->data)) : 0;
  2335. SET_FW_SENSE_LEN(sp, sense_len);
  2336. /* Place command on done queue. */
  2337. if (sense_len == 0) {
  2338. rsp->status_srb = NULL;
  2339. sp->done(ha, sp, cp->result);
  2340. }
  2341. }
  2342. /**
  2343. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2344. * @ha: SCSI driver HA context
  2345. */
  2346. static void
  2347. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2348. struct rsp_que *rsp, void *pkt)
  2349. {
  2350. srb_t *sp;
  2351. struct multi_sts_entry_fx00 *stsmfx;
  2352. struct qla_hw_data *ha = vha->hw;
  2353. uint32_t handle, hindex, handle_count, i;
  2354. uint16_t que;
  2355. struct req_que *req;
  2356. __le32 *handle_ptr;
  2357. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2358. handle_count = stsmfx->handle_count;
  2359. if (handle_count > MAX_HANDLE_COUNT) {
  2360. ql_dbg(ql_dbg_io, vha, 0x3035,
  2361. "Invalid handle count (0x%x).\n", handle_count);
  2362. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2363. qla2xxx_wake_dpc(vha);
  2364. return;
  2365. }
  2366. handle_ptr = &stsmfx->handles[0];
  2367. for (i = 0; i < handle_count; i++) {
  2368. hindex = le32_to_cpu(*handle_ptr);
  2369. handle = LSW(hindex);
  2370. que = MSW(hindex);
  2371. req = ha->req_q_map[que];
  2372. /* Validate handle. */
  2373. if (handle < req->num_outstanding_cmds)
  2374. sp = req->outstanding_cmds[handle];
  2375. else
  2376. sp = NULL;
  2377. if (sp == NULL) {
  2378. ql_dbg(ql_dbg_io, vha, 0x3044,
  2379. "Invalid status handle (0x%x).\n", handle);
  2380. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2381. qla2xxx_wake_dpc(vha);
  2382. return;
  2383. }
  2384. qla2x00_process_completed_request(vha, req, handle);
  2385. handle_ptr++;
  2386. }
  2387. }
  2388. /**
  2389. * qlafx00_error_entry() - Process an error entry.
  2390. * @ha: SCSI driver HA context
  2391. * @pkt: Entry pointer
  2392. */
  2393. static void
  2394. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2395. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2396. {
  2397. srb_t *sp;
  2398. struct qla_hw_data *ha = vha->hw;
  2399. const char func[] = "ERROR-IOCB";
  2400. uint16_t que = MSW(pkt->handle);
  2401. struct req_que *req = NULL;
  2402. int res = DID_ERROR << 16;
  2403. ql_dbg(ql_dbg_async, vha, 0x507f,
  2404. "type of error status in response: 0x%x\n", estatus);
  2405. req = ha->req_q_map[que];
  2406. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2407. if (sp) {
  2408. sp->done(ha, sp, res);
  2409. return;
  2410. }
  2411. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2412. qla2xxx_wake_dpc(vha);
  2413. }
  2414. /**
  2415. * qlafx00_process_response_queue() - Process response queue entries.
  2416. * @ha: SCSI driver HA context
  2417. */
  2418. static void
  2419. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2420. struct rsp_que *rsp)
  2421. {
  2422. struct sts_entry_fx00 *pkt;
  2423. response_t *lptr;
  2424. while (RD_REG_DWORD((void __iomem *)&(rsp->ring_ptr->signature)) !=
  2425. RESPONSE_PROCESSED) {
  2426. lptr = rsp->ring_ptr;
  2427. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2428. sizeof(rsp->rsp_pkt));
  2429. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2430. rsp->ring_index++;
  2431. if (rsp->ring_index == rsp->length) {
  2432. rsp->ring_index = 0;
  2433. rsp->ring_ptr = rsp->ring;
  2434. } else {
  2435. rsp->ring_ptr++;
  2436. }
  2437. if (pkt->entry_status != 0 &&
  2438. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2439. qlafx00_error_entry(vha, rsp,
  2440. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2441. pkt->entry_type);
  2442. goto next_iter;
  2443. continue;
  2444. }
  2445. switch (pkt->entry_type) {
  2446. case STATUS_TYPE_FX00:
  2447. qlafx00_status_entry(vha, rsp, pkt);
  2448. break;
  2449. case STATUS_CONT_TYPE_FX00:
  2450. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2451. break;
  2452. case MULTI_STATUS_TYPE_FX00:
  2453. qlafx00_multistatus_entry(vha, rsp, pkt);
  2454. break;
  2455. case ABORT_IOCB_TYPE_FX00:
  2456. qlafx00_abort_iocb_entry(vha, rsp->req,
  2457. (struct abort_iocb_entry_fx00 *)pkt);
  2458. break;
  2459. case IOCTL_IOSB_TYPE_FX00:
  2460. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2461. (struct ioctl_iocb_entry_fx00 *)pkt);
  2462. break;
  2463. default:
  2464. /* Type Not Supported. */
  2465. ql_dbg(ql_dbg_async, vha, 0x5081,
  2466. "Received unknown response pkt type %x "
  2467. "entry status=%x.\n",
  2468. pkt->entry_type, pkt->entry_status);
  2469. break;
  2470. }
  2471. next_iter:
  2472. WRT_REG_DWORD((void __iomem *)&lptr->signature,
  2473. RESPONSE_PROCESSED);
  2474. wmb();
  2475. }
  2476. /* Adjust ring index */
  2477. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2478. }
  2479. /**
  2480. * qlafx00_async_event() - Process aynchronous events.
  2481. * @ha: SCSI driver HA context
  2482. */
  2483. static void
  2484. qlafx00_async_event(scsi_qla_host_t *vha)
  2485. {
  2486. struct qla_hw_data *ha = vha->hw;
  2487. struct device_reg_fx00 __iomem *reg;
  2488. int data_size = 1;
  2489. reg = &ha->iobase->ispfx00;
  2490. /* Setup to process RIO completion. */
  2491. switch (ha->aenmb[0]) {
  2492. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2493. ql_log(ql_log_warn, vha, 0x5079,
  2494. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2495. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2496. break;
  2497. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2498. ql_dbg(ql_dbg_async, vha, 0x5076,
  2499. "Asynchronous FW shutdown requested.\n");
  2500. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2501. qla2xxx_wake_dpc(vha);
  2502. break;
  2503. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2504. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2505. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2506. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2507. ql_dbg(ql_dbg_async, vha, 0x5077,
  2508. "Asynchronous port Update received "
  2509. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2510. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2511. data_size = 4;
  2512. break;
  2513. case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
  2514. case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
  2515. ql_log(ql_log_info, vha, 0x5083,
  2516. "Asynchronous critical temperature event received "
  2517. "aenmb[0]: %x\n",
  2518. ha->aenmb[0]);
  2519. break;
  2520. default:
  2521. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2522. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2523. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2524. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2525. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2526. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2527. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2528. ql_dbg(ql_dbg_async, vha, 0x5078,
  2529. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2530. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2531. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2532. break;
  2533. }
  2534. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2535. (uint32_t *)ha->aenmb, data_size);
  2536. }
  2537. /**
  2538. *
  2539. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2540. * @ha: SCSI driver HA context
  2541. * @mb16: Mailbox16 register
  2542. */
  2543. static void
  2544. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2545. {
  2546. uint16_t cnt;
  2547. uint16_t __iomem *wptr;
  2548. struct qla_hw_data *ha = vha->hw;
  2549. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2550. if (!ha->mcp32)
  2551. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2552. /* Load return mailbox registers. */
  2553. ha->flags.mbox_int = 1;
  2554. ha->mailbox_out32[0] = mb0;
  2555. wptr = (uint16_t __iomem *)&reg->mailbox17;
  2556. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2557. ha->mailbox_out32[cnt] = RD_REG_WORD(wptr);
  2558. wptr++;
  2559. }
  2560. }
  2561. /**
  2562. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2563. * @irq:
  2564. * @dev_id: SCSI driver HA context
  2565. *
  2566. * Called by system whenever the host adapter generates an interrupt.
  2567. *
  2568. * Returns handled flag.
  2569. */
  2570. irqreturn_t
  2571. qlafx00_intr_handler(int irq, void *dev_id)
  2572. {
  2573. scsi_qla_host_t *vha;
  2574. struct qla_hw_data *ha;
  2575. struct device_reg_fx00 __iomem *reg;
  2576. int status;
  2577. unsigned long iter;
  2578. uint32_t stat;
  2579. uint32_t mb[8];
  2580. struct rsp_que *rsp;
  2581. unsigned long flags;
  2582. uint32_t clr_intr = 0;
  2583. rsp = (struct rsp_que *) dev_id;
  2584. if (!rsp) {
  2585. ql_log(ql_log_info, NULL, 0x507d,
  2586. "%s: NULL response queue pointer.\n", __func__);
  2587. return IRQ_NONE;
  2588. }
  2589. ha = rsp->hw;
  2590. reg = &ha->iobase->ispfx00;
  2591. status = 0;
  2592. if (unlikely(pci_channel_offline(ha->pdev)))
  2593. return IRQ_HANDLED;
  2594. spin_lock_irqsave(&ha->hardware_lock, flags);
  2595. vha = pci_get_drvdata(ha->pdev);
  2596. for (iter = 50; iter--; clr_intr = 0) {
  2597. stat = QLAFX00_RD_INTR_REG(ha);
  2598. if ((stat & QLAFX00_HST_INT_STS_BITS) == 0)
  2599. break;
  2600. switch (stat & QLAFX00_HST_INT_STS_BITS) {
  2601. case QLAFX00_INTR_MB_CMPLT:
  2602. case QLAFX00_INTR_MB_RSP_CMPLT:
  2603. case QLAFX00_INTR_MB_ASYNC_CMPLT:
  2604. case QLAFX00_INTR_ALL_CMPLT:
  2605. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2606. qlafx00_mbx_completion(vha, mb[0]);
  2607. status |= MBX_INTERRUPT;
  2608. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2609. break;
  2610. case QLAFX00_INTR_ASYNC_CMPLT:
  2611. case QLAFX00_INTR_RSP_ASYNC_CMPLT:
  2612. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2613. qlafx00_async_event(vha);
  2614. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2615. break;
  2616. case QLAFX00_INTR_RSP_CMPLT:
  2617. qlafx00_process_response_queue(vha, rsp);
  2618. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2619. break;
  2620. default:
  2621. ql_dbg(ql_dbg_async, vha, 0x507a,
  2622. "Unrecognized interrupt type (%d).\n", stat);
  2623. break;
  2624. }
  2625. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2626. QLAFX00_RD_INTR_REG(ha);
  2627. }
  2628. qla2x00_handle_mbx_completion(ha, status);
  2629. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2630. return IRQ_HANDLED;
  2631. }
  2632. /** QLAFX00 specific IOCB implementation functions */
  2633. static inline cont_a64_entry_t *
  2634. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2635. cont_a64_entry_t *lcont_pkt)
  2636. {
  2637. cont_a64_entry_t *cont_pkt;
  2638. /* Adjust ring index. */
  2639. req->ring_index++;
  2640. if (req->ring_index == req->length) {
  2641. req->ring_index = 0;
  2642. req->ring_ptr = req->ring;
  2643. } else {
  2644. req->ring_ptr++;
  2645. }
  2646. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2647. /* Load packet defaults. */
  2648. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2649. return cont_pkt;
  2650. }
  2651. static inline void
  2652. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2653. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2654. {
  2655. uint16_t avail_dsds;
  2656. __le32 *cur_dsd;
  2657. scsi_qla_host_t *vha;
  2658. struct scsi_cmnd *cmd;
  2659. struct scatterlist *sg;
  2660. int i, cont;
  2661. struct req_que *req;
  2662. cont_a64_entry_t lcont_pkt;
  2663. cont_a64_entry_t *cont_pkt;
  2664. vha = sp->fcport->vha;
  2665. req = vha->req;
  2666. cmd = GET_CMD_SP(sp);
  2667. cont = 0;
  2668. cont_pkt = NULL;
  2669. /* Update entry type to indicate Command Type 3 IOCB */
  2670. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2671. /* No data transfer */
  2672. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2673. lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
  2674. return;
  2675. }
  2676. /* Set transfer direction */
  2677. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2678. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2679. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2680. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2681. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2682. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2683. }
  2684. /* One DSD is available in the Command Type 3 IOCB */
  2685. avail_dsds = 1;
  2686. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2687. /* Load data segments */
  2688. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2689. dma_addr_t sle_dma;
  2690. /* Allocate additional continuation packets? */
  2691. if (avail_dsds == 0) {
  2692. /*
  2693. * Five DSDs are available in the Continuation
  2694. * Type 1 IOCB.
  2695. */
  2696. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2697. cont_pkt =
  2698. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2699. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2700. avail_dsds = 5;
  2701. cont = 1;
  2702. }
  2703. sle_dma = sg_dma_address(sg);
  2704. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2705. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2706. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2707. avail_dsds--;
  2708. if (avail_dsds == 0 && cont == 1) {
  2709. cont = 0;
  2710. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2711. REQUEST_ENTRY_SIZE);
  2712. }
  2713. }
  2714. if (avail_dsds != 0 && cont == 1) {
  2715. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2716. REQUEST_ENTRY_SIZE);
  2717. }
  2718. }
  2719. /**
  2720. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2721. * @sp: command to send to the ISP
  2722. *
  2723. * Returns non-zero if a failure occurred, else zero.
  2724. */
  2725. int
  2726. qlafx00_start_scsi(srb_t *sp)
  2727. {
  2728. int ret, nseg;
  2729. unsigned long flags;
  2730. uint32_t index;
  2731. uint32_t handle;
  2732. uint16_t cnt;
  2733. uint16_t req_cnt;
  2734. uint16_t tot_dsds;
  2735. struct req_que *req = NULL;
  2736. struct rsp_que *rsp = NULL;
  2737. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2738. struct scsi_qla_host *vha = sp->fcport->vha;
  2739. struct qla_hw_data *ha = vha->hw;
  2740. struct cmd_type_7_fx00 *cmd_pkt;
  2741. struct cmd_type_7_fx00 lcmd_pkt;
  2742. struct scsi_lun llun;
  2743. char tag[2];
  2744. /* Setup device pointers. */
  2745. ret = 0;
  2746. rsp = ha->rsp_q_map[0];
  2747. req = vha->req;
  2748. /* So we know we haven't pci_map'ed anything yet */
  2749. tot_dsds = 0;
  2750. /* Forcing marker needed for now */
  2751. vha->marker_needed = 0;
  2752. /* Send marker if required */
  2753. if (vha->marker_needed != 0) {
  2754. if (qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL) !=
  2755. QLA_SUCCESS)
  2756. return QLA_FUNCTION_FAILED;
  2757. vha->marker_needed = 0;
  2758. }
  2759. /* Acquire ring specific lock */
  2760. spin_lock_irqsave(&ha->hardware_lock, flags);
  2761. /* Check for room in outstanding command list. */
  2762. handle = req->current_outstanding_cmd;
  2763. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2764. handle++;
  2765. if (handle == req->num_outstanding_cmds)
  2766. handle = 1;
  2767. if (!req->outstanding_cmds[handle])
  2768. break;
  2769. }
  2770. if (index == req->num_outstanding_cmds)
  2771. goto queuing_error;
  2772. /* Map the sg table so we have an accurate count of sg entries needed */
  2773. if (scsi_sg_count(cmd)) {
  2774. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2775. scsi_sg_count(cmd), cmd->sc_data_direction);
  2776. if (unlikely(!nseg))
  2777. goto queuing_error;
  2778. } else
  2779. nseg = 0;
  2780. tot_dsds = nseg;
  2781. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2782. if (req->cnt < (req_cnt + 2)) {
  2783. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2784. if (req->ring_index < cnt)
  2785. req->cnt = cnt - req->ring_index;
  2786. else
  2787. req->cnt = req->length -
  2788. (req->ring_index - cnt);
  2789. if (req->cnt < (req_cnt + 2))
  2790. goto queuing_error;
  2791. }
  2792. /* Build command packet. */
  2793. req->current_outstanding_cmd = handle;
  2794. req->outstanding_cmds[handle] = sp;
  2795. sp->handle = handle;
  2796. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2797. req->cnt -= req_cnt;
  2798. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2799. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2800. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2801. lcmd_pkt.handle_hi = 0;
  2802. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2803. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2804. int_to_scsilun(cmd->device->lun, &llun);
  2805. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2806. sizeof(lcmd_pkt.lun));
  2807. /* Update tagged queuing modifier -- default is TSK_SIMPLE (0). */
  2808. if (scsi_populate_tag_msg(cmd, tag)) {
  2809. switch (tag[0]) {
  2810. case HEAD_OF_QUEUE_TAG:
  2811. lcmd_pkt.task = TSK_HEAD_OF_QUEUE;
  2812. break;
  2813. case ORDERED_QUEUE_TAG:
  2814. lcmd_pkt.task = TSK_ORDERED;
  2815. break;
  2816. }
  2817. }
  2818. /* Load SCSI command packet. */
  2819. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2820. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2821. /* Build IOCB segments */
  2822. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2823. /* Set total data segment count. */
  2824. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2825. /* Specify response queue number where completion should happen */
  2826. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2827. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2828. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2829. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2830. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2831. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2832. wmb();
  2833. /* Adjust ring index. */
  2834. req->ring_index++;
  2835. if (req->ring_index == req->length) {
  2836. req->ring_index = 0;
  2837. req->ring_ptr = req->ring;
  2838. } else
  2839. req->ring_ptr++;
  2840. sp->flags |= SRB_DMA_VALID;
  2841. /* Set chip new ring index. */
  2842. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2843. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2844. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2845. return QLA_SUCCESS;
  2846. queuing_error:
  2847. if (tot_dsds)
  2848. scsi_dma_unmap(cmd);
  2849. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2850. return QLA_FUNCTION_FAILED;
  2851. }
  2852. void
  2853. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2854. {
  2855. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2856. scsi_qla_host_t *vha = sp->fcport->vha;
  2857. struct req_que *req = vha->req;
  2858. struct tsk_mgmt_entry_fx00 tm_iocb;
  2859. struct scsi_lun llun;
  2860. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2861. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2862. tm_iocb.entry_count = 1;
  2863. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2864. tm_iocb.handle_hi = 0;
  2865. tm_iocb.timeout = cpu_to_le16(qla2x00_get_async_timeout(vha) + 2);
  2866. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2867. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2868. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2869. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2870. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2871. sizeof(struct scsi_lun));
  2872. }
  2873. memcpy((void *)ptm_iocb, &tm_iocb,
  2874. sizeof(struct tsk_mgmt_entry_fx00));
  2875. wmb();
  2876. }
  2877. void
  2878. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2879. {
  2880. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2881. scsi_qla_host_t *vha = sp->fcport->vha;
  2882. struct req_que *req = vha->req;
  2883. struct abort_iocb_entry_fx00 abt_iocb;
  2884. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2885. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2886. abt_iocb.entry_count = 1;
  2887. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2888. abt_iocb.abort_handle =
  2889. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2890. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2891. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2892. memcpy((void *)pabt_iocb, &abt_iocb,
  2893. sizeof(struct abort_iocb_entry_fx00));
  2894. wmb();
  2895. }
  2896. void
  2897. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2898. {
  2899. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2900. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2901. struct fc_bsg_job *bsg_job;
  2902. struct fxdisc_entry_fx00 fx_iocb;
  2903. uint8_t entry_cnt = 1;
  2904. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2905. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2906. fx_iocb.handle = cpu_to_le32(sp->handle);
  2907. fx_iocb.entry_count = entry_cnt;
  2908. if (sp->type == SRB_FXIOCB_DCMD) {
  2909. fx_iocb.func_num =
  2910. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2911. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2912. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2913. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2914. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2915. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2916. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2917. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2918. fx_iocb.req_xfrcnt =
  2919. cpu_to_le16(fxio->u.fxiocb.req_len);
  2920. fx_iocb.dseg_rq_address[0] =
  2921. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2922. fx_iocb.dseg_rq_address[1] =
  2923. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2924. fx_iocb.dseg_rq_len =
  2925. cpu_to_le32(fxio->u.fxiocb.req_len);
  2926. }
  2927. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2928. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2929. fx_iocb.rsp_xfrcnt =
  2930. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2931. fx_iocb.dseg_rsp_address[0] =
  2932. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2933. fx_iocb.dseg_rsp_address[1] =
  2934. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2935. fx_iocb.dseg_rsp_len =
  2936. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2937. }
  2938. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2939. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2940. }
  2941. fx_iocb.flags = fxio->u.fxiocb.flags;
  2942. } else {
  2943. struct scatterlist *sg;
  2944. bsg_job = sp->u.bsg_job;
  2945. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2946. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2947. fx_iocb.func_num = piocb_rqst->func_type;
  2948. fx_iocb.adapid = piocb_rqst->adapid;
  2949. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2950. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2951. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2952. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2953. fx_iocb.dataword = piocb_rqst->dataword;
  2954. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2955. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2956. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2957. int avail_dsds, tot_dsds;
  2958. cont_a64_entry_t lcont_pkt;
  2959. cont_a64_entry_t *cont_pkt = NULL;
  2960. __le32 *cur_dsd;
  2961. int index = 0, cont = 0;
  2962. fx_iocb.req_dsdcnt =
  2963. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2964. tot_dsds =
  2965. bsg_job->request_payload.sg_cnt;
  2966. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2967. avail_dsds = 1;
  2968. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2969. tot_dsds, index) {
  2970. dma_addr_t sle_dma;
  2971. /* Allocate additional continuation packets? */
  2972. if (avail_dsds == 0) {
  2973. /*
  2974. * Five DSDs are available in the Cont.
  2975. * Type 1 IOCB.
  2976. */
  2977. memset(&lcont_pkt, 0,
  2978. REQUEST_ENTRY_SIZE);
  2979. cont_pkt =
  2980. qlafx00_prep_cont_type1_iocb(
  2981. sp->fcport->vha->req,
  2982. &lcont_pkt);
  2983. cur_dsd = (__le32 *)
  2984. lcont_pkt.dseg_0_address;
  2985. avail_dsds = 5;
  2986. cont = 1;
  2987. entry_cnt++;
  2988. }
  2989. sle_dma = sg_dma_address(sg);
  2990. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2991. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2992. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2993. avail_dsds--;
  2994. if (avail_dsds == 0 && cont == 1) {
  2995. cont = 0;
  2996. memcpy_toio(
  2997. (void __iomem *)cont_pkt,
  2998. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2999. ql_dump_buffer(
  3000. ql_dbg_user + ql_dbg_verbose,
  3001. sp->fcport->vha, 0x3042,
  3002. (uint8_t *)&lcont_pkt,
  3003. REQUEST_ENTRY_SIZE);
  3004. }
  3005. }
  3006. if (avail_dsds != 0 && cont == 1) {
  3007. memcpy_toio((void __iomem *)cont_pkt,
  3008. &lcont_pkt, REQUEST_ENTRY_SIZE);
  3009. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  3010. sp->fcport->vha, 0x3043,
  3011. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  3012. }
  3013. }
  3014. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  3015. int avail_dsds, tot_dsds;
  3016. cont_a64_entry_t lcont_pkt;
  3017. cont_a64_entry_t *cont_pkt = NULL;
  3018. __le32 *cur_dsd;
  3019. int index = 0, cont = 0;
  3020. fx_iocb.rsp_dsdcnt =
  3021. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  3022. tot_dsds = bsg_job->reply_payload.sg_cnt;
  3023. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  3024. avail_dsds = 1;
  3025. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  3026. tot_dsds, index) {
  3027. dma_addr_t sle_dma;
  3028. /* Allocate additional continuation packets? */
  3029. if (avail_dsds == 0) {
  3030. /*
  3031. * Five DSDs are available in the Cont.
  3032. * Type 1 IOCB.
  3033. */
  3034. memset(&lcont_pkt, 0,
  3035. REQUEST_ENTRY_SIZE);
  3036. cont_pkt =
  3037. qlafx00_prep_cont_type1_iocb(
  3038. sp->fcport->vha->req,
  3039. &lcont_pkt);
  3040. cur_dsd = (__le32 *)
  3041. lcont_pkt.dseg_0_address;
  3042. avail_dsds = 5;
  3043. cont = 1;
  3044. entry_cnt++;
  3045. }
  3046. sle_dma = sg_dma_address(sg);
  3047. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  3048. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  3049. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  3050. avail_dsds--;
  3051. if (avail_dsds == 0 && cont == 1) {
  3052. cont = 0;
  3053. memcpy_toio((void __iomem *)cont_pkt,
  3054. &lcont_pkt,
  3055. REQUEST_ENTRY_SIZE);
  3056. ql_dump_buffer(
  3057. ql_dbg_user + ql_dbg_verbose,
  3058. sp->fcport->vha, 0x3045,
  3059. (uint8_t *)&lcont_pkt,
  3060. REQUEST_ENTRY_SIZE);
  3061. }
  3062. }
  3063. if (avail_dsds != 0 && cont == 1) {
  3064. memcpy_toio((void __iomem *)cont_pkt,
  3065. &lcont_pkt, REQUEST_ENTRY_SIZE);
  3066. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  3067. sp->fcport->vha, 0x3046,
  3068. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  3069. }
  3070. }
  3071. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  3072. fx_iocb.dataword = piocb_rqst->dataword;
  3073. fx_iocb.flags = piocb_rqst->flags;
  3074. fx_iocb.entry_count = entry_cnt;
  3075. }
  3076. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  3077. sp->fcport->vha, 0x3047,
  3078. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  3079. memcpy((void *)pfxiocb, &fx_iocb,
  3080. sizeof(struct fxdisc_entry_fx00));
  3081. wmb();
  3082. }