sh_dma.h 2.5 KB

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  1. /*
  2. * Header for the new SH dmaengine driver
  3. *
  4. * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef SH_DMA_H
  11. #define SH_DMA_H
  12. #include <linux/list.h>
  13. #include <linux/dmaengine.h>
  14. /* Used by slave DMA clients to request DMA to/from a specific peripheral */
  15. struct sh_dmae_slave {
  16. unsigned int slave_id; /* Set by the platform */
  17. struct device *dma_dev; /* Set by the platform */
  18. const struct sh_dmae_slave_config *config; /* Set by the driver */
  19. };
  20. struct sh_dmae_regs {
  21. u32 sar; /* SAR / source address */
  22. u32 dar; /* DAR / destination address */
  23. u32 tcr; /* TCR / transfer count */
  24. };
  25. struct sh_desc {
  26. struct sh_dmae_regs hw;
  27. struct list_head node;
  28. struct dma_async_tx_descriptor async_tx;
  29. enum dma_transfer_direction direction;
  30. dma_cookie_t cookie;
  31. size_t partial;
  32. int chunks;
  33. int mark;
  34. };
  35. struct sh_dmae_slave_config {
  36. unsigned int slave_id;
  37. dma_addr_t addr;
  38. u32 chcr;
  39. char mid_rid;
  40. };
  41. struct sh_dmae_channel {
  42. unsigned int offset;
  43. unsigned int dmars;
  44. unsigned int dmars_bit;
  45. unsigned int chclr_offset;
  46. };
  47. struct sh_dmae_pdata {
  48. const struct sh_dmae_slave_config *slave;
  49. int slave_num;
  50. const struct sh_dmae_channel *channel;
  51. int channel_num;
  52. unsigned int ts_low_shift;
  53. unsigned int ts_low_mask;
  54. unsigned int ts_high_shift;
  55. unsigned int ts_high_mask;
  56. const unsigned int *ts_shift;
  57. int ts_shift_num;
  58. u16 dmaor_init;
  59. unsigned int chcr_offset;
  60. u32 chcr_ie_bit;
  61. unsigned int dmaor_is_32bit:1;
  62. unsigned int needs_tend_set:1;
  63. unsigned int no_dmars:1;
  64. unsigned int chclr_present:1;
  65. };
  66. /* DMA register */
  67. #define SAR 0x00
  68. #define DAR 0x04
  69. #define TCR 0x08
  70. #define CHCR 0x0C
  71. #define DMAOR 0x40
  72. #define TEND 0x18 /* USB-DMAC */
  73. /* DMAOR definitions */
  74. #define DMAOR_AE 0x00000004
  75. #define DMAOR_NMIF 0x00000002
  76. #define DMAOR_DME 0x00000001
  77. /* Definitions for the SuperH DMAC */
  78. #define REQ_L 0x00000000
  79. #define REQ_E 0x00080000
  80. #define RACK_H 0x00000000
  81. #define RACK_L 0x00040000
  82. #define ACK_R 0x00000000
  83. #define ACK_W 0x00020000
  84. #define ACK_H 0x00000000
  85. #define ACK_L 0x00010000
  86. #define DM_INC 0x00004000
  87. #define DM_DEC 0x00008000
  88. #define DM_FIX 0x0000c000
  89. #define SM_INC 0x00001000
  90. #define SM_DEC 0x00002000
  91. #define SM_FIX 0x00003000
  92. #define RS_IN 0x00000200
  93. #define RS_OUT 0x00000300
  94. #define TS_BLK 0x00000040
  95. #define TM_BUR 0x00000020
  96. #define CHCR_DE 0x00000001
  97. #define CHCR_TE 0x00000002
  98. #define CHCR_IE 0x00000004
  99. #endif