cnic.c 144 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  47. #include "cnic.h"
  48. #include "cnic_defs.h"
  49. #define DRV_MODULE_NAME "cnic"
  50. static char version[] __devinitdata =
  51. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  52. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  53. "Chen (zongxi@broadcom.com");
  54. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(CNIC_MODULE_VERSION);
  57. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  58. static LIST_HEAD(cnic_dev_list);
  59. static LIST_HEAD(cnic_udev_list);
  60. static DEFINE_RWLOCK(cnic_dev_lock);
  61. static DEFINE_MUTEX(cnic_lock);
  62. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  63. /* helper function, assuming cnic_lock is held */
  64. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  65. {
  66. return rcu_dereference_protected(cnic_ulp_tbl[type],
  67. lockdep_is_held(&cnic_lock));
  68. }
  69. static int cnic_service_bnx2(void *, void *);
  70. static int cnic_service_bnx2x(void *, void *);
  71. static int cnic_ctl(void *, struct cnic_ctl_info *);
  72. static struct cnic_ops cnic_bnx2_ops = {
  73. .cnic_owner = THIS_MODULE,
  74. .cnic_handler = cnic_service_bnx2,
  75. .cnic_ctl = cnic_ctl,
  76. };
  77. static struct cnic_ops cnic_bnx2x_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2x,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct workqueue_struct *cnic_wq;
  83. static void cnic_shutdown_rings(struct cnic_dev *);
  84. static void cnic_init_rings(struct cnic_dev *);
  85. static int cnic_cm_set_pg(struct cnic_sock *);
  86. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  87. {
  88. struct cnic_uio_dev *udev = uinfo->priv;
  89. struct cnic_dev *dev;
  90. if (!capable(CAP_NET_ADMIN))
  91. return -EPERM;
  92. if (udev->uio_dev != -1)
  93. return -EBUSY;
  94. rtnl_lock();
  95. dev = udev->dev;
  96. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  97. rtnl_unlock();
  98. return -ENODEV;
  99. }
  100. udev->uio_dev = iminor(inode);
  101. cnic_shutdown_rings(dev);
  102. cnic_init_rings(dev);
  103. rtnl_unlock();
  104. return 0;
  105. }
  106. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  107. {
  108. struct cnic_uio_dev *udev = uinfo->priv;
  109. udev->uio_dev = -1;
  110. return 0;
  111. }
  112. static inline void cnic_hold(struct cnic_dev *dev)
  113. {
  114. atomic_inc(&dev->ref_count);
  115. }
  116. static inline void cnic_put(struct cnic_dev *dev)
  117. {
  118. atomic_dec(&dev->ref_count);
  119. }
  120. static inline void csk_hold(struct cnic_sock *csk)
  121. {
  122. atomic_inc(&csk->ref_count);
  123. }
  124. static inline void csk_put(struct cnic_sock *csk)
  125. {
  126. atomic_dec(&csk->ref_count);
  127. }
  128. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  129. {
  130. struct cnic_dev *cdev;
  131. read_lock(&cnic_dev_lock);
  132. list_for_each_entry(cdev, &cnic_dev_list, list) {
  133. if (netdev == cdev->netdev) {
  134. cnic_hold(cdev);
  135. read_unlock(&cnic_dev_lock);
  136. return cdev;
  137. }
  138. }
  139. read_unlock(&cnic_dev_lock);
  140. return NULL;
  141. }
  142. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  143. {
  144. atomic_inc(&ulp_ops->ref_count);
  145. }
  146. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_dec(&ulp_ops->ref_count);
  149. }
  150. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTX_WR_CMD;
  157. io->cid_addr = cid_addr;
  158. io->offset = off;
  159. io->data = val;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_io *io = &info.data.io;
  168. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  169. io->offset = off;
  170. io->dma_addr = addr;
  171. ethdev->drv_ctl(dev->netdev, &info);
  172. }
  173. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  174. {
  175. struct cnic_local *cp = dev->cnic_priv;
  176. struct cnic_eth_dev *ethdev = cp->ethdev;
  177. struct drv_ctl_info info;
  178. struct drv_ctl_l2_ring *ring = &info.data.ring;
  179. if (start)
  180. info.cmd = DRV_CTL_START_L2_CMD;
  181. else
  182. info.cmd = DRV_CTL_STOP_L2_CMD;
  183. ring->cid = cid;
  184. ring->client_id = cl_id;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_WR_CMD;
  194. io->offset = off;
  195. io->data = val;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. }
  198. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  199. {
  200. struct cnic_local *cp = dev->cnic_priv;
  201. struct cnic_eth_dev *ethdev = cp->ethdev;
  202. struct drv_ctl_info info;
  203. struct drv_ctl_io *io = &info.data.io;
  204. info.cmd = DRV_CTL_IO_RD_CMD;
  205. io->offset = off;
  206. ethdev->drv_ctl(dev->netdev, &info);
  207. return io->data;
  208. }
  209. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  210. {
  211. struct cnic_local *cp = dev->cnic_priv;
  212. struct cnic_eth_dev *ethdev = cp->ethdev;
  213. struct drv_ctl_info info;
  214. if (reg)
  215. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  216. else
  217. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  218. info.data.ulp_type = ulp_type;
  219. ethdev->drv_ctl(dev->netdev, &info);
  220. }
  221. static int cnic_in_use(struct cnic_sock *csk)
  222. {
  223. return test_bit(SK_F_INUSE, &csk->flags);
  224. }
  225. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  226. {
  227. struct cnic_local *cp = dev->cnic_priv;
  228. struct cnic_eth_dev *ethdev = cp->ethdev;
  229. struct drv_ctl_info info;
  230. info.cmd = cmd;
  231. info.data.credit.credit_count = count;
  232. ethdev->drv_ctl(dev->netdev, &info);
  233. }
  234. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  235. {
  236. u32 i;
  237. for (i = 0; i < cp->max_cid_space; i++) {
  238. if (cp->ctx_tbl[i].cid == cid) {
  239. *l5_cid = i;
  240. return 0;
  241. }
  242. }
  243. return -EINVAL;
  244. }
  245. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  246. struct cnic_sock *csk)
  247. {
  248. struct iscsi_path path_req;
  249. char *buf = NULL;
  250. u16 len = 0;
  251. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  252. struct cnic_ulp_ops *ulp_ops;
  253. struct cnic_uio_dev *udev = cp->udev;
  254. int rc = 0, retry = 0;
  255. if (!udev || udev->uio_dev == -1)
  256. return -ENODEV;
  257. if (csk) {
  258. len = sizeof(path_req);
  259. buf = (char *) &path_req;
  260. memset(&path_req, 0, len);
  261. msg_type = ISCSI_KEVENT_PATH_REQ;
  262. path_req.handle = (u64) csk->l5_cid;
  263. if (test_bit(SK_F_IPV6, &csk->flags)) {
  264. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  265. sizeof(struct in6_addr));
  266. path_req.ip_addr_len = 16;
  267. } else {
  268. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  269. sizeof(struct in_addr));
  270. path_req.ip_addr_len = 4;
  271. }
  272. path_req.vlan_id = csk->vlan_id;
  273. path_req.pmtu = csk->mtu;
  274. }
  275. while (retry < 3) {
  276. rc = 0;
  277. rcu_read_lock();
  278. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  279. if (ulp_ops)
  280. rc = ulp_ops->iscsi_nl_send_msg(
  281. cp->ulp_handle[CNIC_ULP_ISCSI],
  282. msg_type, buf, len);
  283. rcu_read_unlock();
  284. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  285. break;
  286. msleep(100);
  287. retry++;
  288. }
  289. return rc;
  290. }
  291. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  292. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  293. char *buf, u16 len)
  294. {
  295. int rc = -EINVAL;
  296. switch (msg_type) {
  297. case ISCSI_UEVENT_PATH_UPDATE: {
  298. struct cnic_local *cp;
  299. u32 l5_cid;
  300. struct cnic_sock *csk;
  301. struct iscsi_path *path_resp;
  302. if (len < sizeof(*path_resp))
  303. break;
  304. path_resp = (struct iscsi_path *) buf;
  305. cp = dev->cnic_priv;
  306. l5_cid = (u32) path_resp->handle;
  307. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  308. break;
  309. rcu_read_lock();
  310. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  311. rc = -ENODEV;
  312. rcu_read_unlock();
  313. break;
  314. }
  315. csk = &cp->csk_tbl[l5_cid];
  316. csk_hold(csk);
  317. if (cnic_in_use(csk) &&
  318. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  319. csk->vlan_id = path_resp->vlan_id;
  320. memcpy(csk->ha, path_resp->mac_addr, 6);
  321. if (test_bit(SK_F_IPV6, &csk->flags))
  322. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  323. sizeof(struct in6_addr));
  324. else
  325. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  326. sizeof(struct in_addr));
  327. if (is_valid_ether_addr(csk->ha)) {
  328. cnic_cm_set_pg(csk);
  329. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  330. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  331. cnic_cm_upcall(cp, csk,
  332. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  333. clear_bit(SK_F_CONNECT_START, &csk->flags);
  334. }
  335. }
  336. csk_put(csk);
  337. rcu_read_unlock();
  338. rc = 0;
  339. }
  340. }
  341. return rc;
  342. }
  343. static int cnic_offld_prep(struct cnic_sock *csk)
  344. {
  345. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  346. return 0;
  347. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  348. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  349. return 0;
  350. }
  351. return 1;
  352. }
  353. static int cnic_close_prep(struct cnic_sock *csk)
  354. {
  355. clear_bit(SK_F_CONNECT_START, &csk->flags);
  356. smp_mb__after_clear_bit();
  357. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  358. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  359. msleep(1);
  360. return 1;
  361. }
  362. return 0;
  363. }
  364. static int cnic_abort_prep(struct cnic_sock *csk)
  365. {
  366. clear_bit(SK_F_CONNECT_START, &csk->flags);
  367. smp_mb__after_clear_bit();
  368. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  369. msleep(1);
  370. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  371. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  372. return 1;
  373. }
  374. return 0;
  375. }
  376. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  377. {
  378. struct cnic_dev *dev;
  379. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  380. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  381. return -EINVAL;
  382. }
  383. mutex_lock(&cnic_lock);
  384. if (cnic_ulp_tbl_prot(ulp_type)) {
  385. pr_err("%s: Type %d has already been registered\n",
  386. __func__, ulp_type);
  387. mutex_unlock(&cnic_lock);
  388. return -EBUSY;
  389. }
  390. read_lock(&cnic_dev_lock);
  391. list_for_each_entry(dev, &cnic_dev_list, list) {
  392. struct cnic_local *cp = dev->cnic_priv;
  393. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  394. }
  395. read_unlock(&cnic_dev_lock);
  396. atomic_set(&ulp_ops->ref_count, 0);
  397. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  398. mutex_unlock(&cnic_lock);
  399. /* Prevent race conditions with netdev_event */
  400. rtnl_lock();
  401. list_for_each_entry(dev, &cnic_dev_list, list) {
  402. struct cnic_local *cp = dev->cnic_priv;
  403. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  404. ulp_ops->cnic_init(dev);
  405. }
  406. rtnl_unlock();
  407. return 0;
  408. }
  409. int cnic_unregister_driver(int ulp_type)
  410. {
  411. struct cnic_dev *dev;
  412. struct cnic_ulp_ops *ulp_ops;
  413. int i = 0;
  414. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  415. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  416. return -EINVAL;
  417. }
  418. mutex_lock(&cnic_lock);
  419. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  420. if (!ulp_ops) {
  421. pr_err("%s: Type %d has not been registered\n",
  422. __func__, ulp_type);
  423. goto out_unlock;
  424. }
  425. read_lock(&cnic_dev_lock);
  426. list_for_each_entry(dev, &cnic_dev_list, list) {
  427. struct cnic_local *cp = dev->cnic_priv;
  428. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  429. pr_err("%s: Type %d still has devices registered\n",
  430. __func__, ulp_type);
  431. read_unlock(&cnic_dev_lock);
  432. goto out_unlock;
  433. }
  434. }
  435. read_unlock(&cnic_dev_lock);
  436. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  437. mutex_unlock(&cnic_lock);
  438. synchronize_rcu();
  439. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  440. msleep(100);
  441. i++;
  442. }
  443. if (atomic_read(&ulp_ops->ref_count) != 0)
  444. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  445. return 0;
  446. out_unlock:
  447. mutex_unlock(&cnic_lock);
  448. return -EINVAL;
  449. }
  450. static int cnic_start_hw(struct cnic_dev *);
  451. static void cnic_stop_hw(struct cnic_dev *);
  452. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  453. void *ulp_ctx)
  454. {
  455. struct cnic_local *cp = dev->cnic_priv;
  456. struct cnic_ulp_ops *ulp_ops;
  457. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  458. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  459. return -EINVAL;
  460. }
  461. mutex_lock(&cnic_lock);
  462. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  463. pr_err("%s: Driver with type %d has not been registered\n",
  464. __func__, ulp_type);
  465. mutex_unlock(&cnic_lock);
  466. return -EAGAIN;
  467. }
  468. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  469. pr_err("%s: Type %d has already been registered to this device\n",
  470. __func__, ulp_type);
  471. mutex_unlock(&cnic_lock);
  472. return -EBUSY;
  473. }
  474. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  475. cp->ulp_handle[ulp_type] = ulp_ctx;
  476. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  477. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  478. cnic_hold(dev);
  479. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  480. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  481. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  482. mutex_unlock(&cnic_lock);
  483. cnic_ulp_ctl(dev, ulp_type, true);
  484. return 0;
  485. }
  486. EXPORT_SYMBOL(cnic_register_driver);
  487. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  488. {
  489. struct cnic_local *cp = dev->cnic_priv;
  490. int i = 0;
  491. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  492. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  493. return -EINVAL;
  494. }
  495. mutex_lock(&cnic_lock);
  496. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  497. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  498. cnic_put(dev);
  499. } else {
  500. pr_err("%s: device not registered to this ulp type %d\n",
  501. __func__, ulp_type);
  502. mutex_unlock(&cnic_lock);
  503. return -EINVAL;
  504. }
  505. mutex_unlock(&cnic_lock);
  506. if (ulp_type == CNIC_ULP_ISCSI)
  507. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  508. synchronize_rcu();
  509. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  510. i < 20) {
  511. msleep(100);
  512. i++;
  513. }
  514. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  515. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  516. cnic_ulp_ctl(dev, ulp_type, false);
  517. return 0;
  518. }
  519. EXPORT_SYMBOL(cnic_unregister_driver);
  520. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  521. u32 next)
  522. {
  523. id_tbl->start = start_id;
  524. id_tbl->max = size;
  525. id_tbl->next = next;
  526. spin_lock_init(&id_tbl->lock);
  527. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  528. if (!id_tbl->table)
  529. return -ENOMEM;
  530. return 0;
  531. }
  532. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  533. {
  534. kfree(id_tbl->table);
  535. id_tbl->table = NULL;
  536. }
  537. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  538. {
  539. int ret = -1;
  540. id -= id_tbl->start;
  541. if (id >= id_tbl->max)
  542. return ret;
  543. spin_lock(&id_tbl->lock);
  544. if (!test_bit(id, id_tbl->table)) {
  545. set_bit(id, id_tbl->table);
  546. ret = 0;
  547. }
  548. spin_unlock(&id_tbl->lock);
  549. return ret;
  550. }
  551. /* Returns -1 if not successful */
  552. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  553. {
  554. u32 id;
  555. spin_lock(&id_tbl->lock);
  556. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  557. if (id >= id_tbl->max) {
  558. id = -1;
  559. if (id_tbl->next != 0) {
  560. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  561. if (id >= id_tbl->next)
  562. id = -1;
  563. }
  564. }
  565. if (id < id_tbl->max) {
  566. set_bit(id, id_tbl->table);
  567. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  568. id += id_tbl->start;
  569. }
  570. spin_unlock(&id_tbl->lock);
  571. return id;
  572. }
  573. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  574. {
  575. if (id == -1)
  576. return;
  577. id -= id_tbl->start;
  578. if (id >= id_tbl->max)
  579. return;
  580. clear_bit(id, id_tbl->table);
  581. }
  582. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  583. {
  584. int i;
  585. if (!dma->pg_arr)
  586. return;
  587. for (i = 0; i < dma->num_pages; i++) {
  588. if (dma->pg_arr[i]) {
  589. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  590. dma->pg_arr[i], dma->pg_map_arr[i]);
  591. dma->pg_arr[i] = NULL;
  592. }
  593. }
  594. if (dma->pgtbl) {
  595. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  596. dma->pgtbl, dma->pgtbl_map);
  597. dma->pgtbl = NULL;
  598. }
  599. kfree(dma->pg_arr);
  600. dma->pg_arr = NULL;
  601. dma->num_pages = 0;
  602. }
  603. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  604. {
  605. int i;
  606. __le32 *page_table = (__le32 *) dma->pgtbl;
  607. for (i = 0; i < dma->num_pages; i++) {
  608. /* Each entry needs to be in big endian format. */
  609. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  610. page_table++;
  611. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  612. page_table++;
  613. }
  614. }
  615. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  616. {
  617. int i;
  618. __le32 *page_table = (__le32 *) dma->pgtbl;
  619. for (i = 0; i < dma->num_pages; i++) {
  620. /* Each entry needs to be in little endian format. */
  621. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  622. page_table++;
  623. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  624. page_table++;
  625. }
  626. }
  627. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  628. int pages, int use_pg_tbl)
  629. {
  630. int i, size;
  631. struct cnic_local *cp = dev->cnic_priv;
  632. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  633. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  634. if (dma->pg_arr == NULL)
  635. return -ENOMEM;
  636. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  637. dma->num_pages = pages;
  638. for (i = 0; i < pages; i++) {
  639. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  640. BCM_PAGE_SIZE,
  641. &dma->pg_map_arr[i],
  642. GFP_ATOMIC);
  643. if (dma->pg_arr[i] == NULL)
  644. goto error;
  645. }
  646. if (!use_pg_tbl)
  647. return 0;
  648. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  649. ~(BCM_PAGE_SIZE - 1);
  650. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  651. &dma->pgtbl_map, GFP_ATOMIC);
  652. if (dma->pgtbl == NULL)
  653. goto error;
  654. cp->setup_pgtbl(dev, dma);
  655. return 0;
  656. error:
  657. cnic_free_dma(dev, dma);
  658. return -ENOMEM;
  659. }
  660. static void cnic_free_context(struct cnic_dev *dev)
  661. {
  662. struct cnic_local *cp = dev->cnic_priv;
  663. int i;
  664. for (i = 0; i < cp->ctx_blks; i++) {
  665. if (cp->ctx_arr[i].ctx) {
  666. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  667. cp->ctx_arr[i].ctx,
  668. cp->ctx_arr[i].mapping);
  669. cp->ctx_arr[i].ctx = NULL;
  670. }
  671. }
  672. }
  673. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  674. {
  675. uio_unregister_device(&udev->cnic_uinfo);
  676. if (udev->l2_buf) {
  677. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  678. udev->l2_buf, udev->l2_buf_map);
  679. udev->l2_buf = NULL;
  680. }
  681. if (udev->l2_ring) {
  682. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  683. udev->l2_ring, udev->l2_ring_map);
  684. udev->l2_ring = NULL;
  685. }
  686. pci_dev_put(udev->pdev);
  687. kfree(udev);
  688. }
  689. static void cnic_free_uio(struct cnic_uio_dev *udev)
  690. {
  691. if (!udev)
  692. return;
  693. write_lock(&cnic_dev_lock);
  694. list_del_init(&udev->list);
  695. write_unlock(&cnic_dev_lock);
  696. __cnic_free_uio(udev);
  697. }
  698. static void cnic_free_resc(struct cnic_dev *dev)
  699. {
  700. struct cnic_local *cp = dev->cnic_priv;
  701. struct cnic_uio_dev *udev = cp->udev;
  702. if (udev) {
  703. udev->dev = NULL;
  704. cp->udev = NULL;
  705. }
  706. cnic_free_context(dev);
  707. kfree(cp->ctx_arr);
  708. cp->ctx_arr = NULL;
  709. cp->ctx_blks = 0;
  710. cnic_free_dma(dev, &cp->gbl_buf_info);
  711. cnic_free_dma(dev, &cp->kwq_info);
  712. cnic_free_dma(dev, &cp->kwq_16_data_info);
  713. cnic_free_dma(dev, &cp->kcq2.dma);
  714. cnic_free_dma(dev, &cp->kcq1.dma);
  715. kfree(cp->iscsi_tbl);
  716. cp->iscsi_tbl = NULL;
  717. kfree(cp->ctx_tbl);
  718. cp->ctx_tbl = NULL;
  719. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  720. cnic_free_id_tbl(&cp->cid_tbl);
  721. }
  722. static int cnic_alloc_context(struct cnic_dev *dev)
  723. {
  724. struct cnic_local *cp = dev->cnic_priv;
  725. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  726. int i, k, arr_size;
  727. cp->ctx_blk_size = BCM_PAGE_SIZE;
  728. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  729. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  730. sizeof(struct cnic_ctx);
  731. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  732. if (cp->ctx_arr == NULL)
  733. return -ENOMEM;
  734. k = 0;
  735. for (i = 0; i < 2; i++) {
  736. u32 j, reg, off, lo, hi;
  737. if (i == 0)
  738. off = BNX2_PG_CTX_MAP;
  739. else
  740. off = BNX2_ISCSI_CTX_MAP;
  741. reg = cnic_reg_rd_ind(dev, off);
  742. lo = reg >> 16;
  743. hi = reg & 0xffff;
  744. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  745. cp->ctx_arr[k].cid = j;
  746. }
  747. cp->ctx_blks = k;
  748. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  749. cp->ctx_blks = 0;
  750. return -ENOMEM;
  751. }
  752. for (i = 0; i < cp->ctx_blks; i++) {
  753. cp->ctx_arr[i].ctx =
  754. dma_alloc_coherent(&dev->pcidev->dev,
  755. BCM_PAGE_SIZE,
  756. &cp->ctx_arr[i].mapping,
  757. GFP_KERNEL);
  758. if (cp->ctx_arr[i].ctx == NULL)
  759. return -ENOMEM;
  760. }
  761. }
  762. return 0;
  763. }
  764. static u16 cnic_bnx2_next_idx(u16 idx)
  765. {
  766. return idx + 1;
  767. }
  768. static u16 cnic_bnx2_hw_idx(u16 idx)
  769. {
  770. return idx;
  771. }
  772. static u16 cnic_bnx2x_next_idx(u16 idx)
  773. {
  774. idx++;
  775. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  776. idx++;
  777. return idx;
  778. }
  779. static u16 cnic_bnx2x_hw_idx(u16 idx)
  780. {
  781. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  782. idx++;
  783. return idx;
  784. }
  785. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  786. bool use_pg_tbl)
  787. {
  788. int err, i, use_page_tbl = 0;
  789. struct kcqe **kcq;
  790. if (use_pg_tbl)
  791. use_page_tbl = 1;
  792. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  793. if (err)
  794. return err;
  795. kcq = (struct kcqe **) info->dma.pg_arr;
  796. info->kcq = kcq;
  797. info->next_idx = cnic_bnx2_next_idx;
  798. info->hw_idx = cnic_bnx2_hw_idx;
  799. if (use_pg_tbl)
  800. return 0;
  801. info->next_idx = cnic_bnx2x_next_idx;
  802. info->hw_idx = cnic_bnx2x_hw_idx;
  803. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  804. struct bnx2x_bd_chain_next *next =
  805. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  806. int j = i + 1;
  807. if (j >= KCQ_PAGE_CNT)
  808. j = 0;
  809. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  810. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  811. }
  812. return 0;
  813. }
  814. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  815. {
  816. struct cnic_local *cp = dev->cnic_priv;
  817. struct cnic_uio_dev *udev;
  818. read_lock(&cnic_dev_lock);
  819. list_for_each_entry(udev, &cnic_udev_list, list) {
  820. if (udev->pdev == dev->pcidev) {
  821. udev->dev = dev;
  822. cp->udev = udev;
  823. read_unlock(&cnic_dev_lock);
  824. return 0;
  825. }
  826. }
  827. read_unlock(&cnic_dev_lock);
  828. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  829. if (!udev)
  830. return -ENOMEM;
  831. udev->uio_dev = -1;
  832. udev->dev = dev;
  833. udev->pdev = dev->pcidev;
  834. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  835. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  836. &udev->l2_ring_map,
  837. GFP_KERNEL | __GFP_COMP);
  838. if (!udev->l2_ring)
  839. goto err_udev;
  840. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  841. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  842. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  843. &udev->l2_buf_map,
  844. GFP_KERNEL | __GFP_COMP);
  845. if (!udev->l2_buf)
  846. goto err_dma;
  847. write_lock(&cnic_dev_lock);
  848. list_add(&udev->list, &cnic_udev_list);
  849. write_unlock(&cnic_dev_lock);
  850. pci_dev_get(udev->pdev);
  851. cp->udev = udev;
  852. return 0;
  853. err_dma:
  854. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  855. udev->l2_ring, udev->l2_ring_map);
  856. err_udev:
  857. kfree(udev);
  858. return -ENOMEM;
  859. }
  860. static int cnic_init_uio(struct cnic_dev *dev)
  861. {
  862. struct cnic_local *cp = dev->cnic_priv;
  863. struct cnic_uio_dev *udev = cp->udev;
  864. struct uio_info *uinfo;
  865. int ret = 0;
  866. if (!udev)
  867. return -ENOMEM;
  868. uinfo = &udev->cnic_uinfo;
  869. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  870. uinfo->mem[0].internal_addr = dev->regview;
  871. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  872. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  873. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  874. TX_MAX_TSS_RINGS + 1);
  875. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  876. PAGE_MASK;
  877. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  878. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  879. else
  880. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  881. uinfo->name = "bnx2_cnic";
  882. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  883. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  884. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  885. PAGE_MASK;
  886. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  887. uinfo->name = "bnx2x_cnic";
  888. }
  889. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  890. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  891. uinfo->mem[2].size = udev->l2_ring_size;
  892. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  893. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  894. uinfo->mem[3].size = udev->l2_buf_size;
  895. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  896. uinfo->version = CNIC_MODULE_VERSION;
  897. uinfo->irq = UIO_IRQ_CUSTOM;
  898. uinfo->open = cnic_uio_open;
  899. uinfo->release = cnic_uio_close;
  900. if (udev->uio_dev == -1) {
  901. if (!uinfo->priv) {
  902. uinfo->priv = udev;
  903. ret = uio_register_device(&udev->pdev->dev, uinfo);
  904. }
  905. } else {
  906. cnic_init_rings(dev);
  907. }
  908. return ret;
  909. }
  910. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  911. {
  912. struct cnic_local *cp = dev->cnic_priv;
  913. int ret;
  914. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  915. if (ret)
  916. goto error;
  917. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  918. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  919. if (ret)
  920. goto error;
  921. ret = cnic_alloc_context(dev);
  922. if (ret)
  923. goto error;
  924. ret = cnic_alloc_uio_rings(dev, 2);
  925. if (ret)
  926. goto error;
  927. ret = cnic_init_uio(dev);
  928. if (ret)
  929. goto error;
  930. return 0;
  931. error:
  932. cnic_free_resc(dev);
  933. return ret;
  934. }
  935. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  936. {
  937. struct cnic_local *cp = dev->cnic_priv;
  938. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  939. int total_mem, blks, i;
  940. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  941. blks = total_mem / ctx_blk_size;
  942. if (total_mem % ctx_blk_size)
  943. blks++;
  944. if (blks > cp->ethdev->ctx_tbl_len)
  945. return -ENOMEM;
  946. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  947. if (cp->ctx_arr == NULL)
  948. return -ENOMEM;
  949. cp->ctx_blks = blks;
  950. cp->ctx_blk_size = ctx_blk_size;
  951. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  952. cp->ctx_align = 0;
  953. else
  954. cp->ctx_align = ctx_blk_size;
  955. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  956. for (i = 0; i < blks; i++) {
  957. cp->ctx_arr[i].ctx =
  958. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  959. &cp->ctx_arr[i].mapping,
  960. GFP_KERNEL);
  961. if (cp->ctx_arr[i].ctx == NULL)
  962. return -ENOMEM;
  963. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  964. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  965. cnic_free_context(dev);
  966. cp->ctx_blk_size += cp->ctx_align;
  967. i = -1;
  968. continue;
  969. }
  970. }
  971. }
  972. return 0;
  973. }
  974. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  975. {
  976. struct cnic_local *cp = dev->cnic_priv;
  977. struct cnic_eth_dev *ethdev = cp->ethdev;
  978. u32 start_cid = ethdev->starting_cid;
  979. int i, j, n, ret, pages;
  980. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  981. cp->iro_arr = ethdev->iro_arr;
  982. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  983. cp->iscsi_start_cid = start_cid;
  984. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  985. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  986. cp->max_cid_space += dev->max_fcoe_conn;
  987. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  988. if (!cp->fcoe_init_cid)
  989. cp->fcoe_init_cid = 0x10;
  990. }
  991. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  992. GFP_KERNEL);
  993. if (!cp->iscsi_tbl)
  994. goto error;
  995. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  996. cp->max_cid_space, GFP_KERNEL);
  997. if (!cp->ctx_tbl)
  998. goto error;
  999. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1000. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1001. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1002. }
  1003. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1004. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1005. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1006. PAGE_SIZE;
  1007. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1008. if (ret)
  1009. return -ENOMEM;
  1010. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1011. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1012. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1013. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1014. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1015. off;
  1016. if ((i % n) == (n - 1))
  1017. j++;
  1018. }
  1019. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1020. if (ret)
  1021. goto error;
  1022. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1023. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1024. if (ret)
  1025. goto error;
  1026. }
  1027. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1028. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1029. if (ret)
  1030. goto error;
  1031. ret = cnic_alloc_bnx2x_context(dev);
  1032. if (ret)
  1033. goto error;
  1034. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1035. cp->l2_rx_ring_size = 15;
  1036. ret = cnic_alloc_uio_rings(dev, 4);
  1037. if (ret)
  1038. goto error;
  1039. ret = cnic_init_uio(dev);
  1040. if (ret)
  1041. goto error;
  1042. return 0;
  1043. error:
  1044. cnic_free_resc(dev);
  1045. return -ENOMEM;
  1046. }
  1047. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1048. {
  1049. return cp->max_kwq_idx -
  1050. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1051. }
  1052. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1053. u32 num_wqes)
  1054. {
  1055. struct cnic_local *cp = dev->cnic_priv;
  1056. struct kwqe *prod_qe;
  1057. u16 prod, sw_prod, i;
  1058. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1059. return -EAGAIN; /* bnx2 is down */
  1060. spin_lock_bh(&cp->cnic_ulp_lock);
  1061. if (num_wqes > cnic_kwq_avail(cp) &&
  1062. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1063. spin_unlock_bh(&cp->cnic_ulp_lock);
  1064. return -EAGAIN;
  1065. }
  1066. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1067. prod = cp->kwq_prod_idx;
  1068. sw_prod = prod & MAX_KWQ_IDX;
  1069. for (i = 0; i < num_wqes; i++) {
  1070. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1071. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1072. prod++;
  1073. sw_prod = prod & MAX_KWQ_IDX;
  1074. }
  1075. cp->kwq_prod_idx = prod;
  1076. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1077. spin_unlock_bh(&cp->cnic_ulp_lock);
  1078. return 0;
  1079. }
  1080. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1081. union l5cm_specific_data *l5_data)
  1082. {
  1083. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1084. dma_addr_t map;
  1085. map = ctx->kwqe_data_mapping;
  1086. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1087. l5_data->phy_address.hi = (u64) map >> 32;
  1088. return ctx->kwqe_data;
  1089. }
  1090. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1091. u32 type, union l5cm_specific_data *l5_data)
  1092. {
  1093. struct cnic_local *cp = dev->cnic_priv;
  1094. struct l5cm_spe kwqe;
  1095. struct kwqe_16 *kwq[1];
  1096. u16 type_16;
  1097. int ret;
  1098. kwqe.hdr.conn_and_cmd_data =
  1099. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1100. BNX2X_HW_CID(cp, cid)));
  1101. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1102. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1103. SPE_HDR_FUNCTION_ID;
  1104. kwqe.hdr.type = cpu_to_le16(type_16);
  1105. kwqe.hdr.reserved1 = 0;
  1106. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1107. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1108. kwq[0] = (struct kwqe_16 *) &kwqe;
  1109. spin_lock_bh(&cp->cnic_ulp_lock);
  1110. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1111. spin_unlock_bh(&cp->cnic_ulp_lock);
  1112. if (ret == 1)
  1113. return 0;
  1114. return ret;
  1115. }
  1116. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1117. struct kcqe *cqes[], u32 num_cqes)
  1118. {
  1119. struct cnic_local *cp = dev->cnic_priv;
  1120. struct cnic_ulp_ops *ulp_ops;
  1121. rcu_read_lock();
  1122. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1123. if (likely(ulp_ops)) {
  1124. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1125. cqes, num_cqes);
  1126. }
  1127. rcu_read_unlock();
  1128. }
  1129. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1130. {
  1131. struct cnic_local *cp = dev->cnic_priv;
  1132. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1133. int hq_bds, pages;
  1134. u32 pfid = cp->pfid;
  1135. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1136. cp->num_ccells = req1->num_ccells_per_conn;
  1137. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1138. cp->num_iscsi_tasks;
  1139. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1140. BNX2X_ISCSI_R2TQE_SIZE;
  1141. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1142. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1143. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1144. cp->num_cqs = req1->num_cqs;
  1145. if (!dev->max_iscsi_conn)
  1146. return 0;
  1147. /* init Tstorm RAM */
  1148. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1149. req1->rq_num_wqes);
  1150. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1151. PAGE_SIZE);
  1152. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1153. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1154. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1155. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1156. req1->num_tasks_per_conn);
  1157. /* init Ustorm RAM */
  1158. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1159. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1160. req1->rq_buffer_size);
  1161. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1162. PAGE_SIZE);
  1163. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1164. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1165. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1166. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1167. req1->num_tasks_per_conn);
  1168. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1169. req1->rq_num_wqes);
  1170. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1171. req1->cq_num_wqes);
  1172. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1173. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1174. /* init Xstorm RAM */
  1175. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1176. PAGE_SIZE);
  1177. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1178. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1179. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1180. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1181. req1->num_tasks_per_conn);
  1182. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1183. hq_bds);
  1184. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1185. req1->num_tasks_per_conn);
  1186. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1187. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1188. /* init Cstorm RAM */
  1189. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1190. PAGE_SIZE);
  1191. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1192. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1193. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1194. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1195. req1->num_tasks_per_conn);
  1196. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1197. req1->cq_num_wqes);
  1198. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1199. hq_bds);
  1200. return 0;
  1201. }
  1202. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1203. {
  1204. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1205. struct cnic_local *cp = dev->cnic_priv;
  1206. u32 pfid = cp->pfid;
  1207. struct iscsi_kcqe kcqe;
  1208. struct kcqe *cqes[1];
  1209. memset(&kcqe, 0, sizeof(kcqe));
  1210. if (!dev->max_iscsi_conn) {
  1211. kcqe.completion_status =
  1212. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1213. goto done;
  1214. }
  1215. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1216. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1217. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1218. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1219. req2->error_bit_map[1]);
  1220. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1221. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1222. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1223. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1224. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1225. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1226. req2->error_bit_map[1]);
  1227. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1228. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1229. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1230. done:
  1231. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1232. cqes[0] = (struct kcqe *) &kcqe;
  1233. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1234. return 0;
  1235. }
  1236. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1237. {
  1238. struct cnic_local *cp = dev->cnic_priv;
  1239. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1240. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1241. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1242. cnic_free_dma(dev, &iscsi->hq_info);
  1243. cnic_free_dma(dev, &iscsi->r2tq_info);
  1244. cnic_free_dma(dev, &iscsi->task_array_info);
  1245. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1246. } else {
  1247. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1248. }
  1249. ctx->cid = 0;
  1250. }
  1251. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1252. {
  1253. u32 cid;
  1254. int ret, pages;
  1255. struct cnic_local *cp = dev->cnic_priv;
  1256. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1257. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1258. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1259. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1260. if (cid == -1) {
  1261. ret = -ENOMEM;
  1262. goto error;
  1263. }
  1264. ctx->cid = cid;
  1265. return 0;
  1266. }
  1267. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1268. if (cid == -1) {
  1269. ret = -ENOMEM;
  1270. goto error;
  1271. }
  1272. ctx->cid = cid;
  1273. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1274. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1275. if (ret)
  1276. goto error;
  1277. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1278. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1279. if (ret)
  1280. goto error;
  1281. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1282. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1283. if (ret)
  1284. goto error;
  1285. return 0;
  1286. error:
  1287. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1288. return ret;
  1289. }
  1290. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1291. struct regpair *ctx_addr)
  1292. {
  1293. struct cnic_local *cp = dev->cnic_priv;
  1294. struct cnic_eth_dev *ethdev = cp->ethdev;
  1295. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1296. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1297. unsigned long align_off = 0;
  1298. dma_addr_t ctx_map;
  1299. void *ctx;
  1300. if (cp->ctx_align) {
  1301. unsigned long mask = cp->ctx_align - 1;
  1302. if (cp->ctx_arr[blk].mapping & mask)
  1303. align_off = cp->ctx_align -
  1304. (cp->ctx_arr[blk].mapping & mask);
  1305. }
  1306. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1307. (off * BNX2X_CONTEXT_MEM_SIZE);
  1308. ctx = cp->ctx_arr[blk].ctx + align_off +
  1309. (off * BNX2X_CONTEXT_MEM_SIZE);
  1310. if (init)
  1311. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1312. ctx_addr->lo = ctx_map & 0xffffffff;
  1313. ctx_addr->hi = (u64) ctx_map >> 32;
  1314. return ctx;
  1315. }
  1316. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1317. u32 num)
  1318. {
  1319. struct cnic_local *cp = dev->cnic_priv;
  1320. struct iscsi_kwqe_conn_offload1 *req1 =
  1321. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1322. struct iscsi_kwqe_conn_offload2 *req2 =
  1323. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1324. struct iscsi_kwqe_conn_offload3 *req3;
  1325. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1326. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1327. u32 cid = ctx->cid;
  1328. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1329. struct iscsi_context *ictx;
  1330. struct regpair context_addr;
  1331. int i, j, n = 2, n_max;
  1332. u8 port = CNIC_PORT(cp);
  1333. ctx->ctx_flags = 0;
  1334. if (!req2->num_additional_wqes)
  1335. return -EINVAL;
  1336. n_max = req2->num_additional_wqes + 2;
  1337. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1338. if (ictx == NULL)
  1339. return -ENOMEM;
  1340. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1341. ictx->xstorm_ag_context.hq_prod = 1;
  1342. ictx->xstorm_st_context.iscsi.first_burst_length =
  1343. ISCSI_DEF_FIRST_BURST_LEN;
  1344. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1345. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1346. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1347. req1->sq_page_table_addr_lo;
  1348. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1349. req1->sq_page_table_addr_hi;
  1350. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1351. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1352. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1353. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1354. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1355. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1356. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1357. iscsi->hq_info.pgtbl[0];
  1358. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1359. iscsi->hq_info.pgtbl[1];
  1360. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1361. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1362. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1363. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1364. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1365. iscsi->r2tq_info.pgtbl[0];
  1366. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1367. iscsi->r2tq_info.pgtbl[1];
  1368. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1369. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1370. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1371. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1372. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1373. BNX2X_ISCSI_PBL_NOT_CACHED;
  1374. ictx->xstorm_st_context.iscsi.flags.flags |=
  1375. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1376. ictx->xstorm_st_context.iscsi.flags.flags |=
  1377. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1378. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1379. ETH_P_8021Q;
  1380. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1381. cp->port_mode == CHIP_2_PORT_MODE) {
  1382. port = 0;
  1383. }
  1384. ictx->xstorm_st_context.common.flags =
  1385. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1386. ictx->xstorm_st_context.common.flags =
  1387. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1388. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1389. /* TSTORM requires the base address of RQ DB & not PTE */
  1390. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1391. req2->rq_page_table_addr_lo & PAGE_MASK;
  1392. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1393. req2->rq_page_table_addr_hi;
  1394. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1395. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1396. ictx->tstorm_st_context.tcp.flags2 |=
  1397. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1398. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1399. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1400. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1401. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1402. req2->rq_page_table_addr_lo;
  1403. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1404. req2->rq_page_table_addr_hi;
  1405. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1406. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1407. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1408. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1409. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1410. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1411. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1412. iscsi->r2tq_info.pgtbl[0];
  1413. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1414. iscsi->r2tq_info.pgtbl[1];
  1415. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1416. req1->cq_page_table_addr_lo;
  1417. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1418. req1->cq_page_table_addr_hi;
  1419. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1420. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1421. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1422. ictx->ustorm_st_context.task_pbe_cache_index =
  1423. BNX2X_ISCSI_PBL_NOT_CACHED;
  1424. ictx->ustorm_st_context.task_pdu_cache_index =
  1425. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1426. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1427. if (j == 3) {
  1428. if (n >= n_max)
  1429. break;
  1430. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1431. j = 0;
  1432. }
  1433. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1434. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1435. req3->qp_first_pte[j].hi;
  1436. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1437. req3->qp_first_pte[j].lo;
  1438. }
  1439. ictx->ustorm_st_context.task_pbl_base.lo =
  1440. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1441. ictx->ustorm_st_context.task_pbl_base.hi =
  1442. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1443. ictx->ustorm_st_context.tce_phy_addr.lo =
  1444. iscsi->task_array_info.pgtbl[0];
  1445. ictx->ustorm_st_context.tce_phy_addr.hi =
  1446. iscsi->task_array_info.pgtbl[1];
  1447. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1448. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1449. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1450. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1451. ISCSI_DEF_MAX_BURST_LEN;
  1452. ictx->ustorm_st_context.negotiated_rx |=
  1453. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1454. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1455. ictx->cstorm_st_context.hq_pbl_base.lo =
  1456. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1457. ictx->cstorm_st_context.hq_pbl_base.hi =
  1458. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1459. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1460. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1461. ictx->cstorm_st_context.task_pbl_base.lo =
  1462. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1463. ictx->cstorm_st_context.task_pbl_base.hi =
  1464. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1465. /* CSTORM and USTORM initialization is different, CSTORM requires
  1466. * CQ DB base & not PTE addr */
  1467. ictx->cstorm_st_context.cq_db_base.lo =
  1468. req1->cq_page_table_addr_lo & PAGE_MASK;
  1469. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1470. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1471. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1472. for (i = 0; i < cp->num_cqs; i++) {
  1473. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1474. ISCSI_INITIAL_SN;
  1475. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1476. ISCSI_INITIAL_SN;
  1477. }
  1478. ictx->xstorm_ag_context.cdu_reserved =
  1479. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1480. ISCSI_CONNECTION_TYPE);
  1481. ictx->ustorm_ag_context.cdu_usage =
  1482. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1483. ISCSI_CONNECTION_TYPE);
  1484. return 0;
  1485. }
  1486. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1487. u32 num, int *work)
  1488. {
  1489. struct iscsi_kwqe_conn_offload1 *req1;
  1490. struct iscsi_kwqe_conn_offload2 *req2;
  1491. struct cnic_local *cp = dev->cnic_priv;
  1492. struct cnic_context *ctx;
  1493. struct iscsi_kcqe kcqe;
  1494. struct kcqe *cqes[1];
  1495. u32 l5_cid;
  1496. int ret = 0;
  1497. if (num < 2) {
  1498. *work = num;
  1499. return -EINVAL;
  1500. }
  1501. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1502. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1503. if ((num - 2) < req2->num_additional_wqes) {
  1504. *work = num;
  1505. return -EINVAL;
  1506. }
  1507. *work = 2 + req2->num_additional_wqes;
  1508. l5_cid = req1->iscsi_conn_id;
  1509. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1510. return -EINVAL;
  1511. memset(&kcqe, 0, sizeof(kcqe));
  1512. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1513. kcqe.iscsi_conn_id = l5_cid;
  1514. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1515. ctx = &cp->ctx_tbl[l5_cid];
  1516. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1517. kcqe.completion_status =
  1518. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1519. goto done;
  1520. }
  1521. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1522. atomic_dec(&cp->iscsi_conn);
  1523. goto done;
  1524. }
  1525. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1526. if (ret) {
  1527. atomic_dec(&cp->iscsi_conn);
  1528. ret = 0;
  1529. goto done;
  1530. }
  1531. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1532. if (ret < 0) {
  1533. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1534. atomic_dec(&cp->iscsi_conn);
  1535. goto done;
  1536. }
  1537. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1538. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1539. done:
  1540. cqes[0] = (struct kcqe *) &kcqe;
  1541. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1542. return 0;
  1543. }
  1544. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1545. {
  1546. struct cnic_local *cp = dev->cnic_priv;
  1547. struct iscsi_kwqe_conn_update *req =
  1548. (struct iscsi_kwqe_conn_update *) kwqe;
  1549. void *data;
  1550. union l5cm_specific_data l5_data;
  1551. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1552. int ret;
  1553. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1554. return -EINVAL;
  1555. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1556. if (!data)
  1557. return -ENOMEM;
  1558. memcpy(data, kwqe, sizeof(struct kwqe));
  1559. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1560. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1561. return ret;
  1562. }
  1563. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1564. {
  1565. struct cnic_local *cp = dev->cnic_priv;
  1566. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1567. union l5cm_specific_data l5_data;
  1568. int ret;
  1569. u32 hw_cid;
  1570. init_waitqueue_head(&ctx->waitq);
  1571. ctx->wait_cond = 0;
  1572. memset(&l5_data, 0, sizeof(l5_data));
  1573. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1574. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1575. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1576. if (ret == 0) {
  1577. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1578. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1579. return -EBUSY;
  1580. }
  1581. return 0;
  1582. }
  1583. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1584. {
  1585. struct cnic_local *cp = dev->cnic_priv;
  1586. struct iscsi_kwqe_conn_destroy *req =
  1587. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1588. u32 l5_cid = req->reserved0;
  1589. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1590. int ret = 0;
  1591. struct iscsi_kcqe kcqe;
  1592. struct kcqe *cqes[1];
  1593. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1594. goto skip_cfc_delete;
  1595. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1596. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1597. if (delta > (2 * HZ))
  1598. delta = 0;
  1599. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1600. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1601. goto destroy_reply;
  1602. }
  1603. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1604. skip_cfc_delete:
  1605. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1606. if (!ret) {
  1607. atomic_dec(&cp->iscsi_conn);
  1608. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1609. }
  1610. destroy_reply:
  1611. memset(&kcqe, 0, sizeof(kcqe));
  1612. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1613. kcqe.iscsi_conn_id = l5_cid;
  1614. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1615. kcqe.iscsi_conn_context_id = req->context_id;
  1616. cqes[0] = (struct kcqe *) &kcqe;
  1617. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1618. return 0;
  1619. }
  1620. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1621. struct l4_kwq_connect_req1 *kwqe1,
  1622. struct l4_kwq_connect_req3 *kwqe3,
  1623. struct l5cm_active_conn_buffer *conn_buf)
  1624. {
  1625. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1626. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1627. &conn_buf->xstorm_conn_buffer;
  1628. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1629. &conn_buf->tstorm_conn_buffer;
  1630. struct regpair context_addr;
  1631. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1632. struct in6_addr src_ip, dst_ip;
  1633. int i;
  1634. u32 *addrp;
  1635. addrp = (u32 *) &conn_addr->local_ip_addr;
  1636. for (i = 0; i < 4; i++, addrp++)
  1637. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1638. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1639. for (i = 0; i < 4; i++, addrp++)
  1640. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1641. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1642. xstorm_buf->context_addr.hi = context_addr.hi;
  1643. xstorm_buf->context_addr.lo = context_addr.lo;
  1644. xstorm_buf->mss = 0xffff;
  1645. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1646. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1647. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1648. xstorm_buf->pseudo_header_checksum =
  1649. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1650. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1651. tstorm_buf->params |=
  1652. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1653. if (kwqe3->ka_timeout) {
  1654. tstorm_buf->ka_enable = 1;
  1655. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1656. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1657. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1658. }
  1659. tstorm_buf->max_rt_time = 0xffffffff;
  1660. }
  1661. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1662. {
  1663. struct cnic_local *cp = dev->cnic_priv;
  1664. u32 pfid = cp->pfid;
  1665. u8 *mac = dev->mac_addr;
  1666. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1667. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1668. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1669. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1670. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1671. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1672. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1673. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1674. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1675. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1676. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1677. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1678. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1679. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1680. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1681. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1682. mac[4]);
  1683. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1684. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1685. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1686. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1687. mac[2]);
  1688. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1689. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1690. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1691. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1692. mac[0]);
  1693. }
  1694. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1695. {
  1696. struct cnic_local *cp = dev->cnic_priv;
  1697. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1698. u16 tstorm_flags = 0;
  1699. if (tcp_ts) {
  1700. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1701. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1702. }
  1703. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1704. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1705. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1706. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1707. }
  1708. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1709. u32 num, int *work)
  1710. {
  1711. struct cnic_local *cp = dev->cnic_priv;
  1712. struct l4_kwq_connect_req1 *kwqe1 =
  1713. (struct l4_kwq_connect_req1 *) wqes[0];
  1714. struct l4_kwq_connect_req3 *kwqe3;
  1715. struct l5cm_active_conn_buffer *conn_buf;
  1716. struct l5cm_conn_addr_params *conn_addr;
  1717. union l5cm_specific_data l5_data;
  1718. u32 l5_cid = kwqe1->pg_cid;
  1719. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1720. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1721. int ret;
  1722. if (num < 2) {
  1723. *work = num;
  1724. return -EINVAL;
  1725. }
  1726. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1727. *work = 3;
  1728. else
  1729. *work = 2;
  1730. if (num < *work) {
  1731. *work = num;
  1732. return -EINVAL;
  1733. }
  1734. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1735. netdev_err(dev->netdev, "conn_buf size too big\n");
  1736. return -ENOMEM;
  1737. }
  1738. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1739. if (!conn_buf)
  1740. return -ENOMEM;
  1741. memset(conn_buf, 0, sizeof(*conn_buf));
  1742. conn_addr = &conn_buf->conn_addr_buf;
  1743. conn_addr->remote_addr_0 = csk->ha[0];
  1744. conn_addr->remote_addr_1 = csk->ha[1];
  1745. conn_addr->remote_addr_2 = csk->ha[2];
  1746. conn_addr->remote_addr_3 = csk->ha[3];
  1747. conn_addr->remote_addr_4 = csk->ha[4];
  1748. conn_addr->remote_addr_5 = csk->ha[5];
  1749. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1750. struct l4_kwq_connect_req2 *kwqe2 =
  1751. (struct l4_kwq_connect_req2 *) wqes[1];
  1752. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1753. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1754. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1755. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1756. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1757. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1758. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1759. }
  1760. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1761. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1762. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1763. conn_addr->local_tcp_port = kwqe1->src_port;
  1764. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1765. conn_addr->pmtu = kwqe3->pmtu;
  1766. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1767. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1768. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1769. cnic_bnx2x_set_tcp_timestamp(dev,
  1770. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1771. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1772. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1773. if (!ret)
  1774. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1775. return ret;
  1776. }
  1777. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1778. {
  1779. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1780. union l5cm_specific_data l5_data;
  1781. int ret;
  1782. memset(&l5_data, 0, sizeof(l5_data));
  1783. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1784. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1785. return ret;
  1786. }
  1787. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1788. {
  1789. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1790. union l5cm_specific_data l5_data;
  1791. int ret;
  1792. memset(&l5_data, 0, sizeof(l5_data));
  1793. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1794. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1795. return ret;
  1796. }
  1797. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1798. {
  1799. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1800. struct l4_kcq kcqe;
  1801. struct kcqe *cqes[1];
  1802. memset(&kcqe, 0, sizeof(kcqe));
  1803. kcqe.pg_host_opaque = req->host_opaque;
  1804. kcqe.pg_cid = req->host_opaque;
  1805. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1806. cqes[0] = (struct kcqe *) &kcqe;
  1807. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1808. return 0;
  1809. }
  1810. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1811. {
  1812. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1813. struct l4_kcq kcqe;
  1814. struct kcqe *cqes[1];
  1815. memset(&kcqe, 0, sizeof(kcqe));
  1816. kcqe.pg_host_opaque = req->pg_host_opaque;
  1817. kcqe.pg_cid = req->pg_cid;
  1818. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1819. cqes[0] = (struct kcqe *) &kcqe;
  1820. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1821. return 0;
  1822. }
  1823. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1824. {
  1825. struct fcoe_kwqe_stat *req;
  1826. struct fcoe_stat_ramrod_params *fcoe_stat;
  1827. union l5cm_specific_data l5_data;
  1828. struct cnic_local *cp = dev->cnic_priv;
  1829. int ret;
  1830. u32 cid;
  1831. req = (struct fcoe_kwqe_stat *) kwqe;
  1832. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1833. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1834. if (!fcoe_stat)
  1835. return -ENOMEM;
  1836. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1837. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1838. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1839. FCOE_CONNECTION_TYPE, &l5_data);
  1840. return ret;
  1841. }
  1842. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1843. u32 num, int *work)
  1844. {
  1845. int ret;
  1846. struct cnic_local *cp = dev->cnic_priv;
  1847. u32 cid;
  1848. struct fcoe_init_ramrod_params *fcoe_init;
  1849. struct fcoe_kwqe_init1 *req1;
  1850. struct fcoe_kwqe_init2 *req2;
  1851. struct fcoe_kwqe_init3 *req3;
  1852. union l5cm_specific_data l5_data;
  1853. if (num < 3) {
  1854. *work = num;
  1855. return -EINVAL;
  1856. }
  1857. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1858. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1859. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1860. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1861. *work = 1;
  1862. return -EINVAL;
  1863. }
  1864. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1865. *work = 2;
  1866. return -EINVAL;
  1867. }
  1868. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1869. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1870. return -ENOMEM;
  1871. }
  1872. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1873. if (!fcoe_init)
  1874. return -ENOMEM;
  1875. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1876. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1877. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1878. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1879. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1880. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1881. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1882. fcoe_init->sb_num = cp->status_blk_num;
  1883. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1884. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1885. cp->kcq2.sw_prod_idx = 0;
  1886. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1887. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1888. FCOE_CONNECTION_TYPE, &l5_data);
  1889. *work = 3;
  1890. return ret;
  1891. }
  1892. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1893. u32 num, int *work)
  1894. {
  1895. int ret = 0;
  1896. u32 cid = -1, l5_cid;
  1897. struct cnic_local *cp = dev->cnic_priv;
  1898. struct fcoe_kwqe_conn_offload1 *req1;
  1899. struct fcoe_kwqe_conn_offload2 *req2;
  1900. struct fcoe_kwqe_conn_offload3 *req3;
  1901. struct fcoe_kwqe_conn_offload4 *req4;
  1902. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1903. struct cnic_context *ctx;
  1904. struct fcoe_context *fctx;
  1905. struct regpair ctx_addr;
  1906. union l5cm_specific_data l5_data;
  1907. struct fcoe_kcqe kcqe;
  1908. struct kcqe *cqes[1];
  1909. if (num < 4) {
  1910. *work = num;
  1911. return -EINVAL;
  1912. }
  1913. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1914. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1915. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1916. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1917. *work = 4;
  1918. l5_cid = req1->fcoe_conn_id;
  1919. if (l5_cid >= dev->max_fcoe_conn)
  1920. goto err_reply;
  1921. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1922. ctx = &cp->ctx_tbl[l5_cid];
  1923. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1924. goto err_reply;
  1925. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1926. if (ret) {
  1927. ret = 0;
  1928. goto err_reply;
  1929. }
  1930. cid = ctx->cid;
  1931. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1932. if (fctx) {
  1933. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1934. u32 val;
  1935. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1936. FCOE_CONNECTION_TYPE);
  1937. fctx->xstorm_ag_context.cdu_reserved = val;
  1938. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1939. FCOE_CONNECTION_TYPE);
  1940. fctx->ustorm_ag_context.cdu_usage = val;
  1941. }
  1942. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1943. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1944. goto err_reply;
  1945. }
  1946. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1947. if (!fcoe_offload)
  1948. goto err_reply;
  1949. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1950. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1951. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1952. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1953. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1954. cid = BNX2X_HW_CID(cp, cid);
  1955. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1956. FCOE_CONNECTION_TYPE, &l5_data);
  1957. if (!ret)
  1958. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1959. return ret;
  1960. err_reply:
  1961. if (cid != -1)
  1962. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1963. memset(&kcqe, 0, sizeof(kcqe));
  1964. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1965. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1966. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1967. cqes[0] = (struct kcqe *) &kcqe;
  1968. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1969. return ret;
  1970. }
  1971. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1972. {
  1973. struct fcoe_kwqe_conn_enable_disable *req;
  1974. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1975. union l5cm_specific_data l5_data;
  1976. int ret;
  1977. u32 cid, l5_cid;
  1978. struct cnic_local *cp = dev->cnic_priv;
  1979. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1980. cid = req->context_id;
  1981. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1982. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1983. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1984. return -ENOMEM;
  1985. }
  1986. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1987. if (!fcoe_enable)
  1988. return -ENOMEM;
  1989. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1990. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1991. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1992. FCOE_CONNECTION_TYPE, &l5_data);
  1993. return ret;
  1994. }
  1995. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1996. {
  1997. struct fcoe_kwqe_conn_enable_disable *req;
  1998. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1999. union l5cm_specific_data l5_data;
  2000. int ret;
  2001. u32 cid, l5_cid;
  2002. struct cnic_local *cp = dev->cnic_priv;
  2003. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2004. cid = req->context_id;
  2005. l5_cid = req->conn_id;
  2006. if (l5_cid >= dev->max_fcoe_conn)
  2007. return -EINVAL;
  2008. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2009. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2010. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2011. return -ENOMEM;
  2012. }
  2013. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2014. if (!fcoe_disable)
  2015. return -ENOMEM;
  2016. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2017. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2018. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2019. FCOE_CONNECTION_TYPE, &l5_data);
  2020. return ret;
  2021. }
  2022. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2023. {
  2024. struct fcoe_kwqe_conn_destroy *req;
  2025. union l5cm_specific_data l5_data;
  2026. int ret;
  2027. u32 cid, l5_cid;
  2028. struct cnic_local *cp = dev->cnic_priv;
  2029. struct cnic_context *ctx;
  2030. struct fcoe_kcqe kcqe;
  2031. struct kcqe *cqes[1];
  2032. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2033. cid = req->context_id;
  2034. l5_cid = req->conn_id;
  2035. if (l5_cid >= dev->max_fcoe_conn)
  2036. return -EINVAL;
  2037. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2038. ctx = &cp->ctx_tbl[l5_cid];
  2039. init_waitqueue_head(&ctx->waitq);
  2040. ctx->wait_cond = 0;
  2041. memset(&kcqe, 0, sizeof(kcqe));
  2042. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2043. memset(&l5_data, 0, sizeof(l5_data));
  2044. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2045. FCOE_CONNECTION_TYPE, &l5_data);
  2046. if (ret == 0) {
  2047. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2048. if (ctx->wait_cond)
  2049. kcqe.completion_status = 0;
  2050. }
  2051. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2052. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2053. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2054. kcqe.fcoe_conn_id = req->conn_id;
  2055. kcqe.fcoe_conn_context_id = cid;
  2056. cqes[0] = (struct kcqe *) &kcqe;
  2057. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2058. return ret;
  2059. }
  2060. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2061. {
  2062. struct cnic_local *cp = dev->cnic_priv;
  2063. u32 i;
  2064. for (i = start_cid; i < cp->max_cid_space; i++) {
  2065. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2066. int j;
  2067. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2068. msleep(10);
  2069. for (j = 0; j < 5; j++) {
  2070. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2071. break;
  2072. msleep(20);
  2073. }
  2074. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2075. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2076. ctx->cid);
  2077. }
  2078. }
  2079. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2080. {
  2081. struct fcoe_kwqe_destroy *req;
  2082. union l5cm_specific_data l5_data;
  2083. struct cnic_local *cp = dev->cnic_priv;
  2084. int ret;
  2085. u32 cid;
  2086. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2087. req = (struct fcoe_kwqe_destroy *) kwqe;
  2088. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2089. memset(&l5_data, 0, sizeof(l5_data));
  2090. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2091. FCOE_CONNECTION_TYPE, &l5_data);
  2092. return ret;
  2093. }
  2094. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2095. {
  2096. struct cnic_local *cp = dev->cnic_priv;
  2097. struct kcqe kcqe;
  2098. struct kcqe *cqes[1];
  2099. u32 cid;
  2100. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2101. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2102. u32 kcqe_op;
  2103. int ulp_type;
  2104. cid = kwqe->kwqe_info0;
  2105. memset(&kcqe, 0, sizeof(kcqe));
  2106. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2107. u32 l5_cid = 0;
  2108. ulp_type = CNIC_ULP_FCOE;
  2109. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2110. struct fcoe_kwqe_conn_enable_disable *req;
  2111. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2112. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2113. cid = req->context_id;
  2114. l5_cid = req->conn_id;
  2115. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2116. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2117. } else {
  2118. return;
  2119. }
  2120. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2121. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2122. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2123. kcqe.kcqe_info2 = cid;
  2124. kcqe.kcqe_info0 = l5_cid;
  2125. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2126. ulp_type = CNIC_ULP_ISCSI;
  2127. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2128. cid = kwqe->kwqe_info1;
  2129. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2130. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2131. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2132. kcqe.kcqe_info2 = cid;
  2133. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2134. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2135. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2136. ulp_type = CNIC_ULP_L4;
  2137. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2138. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2139. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2140. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2141. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2142. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2143. else
  2144. return;
  2145. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2146. KCQE_FLAGS_LAYER_MASK_L4;
  2147. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2148. l4kcqe->cid = cid;
  2149. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2150. } else {
  2151. return;
  2152. }
  2153. cqes[0] = (struct kcqe *) &kcqe;
  2154. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2155. }
  2156. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2157. struct kwqe *wqes[], u32 num_wqes)
  2158. {
  2159. int i, work, ret;
  2160. u32 opcode;
  2161. struct kwqe *kwqe;
  2162. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2163. return -EAGAIN; /* bnx2 is down */
  2164. for (i = 0; i < num_wqes; ) {
  2165. kwqe = wqes[i];
  2166. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2167. work = 1;
  2168. switch (opcode) {
  2169. case ISCSI_KWQE_OPCODE_INIT1:
  2170. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2171. break;
  2172. case ISCSI_KWQE_OPCODE_INIT2:
  2173. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2174. break;
  2175. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2176. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2177. num_wqes - i, &work);
  2178. break;
  2179. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2180. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2181. break;
  2182. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2183. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2184. break;
  2185. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2186. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2187. &work);
  2188. break;
  2189. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2190. ret = cnic_bnx2x_close(dev, kwqe);
  2191. break;
  2192. case L4_KWQE_OPCODE_VALUE_RESET:
  2193. ret = cnic_bnx2x_reset(dev, kwqe);
  2194. break;
  2195. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2196. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2197. break;
  2198. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2199. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2200. break;
  2201. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2202. ret = 0;
  2203. break;
  2204. default:
  2205. ret = 0;
  2206. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2207. opcode);
  2208. break;
  2209. }
  2210. if (ret < 0) {
  2211. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2212. opcode);
  2213. /* Possibly bnx2x parity error, send completion
  2214. * to ulp drivers with error code to speed up
  2215. * cleanup and reset recovery.
  2216. */
  2217. if (ret == -EIO || ret == -EAGAIN)
  2218. cnic_bnx2x_kwqe_err(dev, kwqe);
  2219. }
  2220. i += work;
  2221. }
  2222. return 0;
  2223. }
  2224. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2225. struct kwqe *wqes[], u32 num_wqes)
  2226. {
  2227. struct cnic_local *cp = dev->cnic_priv;
  2228. int i, work, ret;
  2229. u32 opcode;
  2230. struct kwqe *kwqe;
  2231. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2232. return -EAGAIN; /* bnx2 is down */
  2233. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2234. return -EINVAL;
  2235. for (i = 0; i < num_wqes; ) {
  2236. kwqe = wqes[i];
  2237. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2238. work = 1;
  2239. switch (opcode) {
  2240. case FCOE_KWQE_OPCODE_INIT1:
  2241. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2242. num_wqes - i, &work);
  2243. break;
  2244. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2245. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2246. num_wqes - i, &work);
  2247. break;
  2248. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2249. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2250. break;
  2251. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2252. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2253. break;
  2254. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2255. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2256. break;
  2257. case FCOE_KWQE_OPCODE_DESTROY:
  2258. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2259. break;
  2260. case FCOE_KWQE_OPCODE_STAT:
  2261. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2262. break;
  2263. default:
  2264. ret = 0;
  2265. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2266. opcode);
  2267. break;
  2268. }
  2269. if (ret < 0) {
  2270. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2271. opcode);
  2272. /* Possibly bnx2x parity error, send completion
  2273. * to ulp drivers with error code to speed up
  2274. * cleanup and reset recovery.
  2275. */
  2276. if (ret == -EIO || ret == -EAGAIN)
  2277. cnic_bnx2x_kwqe_err(dev, kwqe);
  2278. }
  2279. i += work;
  2280. }
  2281. return 0;
  2282. }
  2283. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2284. u32 num_wqes)
  2285. {
  2286. int ret = -EINVAL;
  2287. u32 layer_code;
  2288. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2289. return -EAGAIN; /* bnx2x is down */
  2290. if (!num_wqes)
  2291. return 0;
  2292. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2293. switch (layer_code) {
  2294. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2295. case KWQE_FLAGS_LAYER_MASK_L4:
  2296. case KWQE_FLAGS_LAYER_MASK_L2:
  2297. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2298. break;
  2299. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2300. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2301. break;
  2302. }
  2303. return ret;
  2304. }
  2305. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2306. {
  2307. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2308. return KCQE_FLAGS_LAYER_MASK_L4;
  2309. return opflag & KCQE_FLAGS_LAYER_MASK;
  2310. }
  2311. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2312. {
  2313. struct cnic_local *cp = dev->cnic_priv;
  2314. int i, j, comp = 0;
  2315. i = 0;
  2316. j = 1;
  2317. while (num_cqes) {
  2318. struct cnic_ulp_ops *ulp_ops;
  2319. int ulp_type;
  2320. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2321. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2322. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2323. comp++;
  2324. while (j < num_cqes) {
  2325. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2326. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2327. break;
  2328. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2329. comp++;
  2330. j++;
  2331. }
  2332. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2333. ulp_type = CNIC_ULP_RDMA;
  2334. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2335. ulp_type = CNIC_ULP_ISCSI;
  2336. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2337. ulp_type = CNIC_ULP_FCOE;
  2338. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2339. ulp_type = CNIC_ULP_L4;
  2340. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2341. goto end;
  2342. else {
  2343. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2344. kcqe_op_flag);
  2345. goto end;
  2346. }
  2347. rcu_read_lock();
  2348. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2349. if (likely(ulp_ops)) {
  2350. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2351. cp->completed_kcq + i, j);
  2352. }
  2353. rcu_read_unlock();
  2354. end:
  2355. num_cqes -= j;
  2356. i += j;
  2357. j = 1;
  2358. }
  2359. if (unlikely(comp))
  2360. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2361. }
  2362. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2363. {
  2364. struct cnic_local *cp = dev->cnic_priv;
  2365. u16 i, ri, hw_prod, last;
  2366. struct kcqe *kcqe;
  2367. int kcqe_cnt = 0, last_cnt = 0;
  2368. i = ri = last = info->sw_prod_idx;
  2369. ri &= MAX_KCQ_IDX;
  2370. hw_prod = *info->hw_prod_idx_ptr;
  2371. hw_prod = info->hw_idx(hw_prod);
  2372. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2373. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2374. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2375. i = info->next_idx(i);
  2376. ri = i & MAX_KCQ_IDX;
  2377. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2378. last_cnt = kcqe_cnt;
  2379. last = i;
  2380. }
  2381. }
  2382. info->sw_prod_idx = last;
  2383. return last_cnt;
  2384. }
  2385. static int cnic_l2_completion(struct cnic_local *cp)
  2386. {
  2387. u16 hw_cons, sw_cons;
  2388. struct cnic_uio_dev *udev = cp->udev;
  2389. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2390. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2391. u32 cmd;
  2392. int comp = 0;
  2393. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2394. return 0;
  2395. hw_cons = *cp->rx_cons_ptr;
  2396. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2397. hw_cons++;
  2398. sw_cons = cp->rx_cons;
  2399. while (sw_cons != hw_cons) {
  2400. u8 cqe_fp_flags;
  2401. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2402. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2403. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2404. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2405. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2406. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2407. cmd == RAMROD_CMD_ID_ETH_HALT)
  2408. comp++;
  2409. }
  2410. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2411. }
  2412. return comp;
  2413. }
  2414. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2415. {
  2416. u16 rx_cons, tx_cons;
  2417. int comp = 0;
  2418. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2419. return;
  2420. rx_cons = *cp->rx_cons_ptr;
  2421. tx_cons = *cp->tx_cons_ptr;
  2422. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2423. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2424. comp = cnic_l2_completion(cp);
  2425. cp->tx_cons = tx_cons;
  2426. cp->rx_cons = rx_cons;
  2427. if (cp->udev)
  2428. uio_event_notify(&cp->udev->cnic_uinfo);
  2429. }
  2430. if (comp)
  2431. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2432. }
  2433. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2434. {
  2435. struct cnic_local *cp = dev->cnic_priv;
  2436. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2437. int kcqe_cnt;
  2438. /* status block index must be read before reading other fields */
  2439. rmb();
  2440. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2441. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2442. service_kcqes(dev, kcqe_cnt);
  2443. /* Tell compiler that status_blk fields can change. */
  2444. barrier();
  2445. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2446. /* status block index must be read first */
  2447. rmb();
  2448. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2449. }
  2450. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2451. cnic_chk_pkt_rings(cp);
  2452. return status_idx;
  2453. }
  2454. static int cnic_service_bnx2(void *data, void *status_blk)
  2455. {
  2456. struct cnic_dev *dev = data;
  2457. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2458. struct status_block *sblk = status_blk;
  2459. return sblk->status_idx;
  2460. }
  2461. return cnic_service_bnx2_queues(dev);
  2462. }
  2463. static void cnic_service_bnx2_msix(unsigned long data)
  2464. {
  2465. struct cnic_dev *dev = (struct cnic_dev *) data;
  2466. struct cnic_local *cp = dev->cnic_priv;
  2467. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2468. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2469. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2470. }
  2471. static void cnic_doirq(struct cnic_dev *dev)
  2472. {
  2473. struct cnic_local *cp = dev->cnic_priv;
  2474. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2475. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2476. prefetch(cp->status_blk.gen);
  2477. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2478. tasklet_schedule(&cp->cnic_irq_task);
  2479. }
  2480. }
  2481. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2482. {
  2483. struct cnic_dev *dev = dev_instance;
  2484. struct cnic_local *cp = dev->cnic_priv;
  2485. if (cp->ack_int)
  2486. cp->ack_int(dev);
  2487. cnic_doirq(dev);
  2488. return IRQ_HANDLED;
  2489. }
  2490. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2491. u16 index, u8 op, u8 update)
  2492. {
  2493. struct cnic_local *cp = dev->cnic_priv;
  2494. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2495. COMMAND_REG_INT_ACK);
  2496. struct igu_ack_register igu_ack;
  2497. igu_ack.status_block_index = index;
  2498. igu_ack.sb_id_and_flags =
  2499. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2500. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2501. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2502. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2503. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2504. }
  2505. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2506. u16 index, u8 op, u8 update)
  2507. {
  2508. struct igu_regular cmd_data;
  2509. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2510. cmd_data.sb_id_and_flags =
  2511. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2512. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2513. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2514. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2515. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2516. }
  2517. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2518. {
  2519. struct cnic_local *cp = dev->cnic_priv;
  2520. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2521. IGU_INT_DISABLE, 0);
  2522. }
  2523. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2524. {
  2525. struct cnic_local *cp = dev->cnic_priv;
  2526. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2527. IGU_INT_DISABLE, 0);
  2528. }
  2529. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2530. {
  2531. u32 last_status = *info->status_idx_ptr;
  2532. int kcqe_cnt;
  2533. /* status block index must be read before reading the KCQ */
  2534. rmb();
  2535. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2536. service_kcqes(dev, kcqe_cnt);
  2537. /* Tell compiler that sblk fields can change. */
  2538. barrier();
  2539. last_status = *info->status_idx_ptr;
  2540. /* status block index must be read before reading the KCQ */
  2541. rmb();
  2542. }
  2543. return last_status;
  2544. }
  2545. static void cnic_service_bnx2x_bh(unsigned long data)
  2546. {
  2547. struct cnic_dev *dev = (struct cnic_dev *) data;
  2548. struct cnic_local *cp = dev->cnic_priv;
  2549. u32 status_idx, new_status_idx;
  2550. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2551. return;
  2552. while (1) {
  2553. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2554. CNIC_WR16(dev, cp->kcq1.io_addr,
  2555. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2556. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2557. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2558. status_idx, IGU_INT_ENABLE, 1);
  2559. break;
  2560. }
  2561. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2562. if (new_status_idx != status_idx)
  2563. continue;
  2564. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2565. MAX_KCQ_IDX);
  2566. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2567. status_idx, IGU_INT_ENABLE, 1);
  2568. break;
  2569. }
  2570. }
  2571. static int cnic_service_bnx2x(void *data, void *status_blk)
  2572. {
  2573. struct cnic_dev *dev = data;
  2574. struct cnic_local *cp = dev->cnic_priv;
  2575. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2576. cnic_doirq(dev);
  2577. cnic_chk_pkt_rings(cp);
  2578. return 0;
  2579. }
  2580. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2581. {
  2582. struct cnic_ulp_ops *ulp_ops;
  2583. if (if_type == CNIC_ULP_ISCSI)
  2584. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2585. mutex_lock(&cnic_lock);
  2586. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2587. lockdep_is_held(&cnic_lock));
  2588. if (!ulp_ops) {
  2589. mutex_unlock(&cnic_lock);
  2590. return;
  2591. }
  2592. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2593. mutex_unlock(&cnic_lock);
  2594. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2595. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2596. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2597. }
  2598. static void cnic_ulp_stop(struct cnic_dev *dev)
  2599. {
  2600. struct cnic_local *cp = dev->cnic_priv;
  2601. int if_type;
  2602. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2603. cnic_ulp_stop_one(cp, if_type);
  2604. }
  2605. static void cnic_ulp_start(struct cnic_dev *dev)
  2606. {
  2607. struct cnic_local *cp = dev->cnic_priv;
  2608. int if_type;
  2609. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2610. struct cnic_ulp_ops *ulp_ops;
  2611. mutex_lock(&cnic_lock);
  2612. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2613. lockdep_is_held(&cnic_lock));
  2614. if (!ulp_ops || !ulp_ops->cnic_start) {
  2615. mutex_unlock(&cnic_lock);
  2616. continue;
  2617. }
  2618. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2619. mutex_unlock(&cnic_lock);
  2620. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2621. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2622. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2623. }
  2624. }
  2625. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2626. {
  2627. struct cnic_local *cp = dev->cnic_priv;
  2628. struct cnic_ulp_ops *ulp_ops;
  2629. int rc;
  2630. mutex_lock(&cnic_lock);
  2631. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2632. if (ulp_ops && ulp_ops->cnic_get_stats)
  2633. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2634. else
  2635. rc = -ENODEV;
  2636. mutex_unlock(&cnic_lock);
  2637. return rc;
  2638. }
  2639. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2640. {
  2641. struct cnic_dev *dev = data;
  2642. int ulp_type = CNIC_ULP_ISCSI;
  2643. switch (info->cmd) {
  2644. case CNIC_CTL_STOP_CMD:
  2645. cnic_hold(dev);
  2646. cnic_ulp_stop(dev);
  2647. cnic_stop_hw(dev);
  2648. cnic_put(dev);
  2649. break;
  2650. case CNIC_CTL_START_CMD:
  2651. cnic_hold(dev);
  2652. if (!cnic_start_hw(dev))
  2653. cnic_ulp_start(dev);
  2654. cnic_put(dev);
  2655. break;
  2656. case CNIC_CTL_STOP_ISCSI_CMD: {
  2657. struct cnic_local *cp = dev->cnic_priv;
  2658. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2659. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2660. break;
  2661. }
  2662. case CNIC_CTL_COMPLETION_CMD: {
  2663. struct cnic_ctl_completion *comp = &info->data.comp;
  2664. u32 cid = BNX2X_SW_CID(comp->cid);
  2665. u32 l5_cid;
  2666. struct cnic_local *cp = dev->cnic_priv;
  2667. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2668. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2669. if (unlikely(comp->error)) {
  2670. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2671. netdev_err(dev->netdev,
  2672. "CID %x CFC delete comp error %x\n",
  2673. cid, comp->error);
  2674. }
  2675. ctx->wait_cond = 1;
  2676. wake_up(&ctx->waitq);
  2677. }
  2678. break;
  2679. }
  2680. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2681. ulp_type = CNIC_ULP_FCOE;
  2682. /* fall through */
  2683. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2684. cnic_hold(dev);
  2685. cnic_copy_ulp_stats(dev, ulp_type);
  2686. cnic_put(dev);
  2687. break;
  2688. default:
  2689. return -EINVAL;
  2690. }
  2691. return 0;
  2692. }
  2693. static void cnic_ulp_init(struct cnic_dev *dev)
  2694. {
  2695. int i;
  2696. struct cnic_local *cp = dev->cnic_priv;
  2697. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2698. struct cnic_ulp_ops *ulp_ops;
  2699. mutex_lock(&cnic_lock);
  2700. ulp_ops = cnic_ulp_tbl_prot(i);
  2701. if (!ulp_ops || !ulp_ops->cnic_init) {
  2702. mutex_unlock(&cnic_lock);
  2703. continue;
  2704. }
  2705. ulp_get(ulp_ops);
  2706. mutex_unlock(&cnic_lock);
  2707. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2708. ulp_ops->cnic_init(dev);
  2709. ulp_put(ulp_ops);
  2710. }
  2711. }
  2712. static void cnic_ulp_exit(struct cnic_dev *dev)
  2713. {
  2714. int i;
  2715. struct cnic_local *cp = dev->cnic_priv;
  2716. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2717. struct cnic_ulp_ops *ulp_ops;
  2718. mutex_lock(&cnic_lock);
  2719. ulp_ops = cnic_ulp_tbl_prot(i);
  2720. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2721. mutex_unlock(&cnic_lock);
  2722. continue;
  2723. }
  2724. ulp_get(ulp_ops);
  2725. mutex_unlock(&cnic_lock);
  2726. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2727. ulp_ops->cnic_exit(dev);
  2728. ulp_put(ulp_ops);
  2729. }
  2730. }
  2731. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2732. {
  2733. struct cnic_dev *dev = csk->dev;
  2734. struct l4_kwq_offload_pg *l4kwqe;
  2735. struct kwqe *wqes[1];
  2736. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2737. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2738. wqes[0] = (struct kwqe *) l4kwqe;
  2739. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2740. l4kwqe->flags =
  2741. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2742. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2743. l4kwqe->da0 = csk->ha[0];
  2744. l4kwqe->da1 = csk->ha[1];
  2745. l4kwqe->da2 = csk->ha[2];
  2746. l4kwqe->da3 = csk->ha[3];
  2747. l4kwqe->da4 = csk->ha[4];
  2748. l4kwqe->da5 = csk->ha[5];
  2749. l4kwqe->sa0 = dev->mac_addr[0];
  2750. l4kwqe->sa1 = dev->mac_addr[1];
  2751. l4kwqe->sa2 = dev->mac_addr[2];
  2752. l4kwqe->sa3 = dev->mac_addr[3];
  2753. l4kwqe->sa4 = dev->mac_addr[4];
  2754. l4kwqe->sa5 = dev->mac_addr[5];
  2755. l4kwqe->etype = ETH_P_IP;
  2756. l4kwqe->ipid_start = DEF_IPID_START;
  2757. l4kwqe->host_opaque = csk->l5_cid;
  2758. if (csk->vlan_id) {
  2759. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2760. l4kwqe->vlan_tag = csk->vlan_id;
  2761. l4kwqe->l2hdr_nbytes += 4;
  2762. }
  2763. return dev->submit_kwqes(dev, wqes, 1);
  2764. }
  2765. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2766. {
  2767. struct cnic_dev *dev = csk->dev;
  2768. struct l4_kwq_update_pg *l4kwqe;
  2769. struct kwqe *wqes[1];
  2770. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2771. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2772. wqes[0] = (struct kwqe *) l4kwqe;
  2773. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2774. l4kwqe->flags =
  2775. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2776. l4kwqe->pg_cid = csk->pg_cid;
  2777. l4kwqe->da0 = csk->ha[0];
  2778. l4kwqe->da1 = csk->ha[1];
  2779. l4kwqe->da2 = csk->ha[2];
  2780. l4kwqe->da3 = csk->ha[3];
  2781. l4kwqe->da4 = csk->ha[4];
  2782. l4kwqe->da5 = csk->ha[5];
  2783. l4kwqe->pg_host_opaque = csk->l5_cid;
  2784. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2785. return dev->submit_kwqes(dev, wqes, 1);
  2786. }
  2787. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2788. {
  2789. struct cnic_dev *dev = csk->dev;
  2790. struct l4_kwq_upload *l4kwqe;
  2791. struct kwqe *wqes[1];
  2792. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2793. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2794. wqes[0] = (struct kwqe *) l4kwqe;
  2795. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2796. l4kwqe->flags =
  2797. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2798. l4kwqe->cid = csk->pg_cid;
  2799. return dev->submit_kwqes(dev, wqes, 1);
  2800. }
  2801. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2802. {
  2803. struct cnic_dev *dev = csk->dev;
  2804. struct l4_kwq_connect_req1 *l4kwqe1;
  2805. struct l4_kwq_connect_req2 *l4kwqe2;
  2806. struct l4_kwq_connect_req3 *l4kwqe3;
  2807. struct kwqe *wqes[3];
  2808. u8 tcp_flags = 0;
  2809. int num_wqes = 2;
  2810. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2811. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2812. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2813. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2814. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2815. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2816. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2817. l4kwqe3->flags =
  2818. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2819. l4kwqe3->ka_timeout = csk->ka_timeout;
  2820. l4kwqe3->ka_interval = csk->ka_interval;
  2821. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2822. l4kwqe3->tos = csk->tos;
  2823. l4kwqe3->ttl = csk->ttl;
  2824. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2825. l4kwqe3->pmtu = csk->mtu;
  2826. l4kwqe3->rcv_buf = csk->rcv_buf;
  2827. l4kwqe3->snd_buf = csk->snd_buf;
  2828. l4kwqe3->seed = csk->seed;
  2829. wqes[0] = (struct kwqe *) l4kwqe1;
  2830. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2831. wqes[1] = (struct kwqe *) l4kwqe2;
  2832. wqes[2] = (struct kwqe *) l4kwqe3;
  2833. num_wqes = 3;
  2834. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2835. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2836. l4kwqe2->flags =
  2837. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2838. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2839. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2840. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2841. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2842. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2843. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2844. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2845. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2846. sizeof(struct tcphdr);
  2847. } else {
  2848. wqes[1] = (struct kwqe *) l4kwqe3;
  2849. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2850. sizeof(struct tcphdr);
  2851. }
  2852. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2853. l4kwqe1->flags =
  2854. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2855. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2856. l4kwqe1->cid = csk->cid;
  2857. l4kwqe1->pg_cid = csk->pg_cid;
  2858. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2859. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2860. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2861. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2862. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2863. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2864. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2865. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2866. if (csk->tcp_flags & SK_TCP_NAGLE)
  2867. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2868. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2869. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2870. if (csk->tcp_flags & SK_TCP_SACK)
  2871. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2872. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2873. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2874. l4kwqe1->tcp_flags = tcp_flags;
  2875. return dev->submit_kwqes(dev, wqes, num_wqes);
  2876. }
  2877. static int cnic_cm_close_req(struct cnic_sock *csk)
  2878. {
  2879. struct cnic_dev *dev = csk->dev;
  2880. struct l4_kwq_close_req *l4kwqe;
  2881. struct kwqe *wqes[1];
  2882. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2883. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2884. wqes[0] = (struct kwqe *) l4kwqe;
  2885. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2886. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2887. l4kwqe->cid = csk->cid;
  2888. return dev->submit_kwqes(dev, wqes, 1);
  2889. }
  2890. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2891. {
  2892. struct cnic_dev *dev = csk->dev;
  2893. struct l4_kwq_reset_req *l4kwqe;
  2894. struct kwqe *wqes[1];
  2895. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2896. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2897. wqes[0] = (struct kwqe *) l4kwqe;
  2898. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2899. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2900. l4kwqe->cid = csk->cid;
  2901. return dev->submit_kwqes(dev, wqes, 1);
  2902. }
  2903. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2904. u32 l5_cid, struct cnic_sock **csk, void *context)
  2905. {
  2906. struct cnic_local *cp = dev->cnic_priv;
  2907. struct cnic_sock *csk1;
  2908. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2909. return -EINVAL;
  2910. if (cp->ctx_tbl) {
  2911. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2912. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2913. return -EAGAIN;
  2914. }
  2915. csk1 = &cp->csk_tbl[l5_cid];
  2916. if (atomic_read(&csk1->ref_count))
  2917. return -EAGAIN;
  2918. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2919. return -EBUSY;
  2920. csk1->dev = dev;
  2921. csk1->cid = cid;
  2922. csk1->l5_cid = l5_cid;
  2923. csk1->ulp_type = ulp_type;
  2924. csk1->context = context;
  2925. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2926. csk1->ka_interval = DEF_KA_INTERVAL;
  2927. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2928. csk1->tos = DEF_TOS;
  2929. csk1->ttl = DEF_TTL;
  2930. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2931. csk1->rcv_buf = DEF_RCV_BUF;
  2932. csk1->snd_buf = DEF_SND_BUF;
  2933. csk1->seed = DEF_SEED;
  2934. *csk = csk1;
  2935. return 0;
  2936. }
  2937. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2938. {
  2939. if (csk->src_port) {
  2940. struct cnic_dev *dev = csk->dev;
  2941. struct cnic_local *cp = dev->cnic_priv;
  2942. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2943. csk->src_port = 0;
  2944. }
  2945. }
  2946. static void cnic_close_conn(struct cnic_sock *csk)
  2947. {
  2948. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2949. cnic_cm_upload_pg(csk);
  2950. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2951. }
  2952. cnic_cm_cleanup(csk);
  2953. }
  2954. static int cnic_cm_destroy(struct cnic_sock *csk)
  2955. {
  2956. if (!cnic_in_use(csk))
  2957. return -EINVAL;
  2958. csk_hold(csk);
  2959. clear_bit(SK_F_INUSE, &csk->flags);
  2960. smp_mb__after_clear_bit();
  2961. while (atomic_read(&csk->ref_count) != 1)
  2962. msleep(1);
  2963. cnic_cm_cleanup(csk);
  2964. csk->flags = 0;
  2965. csk_put(csk);
  2966. return 0;
  2967. }
  2968. static inline u16 cnic_get_vlan(struct net_device *dev,
  2969. struct net_device **vlan_dev)
  2970. {
  2971. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2972. *vlan_dev = vlan_dev_real_dev(dev);
  2973. return vlan_dev_vlan_id(dev);
  2974. }
  2975. *vlan_dev = dev;
  2976. return 0;
  2977. }
  2978. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2979. struct dst_entry **dst)
  2980. {
  2981. #if defined(CONFIG_INET)
  2982. struct rtable *rt;
  2983. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2984. if (!IS_ERR(rt)) {
  2985. *dst = &rt->dst;
  2986. return 0;
  2987. }
  2988. return PTR_ERR(rt);
  2989. #else
  2990. return -ENETUNREACH;
  2991. #endif
  2992. }
  2993. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2994. struct dst_entry **dst)
  2995. {
  2996. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2997. struct flowi6 fl6;
  2998. memset(&fl6, 0, sizeof(fl6));
  2999. fl6.daddr = dst_addr->sin6_addr;
  3000. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3001. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3002. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3003. if ((*dst)->error) {
  3004. dst_release(*dst);
  3005. *dst = NULL;
  3006. return -ENETUNREACH;
  3007. } else
  3008. return 0;
  3009. #endif
  3010. return -ENETUNREACH;
  3011. }
  3012. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3013. int ulp_type)
  3014. {
  3015. struct cnic_dev *dev = NULL;
  3016. struct dst_entry *dst;
  3017. struct net_device *netdev = NULL;
  3018. int err = -ENETUNREACH;
  3019. if (dst_addr->sin_family == AF_INET)
  3020. err = cnic_get_v4_route(dst_addr, &dst);
  3021. else if (dst_addr->sin_family == AF_INET6) {
  3022. struct sockaddr_in6 *dst_addr6 =
  3023. (struct sockaddr_in6 *) dst_addr;
  3024. err = cnic_get_v6_route(dst_addr6, &dst);
  3025. } else
  3026. return NULL;
  3027. if (err)
  3028. return NULL;
  3029. if (!dst->dev)
  3030. goto done;
  3031. cnic_get_vlan(dst->dev, &netdev);
  3032. dev = cnic_from_netdev(netdev);
  3033. done:
  3034. dst_release(dst);
  3035. if (dev)
  3036. cnic_put(dev);
  3037. return dev;
  3038. }
  3039. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3040. {
  3041. struct cnic_dev *dev = csk->dev;
  3042. struct cnic_local *cp = dev->cnic_priv;
  3043. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3044. }
  3045. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3046. {
  3047. struct cnic_dev *dev = csk->dev;
  3048. struct cnic_local *cp = dev->cnic_priv;
  3049. int is_v6, rc = 0;
  3050. struct dst_entry *dst = NULL;
  3051. struct net_device *realdev;
  3052. __be16 local_port;
  3053. u32 port_id;
  3054. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3055. saddr->remote.v6.sin6_family == AF_INET6)
  3056. is_v6 = 1;
  3057. else if (saddr->local.v4.sin_family == AF_INET &&
  3058. saddr->remote.v4.sin_family == AF_INET)
  3059. is_v6 = 0;
  3060. else
  3061. return -EINVAL;
  3062. clear_bit(SK_F_IPV6, &csk->flags);
  3063. if (is_v6) {
  3064. set_bit(SK_F_IPV6, &csk->flags);
  3065. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3066. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3067. sizeof(struct in6_addr));
  3068. csk->dst_port = saddr->remote.v6.sin6_port;
  3069. local_port = saddr->local.v6.sin6_port;
  3070. } else {
  3071. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3072. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3073. csk->dst_port = saddr->remote.v4.sin_port;
  3074. local_port = saddr->local.v4.sin_port;
  3075. }
  3076. csk->vlan_id = 0;
  3077. csk->mtu = dev->netdev->mtu;
  3078. if (dst && dst->dev) {
  3079. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3080. if (realdev == dev->netdev) {
  3081. csk->vlan_id = vlan;
  3082. csk->mtu = dst_mtu(dst);
  3083. }
  3084. }
  3085. port_id = be16_to_cpu(local_port);
  3086. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3087. port_id < CNIC_LOCAL_PORT_MAX) {
  3088. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3089. port_id = 0;
  3090. } else
  3091. port_id = 0;
  3092. if (!port_id) {
  3093. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3094. if (port_id == -1) {
  3095. rc = -ENOMEM;
  3096. goto err_out;
  3097. }
  3098. local_port = cpu_to_be16(port_id);
  3099. }
  3100. csk->src_port = local_port;
  3101. err_out:
  3102. dst_release(dst);
  3103. return rc;
  3104. }
  3105. static void cnic_init_csk_state(struct cnic_sock *csk)
  3106. {
  3107. csk->state = 0;
  3108. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3109. clear_bit(SK_F_CLOSING, &csk->flags);
  3110. }
  3111. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3112. {
  3113. struct cnic_local *cp = csk->dev->cnic_priv;
  3114. int err = 0;
  3115. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3116. return -EOPNOTSUPP;
  3117. if (!cnic_in_use(csk))
  3118. return -EINVAL;
  3119. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3120. return -EINVAL;
  3121. cnic_init_csk_state(csk);
  3122. err = cnic_get_route(csk, saddr);
  3123. if (err)
  3124. goto err_out;
  3125. err = cnic_resolve_addr(csk, saddr);
  3126. if (!err)
  3127. return 0;
  3128. err_out:
  3129. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3130. return err;
  3131. }
  3132. static int cnic_cm_abort(struct cnic_sock *csk)
  3133. {
  3134. struct cnic_local *cp = csk->dev->cnic_priv;
  3135. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3136. if (!cnic_in_use(csk))
  3137. return -EINVAL;
  3138. if (cnic_abort_prep(csk))
  3139. return cnic_cm_abort_req(csk);
  3140. /* Getting here means that we haven't started connect, or
  3141. * connect was not successful.
  3142. */
  3143. cp->close_conn(csk, opcode);
  3144. if (csk->state != opcode)
  3145. return -EALREADY;
  3146. return 0;
  3147. }
  3148. static int cnic_cm_close(struct cnic_sock *csk)
  3149. {
  3150. if (!cnic_in_use(csk))
  3151. return -EINVAL;
  3152. if (cnic_close_prep(csk)) {
  3153. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3154. return cnic_cm_close_req(csk);
  3155. } else {
  3156. return -EALREADY;
  3157. }
  3158. return 0;
  3159. }
  3160. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3161. u8 opcode)
  3162. {
  3163. struct cnic_ulp_ops *ulp_ops;
  3164. int ulp_type = csk->ulp_type;
  3165. rcu_read_lock();
  3166. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3167. if (ulp_ops) {
  3168. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3169. ulp_ops->cm_connect_complete(csk);
  3170. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3171. ulp_ops->cm_close_complete(csk);
  3172. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3173. ulp_ops->cm_remote_abort(csk);
  3174. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3175. ulp_ops->cm_abort_complete(csk);
  3176. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3177. ulp_ops->cm_remote_close(csk);
  3178. }
  3179. rcu_read_unlock();
  3180. }
  3181. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3182. {
  3183. if (cnic_offld_prep(csk)) {
  3184. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3185. cnic_cm_update_pg(csk);
  3186. else
  3187. cnic_cm_offload_pg(csk);
  3188. }
  3189. return 0;
  3190. }
  3191. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3192. {
  3193. struct cnic_local *cp = dev->cnic_priv;
  3194. u32 l5_cid = kcqe->pg_host_opaque;
  3195. u8 opcode = kcqe->op_code;
  3196. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3197. csk_hold(csk);
  3198. if (!cnic_in_use(csk))
  3199. goto done;
  3200. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3201. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3202. goto done;
  3203. }
  3204. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3205. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3206. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3207. cnic_cm_upcall(cp, csk,
  3208. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3209. goto done;
  3210. }
  3211. csk->pg_cid = kcqe->pg_cid;
  3212. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3213. cnic_cm_conn_req(csk);
  3214. done:
  3215. csk_put(csk);
  3216. }
  3217. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3218. {
  3219. struct cnic_local *cp = dev->cnic_priv;
  3220. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3221. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3222. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3223. ctx->timestamp = jiffies;
  3224. ctx->wait_cond = 1;
  3225. wake_up(&ctx->waitq);
  3226. }
  3227. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3228. {
  3229. struct cnic_local *cp = dev->cnic_priv;
  3230. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3231. u8 opcode = l4kcqe->op_code;
  3232. u32 l5_cid;
  3233. struct cnic_sock *csk;
  3234. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3235. cnic_process_fcoe_term_conn(dev, kcqe);
  3236. return;
  3237. }
  3238. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3239. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3240. cnic_cm_process_offld_pg(dev, l4kcqe);
  3241. return;
  3242. }
  3243. l5_cid = l4kcqe->conn_id;
  3244. if (opcode & 0x80)
  3245. l5_cid = l4kcqe->cid;
  3246. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3247. return;
  3248. csk = &cp->csk_tbl[l5_cid];
  3249. csk_hold(csk);
  3250. if (!cnic_in_use(csk)) {
  3251. csk_put(csk);
  3252. return;
  3253. }
  3254. switch (opcode) {
  3255. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3256. if (l4kcqe->status != 0) {
  3257. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3258. cnic_cm_upcall(cp, csk,
  3259. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3260. }
  3261. break;
  3262. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3263. if (l4kcqe->status == 0)
  3264. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3265. else if (l4kcqe->status ==
  3266. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3267. set_bit(SK_F_HW_ERR, &csk->flags);
  3268. smp_mb__before_clear_bit();
  3269. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3270. cnic_cm_upcall(cp, csk, opcode);
  3271. break;
  3272. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3273. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3274. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3275. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3276. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3277. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3278. set_bit(SK_F_HW_ERR, &csk->flags);
  3279. cp->close_conn(csk, opcode);
  3280. break;
  3281. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3282. /* after we already sent CLOSE_REQ */
  3283. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3284. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3285. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3286. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3287. else
  3288. cnic_cm_upcall(cp, csk, opcode);
  3289. break;
  3290. }
  3291. csk_put(csk);
  3292. }
  3293. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3294. {
  3295. struct cnic_dev *dev = data;
  3296. int i;
  3297. for (i = 0; i < num; i++)
  3298. cnic_cm_process_kcqe(dev, kcqe[i]);
  3299. }
  3300. static struct cnic_ulp_ops cm_ulp_ops = {
  3301. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3302. };
  3303. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3304. {
  3305. struct cnic_local *cp = dev->cnic_priv;
  3306. kfree(cp->csk_tbl);
  3307. cp->csk_tbl = NULL;
  3308. cnic_free_id_tbl(&cp->csk_port_tbl);
  3309. }
  3310. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3311. {
  3312. struct cnic_local *cp = dev->cnic_priv;
  3313. u32 port_id;
  3314. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3315. GFP_KERNEL);
  3316. if (!cp->csk_tbl)
  3317. return -ENOMEM;
  3318. port_id = random32();
  3319. port_id %= CNIC_LOCAL_PORT_RANGE;
  3320. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3321. CNIC_LOCAL_PORT_MIN, port_id)) {
  3322. cnic_cm_free_mem(dev);
  3323. return -ENOMEM;
  3324. }
  3325. return 0;
  3326. }
  3327. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3328. {
  3329. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3330. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3331. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3332. csk->state = opcode;
  3333. }
  3334. /* 1. If event opcode matches the expected event in csk->state
  3335. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3336. * event
  3337. * 3. If the expected event is 0, meaning the connection was never
  3338. * never established, we accept the opcode from cm_abort.
  3339. */
  3340. if (opcode == csk->state || csk->state == 0 ||
  3341. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3342. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3343. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3344. if (csk->state == 0)
  3345. csk->state = opcode;
  3346. return 1;
  3347. }
  3348. }
  3349. return 0;
  3350. }
  3351. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3352. {
  3353. struct cnic_dev *dev = csk->dev;
  3354. struct cnic_local *cp = dev->cnic_priv;
  3355. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3356. cnic_cm_upcall(cp, csk, opcode);
  3357. return;
  3358. }
  3359. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3360. cnic_close_conn(csk);
  3361. csk->state = opcode;
  3362. cnic_cm_upcall(cp, csk, opcode);
  3363. }
  3364. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3365. {
  3366. }
  3367. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3368. {
  3369. u32 seed;
  3370. seed = random32();
  3371. cnic_ctx_wr(dev, 45, 0, seed);
  3372. return 0;
  3373. }
  3374. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3375. {
  3376. struct cnic_dev *dev = csk->dev;
  3377. struct cnic_local *cp = dev->cnic_priv;
  3378. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3379. union l5cm_specific_data l5_data;
  3380. u32 cmd = 0;
  3381. int close_complete = 0;
  3382. switch (opcode) {
  3383. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3384. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3385. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3386. if (cnic_ready_to_close(csk, opcode)) {
  3387. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3388. close_complete = 1;
  3389. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3390. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3391. else
  3392. close_complete = 1;
  3393. }
  3394. break;
  3395. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3396. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3397. break;
  3398. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3399. close_complete = 1;
  3400. break;
  3401. }
  3402. if (cmd) {
  3403. memset(&l5_data, 0, sizeof(l5_data));
  3404. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3405. &l5_data);
  3406. } else if (close_complete) {
  3407. ctx->timestamp = jiffies;
  3408. cnic_close_conn(csk);
  3409. cnic_cm_upcall(cp, csk, csk->state);
  3410. }
  3411. }
  3412. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3413. {
  3414. struct cnic_local *cp = dev->cnic_priv;
  3415. if (!cp->ctx_tbl)
  3416. return;
  3417. if (!netif_running(dev->netdev))
  3418. return;
  3419. cnic_bnx2x_delete_wait(dev, 0);
  3420. cancel_delayed_work(&cp->delete_task);
  3421. flush_workqueue(cnic_wq);
  3422. if (atomic_read(&cp->iscsi_conn) != 0)
  3423. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3424. atomic_read(&cp->iscsi_conn));
  3425. }
  3426. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3427. {
  3428. struct cnic_local *cp = dev->cnic_priv;
  3429. u32 pfid = cp->pfid;
  3430. u32 port = CNIC_PORT(cp);
  3431. cnic_init_bnx2x_mac(dev);
  3432. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3433. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3434. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3435. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3436. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3437. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3438. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3439. DEF_MAX_DA_COUNT);
  3440. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3441. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3442. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3443. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3444. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3445. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3446. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3447. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3448. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3449. DEF_MAX_CWND);
  3450. return 0;
  3451. }
  3452. static void cnic_delete_task(struct work_struct *work)
  3453. {
  3454. struct cnic_local *cp;
  3455. struct cnic_dev *dev;
  3456. u32 i;
  3457. int need_resched = 0;
  3458. cp = container_of(work, struct cnic_local, delete_task.work);
  3459. dev = cp->dev;
  3460. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3461. struct drv_ctl_info info;
  3462. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3463. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3464. cp->ethdev->drv_ctl(dev->netdev, &info);
  3465. }
  3466. for (i = 0; i < cp->max_cid_space; i++) {
  3467. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3468. int err;
  3469. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3470. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3471. continue;
  3472. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3473. need_resched = 1;
  3474. continue;
  3475. }
  3476. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3477. continue;
  3478. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3479. cnic_free_bnx2x_conn_resc(dev, i);
  3480. if (!err) {
  3481. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3482. atomic_dec(&cp->iscsi_conn);
  3483. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3484. }
  3485. }
  3486. if (need_resched)
  3487. queue_delayed_work(cnic_wq, &cp->delete_task,
  3488. msecs_to_jiffies(10));
  3489. }
  3490. static int cnic_cm_open(struct cnic_dev *dev)
  3491. {
  3492. struct cnic_local *cp = dev->cnic_priv;
  3493. int err;
  3494. err = cnic_cm_alloc_mem(dev);
  3495. if (err)
  3496. return err;
  3497. err = cp->start_cm(dev);
  3498. if (err)
  3499. goto err_out;
  3500. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3501. dev->cm_create = cnic_cm_create;
  3502. dev->cm_destroy = cnic_cm_destroy;
  3503. dev->cm_connect = cnic_cm_connect;
  3504. dev->cm_abort = cnic_cm_abort;
  3505. dev->cm_close = cnic_cm_close;
  3506. dev->cm_select_dev = cnic_cm_select_dev;
  3507. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3508. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3509. return 0;
  3510. err_out:
  3511. cnic_cm_free_mem(dev);
  3512. return err;
  3513. }
  3514. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3515. {
  3516. struct cnic_local *cp = dev->cnic_priv;
  3517. int i;
  3518. cp->stop_cm(dev);
  3519. if (!cp->csk_tbl)
  3520. return 0;
  3521. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3522. struct cnic_sock *csk = &cp->csk_tbl[i];
  3523. clear_bit(SK_F_INUSE, &csk->flags);
  3524. cnic_cm_cleanup(csk);
  3525. }
  3526. cnic_cm_free_mem(dev);
  3527. return 0;
  3528. }
  3529. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3530. {
  3531. u32 cid_addr;
  3532. int i;
  3533. cid_addr = GET_CID_ADDR(cid);
  3534. for (i = 0; i < CTX_SIZE; i += 4)
  3535. cnic_ctx_wr(dev, cid_addr, i, 0);
  3536. }
  3537. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3538. {
  3539. struct cnic_local *cp = dev->cnic_priv;
  3540. int ret = 0, i;
  3541. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3542. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3543. return 0;
  3544. for (i = 0; i < cp->ctx_blks; i++) {
  3545. int j;
  3546. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3547. u32 val;
  3548. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3549. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3550. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3551. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3552. (u64) cp->ctx_arr[i].mapping >> 32);
  3553. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3554. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3555. for (j = 0; j < 10; j++) {
  3556. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3557. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3558. break;
  3559. udelay(5);
  3560. }
  3561. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3562. ret = -EBUSY;
  3563. break;
  3564. }
  3565. }
  3566. return ret;
  3567. }
  3568. static void cnic_free_irq(struct cnic_dev *dev)
  3569. {
  3570. struct cnic_local *cp = dev->cnic_priv;
  3571. struct cnic_eth_dev *ethdev = cp->ethdev;
  3572. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3573. cp->disable_int_sync(dev);
  3574. tasklet_kill(&cp->cnic_irq_task);
  3575. free_irq(ethdev->irq_arr[0].vector, dev);
  3576. }
  3577. }
  3578. static int cnic_request_irq(struct cnic_dev *dev)
  3579. {
  3580. struct cnic_local *cp = dev->cnic_priv;
  3581. struct cnic_eth_dev *ethdev = cp->ethdev;
  3582. int err;
  3583. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3584. if (err)
  3585. tasklet_disable(&cp->cnic_irq_task);
  3586. return err;
  3587. }
  3588. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3589. {
  3590. struct cnic_local *cp = dev->cnic_priv;
  3591. struct cnic_eth_dev *ethdev = cp->ethdev;
  3592. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3593. int err, i = 0;
  3594. int sblk_num = cp->status_blk_num;
  3595. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3596. BNX2_HC_SB_CONFIG_1;
  3597. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3598. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3599. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3600. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3601. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3602. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3603. (unsigned long) dev);
  3604. err = cnic_request_irq(dev);
  3605. if (err)
  3606. return err;
  3607. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3608. i < 10) {
  3609. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3610. 1 << (11 + sblk_num));
  3611. udelay(10);
  3612. i++;
  3613. barrier();
  3614. }
  3615. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3616. cnic_free_irq(dev);
  3617. goto failed;
  3618. }
  3619. } else {
  3620. struct status_block *sblk = cp->status_blk.gen;
  3621. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3622. int i = 0;
  3623. while (sblk->status_completion_producer_index && i < 10) {
  3624. CNIC_WR(dev, BNX2_HC_COMMAND,
  3625. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3626. udelay(10);
  3627. i++;
  3628. barrier();
  3629. }
  3630. if (sblk->status_completion_producer_index)
  3631. goto failed;
  3632. }
  3633. return 0;
  3634. failed:
  3635. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3636. return -EBUSY;
  3637. }
  3638. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3639. {
  3640. struct cnic_local *cp = dev->cnic_priv;
  3641. struct cnic_eth_dev *ethdev = cp->ethdev;
  3642. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3643. return;
  3644. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3645. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3646. }
  3647. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3648. {
  3649. struct cnic_local *cp = dev->cnic_priv;
  3650. struct cnic_eth_dev *ethdev = cp->ethdev;
  3651. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3652. return;
  3653. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3654. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3655. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3656. synchronize_irq(ethdev->irq_arr[0].vector);
  3657. }
  3658. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3659. {
  3660. struct cnic_local *cp = dev->cnic_priv;
  3661. struct cnic_eth_dev *ethdev = cp->ethdev;
  3662. struct cnic_uio_dev *udev = cp->udev;
  3663. u32 cid_addr, tx_cid, sb_id;
  3664. u32 val, offset0, offset1, offset2, offset3;
  3665. int i;
  3666. struct tx_bd *txbd;
  3667. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3668. struct status_block *s_blk = cp->status_blk.gen;
  3669. sb_id = cp->status_blk_num;
  3670. tx_cid = 20;
  3671. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3672. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3673. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3674. tx_cid = TX_TSS_CID + sb_id - 1;
  3675. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3676. (TX_TSS_CID << 7));
  3677. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3678. }
  3679. cp->tx_cons = *cp->tx_cons_ptr;
  3680. cid_addr = GET_CID_ADDR(tx_cid);
  3681. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3682. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3683. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3684. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3685. offset0 = BNX2_L2CTX_TYPE_XI;
  3686. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3687. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3688. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3689. } else {
  3690. cnic_init_context(dev, tx_cid);
  3691. cnic_init_context(dev, tx_cid + 1);
  3692. offset0 = BNX2_L2CTX_TYPE;
  3693. offset1 = BNX2_L2CTX_CMD_TYPE;
  3694. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3695. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3696. }
  3697. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3698. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3699. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3700. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3701. txbd = udev->l2_ring;
  3702. buf_map = udev->l2_buf_map;
  3703. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3704. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3705. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3706. }
  3707. val = (u64) ring_map >> 32;
  3708. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3709. txbd->tx_bd_haddr_hi = val;
  3710. val = (u64) ring_map & 0xffffffff;
  3711. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3712. txbd->tx_bd_haddr_lo = val;
  3713. }
  3714. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3715. {
  3716. struct cnic_local *cp = dev->cnic_priv;
  3717. struct cnic_eth_dev *ethdev = cp->ethdev;
  3718. struct cnic_uio_dev *udev = cp->udev;
  3719. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3720. int i;
  3721. struct rx_bd *rxbd;
  3722. struct status_block *s_blk = cp->status_blk.gen;
  3723. dma_addr_t ring_map = udev->l2_ring_map;
  3724. sb_id = cp->status_blk_num;
  3725. cnic_init_context(dev, 2);
  3726. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3727. coal_reg = BNX2_HC_COMMAND;
  3728. coal_val = CNIC_RD(dev, coal_reg);
  3729. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3730. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3731. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3732. coal_reg = BNX2_HC_COALESCE_NOW;
  3733. coal_val = 1 << (11 + sb_id);
  3734. }
  3735. i = 0;
  3736. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3737. CNIC_WR(dev, coal_reg, coal_val);
  3738. udelay(10);
  3739. i++;
  3740. barrier();
  3741. }
  3742. cp->rx_cons = *cp->rx_cons_ptr;
  3743. cid_addr = GET_CID_ADDR(2);
  3744. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3745. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3746. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3747. if (sb_id == 0)
  3748. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3749. else
  3750. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3751. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3752. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3753. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3754. dma_addr_t buf_map;
  3755. int n = (i % cp->l2_rx_ring_size) + 1;
  3756. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3757. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3758. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3759. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3760. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3761. }
  3762. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3763. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3764. rxbd->rx_bd_haddr_hi = val;
  3765. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3766. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3767. rxbd->rx_bd_haddr_lo = val;
  3768. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3769. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3770. }
  3771. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3772. {
  3773. struct kwqe *wqes[1], l2kwqe;
  3774. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3775. wqes[0] = &l2kwqe;
  3776. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3777. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3778. KWQE_OPCODE_SHIFT) | 2;
  3779. dev->submit_kwqes(dev, wqes, 1);
  3780. }
  3781. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3782. {
  3783. struct cnic_local *cp = dev->cnic_priv;
  3784. u32 val;
  3785. val = cp->func << 2;
  3786. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3787. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3788. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3789. dev->mac_addr[0] = (u8) (val >> 8);
  3790. dev->mac_addr[1] = (u8) val;
  3791. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3792. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3793. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3794. dev->mac_addr[2] = (u8) (val >> 24);
  3795. dev->mac_addr[3] = (u8) (val >> 16);
  3796. dev->mac_addr[4] = (u8) (val >> 8);
  3797. dev->mac_addr[5] = (u8) val;
  3798. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3799. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3800. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3801. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3802. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3803. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3804. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3805. }
  3806. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3807. {
  3808. struct cnic_local *cp = dev->cnic_priv;
  3809. struct cnic_eth_dev *ethdev = cp->ethdev;
  3810. struct status_block *sblk = cp->status_blk.gen;
  3811. u32 val, kcq_cid_addr, kwq_cid_addr;
  3812. int err;
  3813. cnic_set_bnx2_mac(dev);
  3814. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3815. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3816. if (BCM_PAGE_BITS > 12)
  3817. val |= (12 - 8) << 4;
  3818. else
  3819. val |= (BCM_PAGE_BITS - 8) << 4;
  3820. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3821. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3822. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3823. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3824. err = cnic_setup_5709_context(dev, 1);
  3825. if (err)
  3826. return err;
  3827. cnic_init_context(dev, KWQ_CID);
  3828. cnic_init_context(dev, KCQ_CID);
  3829. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3830. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3831. cp->max_kwq_idx = MAX_KWQ_IDX;
  3832. cp->kwq_prod_idx = 0;
  3833. cp->kwq_con_idx = 0;
  3834. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3835. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3836. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3837. else
  3838. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3839. /* Initialize the kernel work queue context. */
  3840. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3841. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3842. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3843. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3844. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3845. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3846. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3847. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3848. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3849. val = (u32) cp->kwq_info.pgtbl_map;
  3850. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3851. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3852. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3853. cp->kcq1.sw_prod_idx = 0;
  3854. cp->kcq1.hw_prod_idx_ptr =
  3855. (u16 *) &sblk->status_completion_producer_index;
  3856. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3857. /* Initialize the kernel complete queue context. */
  3858. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3859. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3860. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3861. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3862. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3863. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3864. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3865. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3866. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3867. val = (u32) cp->kcq1.dma.pgtbl_map;
  3868. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3869. cp->int_num = 0;
  3870. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3871. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3872. u32 sb_id = cp->status_blk_num;
  3873. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3874. cp->kcq1.hw_prod_idx_ptr =
  3875. (u16 *) &msblk->status_completion_producer_index;
  3876. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3877. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3878. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3879. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3880. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3881. }
  3882. /* Enable Commnad Scheduler notification when we write to the
  3883. * host producer index of the kernel contexts. */
  3884. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3885. /* Enable Command Scheduler notification when we write to either
  3886. * the Send Queue or Receive Queue producer indexes of the kernel
  3887. * bypass contexts. */
  3888. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3889. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3890. /* Notify COM when the driver post an application buffer. */
  3891. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3892. /* Set the CP and COM doorbells. These two processors polls the
  3893. * doorbell for a non zero value before running. This must be done
  3894. * after setting up the kernel queue contexts. */
  3895. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3896. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3897. cnic_init_bnx2_tx_ring(dev);
  3898. cnic_init_bnx2_rx_ring(dev);
  3899. err = cnic_init_bnx2_irq(dev);
  3900. if (err) {
  3901. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3902. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3903. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3904. return err;
  3905. }
  3906. return 0;
  3907. }
  3908. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3909. {
  3910. struct cnic_local *cp = dev->cnic_priv;
  3911. struct cnic_eth_dev *ethdev = cp->ethdev;
  3912. u32 start_offset = ethdev->ctx_tbl_offset;
  3913. int i;
  3914. for (i = 0; i < cp->ctx_blks; i++) {
  3915. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3916. dma_addr_t map = ctx->mapping;
  3917. if (cp->ctx_align) {
  3918. unsigned long mask = cp->ctx_align - 1;
  3919. map = (map + mask) & ~mask;
  3920. }
  3921. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3922. }
  3923. }
  3924. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3925. {
  3926. struct cnic_local *cp = dev->cnic_priv;
  3927. struct cnic_eth_dev *ethdev = cp->ethdev;
  3928. int err = 0;
  3929. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3930. (unsigned long) dev);
  3931. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3932. err = cnic_request_irq(dev);
  3933. return err;
  3934. }
  3935. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3936. u16 sb_id, u8 sb_index,
  3937. u8 disable)
  3938. {
  3939. u32 addr = BAR_CSTRORM_INTMEM +
  3940. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3941. offsetof(struct hc_status_block_data_e1x, index_data) +
  3942. sizeof(struct hc_index_data)*sb_index +
  3943. offsetof(struct hc_index_data, flags);
  3944. u16 flags = CNIC_RD16(dev, addr);
  3945. /* clear and set */
  3946. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3947. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3948. HC_INDEX_DATA_HC_ENABLED);
  3949. CNIC_WR16(dev, addr, flags);
  3950. }
  3951. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3952. {
  3953. struct cnic_local *cp = dev->cnic_priv;
  3954. u8 sb_id = cp->status_blk_num;
  3955. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3956. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3957. offsetof(struct hc_status_block_data_e1x, index_data) +
  3958. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3959. offsetof(struct hc_index_data, timeout), 64 / 4);
  3960. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3961. }
  3962. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3963. {
  3964. }
  3965. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3966. struct client_init_ramrod_data *data)
  3967. {
  3968. struct cnic_local *cp = dev->cnic_priv;
  3969. struct cnic_uio_dev *udev = cp->udev;
  3970. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3971. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3972. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3973. int i;
  3974. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3975. u32 val;
  3976. memset(txbd, 0, BCM_PAGE_SIZE);
  3977. buf_map = udev->l2_buf_map;
  3978. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3979. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3980. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3981. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3982. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3983. reg_bd->addr_hi = start_bd->addr_hi;
  3984. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3985. start_bd->nbytes = cpu_to_le16(0x10);
  3986. start_bd->nbd = cpu_to_le16(3);
  3987. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3988. start_bd->general_data = (UNICAST_ADDRESS <<
  3989. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3990. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3991. }
  3992. val = (u64) ring_map >> 32;
  3993. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3994. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3995. val = (u64) ring_map & 0xffffffff;
  3996. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3997. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3998. /* Other ramrod params */
  3999. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4000. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4001. /* reset xstorm per client statistics */
  4002. if (cli < MAX_STAT_COUNTER_ID) {
  4003. data->general.statistics_zero_flg = 1;
  4004. data->general.statistics_en_flg = 1;
  4005. data->general.statistics_counter_id = cli;
  4006. }
  4007. cp->tx_cons_ptr =
  4008. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4009. }
  4010. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4011. struct client_init_ramrod_data *data)
  4012. {
  4013. struct cnic_local *cp = dev->cnic_priv;
  4014. struct cnic_uio_dev *udev = cp->udev;
  4015. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4016. BCM_PAGE_SIZE);
  4017. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4018. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4019. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4020. int i;
  4021. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4022. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4023. u32 val;
  4024. dma_addr_t ring_map = udev->l2_ring_map;
  4025. /* General data */
  4026. data->general.client_id = cli;
  4027. data->general.activate_flg = 1;
  4028. data->general.sp_client_id = cli;
  4029. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4030. data->general.func_id = cp->pfid;
  4031. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4032. dma_addr_t buf_map;
  4033. int n = (i % cp->l2_rx_ring_size) + 1;
  4034. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4035. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4036. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4037. }
  4038. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4039. rxbd->addr_hi = cpu_to_le32(val);
  4040. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4041. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4042. rxbd->addr_lo = cpu_to_le32(val);
  4043. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4044. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4045. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4046. rxcqe->addr_hi = cpu_to_le32(val);
  4047. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4048. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4049. rxcqe->addr_lo = cpu_to_le32(val);
  4050. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4051. /* Other ramrod params */
  4052. data->rx.client_qzone_id = cl_qzone_id;
  4053. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4054. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4055. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4056. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4057. data->rx.outer_vlan_removal_enable_flg = 1;
  4058. data->rx.silent_vlan_removal_flg = 1;
  4059. data->rx.silent_vlan_value = 0;
  4060. data->rx.silent_vlan_mask = 0xffff;
  4061. cp->rx_cons_ptr =
  4062. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4063. cp->rx_cons = *cp->rx_cons_ptr;
  4064. }
  4065. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4066. {
  4067. struct cnic_local *cp = dev->cnic_priv;
  4068. u32 pfid = cp->pfid;
  4069. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4070. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4071. cp->kcq1.sw_prod_idx = 0;
  4072. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4073. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4074. cp->kcq1.hw_prod_idx_ptr =
  4075. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4076. cp->kcq1.status_idx_ptr =
  4077. &sb->sb.running_index[SM_RX_ID];
  4078. } else {
  4079. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4080. cp->kcq1.hw_prod_idx_ptr =
  4081. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4082. cp->kcq1.status_idx_ptr =
  4083. &sb->sb.running_index[SM_RX_ID];
  4084. }
  4085. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4086. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4087. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4088. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4089. cp->kcq2.sw_prod_idx = 0;
  4090. cp->kcq2.hw_prod_idx_ptr =
  4091. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4092. cp->kcq2.status_idx_ptr =
  4093. &sb->sb.running_index[SM_RX_ID];
  4094. }
  4095. }
  4096. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4097. {
  4098. struct cnic_local *cp = dev->cnic_priv;
  4099. struct cnic_eth_dev *ethdev = cp->ethdev;
  4100. int func = CNIC_FUNC(cp), ret;
  4101. u32 pfid;
  4102. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4103. cp->port_mode = CHIP_PORT_MODE_NONE;
  4104. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4105. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4106. if (!(val & 1))
  4107. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4108. else
  4109. val = (val >> 1) & 1;
  4110. if (val) {
  4111. cp->port_mode = CHIP_4_PORT_MODE;
  4112. cp->pfid = func >> 1;
  4113. } else {
  4114. cp->port_mode = CHIP_2_PORT_MODE;
  4115. cp->pfid = func & 0x6;
  4116. }
  4117. } else {
  4118. cp->pfid = func;
  4119. }
  4120. pfid = cp->pfid;
  4121. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4122. cp->iscsi_start_cid, 0);
  4123. if (ret)
  4124. return -ENOMEM;
  4125. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4126. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4127. cp->fcoe_start_cid, 0);
  4128. if (ret)
  4129. return -ENOMEM;
  4130. }
  4131. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4132. cnic_init_bnx2x_kcq(dev);
  4133. /* Only 1 EQ */
  4134. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4135. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4136. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4137. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4138. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4139. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4140. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4141. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4142. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4143. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4144. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4145. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4146. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4147. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4148. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4149. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4150. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4151. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4152. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4153. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4154. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4155. HC_INDEX_ISCSI_EQ_CONS);
  4156. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4157. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4158. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4159. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4160. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4161. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4162. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4163. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4164. cnic_setup_bnx2x_context(dev);
  4165. ret = cnic_init_bnx2x_irq(dev);
  4166. if (ret)
  4167. return ret;
  4168. return 0;
  4169. }
  4170. static void cnic_init_rings(struct cnic_dev *dev)
  4171. {
  4172. struct cnic_local *cp = dev->cnic_priv;
  4173. struct cnic_uio_dev *udev = cp->udev;
  4174. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4175. return;
  4176. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4177. cnic_init_bnx2_tx_ring(dev);
  4178. cnic_init_bnx2_rx_ring(dev);
  4179. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4180. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4181. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4182. u32 cid = cp->ethdev->iscsi_l2_cid;
  4183. u32 cl_qzone_id;
  4184. struct client_init_ramrod_data *data;
  4185. union l5cm_specific_data l5_data;
  4186. struct ustorm_eth_rx_producers rx_prods = {0};
  4187. u32 off, i, *cid_ptr;
  4188. rx_prods.bd_prod = 0;
  4189. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4190. barrier();
  4191. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4192. off = BAR_USTRORM_INTMEM +
  4193. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4194. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4195. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4196. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4197. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4198. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4199. data = udev->l2_buf;
  4200. cid_ptr = udev->l2_buf + 12;
  4201. memset(data, 0, sizeof(*data));
  4202. cnic_init_bnx2x_tx_ring(dev, data);
  4203. cnic_init_bnx2x_rx_ring(dev, data);
  4204. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4205. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4206. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4207. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4208. cid, ETH_CONNECTION_TYPE, &l5_data);
  4209. i = 0;
  4210. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4211. ++i < 10)
  4212. msleep(1);
  4213. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4214. netdev_err(dev->netdev,
  4215. "iSCSI CLIENT_SETUP did not complete\n");
  4216. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4217. cnic_ring_ctl(dev, cid, cli, 1);
  4218. *cid_ptr = cid;
  4219. }
  4220. }
  4221. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4222. {
  4223. struct cnic_local *cp = dev->cnic_priv;
  4224. struct cnic_uio_dev *udev = cp->udev;
  4225. void *rx_ring;
  4226. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4227. return;
  4228. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4229. cnic_shutdown_bnx2_rx_ring(dev);
  4230. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4231. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4232. u32 cid = cp->ethdev->iscsi_l2_cid;
  4233. union l5cm_specific_data l5_data;
  4234. int i;
  4235. cnic_ring_ctl(dev, cid, cli, 0);
  4236. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4237. l5_data.phy_address.lo = cli;
  4238. l5_data.phy_address.hi = 0;
  4239. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4240. cid, ETH_CONNECTION_TYPE, &l5_data);
  4241. i = 0;
  4242. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4243. ++i < 10)
  4244. msleep(1);
  4245. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4246. netdev_err(dev->netdev,
  4247. "iSCSI CLIENT_HALT did not complete\n");
  4248. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4249. memset(&l5_data, 0, sizeof(l5_data));
  4250. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4251. cid, NONE_CONNECTION_TYPE, &l5_data);
  4252. msleep(10);
  4253. }
  4254. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4255. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4256. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4257. }
  4258. static int cnic_register_netdev(struct cnic_dev *dev)
  4259. {
  4260. struct cnic_local *cp = dev->cnic_priv;
  4261. struct cnic_eth_dev *ethdev = cp->ethdev;
  4262. int err;
  4263. if (!ethdev)
  4264. return -ENODEV;
  4265. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4266. return 0;
  4267. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4268. if (err)
  4269. netdev_err(dev->netdev, "register_cnic failed\n");
  4270. return err;
  4271. }
  4272. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4273. {
  4274. struct cnic_local *cp = dev->cnic_priv;
  4275. struct cnic_eth_dev *ethdev = cp->ethdev;
  4276. if (!ethdev)
  4277. return;
  4278. ethdev->drv_unregister_cnic(dev->netdev);
  4279. }
  4280. static int cnic_start_hw(struct cnic_dev *dev)
  4281. {
  4282. struct cnic_local *cp = dev->cnic_priv;
  4283. struct cnic_eth_dev *ethdev = cp->ethdev;
  4284. int err;
  4285. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4286. return -EALREADY;
  4287. dev->regview = ethdev->io_base;
  4288. pci_dev_get(dev->pcidev);
  4289. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4290. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4291. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4292. err = cp->alloc_resc(dev);
  4293. if (err) {
  4294. netdev_err(dev->netdev, "allocate resource failure\n");
  4295. goto err1;
  4296. }
  4297. err = cp->start_hw(dev);
  4298. if (err)
  4299. goto err1;
  4300. err = cnic_cm_open(dev);
  4301. if (err)
  4302. goto err1;
  4303. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4304. cp->enable_int(dev);
  4305. return 0;
  4306. err1:
  4307. cp->free_resc(dev);
  4308. pci_dev_put(dev->pcidev);
  4309. return err;
  4310. }
  4311. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4312. {
  4313. cnic_disable_bnx2_int_sync(dev);
  4314. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4315. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4316. cnic_init_context(dev, KWQ_CID);
  4317. cnic_init_context(dev, KCQ_CID);
  4318. cnic_setup_5709_context(dev, 0);
  4319. cnic_free_irq(dev);
  4320. cnic_free_resc(dev);
  4321. }
  4322. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4323. {
  4324. struct cnic_local *cp = dev->cnic_priv;
  4325. cnic_free_irq(dev);
  4326. *cp->kcq1.hw_prod_idx_ptr = 0;
  4327. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4328. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4329. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4330. cnic_free_resc(dev);
  4331. }
  4332. static void cnic_stop_hw(struct cnic_dev *dev)
  4333. {
  4334. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4335. struct cnic_local *cp = dev->cnic_priv;
  4336. int i = 0;
  4337. /* Need to wait for the ring shutdown event to complete
  4338. * before clearing the CNIC_UP flag.
  4339. */
  4340. while (cp->udev->uio_dev != -1 && i < 15) {
  4341. msleep(100);
  4342. i++;
  4343. }
  4344. cnic_shutdown_rings(dev);
  4345. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4346. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4347. synchronize_rcu();
  4348. cnic_cm_shutdown(dev);
  4349. cp->stop_hw(dev);
  4350. pci_dev_put(dev->pcidev);
  4351. }
  4352. }
  4353. static void cnic_free_dev(struct cnic_dev *dev)
  4354. {
  4355. int i = 0;
  4356. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4357. msleep(100);
  4358. i++;
  4359. }
  4360. if (atomic_read(&dev->ref_count) != 0)
  4361. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4362. netdev_info(dev->netdev, "Removed CNIC device\n");
  4363. dev_put(dev->netdev);
  4364. kfree(dev);
  4365. }
  4366. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4367. struct pci_dev *pdev)
  4368. {
  4369. struct cnic_dev *cdev;
  4370. struct cnic_local *cp;
  4371. int alloc_size;
  4372. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4373. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4374. if (cdev == NULL) {
  4375. netdev_err(dev, "allocate dev struct failure\n");
  4376. return NULL;
  4377. }
  4378. cdev->netdev = dev;
  4379. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4380. cdev->register_device = cnic_register_device;
  4381. cdev->unregister_device = cnic_unregister_device;
  4382. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4383. cp = cdev->cnic_priv;
  4384. cp->dev = cdev;
  4385. cp->l2_single_buf_size = 0x400;
  4386. cp->l2_rx_ring_size = 3;
  4387. spin_lock_init(&cp->cnic_ulp_lock);
  4388. netdev_info(dev, "Added CNIC device\n");
  4389. return cdev;
  4390. }
  4391. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4392. {
  4393. struct pci_dev *pdev;
  4394. struct cnic_dev *cdev;
  4395. struct cnic_local *cp;
  4396. struct cnic_eth_dev *ethdev = NULL;
  4397. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4398. probe = symbol_get(bnx2_cnic_probe);
  4399. if (probe) {
  4400. ethdev = (*probe)(dev);
  4401. symbol_put(bnx2_cnic_probe);
  4402. }
  4403. if (!ethdev)
  4404. return NULL;
  4405. pdev = ethdev->pdev;
  4406. if (!pdev)
  4407. return NULL;
  4408. dev_hold(dev);
  4409. pci_dev_get(pdev);
  4410. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4411. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4412. (pdev->revision < 0x10)) {
  4413. pci_dev_put(pdev);
  4414. goto cnic_err;
  4415. }
  4416. pci_dev_put(pdev);
  4417. cdev = cnic_alloc_dev(dev, pdev);
  4418. if (cdev == NULL)
  4419. goto cnic_err;
  4420. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4421. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4422. cp = cdev->cnic_priv;
  4423. cp->ethdev = ethdev;
  4424. cdev->pcidev = pdev;
  4425. cp->chip_id = ethdev->chip_id;
  4426. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4427. cp->cnic_ops = &cnic_bnx2_ops;
  4428. cp->start_hw = cnic_start_bnx2_hw;
  4429. cp->stop_hw = cnic_stop_bnx2_hw;
  4430. cp->setup_pgtbl = cnic_setup_page_tbl;
  4431. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4432. cp->free_resc = cnic_free_resc;
  4433. cp->start_cm = cnic_cm_init_bnx2_hw;
  4434. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4435. cp->enable_int = cnic_enable_bnx2_int;
  4436. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4437. cp->close_conn = cnic_close_bnx2_conn;
  4438. return cdev;
  4439. cnic_err:
  4440. dev_put(dev);
  4441. return NULL;
  4442. }
  4443. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4444. {
  4445. struct pci_dev *pdev;
  4446. struct cnic_dev *cdev;
  4447. struct cnic_local *cp;
  4448. struct cnic_eth_dev *ethdev = NULL;
  4449. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4450. probe = symbol_get(bnx2x_cnic_probe);
  4451. if (probe) {
  4452. ethdev = (*probe)(dev);
  4453. symbol_put(bnx2x_cnic_probe);
  4454. }
  4455. if (!ethdev)
  4456. return NULL;
  4457. pdev = ethdev->pdev;
  4458. if (!pdev)
  4459. return NULL;
  4460. dev_hold(dev);
  4461. cdev = cnic_alloc_dev(dev, pdev);
  4462. if (cdev == NULL) {
  4463. dev_put(dev);
  4464. return NULL;
  4465. }
  4466. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4467. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4468. cp = cdev->cnic_priv;
  4469. cp->ethdev = ethdev;
  4470. cdev->pcidev = pdev;
  4471. cp->chip_id = ethdev->chip_id;
  4472. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4473. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4474. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4475. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4476. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4477. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4478. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4479. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4480. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4481. cp->cnic_ops = &cnic_bnx2x_ops;
  4482. cp->start_hw = cnic_start_bnx2x_hw;
  4483. cp->stop_hw = cnic_stop_bnx2x_hw;
  4484. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4485. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4486. cp->free_resc = cnic_free_resc;
  4487. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4488. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4489. cp->enable_int = cnic_enable_bnx2x_int;
  4490. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4491. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4492. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4493. else
  4494. cp->ack_int = cnic_ack_bnx2x_msix;
  4495. cp->close_conn = cnic_close_bnx2x_conn;
  4496. return cdev;
  4497. }
  4498. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4499. {
  4500. struct ethtool_drvinfo drvinfo;
  4501. struct cnic_dev *cdev = NULL;
  4502. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4503. memset(&drvinfo, 0, sizeof(drvinfo));
  4504. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4505. if (!strcmp(drvinfo.driver, "bnx2"))
  4506. cdev = init_bnx2_cnic(dev);
  4507. if (!strcmp(drvinfo.driver, "bnx2x"))
  4508. cdev = init_bnx2x_cnic(dev);
  4509. if (cdev) {
  4510. write_lock(&cnic_dev_lock);
  4511. list_add(&cdev->list, &cnic_dev_list);
  4512. write_unlock(&cnic_dev_lock);
  4513. }
  4514. }
  4515. return cdev;
  4516. }
  4517. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4518. u16 vlan_id)
  4519. {
  4520. int if_type;
  4521. rcu_read_lock();
  4522. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4523. struct cnic_ulp_ops *ulp_ops;
  4524. void *ctx;
  4525. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4526. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4527. continue;
  4528. ctx = cp->ulp_handle[if_type];
  4529. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4530. }
  4531. rcu_read_unlock();
  4532. }
  4533. /**
  4534. * netdev event handler
  4535. */
  4536. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4537. void *ptr)
  4538. {
  4539. struct net_device *netdev = ptr;
  4540. struct cnic_dev *dev;
  4541. int new_dev = 0;
  4542. dev = cnic_from_netdev(netdev);
  4543. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4544. /* Check for the hot-plug device */
  4545. dev = is_cnic_dev(netdev);
  4546. if (dev) {
  4547. new_dev = 1;
  4548. cnic_hold(dev);
  4549. }
  4550. }
  4551. if (dev) {
  4552. struct cnic_local *cp = dev->cnic_priv;
  4553. if (new_dev)
  4554. cnic_ulp_init(dev);
  4555. else if (event == NETDEV_UNREGISTER)
  4556. cnic_ulp_exit(dev);
  4557. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4558. if (cnic_register_netdev(dev) != 0) {
  4559. cnic_put(dev);
  4560. goto done;
  4561. }
  4562. if (!cnic_start_hw(dev))
  4563. cnic_ulp_start(dev);
  4564. }
  4565. cnic_rcv_netevent(cp, event, 0);
  4566. if (event == NETDEV_GOING_DOWN) {
  4567. cnic_ulp_stop(dev);
  4568. cnic_stop_hw(dev);
  4569. cnic_unregister_netdev(dev);
  4570. } else if (event == NETDEV_UNREGISTER) {
  4571. write_lock(&cnic_dev_lock);
  4572. list_del_init(&dev->list);
  4573. write_unlock(&cnic_dev_lock);
  4574. cnic_put(dev);
  4575. cnic_free_dev(dev);
  4576. goto done;
  4577. }
  4578. cnic_put(dev);
  4579. } else {
  4580. struct net_device *realdev;
  4581. u16 vid;
  4582. vid = cnic_get_vlan(netdev, &realdev);
  4583. if (realdev) {
  4584. dev = cnic_from_netdev(realdev);
  4585. if (dev) {
  4586. vid |= VLAN_TAG_PRESENT;
  4587. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4588. cnic_put(dev);
  4589. }
  4590. }
  4591. }
  4592. done:
  4593. return NOTIFY_DONE;
  4594. }
  4595. static struct notifier_block cnic_netdev_notifier = {
  4596. .notifier_call = cnic_netdev_event
  4597. };
  4598. static void cnic_release(void)
  4599. {
  4600. struct cnic_dev *dev;
  4601. struct cnic_uio_dev *udev;
  4602. while (!list_empty(&cnic_dev_list)) {
  4603. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4604. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4605. cnic_ulp_stop(dev);
  4606. cnic_stop_hw(dev);
  4607. }
  4608. cnic_ulp_exit(dev);
  4609. cnic_unregister_netdev(dev);
  4610. list_del_init(&dev->list);
  4611. cnic_free_dev(dev);
  4612. }
  4613. while (!list_empty(&cnic_udev_list)) {
  4614. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4615. list);
  4616. cnic_free_uio(udev);
  4617. }
  4618. }
  4619. static int __init cnic_init(void)
  4620. {
  4621. int rc = 0;
  4622. pr_info("%s", version);
  4623. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4624. if (rc) {
  4625. cnic_release();
  4626. return rc;
  4627. }
  4628. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4629. if (!cnic_wq) {
  4630. cnic_release();
  4631. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4632. return -ENOMEM;
  4633. }
  4634. return 0;
  4635. }
  4636. static void __exit cnic_exit(void)
  4637. {
  4638. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4639. cnic_release();
  4640. destroy_workqueue(cnic_wq);
  4641. }
  4642. module_init(cnic_init);
  4643. module_exit(cnic_exit);