twl4030.c 17 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x93, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x24, /* REG_ANAMICL (0x5) */
  47. 0x04, /* REG_ANAMICR (0x6) */
  48. 0x0a, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /*
  117. * read twl4030 register cache
  118. */
  119. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  120. unsigned int reg)
  121. {
  122. u8 *cache = codec->reg_cache;
  123. return cache[reg];
  124. }
  125. /*
  126. * write twl4030 register cache
  127. */
  128. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  129. u8 reg, u8 value)
  130. {
  131. u8 *cache = codec->reg_cache;
  132. if (reg >= TWL4030_CACHEREGNUM)
  133. return;
  134. cache[reg] = value;
  135. }
  136. /*
  137. * write to the twl4030 register space
  138. */
  139. static int twl4030_write(struct snd_soc_codec *codec,
  140. unsigned int reg, unsigned int value)
  141. {
  142. twl4030_write_reg_cache(codec, reg, value);
  143. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  144. }
  145. static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
  146. {
  147. u8 mode;
  148. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  149. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  150. mode & ~TWL4030_CODECPDZ);
  151. /* REVISIT: this delay is present in TI sample drivers */
  152. /* but there seems to be no TRM requirement for it */
  153. udelay(10);
  154. }
  155. static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
  156. {
  157. u8 mode;
  158. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  159. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  160. mode | TWL4030_CODECPDZ);
  161. /* REVISIT: this delay is present in TI sample drivers */
  162. /* but there seems to be no TRM requirement for it */
  163. udelay(10);
  164. }
  165. static void twl4030_init_chip(struct snd_soc_codec *codec)
  166. {
  167. int i;
  168. /* clear CODECPDZ prior to setting register defaults */
  169. twl4030_clear_codecpdz(codec);
  170. /* set all audio section registers to reasonable defaults */
  171. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  172. twl4030_write(codec, i, twl4030_reg[i]);
  173. }
  174. /*
  175. * FGAIN volume control:
  176. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  177. */
  178. static DECLARE_TLV_DB_SCALE(master_tlv, -6300, 100, 1);
  179. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  180. SOC_DOUBLE_R_TLV("Master Playback Volume",
  181. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  182. 0, 0x3f, 0, master_tlv),
  183. SOC_DOUBLE_R("Capture Volume",
  184. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  185. 0, 0x1f, 0),
  186. };
  187. /* add non dapm controls */
  188. static int twl4030_add_controls(struct snd_soc_codec *codec)
  189. {
  190. int err, i;
  191. for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
  192. err = snd_ctl_add(codec->card,
  193. snd_soc_cnew(&twl4030_snd_controls[i],
  194. codec, NULL));
  195. if (err < 0)
  196. return err;
  197. }
  198. return 0;
  199. }
  200. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  201. SND_SOC_DAPM_INPUT("INL"),
  202. SND_SOC_DAPM_INPUT("INR"),
  203. SND_SOC_DAPM_OUTPUT("OUTL"),
  204. SND_SOC_DAPM_OUTPUT("OUTR"),
  205. SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
  206. SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
  207. SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
  208. SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
  209. };
  210. static const struct snd_soc_dapm_route intercon[] = {
  211. /* outputs */
  212. {"OUTL", NULL, "DACL"},
  213. {"OUTR", NULL, "DACR"},
  214. /* inputs */
  215. {"ADCL", NULL, "INL"},
  216. {"ADCR", NULL, "INR"},
  217. };
  218. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  219. {
  220. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  221. ARRAY_SIZE(twl4030_dapm_widgets));
  222. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  223. snd_soc_dapm_new_widgets(codec);
  224. return 0;
  225. }
  226. static void twl4030_power_up(struct snd_soc_codec *codec)
  227. {
  228. u8 anamicl, regmisc1, byte, popn, hsgain;
  229. int i = 0;
  230. /* set CODECPDZ to turn on codec */
  231. twl4030_set_codecpdz(codec);
  232. /* initiate offset cancellation */
  233. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  234. twl4030_write(codec, TWL4030_REG_ANAMICL,
  235. anamicl | TWL4030_CNCL_OFFSET_START);
  236. /* wait for offset cancellation to complete */
  237. do {
  238. /* this takes a little while, so don't slam i2c */
  239. udelay(2000);
  240. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  241. TWL4030_REG_ANAMICL);
  242. } while ((i++ < 100) &&
  243. ((byte & TWL4030_CNCL_OFFSET_START) ==
  244. TWL4030_CNCL_OFFSET_START));
  245. /* anti-pop when changing analog gain */
  246. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  247. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  248. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  249. /* toggle CODECPDZ as per TRM */
  250. twl4030_clear_codecpdz(codec);
  251. twl4030_set_codecpdz(codec);
  252. /* program anti-pop with bias ramp delay */
  253. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  254. popn &= TWL4030_RAMP_DELAY;
  255. popn |= TWL4030_RAMP_DELAY_645MS;
  256. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  257. popn |= TWL4030_VMID_EN;
  258. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  259. /* enable output stage and gain setting */
  260. hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
  261. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
  262. /* enable anti-pop ramp */
  263. popn |= TWL4030_RAMP_EN;
  264. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  265. }
  266. static void twl4030_power_down(struct snd_soc_codec *codec)
  267. {
  268. u8 popn, hsgain;
  269. /* disable anti-pop ramp */
  270. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  271. popn &= ~TWL4030_RAMP_EN;
  272. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  273. /* disable output stage and gain setting */
  274. hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
  275. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
  276. /* disable bias out */
  277. popn &= ~TWL4030_VMID_EN;
  278. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  279. /* power down */
  280. twl4030_clear_codecpdz(codec);
  281. }
  282. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  283. enum snd_soc_bias_level level)
  284. {
  285. switch (level) {
  286. case SND_SOC_BIAS_ON:
  287. twl4030_power_up(codec);
  288. break;
  289. case SND_SOC_BIAS_PREPARE:
  290. /* TODO: develop a twl4030_prepare function */
  291. break;
  292. case SND_SOC_BIAS_STANDBY:
  293. /* TODO: develop a twl4030_standby function */
  294. twl4030_power_down(codec);
  295. break;
  296. case SND_SOC_BIAS_OFF:
  297. twl4030_power_down(codec);
  298. break;
  299. }
  300. codec->bias_level = level;
  301. return 0;
  302. }
  303. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  304. struct snd_pcm_hw_params *params,
  305. struct snd_soc_dai *dai)
  306. {
  307. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  308. struct snd_soc_device *socdev = rtd->socdev;
  309. struct snd_soc_codec *codec = socdev->codec;
  310. u8 mode, old_mode, format, old_format;
  311. /* bit rate */
  312. old_mode = twl4030_read_reg_cache(codec,
  313. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  314. mode = old_mode & ~TWL4030_APLL_RATE;
  315. switch (params_rate(params)) {
  316. case 8000:
  317. mode |= TWL4030_APLL_RATE_8000;
  318. break;
  319. case 11025:
  320. mode |= TWL4030_APLL_RATE_11025;
  321. break;
  322. case 12000:
  323. mode |= TWL4030_APLL_RATE_12000;
  324. break;
  325. case 16000:
  326. mode |= TWL4030_APLL_RATE_16000;
  327. break;
  328. case 22050:
  329. mode |= TWL4030_APLL_RATE_22050;
  330. break;
  331. case 24000:
  332. mode |= TWL4030_APLL_RATE_24000;
  333. break;
  334. case 32000:
  335. mode |= TWL4030_APLL_RATE_32000;
  336. break;
  337. case 44100:
  338. mode |= TWL4030_APLL_RATE_44100;
  339. break;
  340. case 48000:
  341. mode |= TWL4030_APLL_RATE_48000;
  342. break;
  343. default:
  344. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  345. params_rate(params));
  346. return -EINVAL;
  347. }
  348. if (mode != old_mode) {
  349. /* change rate and set CODECPDZ */
  350. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  351. twl4030_set_codecpdz(codec);
  352. }
  353. /* sample size */
  354. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  355. format = old_format;
  356. format &= ~TWL4030_DATA_WIDTH;
  357. switch (params_format(params)) {
  358. case SNDRV_PCM_FORMAT_S16_LE:
  359. format |= TWL4030_DATA_WIDTH_16S_16W;
  360. break;
  361. case SNDRV_PCM_FORMAT_S24_LE:
  362. format |= TWL4030_DATA_WIDTH_32S_24W;
  363. break;
  364. default:
  365. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  366. params_format(params));
  367. return -EINVAL;
  368. }
  369. if (format != old_format) {
  370. /* clear CODECPDZ before changing format (codec requirement) */
  371. twl4030_clear_codecpdz(codec);
  372. /* change format */
  373. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  374. /* set CODECPDZ afterwards */
  375. twl4030_set_codecpdz(codec);
  376. }
  377. return 0;
  378. }
  379. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  380. int clk_id, unsigned int freq, int dir)
  381. {
  382. struct snd_soc_codec *codec = codec_dai->codec;
  383. u8 infreq;
  384. switch (freq) {
  385. case 19200000:
  386. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  387. break;
  388. case 26000000:
  389. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  390. break;
  391. case 38400000:
  392. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  393. break;
  394. default:
  395. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  396. freq);
  397. return -EINVAL;
  398. }
  399. infreq |= TWL4030_APLL_EN;
  400. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  401. return 0;
  402. }
  403. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  404. unsigned int fmt)
  405. {
  406. struct snd_soc_codec *codec = codec_dai->codec;
  407. u8 old_format, format;
  408. /* get format */
  409. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  410. format = old_format;
  411. /* set master/slave audio interface */
  412. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  413. case SND_SOC_DAIFMT_CBM_CFM:
  414. format &= ~(TWL4030_AIF_SLAVE_EN);
  415. format &= ~(TWL4030_CLK256FS_EN);
  416. break;
  417. case SND_SOC_DAIFMT_CBS_CFS:
  418. format |= TWL4030_AIF_SLAVE_EN;
  419. format |= TWL4030_CLK256FS_EN;
  420. break;
  421. default:
  422. return -EINVAL;
  423. }
  424. /* interface format */
  425. format &= ~TWL4030_AIF_FORMAT;
  426. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  427. case SND_SOC_DAIFMT_I2S:
  428. format |= TWL4030_AIF_FORMAT_CODEC;
  429. break;
  430. default:
  431. return -EINVAL;
  432. }
  433. if (format != old_format) {
  434. /* clear CODECPDZ before changing format (codec requirement) */
  435. twl4030_clear_codecpdz(codec);
  436. /* change format */
  437. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  438. /* set CODECPDZ afterwards */
  439. twl4030_set_codecpdz(codec);
  440. }
  441. return 0;
  442. }
  443. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  444. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  445. struct snd_soc_dai twl4030_dai = {
  446. .name = "twl4030",
  447. .playback = {
  448. .stream_name = "Playback",
  449. .channels_min = 2,
  450. .channels_max = 2,
  451. .rates = TWL4030_RATES,
  452. .formats = TWL4030_FORMATS,},
  453. .capture = {
  454. .stream_name = "Capture",
  455. .channels_min = 2,
  456. .channels_max = 2,
  457. .rates = TWL4030_RATES,
  458. .formats = TWL4030_FORMATS,},
  459. .ops = {
  460. .hw_params = twl4030_hw_params,
  461. .set_sysclk = twl4030_set_dai_sysclk,
  462. .set_fmt = twl4030_set_dai_fmt,
  463. }
  464. };
  465. EXPORT_SYMBOL_GPL(twl4030_dai);
  466. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  467. {
  468. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  469. struct snd_soc_codec *codec = socdev->codec;
  470. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  471. return 0;
  472. }
  473. static int twl4030_resume(struct platform_device *pdev)
  474. {
  475. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  476. struct snd_soc_codec *codec = socdev->codec;
  477. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  478. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  479. return 0;
  480. }
  481. /*
  482. * initialize the driver
  483. * register the mixer and dsp interfaces with the kernel
  484. */
  485. static int twl4030_init(struct snd_soc_device *socdev)
  486. {
  487. struct snd_soc_codec *codec = socdev->codec;
  488. int ret = 0;
  489. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  490. codec->name = "twl4030";
  491. codec->owner = THIS_MODULE;
  492. codec->read = twl4030_read_reg_cache;
  493. codec->write = twl4030_write;
  494. codec->set_bias_level = twl4030_set_bias_level;
  495. codec->dai = &twl4030_dai;
  496. codec->num_dai = 1;
  497. codec->reg_cache_size = sizeof(twl4030_reg);
  498. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  499. GFP_KERNEL);
  500. if (codec->reg_cache == NULL)
  501. return -ENOMEM;
  502. /* register pcms */
  503. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  504. if (ret < 0) {
  505. printk(KERN_ERR "twl4030: failed to create pcms\n");
  506. goto pcm_err;
  507. }
  508. twl4030_init_chip(codec);
  509. /* power on device */
  510. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  511. twl4030_add_controls(codec);
  512. twl4030_add_widgets(codec);
  513. ret = snd_soc_register_card(socdev);
  514. if (ret < 0) {
  515. printk(KERN_ERR "twl4030: failed to register card\n");
  516. goto card_err;
  517. }
  518. return ret;
  519. card_err:
  520. snd_soc_free_pcms(socdev);
  521. snd_soc_dapm_free(socdev);
  522. pcm_err:
  523. kfree(codec->reg_cache);
  524. return ret;
  525. }
  526. static struct snd_soc_device *twl4030_socdev;
  527. static int twl4030_probe(struct platform_device *pdev)
  528. {
  529. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  530. struct snd_soc_codec *codec;
  531. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  532. if (codec == NULL)
  533. return -ENOMEM;
  534. socdev->codec = codec;
  535. mutex_init(&codec->mutex);
  536. INIT_LIST_HEAD(&codec->dapm_widgets);
  537. INIT_LIST_HEAD(&codec->dapm_paths);
  538. twl4030_socdev = socdev;
  539. twl4030_init(socdev);
  540. return 0;
  541. }
  542. static int twl4030_remove(struct platform_device *pdev)
  543. {
  544. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  545. struct snd_soc_codec *codec = socdev->codec;
  546. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  547. kfree(codec);
  548. return 0;
  549. }
  550. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  551. .probe = twl4030_probe,
  552. .remove = twl4030_remove,
  553. .suspend = twl4030_suspend,
  554. .resume = twl4030_resume,
  555. };
  556. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  557. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  558. MODULE_AUTHOR("Steve Sakoman");
  559. MODULE_LICENSE("GPL");