dhd_sdio.c 108 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/kthread.h>
  19. #include <linux/printk.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/mmc/sdio.h>
  25. #include <linux/mmc/sdio_func.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/firmware.h>
  29. #include <linux/module.h>
  30. #include <linux/bcma/bcma.h>
  31. #include <asm/unaligned.h>
  32. #include <defs.h>
  33. #include <brcmu_wifi.h>
  34. #include <brcmu_utils.h>
  35. #include <brcm_hw_ids.h>
  36. #include <soc.h>
  37. #include "sdio_host.h"
  38. #include "sdio_chip.h"
  39. #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
  40. #ifdef BCMDBG
  41. #define BRCMF_TRAP_INFO_SIZE 80
  42. #define CBUF_LEN (128)
  43. struct rte_log_le {
  44. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  45. __le32 buf_size;
  46. __le32 idx;
  47. char *_buf_compat; /* Redundant pointer for backward compat. */
  48. };
  49. struct rte_console {
  50. /* Virtual UART
  51. * When there is no UART (e.g. Quickturn),
  52. * the host should write a complete
  53. * input line directly into cbuf and then write
  54. * the length into vcons_in.
  55. * This may also be used when there is a real UART
  56. * (at risk of conflicting with
  57. * the real UART). vcons_out is currently unused.
  58. */
  59. uint vcons_in;
  60. uint vcons_out;
  61. /* Output (logging) buffer
  62. * Console output is written to a ring buffer log_buf at index log_idx.
  63. * The host may read the output when it sees log_idx advance.
  64. * Output will be lost if the output wraps around faster than the host
  65. * polls.
  66. */
  67. struct rte_log_le log_le;
  68. /* Console input line buffer
  69. * Characters are read one at a time into cbuf
  70. * until <CR> is received, then
  71. * the buffer is processed as a command line.
  72. * Also used for virtual UART.
  73. */
  74. uint cbuf_idx;
  75. char cbuf[CBUF_LEN];
  76. };
  77. #endif /* BCMDBG */
  78. #include <chipcommon.h>
  79. #include "dhd_bus.h"
  80. #include "dhd_dbg.h"
  81. #define TXQLEN 2048 /* bulk tx queue length */
  82. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  83. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  84. #define PRIOMASK 7
  85. #define TXRETRIES 2 /* # of retries for tx frames */
  86. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  87. one scheduling */
  88. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  89. one scheduling */
  90. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  91. #define MEMBLOCK 2048 /* Block size used for downloading
  92. of dongle image */
  93. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  94. biggest possible glom */
  95. #define BRCMF_FIRSTREAD (1 << 6)
  96. /* SBSDIO_DEVICE_CTL */
  97. /* 1: device will assert busy signal when receiving CMD53 */
  98. #define SBSDIO_DEVCTL_SETBUSY 0x01
  99. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  100. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  101. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  102. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  103. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  104. * sdio bus power cycle to clear (rev 9) */
  105. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  106. /* Force SD->SB reset mapping (rev 11) */
  107. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  108. /* Determined by CoreControl bit */
  109. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  110. /* Force backplane reset */
  111. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  112. /* Force no backplane reset */
  113. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  114. /* direct(mapped) cis space */
  115. /* MAPPED common CIS address */
  116. #define SBSDIO_CIS_BASE_COMMON 0x1000
  117. /* maximum bytes in one CIS */
  118. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  119. /* cis offset addr is < 17 bits */
  120. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  121. /* manfid tuple length, include tuple, link bytes */
  122. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  123. /* intstatus */
  124. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  125. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  126. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  127. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  128. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  129. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  130. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  131. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  132. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  133. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  134. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  135. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  136. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  137. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  138. #define I_PC (1 << 10) /* descriptor error */
  139. #define I_PD (1 << 11) /* data error */
  140. #define I_DE (1 << 12) /* Descriptor protocol Error */
  141. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  142. #define I_RO (1 << 14) /* Receive fifo Overflow */
  143. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  144. #define I_RI (1 << 16) /* Receive Interrupt */
  145. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  146. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  147. #define I_XI (1 << 24) /* Transmit Interrupt */
  148. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  149. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  150. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  151. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  152. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  153. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  154. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  155. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  156. #define I_DMA (I_RI | I_XI | I_ERRORS)
  157. /* corecontrol */
  158. #define CC_CISRDY (1 << 0) /* CIS Ready */
  159. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  160. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  161. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  162. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  163. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  164. /* SDA_FRAMECTRL */
  165. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  166. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  167. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  168. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  169. /* HW frame tag */
  170. #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
  171. /* Total length of frame header for dongle protocol */
  172. #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
  173. #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
  174. /*
  175. * Software allocation of To SB Mailbox resources
  176. */
  177. /* tosbmailbox bits corresponding to intstatus bits */
  178. #define SMB_NAK (1 << 0) /* Frame NAK */
  179. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  180. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  181. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  182. /* tosbmailboxdata */
  183. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  184. /*
  185. * Software allocation of To Host Mailbox resources
  186. */
  187. /* intstatus bits */
  188. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  189. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  190. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  191. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  192. /* tohostmailboxdata */
  193. #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
  194. #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
  195. #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
  196. #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
  197. #define HMB_DATA_FCDATA_MASK 0xff000000
  198. #define HMB_DATA_FCDATA_SHIFT 24
  199. #define HMB_DATA_VERSION_MASK 0x00ff0000
  200. #define HMB_DATA_VERSION_SHIFT 16
  201. /*
  202. * Software-defined protocol header
  203. */
  204. /* Current protocol version */
  205. #define SDPCM_PROT_VERSION 4
  206. /* SW frame header */
  207. #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
  208. #define SDPCM_CHANNEL_MASK 0x00000f00
  209. #define SDPCM_CHANNEL_SHIFT 8
  210. #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
  211. #define SDPCM_NEXTLEN_OFFSET 2
  212. /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
  213. #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
  214. #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
  215. #define SDPCM_DOFFSET_MASK 0xff000000
  216. #define SDPCM_DOFFSET_SHIFT 24
  217. #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
  218. #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
  219. #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
  220. #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
  221. #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
  222. /* logical channel numbers */
  223. #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
  224. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
  225. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
  226. #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
  227. #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
  228. #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
  229. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  230. /*
  231. * Shared structure between dongle and the host.
  232. * The structure contains pointers to trap or assert information.
  233. */
  234. #define SDPCM_SHARED_VERSION 0x0002
  235. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  236. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  237. #define SDPCM_SHARED_ASSERT 0x0200
  238. #define SDPCM_SHARED_TRAP 0x0400
  239. /* Space for header read, limit for data packets */
  240. #define MAX_HDR_READ (1 << 6)
  241. #define MAX_RX_DATASZ 2048
  242. /* Maximum milliseconds to wait for F2 to come up */
  243. #define BRCMF_WAIT_F2RDY 3000
  244. /* Bump up limit on waiting for HT to account for first startup;
  245. * if the image is doing a CRC calculation before programming the PMU
  246. * for HT availability, it could take a couple hundred ms more, so
  247. * max out at a 1 second (1000000us).
  248. */
  249. #undef PMU_MAX_TRANSITION_DLY
  250. #define PMU_MAX_TRANSITION_DLY 1000000
  251. /* Value for ChipClockCSR during initial setup */
  252. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  253. SBSDIO_ALP_AVAIL_REQ)
  254. /* Flags for SDH calls */
  255. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  256. #define BRCMFMAC_FW_NAME "brcm/brcmfmac.bin"
  257. #define BRCMFMAC_NV_NAME "brcm/brcmfmac.txt"
  258. MODULE_FIRMWARE(BRCMFMAC_FW_NAME);
  259. MODULE_FIRMWARE(BRCMFMAC_NV_NAME);
  260. #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */
  261. #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
  262. * when idle
  263. */
  264. #define BRCMF_IDLE_INTERVAL 1
  265. /*
  266. * Conversion of 802.1D priority to precedence level
  267. */
  268. static uint prio2prec(u32 prio)
  269. {
  270. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  271. (prio^2) : prio;
  272. }
  273. /* core registers */
  274. struct sdpcmd_regs {
  275. u32 corecontrol; /* 0x00, rev8 */
  276. u32 corestatus; /* rev8 */
  277. u32 PAD[1];
  278. u32 biststatus; /* rev8 */
  279. /* PCMCIA access */
  280. u16 pcmciamesportaladdr; /* 0x010, rev8 */
  281. u16 PAD[1];
  282. u16 pcmciamesportalmask; /* rev8 */
  283. u16 PAD[1];
  284. u16 pcmciawrframebc; /* rev8 */
  285. u16 PAD[1];
  286. u16 pcmciaunderflowtimer; /* rev8 */
  287. u16 PAD[1];
  288. /* interrupt */
  289. u32 intstatus; /* 0x020, rev8 */
  290. u32 hostintmask; /* rev8 */
  291. u32 intmask; /* rev8 */
  292. u32 sbintstatus; /* rev8 */
  293. u32 sbintmask; /* rev8 */
  294. u32 funcintmask; /* rev4 */
  295. u32 PAD[2];
  296. u32 tosbmailbox; /* 0x040, rev8 */
  297. u32 tohostmailbox; /* rev8 */
  298. u32 tosbmailboxdata; /* rev8 */
  299. u32 tohostmailboxdata; /* rev8 */
  300. /* synchronized access to registers in SDIO clock domain */
  301. u32 sdioaccess; /* 0x050, rev8 */
  302. u32 PAD[3];
  303. /* PCMCIA frame control */
  304. u8 pcmciaframectrl; /* 0x060, rev8 */
  305. u8 PAD[3];
  306. u8 pcmciawatermark; /* rev8 */
  307. u8 PAD[155];
  308. /* interrupt batching control */
  309. u32 intrcvlazy; /* 0x100, rev8 */
  310. u32 PAD[3];
  311. /* counters */
  312. u32 cmd52rd; /* 0x110, rev8 */
  313. u32 cmd52wr; /* rev8 */
  314. u32 cmd53rd; /* rev8 */
  315. u32 cmd53wr; /* rev8 */
  316. u32 abort; /* rev8 */
  317. u32 datacrcerror; /* rev8 */
  318. u32 rdoutofsync; /* rev8 */
  319. u32 wroutofsync; /* rev8 */
  320. u32 writebusy; /* rev8 */
  321. u32 readwait; /* rev8 */
  322. u32 readterm; /* rev8 */
  323. u32 writeterm; /* rev8 */
  324. u32 PAD[40];
  325. u32 clockctlstatus; /* rev8 */
  326. u32 PAD[7];
  327. u32 PAD[128]; /* DMA engines */
  328. /* SDIO/PCMCIA CIS region */
  329. char cis[512]; /* 0x400-0x5ff, rev6 */
  330. /* PCMCIA function control registers */
  331. char pcmciafcr[256]; /* 0x600-6ff, rev6 */
  332. u16 PAD[55];
  333. /* PCMCIA backplane access */
  334. u16 backplanecsr; /* 0x76E, rev6 */
  335. u16 backplaneaddr0; /* rev6 */
  336. u16 backplaneaddr1; /* rev6 */
  337. u16 backplaneaddr2; /* rev6 */
  338. u16 backplaneaddr3; /* rev6 */
  339. u16 backplanedata0; /* rev6 */
  340. u16 backplanedata1; /* rev6 */
  341. u16 backplanedata2; /* rev6 */
  342. u16 backplanedata3; /* rev6 */
  343. u16 PAD[31];
  344. /* sprom "size" & "blank" info */
  345. u16 spromstatus; /* 0x7BE, rev2 */
  346. u32 PAD[464];
  347. u16 PAD[0x80];
  348. };
  349. #ifdef BCMDBG
  350. /* Device console log buffer state */
  351. struct brcmf_console {
  352. uint count; /* Poll interval msec counter */
  353. uint log_addr; /* Log struct address (fixed) */
  354. struct rte_log_le log_le; /* Log struct (host copy) */
  355. uint bufsize; /* Size of log buffer */
  356. u8 *buf; /* Log buffer (host copy) */
  357. uint last; /* Last buffer read index */
  358. };
  359. #endif /* BCMDBG */
  360. struct sdpcm_shared {
  361. u32 flags;
  362. u32 trap_addr;
  363. u32 assert_exp_addr;
  364. u32 assert_file_addr;
  365. u32 assert_line;
  366. u32 console_addr; /* Address of struct rte_console */
  367. u32 msgtrace_addr;
  368. u8 tag[32];
  369. };
  370. struct sdpcm_shared_le {
  371. __le32 flags;
  372. __le32 trap_addr;
  373. __le32 assert_exp_addr;
  374. __le32 assert_file_addr;
  375. __le32 assert_line;
  376. __le32 console_addr; /* Address of struct rte_console */
  377. __le32 msgtrace_addr;
  378. u8 tag[32];
  379. };
  380. /* misc chip info needed by some of the routines */
  381. /* Private data for SDIO bus interaction */
  382. struct brcmf_sdio {
  383. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  384. struct chip_info *ci; /* Chip info struct */
  385. char *vars; /* Variables (from CIS and/or other) */
  386. uint varsz; /* Size of variables buffer */
  387. u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
  388. u32 hostintmask; /* Copy of Host Interrupt Mask */
  389. u32 intstatus; /* Intstatus bits (events) pending */
  390. bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
  391. bool fcstate; /* State of dongle flow-control */
  392. uint blocksize; /* Block size of SDIO transfers */
  393. uint roundup; /* Max roundup limit */
  394. struct pktq txq; /* Queue length used for flow-control */
  395. u8 flowcontrol; /* per prio flow control bitmask */
  396. u8 tx_seq; /* Transmit sequence number (next) */
  397. u8 tx_max; /* Maximum transmit sequence allowed */
  398. u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
  399. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  400. u16 nextlen; /* Next Read Len from last header */
  401. u8 rx_seq; /* Receive sequence number (expected) */
  402. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  403. uint rxbound; /* Rx frames to read before resched */
  404. uint txbound; /* Tx frames to send before resched */
  405. uint txminmax;
  406. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  407. struct sk_buff_head glom; /* Packet list for glommed superframe */
  408. uint glomerr; /* Glom packet read errors */
  409. u8 *rxbuf; /* Buffer for receiving control packets */
  410. uint rxblen; /* Allocated length of rxbuf */
  411. u8 *rxctl; /* Aligned pointer into rxbuf */
  412. u8 *databuf; /* Buffer for receiving big glom packet */
  413. u8 *dataptr; /* Aligned pointer into databuf */
  414. uint rxlen; /* Length of valid data in buffer */
  415. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  416. bool intr; /* Use interrupts */
  417. bool poll; /* Use polling */
  418. bool ipend; /* Device interrupt is pending */
  419. uint intrcount; /* Count of device interrupt callbacks */
  420. uint lastintrs; /* Count as of last watchdog timer */
  421. uint spurious; /* Count of spurious interrupts */
  422. uint pollrate; /* Ticks between device polls */
  423. uint polltick; /* Tick counter */
  424. uint pollcnt; /* Count of active polls */
  425. #ifdef BCMDBG
  426. uint console_interval;
  427. struct brcmf_console console; /* Console output polling support */
  428. uint console_addr; /* Console address from shared struct */
  429. #endif /* BCMDBG */
  430. uint regfails; /* Count of R_REG failures */
  431. uint clkstate; /* State of sd and backplane clock(s) */
  432. bool activity; /* Activity flag for clock down */
  433. s32 idletime; /* Control for activity timeout */
  434. s32 idlecount; /* Activity timeout counter */
  435. s32 idleclock; /* How to set bus driver when idle */
  436. s32 sd_rxchain;
  437. bool use_rxchain; /* If brcmf should use PKT chains */
  438. bool sleeping; /* Is SDIO bus sleeping? */
  439. bool rxflow_mode; /* Rx flow control mode */
  440. bool rxflow; /* Is rx flow control on */
  441. bool alp_only; /* Don't use HT clock (ALP only) */
  442. /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
  443. bool usebufpool;
  444. /* Some additional counters */
  445. uint tx_sderrs; /* Count of tx attempts with sd errors */
  446. uint fcqueued; /* Tx packets that got queued */
  447. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  448. uint rx_toolong; /* Receive frames too long to receive */
  449. uint rxc_errors; /* SDIO errors when reading control frames */
  450. uint rx_hdrfail; /* SDIO errors on header reads */
  451. uint rx_badhdr; /* Bad received headers (roosync?) */
  452. uint rx_badseq; /* Mismatched rx sequence number */
  453. uint fc_rcvd; /* Number of flow-control events received */
  454. uint fc_xoff; /* Number which turned on flow-control */
  455. uint fc_xon; /* Number which turned off flow-control */
  456. uint rxglomfail; /* Failed deglom attempts */
  457. uint rxglomframes; /* Number of glom frames (superframes) */
  458. uint rxglompkts; /* Number of packets from glom frames */
  459. uint f2rxhdrs; /* Number of header reads */
  460. uint f2rxdata; /* Number of frame data reads */
  461. uint f2txdata; /* Number of f2 frame writes */
  462. uint f1regdata; /* Number of f1 register accesses */
  463. uint tickcnt; /* Number of watchdog been schedule */
  464. unsigned long tx_ctlerrs; /* Err of sending ctrl frames */
  465. unsigned long tx_ctlpkts; /* Ctrl frames sent to dongle */
  466. unsigned long rx_ctlerrs; /* Err of processing rx ctrl frames */
  467. unsigned long rx_ctlpkts; /* Ctrl frames processed from dongle */
  468. unsigned long rx_readahead_cnt; /* Number of packets where header
  469. * read-ahead was used. */
  470. u8 *ctrl_frame_buf;
  471. u32 ctrl_frame_len;
  472. bool ctrl_frame_stat;
  473. spinlock_t txqlock;
  474. wait_queue_head_t ctrl_wait;
  475. wait_queue_head_t dcmd_resp_wait;
  476. struct timer_list timer;
  477. struct completion watchdog_wait;
  478. struct task_struct *watchdog_tsk;
  479. bool wd_timer_valid;
  480. uint save_ms;
  481. struct task_struct *dpc_tsk;
  482. struct completion dpc_wait;
  483. struct semaphore sdsem;
  484. const struct firmware *firmware;
  485. u32 fw_ptr;
  486. bool txoff; /* Transmit flow-controlled */
  487. };
  488. /* clkstate */
  489. #define CLK_NONE 0
  490. #define CLK_SDONLY 1
  491. #define CLK_PENDING 2 /* Not used yet */
  492. #define CLK_AVAIL 3
  493. #ifdef BCMDBG
  494. static int qcount[NUMPRIO];
  495. static int tx_packets[NUMPRIO];
  496. #endif /* BCMDBG */
  497. #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  498. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  499. /* Retry count for register access failures */
  500. static const uint retry_limit = 2;
  501. /* Limit on rounding up frames */
  502. static const uint max_roundup = 512;
  503. #define ALIGNMENT 4
  504. static void pkt_align(struct sk_buff *p, int len, int align)
  505. {
  506. uint datalign;
  507. datalign = (unsigned long)(p->data);
  508. datalign = roundup(datalign, (align)) - datalign;
  509. if (datalign)
  510. skb_pull(p, datalign);
  511. __skb_trim(p, len);
  512. }
  513. /* To check if there's window offered */
  514. static bool data_ok(struct brcmf_sdio *bus)
  515. {
  516. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  517. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  518. }
  519. /*
  520. * Reads a register in the SDIO hardware block. This block occupies a series of
  521. * adresses on the 32 bit backplane bus.
  522. */
  523. static void
  524. r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
  525. {
  526. u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  527. *retryvar = 0;
  528. do {
  529. *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
  530. bus->ci->c_inf[idx].base + reg_offset,
  531. sizeof(u32));
  532. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  533. (++(*retryvar) <= retry_limit));
  534. if (*retryvar) {
  535. bus->regfails += (*retryvar-1);
  536. if (*retryvar > retry_limit) {
  537. brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
  538. *regvar = 0;
  539. }
  540. }
  541. }
  542. static void
  543. w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset, u32 *retryvar)
  544. {
  545. u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  546. *retryvar = 0;
  547. do {
  548. brcmf_sdcard_reg_write(bus->sdiodev,
  549. bus->ci->c_inf[idx].base + reg_offset,
  550. sizeof(u32), regval);
  551. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  552. (++(*retryvar) <= retry_limit));
  553. if (*retryvar) {
  554. bus->regfails += (*retryvar-1);
  555. if (*retryvar > retry_limit)
  556. brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
  557. reg_offset);
  558. }
  559. }
  560. #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
  561. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  562. /* Packet free applicable unconditionally for sdio and sdspi.
  563. * Conditional if bufpool was present for gspi bus.
  564. */
  565. static void brcmf_sdbrcm_pktfree2(struct brcmf_sdio *bus, struct sk_buff *pkt)
  566. {
  567. if (bus->usebufpool)
  568. brcmu_pkt_buf_free_skb(pkt);
  569. }
  570. /* Turn backplane clock on or off */
  571. static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
  572. {
  573. int err;
  574. u8 clkctl, clkreq, devctl;
  575. unsigned long timeout;
  576. brcmf_dbg(TRACE, "Enter\n");
  577. clkctl = 0;
  578. if (on) {
  579. /* Request HT Avail */
  580. clkreq =
  581. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  582. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  583. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  584. if (err) {
  585. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  586. return -EBADE;
  587. }
  588. /* Check current status */
  589. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  590. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  591. if (err) {
  592. brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
  593. return -EBADE;
  594. }
  595. /* Go to pending and await interrupt if appropriate */
  596. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  597. /* Allow only clock-available interrupt */
  598. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  599. SDIO_FUNC_1,
  600. SBSDIO_DEVICE_CTL, &err);
  601. if (err) {
  602. brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
  603. err);
  604. return -EBADE;
  605. }
  606. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  607. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  608. SBSDIO_DEVICE_CTL, devctl, &err);
  609. brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
  610. bus->clkstate = CLK_PENDING;
  611. return 0;
  612. } else if (bus->clkstate == CLK_PENDING) {
  613. /* Cancel CA-only interrupt filter */
  614. devctl =
  615. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  616. SBSDIO_DEVICE_CTL, &err);
  617. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  618. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  619. SBSDIO_DEVICE_CTL, devctl, &err);
  620. }
  621. /* Otherwise, wait here (polling) for HT Avail */
  622. timeout = jiffies +
  623. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  624. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  625. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  626. SDIO_FUNC_1,
  627. SBSDIO_FUNC1_CHIPCLKCSR,
  628. &err);
  629. if (time_after(jiffies, timeout))
  630. break;
  631. else
  632. usleep_range(5000, 10000);
  633. }
  634. if (err) {
  635. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  636. return -EBADE;
  637. }
  638. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  639. brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
  640. PMU_MAX_TRANSITION_DLY, clkctl);
  641. return -EBADE;
  642. }
  643. /* Mark clock available */
  644. bus->clkstate = CLK_AVAIL;
  645. brcmf_dbg(INFO, "CLKCTL: turned ON\n");
  646. #if defined(BCMDBG)
  647. if (bus->alp_only != true) {
  648. if (SBSDIO_ALPONLY(clkctl))
  649. brcmf_dbg(ERROR, "HT Clock should be on\n");
  650. }
  651. #endif /* defined (BCMDBG) */
  652. bus->activity = true;
  653. } else {
  654. clkreq = 0;
  655. if (bus->clkstate == CLK_PENDING) {
  656. /* Cancel CA-only interrupt filter */
  657. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  658. SDIO_FUNC_1,
  659. SBSDIO_DEVICE_CTL, &err);
  660. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  661. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  662. SBSDIO_DEVICE_CTL, devctl, &err);
  663. }
  664. bus->clkstate = CLK_SDONLY;
  665. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  666. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  667. brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
  668. if (err) {
  669. brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
  670. err);
  671. return -EBADE;
  672. }
  673. }
  674. return 0;
  675. }
  676. /* Change idle/active SD state */
  677. static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
  678. {
  679. brcmf_dbg(TRACE, "Enter\n");
  680. if (on)
  681. bus->clkstate = CLK_SDONLY;
  682. else
  683. bus->clkstate = CLK_NONE;
  684. return 0;
  685. }
  686. /* Transition SD and backplane clock readiness */
  687. static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
  688. {
  689. #ifdef BCMDBG
  690. uint oldstate = bus->clkstate;
  691. #endif /* BCMDBG */
  692. brcmf_dbg(TRACE, "Enter\n");
  693. /* Early exit if we're already there */
  694. if (bus->clkstate == target) {
  695. if (target == CLK_AVAIL) {
  696. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  697. bus->activity = true;
  698. }
  699. return 0;
  700. }
  701. switch (target) {
  702. case CLK_AVAIL:
  703. /* Make sure SD clock is available */
  704. if (bus->clkstate == CLK_NONE)
  705. brcmf_sdbrcm_sdclk(bus, true);
  706. /* Now request HT Avail on the backplane */
  707. brcmf_sdbrcm_htclk(bus, true, pendok);
  708. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  709. bus->activity = true;
  710. break;
  711. case CLK_SDONLY:
  712. /* Remove HT request, or bring up SD clock */
  713. if (bus->clkstate == CLK_NONE)
  714. brcmf_sdbrcm_sdclk(bus, true);
  715. else if (bus->clkstate == CLK_AVAIL)
  716. brcmf_sdbrcm_htclk(bus, false, false);
  717. else
  718. brcmf_dbg(ERROR, "request for %d -> %d\n",
  719. bus->clkstate, target);
  720. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  721. break;
  722. case CLK_NONE:
  723. /* Make sure to remove HT request */
  724. if (bus->clkstate == CLK_AVAIL)
  725. brcmf_sdbrcm_htclk(bus, false, false);
  726. /* Now remove the SD clock */
  727. brcmf_sdbrcm_sdclk(bus, false);
  728. brcmf_sdbrcm_wd_timer(bus, 0);
  729. break;
  730. }
  731. #ifdef BCMDBG
  732. brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
  733. #endif /* BCMDBG */
  734. return 0;
  735. }
  736. static int brcmf_sdbrcm_bussleep(struct brcmf_sdio *bus, bool sleep)
  737. {
  738. uint retries = 0;
  739. brcmf_dbg(INFO, "request %s (currently %s)\n",
  740. sleep ? "SLEEP" : "WAKE",
  741. bus->sleeping ? "SLEEP" : "WAKE");
  742. /* Done if we're already in the requested state */
  743. if (sleep == bus->sleeping)
  744. return 0;
  745. /* Going to sleep: set the alarm and turn off the lights... */
  746. if (sleep) {
  747. /* Don't sleep if something is pending */
  748. if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
  749. return -EBUSY;
  750. /* Make sure the controller has the bus up */
  751. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  752. /* Tell device to start using OOB wakeup */
  753. w_sdreg32(bus, SMB_USE_OOB,
  754. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  755. if (retries > retry_limit)
  756. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
  757. /* Turn off our contribution to the HT clock request */
  758. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  759. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  760. SBSDIO_FUNC1_CHIPCLKCSR,
  761. SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
  762. /* Isolate the bus */
  763. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  764. SBSDIO_DEVICE_CTL,
  765. SBSDIO_DEVCTL_PADS_ISO, NULL);
  766. /* Change state */
  767. bus->sleeping = true;
  768. } else {
  769. /* Waking up: bus power up is ok, set local state */
  770. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  771. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  772. /* Make sure the controller has the bus up */
  773. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  774. /* Send misc interrupt to indicate OOB not needed */
  775. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
  776. &retries);
  777. if (retries <= retry_limit)
  778. w_sdreg32(bus, SMB_DEV_INT,
  779. offsetof(struct sdpcmd_regs, tosbmailbox),
  780. &retries);
  781. if (retries > retry_limit)
  782. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
  783. /* Make sure we have SD bus access */
  784. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  785. /* Change state */
  786. bus->sleeping = false;
  787. }
  788. return 0;
  789. }
  790. static void bus_wake(struct brcmf_sdio *bus)
  791. {
  792. if (bus->sleeping)
  793. brcmf_sdbrcm_bussleep(bus, false);
  794. }
  795. static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
  796. {
  797. u32 intstatus = 0;
  798. u32 hmb_data;
  799. u8 fcbits;
  800. uint retries = 0;
  801. brcmf_dbg(TRACE, "Enter\n");
  802. /* Read mailbox data and ack that we did so */
  803. r_sdreg32(bus, &hmb_data,
  804. offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
  805. if (retries <= retry_limit)
  806. w_sdreg32(bus, SMB_INT_ACK,
  807. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  808. bus->f1regdata += 2;
  809. /* Dongle recomposed rx frames, accept them again */
  810. if (hmb_data & HMB_DATA_NAKHANDLED) {
  811. brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
  812. bus->rx_seq);
  813. if (!bus->rxskip)
  814. brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
  815. bus->rxskip = false;
  816. intstatus |= I_HMB_FRAME_IND;
  817. }
  818. /*
  819. * DEVREADY does not occur with gSPI.
  820. */
  821. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  822. bus->sdpcm_ver =
  823. (hmb_data & HMB_DATA_VERSION_MASK) >>
  824. HMB_DATA_VERSION_SHIFT;
  825. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  826. brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
  827. "expecting %d\n",
  828. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  829. else
  830. brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
  831. bus->sdpcm_ver);
  832. }
  833. /*
  834. * Flow Control has been moved into the RX headers and this out of band
  835. * method isn't used any more.
  836. * remaining backward compatible with older dongles.
  837. */
  838. if (hmb_data & HMB_DATA_FC) {
  839. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  840. HMB_DATA_FCDATA_SHIFT;
  841. if (fcbits & ~bus->flowcontrol)
  842. bus->fc_xoff++;
  843. if (bus->flowcontrol & ~fcbits)
  844. bus->fc_xon++;
  845. bus->fc_rcvd++;
  846. bus->flowcontrol = fcbits;
  847. }
  848. /* Shouldn't be any others */
  849. if (hmb_data & ~(HMB_DATA_DEVREADY |
  850. HMB_DATA_NAKHANDLED |
  851. HMB_DATA_FC |
  852. HMB_DATA_FWREADY |
  853. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  854. brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
  855. hmb_data);
  856. return intstatus;
  857. }
  858. static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
  859. {
  860. uint retries = 0;
  861. u16 lastrbc;
  862. u8 hi, lo;
  863. int err;
  864. brcmf_dbg(ERROR, "%sterminate frame%s\n",
  865. abort ? "abort command, " : "",
  866. rtx ? ", send NAK" : "");
  867. if (abort)
  868. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  869. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  870. SBSDIO_FUNC1_FRAMECTRL,
  871. SFC_RF_TERM, &err);
  872. bus->f1regdata++;
  873. /* Wait until the packet has been flushed (device/FIFO stable) */
  874. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  875. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  876. SBSDIO_FUNC1_RFRAMEBCHI, NULL);
  877. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  878. SBSDIO_FUNC1_RFRAMEBCLO, NULL);
  879. bus->f1regdata += 2;
  880. if ((hi == 0) && (lo == 0))
  881. break;
  882. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  883. brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
  884. lastrbc, (hi << 8) + lo);
  885. }
  886. lastrbc = (hi << 8) + lo;
  887. }
  888. if (!retries)
  889. brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
  890. else
  891. brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
  892. if (rtx) {
  893. bus->rxrtx++;
  894. w_sdreg32(bus, SMB_NAK,
  895. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  896. bus->f1regdata++;
  897. if (retries <= retry_limit)
  898. bus->rxskip = true;
  899. }
  900. /* Clear partial in any case */
  901. bus->nextlen = 0;
  902. /* If we can't reach the device, signal failure */
  903. if (err || brcmf_sdcard_regfail(bus->sdiodev))
  904. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  905. }
  906. /* copy a buffer into a pkt buffer chain */
  907. static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len)
  908. {
  909. uint n, ret = 0;
  910. struct sk_buff *p;
  911. u8 *buf;
  912. buf = bus->dataptr;
  913. /* copy the data */
  914. skb_queue_walk(&bus->glom, p) {
  915. n = min_t(uint, p->len, len);
  916. memcpy(p->data, buf, n);
  917. buf += n;
  918. len -= n;
  919. ret += n;
  920. if (!len)
  921. break;
  922. }
  923. return ret;
  924. }
  925. /* return total length of buffer chain */
  926. static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
  927. {
  928. struct sk_buff *p;
  929. uint total;
  930. total = 0;
  931. skb_queue_walk(&bus->glom, p)
  932. total += p->len;
  933. return total;
  934. }
  935. static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
  936. {
  937. struct sk_buff *cur, *next;
  938. skb_queue_walk_safe(&bus->glom, cur, next) {
  939. skb_unlink(cur, &bus->glom);
  940. brcmu_pkt_buf_free_skb(cur);
  941. }
  942. }
  943. static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
  944. {
  945. u16 dlen, totlen;
  946. u8 *dptr, num = 0;
  947. u16 sublen, check;
  948. struct sk_buff *pfirst, *pnext;
  949. int errcode;
  950. u8 chan, seq, doff, sfdoff;
  951. u8 txmax;
  952. int ifidx = 0;
  953. bool usechain = bus->use_rxchain;
  954. /* If packets, issue read(s) and send up packet chain */
  955. /* Return sequence numbers consumed? */
  956. brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
  957. bus->glomd, skb_peek(&bus->glom));
  958. /* If there's a descriptor, generate the packet chain */
  959. if (bus->glomd) {
  960. pfirst = pnext = NULL;
  961. dlen = (u16) (bus->glomd->len);
  962. dptr = bus->glomd->data;
  963. if (!dlen || (dlen & 1)) {
  964. brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
  965. dlen);
  966. dlen = 0;
  967. }
  968. for (totlen = num = 0; dlen; num++) {
  969. /* Get (and move past) next length */
  970. sublen = get_unaligned_le16(dptr);
  971. dlen -= sizeof(u16);
  972. dptr += sizeof(u16);
  973. if ((sublen < SDPCM_HDRLEN) ||
  974. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  975. brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
  976. num, sublen);
  977. pnext = NULL;
  978. break;
  979. }
  980. if (sublen % BRCMF_SDALIGN) {
  981. brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
  982. sublen, BRCMF_SDALIGN);
  983. usechain = false;
  984. }
  985. totlen += sublen;
  986. /* For last frame, adjust read len so total
  987. is a block multiple */
  988. if (!dlen) {
  989. sublen +=
  990. (roundup(totlen, bus->blocksize) - totlen);
  991. totlen = roundup(totlen, bus->blocksize);
  992. }
  993. /* Allocate/chain packet for next subframe */
  994. pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
  995. if (pnext == NULL) {
  996. brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
  997. num, sublen);
  998. break;
  999. }
  1000. skb_queue_tail(&bus->glom, pnext);
  1001. /* Adhere to start alignment requirements */
  1002. pkt_align(pnext, sublen, BRCMF_SDALIGN);
  1003. }
  1004. /* If all allocations succeeded, save packet chain
  1005. in bus structure */
  1006. if (pnext) {
  1007. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  1008. totlen, num);
  1009. if (BRCMF_GLOM_ON() && bus->nextlen &&
  1010. totlen != bus->nextlen) {
  1011. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  1012. bus->nextlen, totlen, rxseq);
  1013. }
  1014. pfirst = pnext = NULL;
  1015. } else {
  1016. brcmf_sdbrcm_free_glom(bus);
  1017. num = 0;
  1018. }
  1019. /* Done with descriptor packet */
  1020. brcmu_pkt_buf_free_skb(bus->glomd);
  1021. bus->glomd = NULL;
  1022. bus->nextlen = 0;
  1023. }
  1024. /* Ok -- either we just generated a packet chain,
  1025. or had one from before */
  1026. if (!skb_queue_empty(&bus->glom)) {
  1027. if (BRCMF_GLOM_ON()) {
  1028. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1029. skb_queue_walk(&bus->glom, pnext) {
  1030. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1031. pnext, (u8 *) (pnext->data),
  1032. pnext->len, pnext->len);
  1033. }
  1034. }
  1035. pfirst = skb_peek(&bus->glom);
  1036. dlen = (u16) brcmf_sdbrcm_glom_len(bus);
  1037. /* Do an SDIO read for the superframe. Configurable iovar to
  1038. * read directly into the chained packet, or allocate a large
  1039. * packet and and copy into the chain.
  1040. */
  1041. if (usechain) {
  1042. errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
  1043. bus->sdiodev->sbwad,
  1044. SDIO_FUNC_2, F2SYNC, &bus->glom);
  1045. } else if (bus->dataptr) {
  1046. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1047. bus->sdiodev->sbwad,
  1048. SDIO_FUNC_2, F2SYNC,
  1049. bus->dataptr, dlen);
  1050. sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
  1051. if (sublen != dlen) {
  1052. brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
  1053. dlen, sublen);
  1054. errcode = -1;
  1055. }
  1056. pnext = NULL;
  1057. } else {
  1058. brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
  1059. dlen);
  1060. errcode = -1;
  1061. }
  1062. bus->f2rxdata++;
  1063. /* On failure, kill the superframe, allow a couple retries */
  1064. if (errcode < 0) {
  1065. brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
  1066. dlen, errcode);
  1067. bus->sdiodev->bus_if->dstats.rx_errors++;
  1068. if (bus->glomerr++ < 3) {
  1069. brcmf_sdbrcm_rxfail(bus, true, true);
  1070. } else {
  1071. bus->glomerr = 0;
  1072. brcmf_sdbrcm_rxfail(bus, true, false);
  1073. bus->rxglomfail++;
  1074. brcmf_sdbrcm_free_glom(bus);
  1075. }
  1076. return 0;
  1077. }
  1078. #ifdef BCMDBG
  1079. if (BRCMF_GLOM_ON()) {
  1080. printk(KERN_DEBUG "SUPERFRAME:\n");
  1081. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1082. pfirst->data, min_t(int, pfirst->len, 48));
  1083. }
  1084. #endif
  1085. /* Validate the superframe header */
  1086. dptr = (u8 *) (pfirst->data);
  1087. sublen = get_unaligned_le16(dptr);
  1088. check = get_unaligned_le16(dptr + sizeof(u16));
  1089. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1090. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1091. bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1092. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1093. brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
  1094. bus->nextlen, seq);
  1095. bus->nextlen = 0;
  1096. }
  1097. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1098. txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1099. errcode = 0;
  1100. if ((u16)~(sublen ^ check)) {
  1101. brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
  1102. sublen, check);
  1103. errcode = -1;
  1104. } else if (roundup(sublen, bus->blocksize) != dlen) {
  1105. brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
  1106. sublen, roundup(sublen, bus->blocksize),
  1107. dlen);
  1108. errcode = -1;
  1109. } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
  1110. SDPCM_GLOM_CHANNEL) {
  1111. brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
  1112. SDPCM_PACKET_CHANNEL(
  1113. &dptr[SDPCM_FRAMETAG_LEN]));
  1114. errcode = -1;
  1115. } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
  1116. brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
  1117. errcode = -1;
  1118. } else if ((doff < SDPCM_HDRLEN) ||
  1119. (doff > (pfirst->len - SDPCM_HDRLEN))) {
  1120. brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
  1121. doff, sublen, pfirst->len, SDPCM_HDRLEN);
  1122. errcode = -1;
  1123. }
  1124. /* Check sequence number of superframe SW header */
  1125. if (rxseq != seq) {
  1126. brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
  1127. seq, rxseq);
  1128. bus->rx_badseq++;
  1129. rxseq = seq;
  1130. }
  1131. /* Check window for sanity */
  1132. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1133. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1134. txmax, bus->tx_seq);
  1135. txmax = bus->tx_seq + 2;
  1136. }
  1137. bus->tx_max = txmax;
  1138. /* Remove superframe header, remember offset */
  1139. skb_pull(pfirst, doff);
  1140. sfdoff = doff;
  1141. num = 0;
  1142. /* Validate all the subframe headers */
  1143. skb_queue_walk(&bus->glom, pnext) {
  1144. /* leave when invalid subframe is found */
  1145. if (errcode)
  1146. break;
  1147. dptr = (u8 *) (pnext->data);
  1148. dlen = (u16) (pnext->len);
  1149. sublen = get_unaligned_le16(dptr);
  1150. check = get_unaligned_le16(dptr + sizeof(u16));
  1151. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1152. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1153. #ifdef BCMDBG
  1154. if (BRCMF_GLOM_ON()) {
  1155. printk(KERN_DEBUG "subframe:\n");
  1156. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1157. dptr, 32);
  1158. }
  1159. #endif
  1160. if ((u16)~(sublen ^ check)) {
  1161. brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
  1162. num, sublen, check);
  1163. errcode = -1;
  1164. } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
  1165. brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
  1166. num, sublen, dlen);
  1167. errcode = -1;
  1168. } else if ((chan != SDPCM_DATA_CHANNEL) &&
  1169. (chan != SDPCM_EVENT_CHANNEL)) {
  1170. brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
  1171. num, chan);
  1172. errcode = -1;
  1173. } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
  1174. brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
  1175. num, doff, sublen, SDPCM_HDRLEN);
  1176. errcode = -1;
  1177. }
  1178. /* increase the subframe count */
  1179. num++;
  1180. }
  1181. if (errcode) {
  1182. /* Terminate frame on error, request
  1183. a couple retries */
  1184. if (bus->glomerr++ < 3) {
  1185. /* Restore superframe header space */
  1186. skb_push(pfirst, sfdoff);
  1187. brcmf_sdbrcm_rxfail(bus, true, true);
  1188. } else {
  1189. bus->glomerr = 0;
  1190. brcmf_sdbrcm_rxfail(bus, true, false);
  1191. bus->rxglomfail++;
  1192. brcmf_sdbrcm_free_glom(bus);
  1193. }
  1194. bus->nextlen = 0;
  1195. return 0;
  1196. }
  1197. /* Basic SD framing looks ok - process each packet (header) */
  1198. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1199. dptr = (u8 *) (pfirst->data);
  1200. sublen = get_unaligned_le16(dptr);
  1201. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1202. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1203. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1204. brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
  1205. num, pfirst, pfirst->data,
  1206. pfirst->len, sublen, chan, seq);
  1207. /* precondition: chan == SDPCM_DATA_CHANNEL ||
  1208. chan == SDPCM_EVENT_CHANNEL */
  1209. if (rxseq != seq) {
  1210. brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
  1211. seq, rxseq);
  1212. bus->rx_badseq++;
  1213. rxseq = seq;
  1214. }
  1215. rxseq++;
  1216. #ifdef BCMDBG
  1217. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1218. printk(KERN_DEBUG "Rx Subframe Data:\n");
  1219. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1220. dptr, dlen);
  1221. }
  1222. #endif
  1223. __skb_trim(pfirst, sublen);
  1224. skb_pull(pfirst, doff);
  1225. if (pfirst->len == 0) {
  1226. skb_unlink(pfirst, &bus->glom);
  1227. brcmu_pkt_buf_free_skb(pfirst);
  1228. continue;
  1229. } else if (brcmf_proto_hdrpull(bus->sdiodev->dev,
  1230. &ifidx, pfirst) != 0) {
  1231. brcmf_dbg(ERROR, "rx protocol error\n");
  1232. bus->sdiodev->bus_if->dstats.rx_errors++;
  1233. skb_unlink(pfirst, &bus->glom);
  1234. brcmu_pkt_buf_free_skb(pfirst);
  1235. continue;
  1236. }
  1237. #ifdef BCMDBG
  1238. if (BRCMF_GLOM_ON()) {
  1239. brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1240. bus->glom.qlen, pfirst, pfirst->data,
  1241. pfirst->len, pfirst->next,
  1242. pfirst->prev);
  1243. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1244. pfirst->data,
  1245. min_t(int, pfirst->len, 32));
  1246. }
  1247. #endif /* BCMDBG */
  1248. }
  1249. /* sent any remaining packets up */
  1250. if (bus->glom.qlen) {
  1251. up(&bus->sdsem);
  1252. brcmf_rx_frame(bus->sdiodev->dev, ifidx, &bus->glom);
  1253. down(&bus->sdsem);
  1254. }
  1255. bus->rxglomframes++;
  1256. bus->rxglompkts += bus->glom.qlen;
  1257. }
  1258. return num;
  1259. }
  1260. static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
  1261. bool *pending)
  1262. {
  1263. DECLARE_WAITQUEUE(wait, current);
  1264. int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
  1265. /* Wait until control frame is available */
  1266. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1267. set_current_state(TASK_INTERRUPTIBLE);
  1268. while (!(*condition) && (!signal_pending(current) && timeout))
  1269. timeout = schedule_timeout(timeout);
  1270. if (signal_pending(current))
  1271. *pending = true;
  1272. set_current_state(TASK_RUNNING);
  1273. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1274. return timeout;
  1275. }
  1276. static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
  1277. {
  1278. if (waitqueue_active(&bus->dcmd_resp_wait))
  1279. wake_up_interruptible(&bus->dcmd_resp_wait);
  1280. return 0;
  1281. }
  1282. static void
  1283. brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
  1284. {
  1285. uint rdlen, pad;
  1286. int sdret;
  1287. brcmf_dbg(TRACE, "Enter\n");
  1288. /* Set rxctl for frame (w/optional alignment) */
  1289. bus->rxctl = bus->rxbuf;
  1290. bus->rxctl += BRCMF_FIRSTREAD;
  1291. pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
  1292. if (pad)
  1293. bus->rxctl += (BRCMF_SDALIGN - pad);
  1294. bus->rxctl -= BRCMF_FIRSTREAD;
  1295. /* Copy the already-read portion over */
  1296. memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
  1297. if (len <= BRCMF_FIRSTREAD)
  1298. goto gotpkt;
  1299. /* Raise rdlen to next SDIO block to avoid tail command */
  1300. rdlen = len - BRCMF_FIRSTREAD;
  1301. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1302. pad = bus->blocksize - (rdlen % bus->blocksize);
  1303. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1304. ((len + pad) < bus->sdiodev->bus_if->maxctl))
  1305. rdlen += pad;
  1306. } else if (rdlen % BRCMF_SDALIGN) {
  1307. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1308. }
  1309. /* Satisfy length-alignment requirements */
  1310. if (rdlen & (ALIGNMENT - 1))
  1311. rdlen = roundup(rdlen, ALIGNMENT);
  1312. /* Drop if the read is too big or it exceeds our maximum */
  1313. if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
  1314. brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
  1315. rdlen, bus->sdiodev->bus_if->maxctl);
  1316. bus->sdiodev->bus_if->dstats.rx_errors++;
  1317. brcmf_sdbrcm_rxfail(bus, false, false);
  1318. goto done;
  1319. }
  1320. if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
  1321. brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1322. len, len - doff, bus->sdiodev->bus_if->maxctl);
  1323. bus->sdiodev->bus_if->dstats.rx_errors++;
  1324. bus->rx_toolong++;
  1325. brcmf_sdbrcm_rxfail(bus, false, false);
  1326. goto done;
  1327. }
  1328. /* Read remainder of frame body into the rxctl buffer */
  1329. sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
  1330. bus->sdiodev->sbwad,
  1331. SDIO_FUNC_2,
  1332. F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen);
  1333. bus->f2rxdata++;
  1334. /* Control frame failures need retransmission */
  1335. if (sdret < 0) {
  1336. brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
  1337. rdlen, sdret);
  1338. bus->rxc_errors++;
  1339. brcmf_sdbrcm_rxfail(bus, true, true);
  1340. goto done;
  1341. }
  1342. gotpkt:
  1343. #ifdef BCMDBG
  1344. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  1345. printk(KERN_DEBUG "RxCtrl:\n");
  1346. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
  1347. }
  1348. #endif
  1349. /* Point to valid data and indicate its length */
  1350. bus->rxctl += doff;
  1351. bus->rxlen = len - doff;
  1352. done:
  1353. /* Awake any waiters */
  1354. brcmf_sdbrcm_dcmd_resp_wake(bus);
  1355. }
  1356. /* Pad read to blocksize for efficiency */
  1357. static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
  1358. {
  1359. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1360. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1361. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1362. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1363. *rdlen += *pad;
  1364. } else if (*rdlen % BRCMF_SDALIGN) {
  1365. *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
  1366. }
  1367. }
  1368. static void
  1369. brcmf_alloc_pkt_and_read(struct brcmf_sdio *bus, u16 rdlen,
  1370. struct sk_buff **pkt, u8 **rxbuf)
  1371. {
  1372. int sdret; /* Return code from calls */
  1373. *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
  1374. if (*pkt == NULL)
  1375. return;
  1376. pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
  1377. *rxbuf = (u8 *) ((*pkt)->data);
  1378. /* Read the entire frame */
  1379. sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1380. SDIO_FUNC_2, F2SYNC, *pkt);
  1381. bus->f2rxdata++;
  1382. if (sdret < 0) {
  1383. brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
  1384. rdlen, sdret);
  1385. brcmu_pkt_buf_free_skb(*pkt);
  1386. bus->sdiodev->bus_if->dstats.rx_errors++;
  1387. /* Force retry w/normal header read.
  1388. * Don't attempt NAK for
  1389. * gSPI
  1390. */
  1391. brcmf_sdbrcm_rxfail(bus, true, true);
  1392. *pkt = NULL;
  1393. }
  1394. }
  1395. /* Checks the header */
  1396. static int
  1397. brcmf_check_rxbuf(struct brcmf_sdio *bus, struct sk_buff *pkt, u8 *rxbuf,
  1398. u8 rxseq, u16 nextlen, u16 *len)
  1399. {
  1400. u16 check;
  1401. bool len_consistent; /* Result of comparing readahead len and
  1402. len from hw-hdr */
  1403. memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
  1404. /* Extract hardware header fields */
  1405. *len = get_unaligned_le16(bus->rxhdr);
  1406. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1407. /* All zeros means readahead info was bad */
  1408. if (!(*len | check)) {
  1409. brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
  1410. goto fail;
  1411. }
  1412. /* Validate check bytes */
  1413. if ((u16)~(*len ^ check)) {
  1414. brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
  1415. nextlen, *len, check);
  1416. bus->rx_badhdr++;
  1417. brcmf_sdbrcm_rxfail(bus, false, false);
  1418. goto fail;
  1419. }
  1420. /* Validate frame length */
  1421. if (*len < SDPCM_HDRLEN) {
  1422. brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
  1423. *len);
  1424. goto fail;
  1425. }
  1426. /* Check for consistency with readahead info */
  1427. len_consistent = (nextlen != (roundup(*len, 16) >> 4));
  1428. if (len_consistent) {
  1429. /* Mismatch, force retry w/normal
  1430. header (may be >4K) */
  1431. brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
  1432. nextlen, *len, roundup(*len, 16),
  1433. rxseq);
  1434. brcmf_sdbrcm_rxfail(bus, true, true);
  1435. goto fail;
  1436. }
  1437. return 0;
  1438. fail:
  1439. brcmf_sdbrcm_pktfree2(bus, pkt);
  1440. return -EINVAL;
  1441. }
  1442. /* Return true if there may be more frames to read */
  1443. static uint
  1444. brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
  1445. {
  1446. u16 len, check; /* Extracted hardware header fields */
  1447. u8 chan, seq, doff; /* Extracted software header fields */
  1448. u8 fcbits; /* Extracted fcbits from software header */
  1449. struct sk_buff *pkt; /* Packet for event or data frames */
  1450. u16 pad; /* Number of pad bytes to read */
  1451. u16 rdlen; /* Total number of bytes to read */
  1452. u8 rxseq; /* Next sequence number to expect */
  1453. uint rxleft = 0; /* Remaining number of frames allowed */
  1454. int sdret; /* Return code from calls */
  1455. u8 txmax; /* Maximum tx sequence offered */
  1456. u8 *rxbuf;
  1457. int ifidx = 0;
  1458. uint rxcount = 0; /* Total frames read */
  1459. brcmf_dbg(TRACE, "Enter\n");
  1460. /* Not finished unless we encounter no more frames indication */
  1461. *finished = false;
  1462. for (rxseq = bus->rx_seq, rxleft = maxframes;
  1463. !bus->rxskip && rxleft &&
  1464. bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN;
  1465. rxseq++, rxleft--) {
  1466. /* Handle glomming separately */
  1467. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1468. u8 cnt;
  1469. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1470. bus->glomd, skb_peek(&bus->glom));
  1471. cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
  1472. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1473. rxseq += cnt - 1;
  1474. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1475. continue;
  1476. }
  1477. /* Try doing single read if we can */
  1478. if (bus->nextlen) {
  1479. u16 nextlen = bus->nextlen;
  1480. bus->nextlen = 0;
  1481. rdlen = len = nextlen << 4;
  1482. brcmf_pad(bus, &pad, &rdlen);
  1483. /*
  1484. * After the frame is received we have to
  1485. * distinguish whether it is data
  1486. * or non-data frame.
  1487. */
  1488. brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
  1489. if (pkt == NULL) {
  1490. /* Give up on data, request rtx of events */
  1491. brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
  1492. len, rdlen, rxseq);
  1493. continue;
  1494. }
  1495. if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
  1496. &len) < 0)
  1497. continue;
  1498. /* Extract software header fields */
  1499. chan = SDPCM_PACKET_CHANNEL(
  1500. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1501. seq = SDPCM_PACKET_SEQUENCE(
  1502. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1503. doff = SDPCM_DOFFSET_VALUE(
  1504. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1505. txmax = SDPCM_WINDOW_VALUE(
  1506. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1507. bus->nextlen =
  1508. bus->rxhdr[SDPCM_FRAMETAG_LEN +
  1509. SDPCM_NEXTLEN_OFFSET];
  1510. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1511. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1512. bus->nextlen, seq);
  1513. bus->nextlen = 0;
  1514. }
  1515. bus->rx_readahead_cnt++;
  1516. /* Handle Flow Control */
  1517. fcbits = SDPCM_FCMASK_VALUE(
  1518. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1519. if (bus->flowcontrol != fcbits) {
  1520. if (~bus->flowcontrol & fcbits)
  1521. bus->fc_xoff++;
  1522. if (bus->flowcontrol & ~fcbits)
  1523. bus->fc_xon++;
  1524. bus->fc_rcvd++;
  1525. bus->flowcontrol = fcbits;
  1526. }
  1527. /* Check and update sequence number */
  1528. if (rxseq != seq) {
  1529. brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
  1530. seq, rxseq);
  1531. bus->rx_badseq++;
  1532. rxseq = seq;
  1533. }
  1534. /* Check window for sanity */
  1535. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1536. brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
  1537. txmax, bus->tx_seq);
  1538. txmax = bus->tx_seq + 2;
  1539. }
  1540. bus->tx_max = txmax;
  1541. #ifdef BCMDBG
  1542. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1543. printk(KERN_DEBUG "Rx Data:\n");
  1544. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1545. rxbuf, len);
  1546. } else if (BRCMF_HDRS_ON()) {
  1547. printk(KERN_DEBUG "RxHdr:\n");
  1548. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1549. bus->rxhdr, SDPCM_HDRLEN);
  1550. }
  1551. #endif
  1552. if (chan == SDPCM_CONTROL_CHANNEL) {
  1553. brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
  1554. seq);
  1555. /* Force retry w/normal header read */
  1556. bus->nextlen = 0;
  1557. brcmf_sdbrcm_rxfail(bus, false, true);
  1558. brcmf_sdbrcm_pktfree2(bus, pkt);
  1559. continue;
  1560. }
  1561. /* Validate data offset */
  1562. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1563. brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
  1564. doff, len, SDPCM_HDRLEN);
  1565. brcmf_sdbrcm_rxfail(bus, false, false);
  1566. brcmf_sdbrcm_pktfree2(bus, pkt);
  1567. continue;
  1568. }
  1569. /* All done with this one -- now deliver the packet */
  1570. goto deliver;
  1571. }
  1572. /* Read frame header (hardware and software) */
  1573. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1574. SDIO_FUNC_2, F2SYNC, bus->rxhdr,
  1575. BRCMF_FIRSTREAD);
  1576. bus->f2rxhdrs++;
  1577. if (sdret < 0) {
  1578. brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
  1579. bus->rx_hdrfail++;
  1580. brcmf_sdbrcm_rxfail(bus, true, true);
  1581. continue;
  1582. }
  1583. #ifdef BCMDBG
  1584. if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
  1585. printk(KERN_DEBUG "RxHdr:\n");
  1586. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1587. bus->rxhdr, SDPCM_HDRLEN);
  1588. }
  1589. #endif
  1590. /* Extract hardware header fields */
  1591. len = get_unaligned_le16(bus->rxhdr);
  1592. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1593. /* All zeros means no more frames */
  1594. if (!(len | check)) {
  1595. *finished = true;
  1596. break;
  1597. }
  1598. /* Validate check bytes */
  1599. if ((u16) ~(len ^ check)) {
  1600. brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
  1601. len, check);
  1602. bus->rx_badhdr++;
  1603. brcmf_sdbrcm_rxfail(bus, false, false);
  1604. continue;
  1605. }
  1606. /* Validate frame length */
  1607. if (len < SDPCM_HDRLEN) {
  1608. brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
  1609. continue;
  1610. }
  1611. /* Extract software header fields */
  1612. chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1613. seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1614. doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1615. txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1616. /* Validate data offset */
  1617. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1618. brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
  1619. doff, len, SDPCM_HDRLEN, seq);
  1620. bus->rx_badhdr++;
  1621. brcmf_sdbrcm_rxfail(bus, false, false);
  1622. continue;
  1623. }
  1624. /* Save the readahead length if there is one */
  1625. bus->nextlen =
  1626. bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1627. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1628. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1629. bus->nextlen, seq);
  1630. bus->nextlen = 0;
  1631. }
  1632. /* Handle Flow Control */
  1633. fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1634. if (bus->flowcontrol != fcbits) {
  1635. if (~bus->flowcontrol & fcbits)
  1636. bus->fc_xoff++;
  1637. if (bus->flowcontrol & ~fcbits)
  1638. bus->fc_xon++;
  1639. bus->fc_rcvd++;
  1640. bus->flowcontrol = fcbits;
  1641. }
  1642. /* Check and update sequence number */
  1643. if (rxseq != seq) {
  1644. brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
  1645. bus->rx_badseq++;
  1646. rxseq = seq;
  1647. }
  1648. /* Check window for sanity */
  1649. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1650. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1651. txmax, bus->tx_seq);
  1652. txmax = bus->tx_seq + 2;
  1653. }
  1654. bus->tx_max = txmax;
  1655. /* Call a separate function for control frames */
  1656. if (chan == SDPCM_CONTROL_CHANNEL) {
  1657. brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
  1658. continue;
  1659. }
  1660. /* precondition: chan is either SDPCM_DATA_CHANNEL,
  1661. SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
  1662. SDPCM_GLOM_CHANNEL */
  1663. /* Length to read */
  1664. rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
  1665. /* May pad read to blocksize for efficiency */
  1666. if (bus->roundup && bus->blocksize &&
  1667. (rdlen > bus->blocksize)) {
  1668. pad = bus->blocksize - (rdlen % bus->blocksize);
  1669. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1670. ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
  1671. rdlen += pad;
  1672. } else if (rdlen % BRCMF_SDALIGN) {
  1673. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1674. }
  1675. /* Satisfy length-alignment requirements */
  1676. if (rdlen & (ALIGNMENT - 1))
  1677. rdlen = roundup(rdlen, ALIGNMENT);
  1678. if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
  1679. /* Too long -- skip this frame */
  1680. brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
  1681. len, rdlen);
  1682. bus->sdiodev->bus_if->dstats.rx_errors++;
  1683. bus->rx_toolong++;
  1684. brcmf_sdbrcm_rxfail(bus, false, false);
  1685. continue;
  1686. }
  1687. pkt = brcmu_pkt_buf_get_skb(rdlen +
  1688. BRCMF_FIRSTREAD + BRCMF_SDALIGN);
  1689. if (!pkt) {
  1690. /* Give up on data, request rtx of events */
  1691. brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
  1692. rdlen, chan);
  1693. bus->sdiodev->bus_if->dstats.rx_dropped++;
  1694. brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
  1695. continue;
  1696. }
  1697. /* Leave room for what we already read, and align remainder */
  1698. skb_pull(pkt, BRCMF_FIRSTREAD);
  1699. pkt_align(pkt, rdlen, BRCMF_SDALIGN);
  1700. /* Read the remaining frame data */
  1701. sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1702. SDIO_FUNC_2, F2SYNC, pkt);
  1703. bus->f2rxdata++;
  1704. if (sdret < 0) {
  1705. brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
  1706. ((chan == SDPCM_EVENT_CHANNEL) ? "event"
  1707. : ((chan == SDPCM_DATA_CHANNEL) ? "data"
  1708. : "test")), sdret);
  1709. brcmu_pkt_buf_free_skb(pkt);
  1710. bus->sdiodev->bus_if->dstats.rx_errors++;
  1711. brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
  1712. continue;
  1713. }
  1714. /* Copy the already-read portion */
  1715. skb_push(pkt, BRCMF_FIRSTREAD);
  1716. memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
  1717. #ifdef BCMDBG
  1718. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1719. printk(KERN_DEBUG "Rx Data:\n");
  1720. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1721. pkt->data, len);
  1722. }
  1723. #endif
  1724. deliver:
  1725. /* Save superframe descriptor and allocate packet frame */
  1726. if (chan == SDPCM_GLOM_CHANNEL) {
  1727. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
  1728. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1729. len);
  1730. #ifdef BCMDBG
  1731. if (BRCMF_GLOM_ON()) {
  1732. printk(KERN_DEBUG "Glom Data:\n");
  1733. print_hex_dump_bytes("",
  1734. DUMP_PREFIX_OFFSET,
  1735. pkt->data, len);
  1736. }
  1737. #endif
  1738. __skb_trim(pkt, len);
  1739. skb_pull(pkt, SDPCM_HDRLEN);
  1740. bus->glomd = pkt;
  1741. } else {
  1742. brcmf_dbg(ERROR, "%s: glom superframe w/o "
  1743. "descriptor!\n", __func__);
  1744. brcmf_sdbrcm_rxfail(bus, false, false);
  1745. }
  1746. continue;
  1747. }
  1748. /* Fill in packet len and prio, deliver upward */
  1749. __skb_trim(pkt, len);
  1750. skb_pull(pkt, doff);
  1751. if (pkt->len == 0) {
  1752. brcmu_pkt_buf_free_skb(pkt);
  1753. continue;
  1754. } else if (brcmf_proto_hdrpull(bus->sdiodev->dev, &ifidx,
  1755. pkt) != 0) {
  1756. brcmf_dbg(ERROR, "rx protocol error\n");
  1757. brcmu_pkt_buf_free_skb(pkt);
  1758. bus->sdiodev->bus_if->dstats.rx_errors++;
  1759. continue;
  1760. }
  1761. /* Unlock during rx call */
  1762. up(&bus->sdsem);
  1763. brcmf_rx_packet(bus->sdiodev->dev, ifidx, pkt);
  1764. down(&bus->sdsem);
  1765. }
  1766. rxcount = maxframes - rxleft;
  1767. #ifdef BCMDBG
  1768. /* Message if we hit the limit */
  1769. if (!rxleft)
  1770. brcmf_dbg(DATA, "hit rx limit of %d frames\n",
  1771. maxframes);
  1772. else
  1773. #endif /* BCMDBG */
  1774. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1775. /* Back off rxseq if awaiting rtx, update rx_seq */
  1776. if (bus->rxskip)
  1777. rxseq--;
  1778. bus->rx_seq = rxseq;
  1779. return rxcount;
  1780. }
  1781. static void
  1782. brcmf_sdbrcm_wait_for_event(struct brcmf_sdio *bus, bool *lockvar)
  1783. {
  1784. up(&bus->sdsem);
  1785. wait_event_interruptible_timeout(bus->ctrl_wait,
  1786. (*lockvar == false), HZ * 2);
  1787. down(&bus->sdsem);
  1788. return;
  1789. }
  1790. static void
  1791. brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
  1792. {
  1793. if (waitqueue_active(&bus->ctrl_wait))
  1794. wake_up_interruptible(&bus->ctrl_wait);
  1795. return;
  1796. }
  1797. /* Writes a HW/SW header into the packet and sends it. */
  1798. /* Assumes: (a) header space already there, (b) caller holds lock */
  1799. static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
  1800. uint chan, bool free_pkt)
  1801. {
  1802. int ret;
  1803. u8 *frame;
  1804. u16 len, pad = 0;
  1805. u32 swheader;
  1806. struct sk_buff *new;
  1807. int i;
  1808. brcmf_dbg(TRACE, "Enter\n");
  1809. frame = (u8 *) (pkt->data);
  1810. /* Add alignment padding, allocate new packet if needed */
  1811. pad = ((unsigned long)frame % BRCMF_SDALIGN);
  1812. if (pad) {
  1813. if (skb_headroom(pkt) < pad) {
  1814. brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
  1815. skb_headroom(pkt), pad);
  1816. bus->sdiodev->bus_if->tx_realloc++;
  1817. new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
  1818. if (!new) {
  1819. brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
  1820. pkt->len + BRCMF_SDALIGN);
  1821. ret = -ENOMEM;
  1822. goto done;
  1823. }
  1824. pkt_align(new, pkt->len, BRCMF_SDALIGN);
  1825. memcpy(new->data, pkt->data, pkt->len);
  1826. if (free_pkt)
  1827. brcmu_pkt_buf_free_skb(pkt);
  1828. /* free the pkt if canned one is not used */
  1829. free_pkt = true;
  1830. pkt = new;
  1831. frame = (u8 *) (pkt->data);
  1832. /* precondition: (frame % BRCMF_SDALIGN) == 0) */
  1833. pad = 0;
  1834. } else {
  1835. skb_push(pkt, pad);
  1836. frame = (u8 *) (pkt->data);
  1837. /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
  1838. memset(frame, 0, pad + SDPCM_HDRLEN);
  1839. }
  1840. }
  1841. /* precondition: pad < BRCMF_SDALIGN */
  1842. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  1843. len = (u16) (pkt->len);
  1844. *(__le16 *) frame = cpu_to_le16(len);
  1845. *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
  1846. /* Software tag: channel, sequence number, data offset */
  1847. swheader =
  1848. ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
  1849. (((pad +
  1850. SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
  1851. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  1852. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  1853. #ifdef BCMDBG
  1854. tx_packets[pkt->priority]++;
  1855. if (BRCMF_BYTES_ON() &&
  1856. (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
  1857. (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
  1858. printk(KERN_DEBUG "Tx Frame:\n");
  1859. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
  1860. } else if (BRCMF_HDRS_ON()) {
  1861. printk(KERN_DEBUG "TxHdr:\n");
  1862. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1863. frame, min_t(u16, len, 16));
  1864. }
  1865. #endif
  1866. /* Raise len to next SDIO block to eliminate tail command */
  1867. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  1868. u16 pad = bus->blocksize - (len % bus->blocksize);
  1869. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  1870. len += pad;
  1871. } else if (len % BRCMF_SDALIGN) {
  1872. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  1873. }
  1874. /* Some controllers have trouble with odd bytes -- round to even */
  1875. if (len & (ALIGNMENT - 1))
  1876. len = roundup(len, ALIGNMENT);
  1877. ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1878. SDIO_FUNC_2, F2SYNC, pkt);
  1879. bus->f2txdata++;
  1880. if (ret < 0) {
  1881. /* On failure, abort the command and terminate the frame */
  1882. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  1883. ret);
  1884. bus->tx_sderrs++;
  1885. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  1886. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  1887. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  1888. NULL);
  1889. bus->f1regdata++;
  1890. for (i = 0; i < 3; i++) {
  1891. u8 hi, lo;
  1892. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  1893. SDIO_FUNC_1,
  1894. SBSDIO_FUNC1_WFRAMEBCHI,
  1895. NULL);
  1896. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  1897. SDIO_FUNC_1,
  1898. SBSDIO_FUNC1_WFRAMEBCLO,
  1899. NULL);
  1900. bus->f1regdata += 2;
  1901. if ((hi == 0) && (lo == 0))
  1902. break;
  1903. }
  1904. }
  1905. if (ret == 0)
  1906. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  1907. done:
  1908. /* restore pkt buffer pointer before calling tx complete routine */
  1909. skb_pull(pkt, SDPCM_HDRLEN + pad);
  1910. up(&bus->sdsem);
  1911. brcmf_txcomplete(bus->sdiodev->dev, pkt, ret != 0);
  1912. down(&bus->sdsem);
  1913. if (free_pkt)
  1914. brcmu_pkt_buf_free_skb(pkt);
  1915. return ret;
  1916. }
  1917. static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
  1918. {
  1919. struct sk_buff *pkt;
  1920. u32 intstatus = 0;
  1921. uint retries = 0;
  1922. int ret = 0, prec_out;
  1923. uint cnt = 0;
  1924. uint datalen;
  1925. u8 tx_prec_map;
  1926. brcmf_dbg(TRACE, "Enter\n");
  1927. tx_prec_map = ~bus->flowcontrol;
  1928. /* Send frames until the limit or some other event */
  1929. for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
  1930. spin_lock_bh(&bus->txqlock);
  1931. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
  1932. if (pkt == NULL) {
  1933. spin_unlock_bh(&bus->txqlock);
  1934. break;
  1935. }
  1936. spin_unlock_bh(&bus->txqlock);
  1937. datalen = pkt->len - SDPCM_HDRLEN;
  1938. ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
  1939. if (ret)
  1940. bus->sdiodev->bus_if->dstats.tx_errors++;
  1941. else
  1942. bus->sdiodev->bus_if->dstats.tx_bytes += datalen;
  1943. /* In poll mode, need to check for other events */
  1944. if (!bus->intr && cnt) {
  1945. /* Check device status, signal pending interrupt */
  1946. r_sdreg32(bus, &intstatus,
  1947. offsetof(struct sdpcmd_regs, intstatus),
  1948. &retries);
  1949. bus->f2txdata++;
  1950. if (brcmf_sdcard_regfail(bus->sdiodev))
  1951. break;
  1952. if (intstatus & bus->hostintmask)
  1953. bus->ipend = true;
  1954. }
  1955. }
  1956. /* Deflow-control stack if needed */
  1957. if (bus->sdiodev->bus_if->drvr_up &&
  1958. (bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) &&
  1959. bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
  1960. bus->txoff = OFF;
  1961. brcmf_txflowcontrol(bus->sdiodev->dev, 0, OFF);
  1962. }
  1963. return cnt;
  1964. }
  1965. static void brcmf_sdbrcm_bus_stop(struct device *dev)
  1966. {
  1967. u32 local_hostintmask;
  1968. u8 saveclk;
  1969. uint retries;
  1970. int err;
  1971. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  1972. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  1973. struct brcmf_sdio *bus = sdiodev->bus;
  1974. brcmf_dbg(TRACE, "Enter\n");
  1975. if (bus->watchdog_tsk) {
  1976. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  1977. kthread_stop(bus->watchdog_tsk);
  1978. bus->watchdog_tsk = NULL;
  1979. }
  1980. if (bus->dpc_tsk && bus->dpc_tsk != current) {
  1981. send_sig(SIGTERM, bus->dpc_tsk, 1);
  1982. kthread_stop(bus->dpc_tsk);
  1983. bus->dpc_tsk = NULL;
  1984. }
  1985. down(&bus->sdsem);
  1986. bus_wake(bus);
  1987. /* Enable clock for device interrupts */
  1988. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  1989. /* Disable and clear interrupts at the chip level also */
  1990. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
  1991. local_hostintmask = bus->hostintmask;
  1992. bus->hostintmask = 0;
  1993. /* Change our idea of bus state */
  1994. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  1995. /* Force clocks on backplane to be sure F2 interrupt propagates */
  1996. saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1997. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  1998. if (!err) {
  1999. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2000. SBSDIO_FUNC1_CHIPCLKCSR,
  2001. (saveclk | SBSDIO_FORCE_HT), &err);
  2002. }
  2003. if (err)
  2004. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2005. /* Turn off the bus (F2), free any pending packets */
  2006. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  2007. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2008. SDIO_FUNC_ENABLE_1, NULL);
  2009. /* Clear any pending interrupts now that F2 is disabled */
  2010. w_sdreg32(bus, local_hostintmask,
  2011. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2012. /* Turn off the backplane clock (only) */
  2013. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2014. /* Clear the data packet queues */
  2015. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  2016. /* Clear any held glomming stuff */
  2017. if (bus->glomd)
  2018. brcmu_pkt_buf_free_skb(bus->glomd);
  2019. brcmf_sdbrcm_free_glom(bus);
  2020. /* Clear rx control and wake any waiters */
  2021. bus->rxlen = 0;
  2022. brcmf_sdbrcm_dcmd_resp_wake(bus);
  2023. /* Reset some F2 state stuff */
  2024. bus->rxskip = false;
  2025. bus->tx_seq = bus->rx_seq = 0;
  2026. up(&bus->sdsem);
  2027. }
  2028. static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
  2029. {
  2030. u32 intstatus, newstatus = 0;
  2031. uint retries = 0;
  2032. uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
  2033. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  2034. uint framecnt = 0; /* Temporary counter of tx/rx frames */
  2035. bool rxdone = true; /* Flag for no more read data */
  2036. bool resched = false; /* Flag indicating resched wanted */
  2037. brcmf_dbg(TRACE, "Enter\n");
  2038. /* Start with leftover status bits */
  2039. intstatus = bus->intstatus;
  2040. down(&bus->sdsem);
  2041. /* If waiting for HTAVAIL, check status */
  2042. if (bus->clkstate == CLK_PENDING) {
  2043. int err;
  2044. u8 clkctl, devctl = 0;
  2045. #ifdef BCMDBG
  2046. /* Check for inconsistent device control */
  2047. devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2048. SBSDIO_DEVICE_CTL, &err);
  2049. if (err) {
  2050. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
  2051. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2052. }
  2053. #endif /* BCMDBG */
  2054. /* Read CSR, if clock on switch to AVAIL, else ignore */
  2055. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2056. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2057. if (err) {
  2058. brcmf_dbg(ERROR, "error reading CSR: %d\n",
  2059. err);
  2060. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2061. }
  2062. brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  2063. devctl, clkctl);
  2064. if (SBSDIO_HTAV(clkctl)) {
  2065. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  2066. SDIO_FUNC_1,
  2067. SBSDIO_DEVICE_CTL, &err);
  2068. if (err) {
  2069. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
  2070. err);
  2071. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2072. }
  2073. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  2074. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2075. SBSDIO_DEVICE_CTL, devctl, &err);
  2076. if (err) {
  2077. brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
  2078. err);
  2079. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2080. }
  2081. bus->clkstate = CLK_AVAIL;
  2082. } else {
  2083. goto clkwait;
  2084. }
  2085. }
  2086. bus_wake(bus);
  2087. /* Make sure backplane clock is on */
  2088. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
  2089. if (bus->clkstate == CLK_PENDING)
  2090. goto clkwait;
  2091. /* Pending interrupt indicates new device status */
  2092. if (bus->ipend) {
  2093. bus->ipend = false;
  2094. r_sdreg32(bus, &newstatus,
  2095. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2096. bus->f1regdata++;
  2097. if (brcmf_sdcard_regfail(bus->sdiodev))
  2098. newstatus = 0;
  2099. newstatus &= bus->hostintmask;
  2100. bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
  2101. if (newstatus) {
  2102. w_sdreg32(bus, newstatus,
  2103. offsetof(struct sdpcmd_regs, intstatus),
  2104. &retries);
  2105. bus->f1regdata++;
  2106. }
  2107. }
  2108. /* Merge new bits with previous */
  2109. intstatus |= newstatus;
  2110. bus->intstatus = 0;
  2111. /* Handle flow-control change: read new state in case our ack
  2112. * crossed another change interrupt. If change still set, assume
  2113. * FC ON for safety, let next loop through do the debounce.
  2114. */
  2115. if (intstatus & I_HMB_FC_CHANGE) {
  2116. intstatus &= ~I_HMB_FC_CHANGE;
  2117. w_sdreg32(bus, I_HMB_FC_CHANGE,
  2118. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2119. r_sdreg32(bus, &newstatus,
  2120. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2121. bus->f1regdata += 2;
  2122. bus->fcstate =
  2123. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
  2124. intstatus |= (newstatus & bus->hostintmask);
  2125. }
  2126. /* Handle host mailbox indication */
  2127. if (intstatus & I_HMB_HOST_INT) {
  2128. intstatus &= ~I_HMB_HOST_INT;
  2129. intstatus |= brcmf_sdbrcm_hostmail(bus);
  2130. }
  2131. /* Generally don't ask for these, can get CRC errors... */
  2132. if (intstatus & I_WR_OOSYNC) {
  2133. brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
  2134. intstatus &= ~I_WR_OOSYNC;
  2135. }
  2136. if (intstatus & I_RD_OOSYNC) {
  2137. brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
  2138. intstatus &= ~I_RD_OOSYNC;
  2139. }
  2140. if (intstatus & I_SBINT) {
  2141. brcmf_dbg(ERROR, "Dongle reports SBINT\n");
  2142. intstatus &= ~I_SBINT;
  2143. }
  2144. /* Would be active due to wake-wlan in gSPI */
  2145. if (intstatus & I_CHIPACTIVE) {
  2146. brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
  2147. intstatus &= ~I_CHIPACTIVE;
  2148. }
  2149. /* Ignore frame indications if rxskip is set */
  2150. if (bus->rxskip)
  2151. intstatus &= ~I_HMB_FRAME_IND;
  2152. /* On frame indication, read available frames */
  2153. if (PKT_AVAILABLE()) {
  2154. framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
  2155. if (rxdone || bus->rxskip)
  2156. intstatus &= ~I_HMB_FRAME_IND;
  2157. rxlimit -= min(framecnt, rxlimit);
  2158. }
  2159. /* Keep still-pending events for next scheduling */
  2160. bus->intstatus = intstatus;
  2161. clkwait:
  2162. if (data_ok(bus) && bus->ctrl_frame_stat &&
  2163. (bus->clkstate == CLK_AVAIL)) {
  2164. int ret, i;
  2165. ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
  2166. SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
  2167. (u32) bus->ctrl_frame_len);
  2168. if (ret < 0) {
  2169. /* On failure, abort the command and
  2170. terminate the frame */
  2171. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2172. ret);
  2173. bus->tx_sderrs++;
  2174. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2175. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2176. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  2177. NULL);
  2178. bus->f1regdata++;
  2179. for (i = 0; i < 3; i++) {
  2180. u8 hi, lo;
  2181. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  2182. SDIO_FUNC_1,
  2183. SBSDIO_FUNC1_WFRAMEBCHI,
  2184. NULL);
  2185. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  2186. SDIO_FUNC_1,
  2187. SBSDIO_FUNC1_WFRAMEBCLO,
  2188. NULL);
  2189. bus->f1regdata += 2;
  2190. if ((hi == 0) && (lo == 0))
  2191. break;
  2192. }
  2193. }
  2194. if (ret == 0)
  2195. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2196. brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
  2197. bus->ctrl_frame_stat = false;
  2198. brcmf_sdbrcm_wait_event_wakeup(bus);
  2199. }
  2200. /* Send queued frames (limit 1 if rx may still be pending) */
  2201. else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
  2202. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
  2203. && data_ok(bus)) {
  2204. framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
  2205. framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
  2206. txlimit -= framecnt;
  2207. }
  2208. /* Resched if events or tx frames are pending,
  2209. else await next interrupt */
  2210. /* On failed register access, all bets are off:
  2211. no resched or interrupts */
  2212. if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) ||
  2213. brcmf_sdcard_regfail(bus->sdiodev)) {
  2214. brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
  2215. brcmf_sdcard_regfail(bus->sdiodev));
  2216. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2217. bus->intstatus = 0;
  2218. } else if (bus->clkstate == CLK_PENDING) {
  2219. brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
  2220. resched = true;
  2221. } else if (bus->intstatus || bus->ipend ||
  2222. (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
  2223. && data_ok(bus)) || PKT_AVAILABLE()) {
  2224. resched = true;
  2225. }
  2226. bus->dpc_sched = resched;
  2227. /* If we're done for now, turn off clock request. */
  2228. if ((bus->clkstate != CLK_PENDING)
  2229. && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
  2230. bus->activity = false;
  2231. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2232. }
  2233. up(&bus->sdsem);
  2234. return resched;
  2235. }
  2236. static int brcmf_sdbrcm_dpc_thread(void *data)
  2237. {
  2238. struct brcmf_sdio *bus = (struct brcmf_sdio *) data;
  2239. allow_signal(SIGTERM);
  2240. /* Run until signal received */
  2241. while (1) {
  2242. if (kthread_should_stop())
  2243. break;
  2244. if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
  2245. /* Call bus dpc unless it indicated down
  2246. (then clean stop) */
  2247. if (bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN) {
  2248. if (brcmf_sdbrcm_dpc(bus))
  2249. complete(&bus->dpc_wait);
  2250. } else {
  2251. /* after stopping the bus, exit thread */
  2252. brcmf_sdbrcm_bus_stop(bus->sdiodev->dev);
  2253. bus->dpc_tsk = NULL;
  2254. break;
  2255. }
  2256. } else
  2257. break;
  2258. }
  2259. return 0;
  2260. }
  2261. static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
  2262. {
  2263. int ret = -EBADE;
  2264. uint datalen, prec;
  2265. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2266. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2267. struct brcmf_sdio *bus = sdiodev->bus;
  2268. brcmf_dbg(TRACE, "Enter\n");
  2269. datalen = pkt->len;
  2270. /* Add space for the header */
  2271. skb_push(pkt, SDPCM_HDRLEN);
  2272. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2273. prec = prio2prec((pkt->priority & PRIOMASK));
  2274. /* Check for existing queue, current flow-control,
  2275. pending event, or pending clock */
  2276. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2277. bus->fcqueued++;
  2278. /* Priority based enq */
  2279. spin_lock_bh(&bus->txqlock);
  2280. if (brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec) ==
  2281. false) {
  2282. skb_pull(pkt, SDPCM_HDRLEN);
  2283. brcmf_txcomplete(bus->sdiodev->dev, pkt, false);
  2284. brcmu_pkt_buf_free_skb(pkt);
  2285. brcmf_dbg(ERROR, "out of bus->txq !!!\n");
  2286. ret = -ENOSR;
  2287. } else {
  2288. ret = 0;
  2289. }
  2290. spin_unlock_bh(&bus->txqlock);
  2291. if (pktq_len(&bus->txq) >= TXHI) {
  2292. bus->txoff = ON;
  2293. brcmf_txflowcontrol(bus->sdiodev->dev, 0, ON);
  2294. }
  2295. #ifdef BCMDBG
  2296. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2297. qcount[prec] = pktq_plen(&bus->txq, prec);
  2298. #endif
  2299. /* Schedule DPC if needed to send queued packet(s) */
  2300. if (!bus->dpc_sched) {
  2301. bus->dpc_sched = true;
  2302. if (bus->dpc_tsk)
  2303. complete(&bus->dpc_wait);
  2304. }
  2305. return ret;
  2306. }
  2307. static int
  2308. brcmf_sdbrcm_membytes(struct brcmf_sdio *bus, bool write, u32 address, u8 *data,
  2309. uint size)
  2310. {
  2311. int bcmerror = 0;
  2312. u32 sdaddr;
  2313. uint dsize;
  2314. /* Determine initial transfer parameters */
  2315. sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
  2316. if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
  2317. dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
  2318. else
  2319. dsize = size;
  2320. /* Set the backplane window to include the start address */
  2321. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
  2322. if (bcmerror) {
  2323. brcmf_dbg(ERROR, "window change failed\n");
  2324. goto xfer_done;
  2325. }
  2326. /* Do the transfer(s) */
  2327. while (size) {
  2328. brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
  2329. write ? "write" : "read", dsize,
  2330. sdaddr, address & SBSDIO_SBWINDOW_MASK);
  2331. bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
  2332. sdaddr, data, dsize);
  2333. if (bcmerror) {
  2334. brcmf_dbg(ERROR, "membytes transfer failed\n");
  2335. break;
  2336. }
  2337. /* Adjust for next transfer (if any) */
  2338. size -= dsize;
  2339. if (size) {
  2340. data += dsize;
  2341. address += dsize;
  2342. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
  2343. address);
  2344. if (bcmerror) {
  2345. brcmf_dbg(ERROR, "window change failed\n");
  2346. break;
  2347. }
  2348. sdaddr = 0;
  2349. dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
  2350. }
  2351. }
  2352. xfer_done:
  2353. /* Return the window to backplane enumeration space for core access */
  2354. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
  2355. brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
  2356. bus->sdiodev->sbwad);
  2357. return bcmerror;
  2358. }
  2359. #ifdef BCMDBG
  2360. #define CONSOLE_LINE_MAX 192
  2361. static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
  2362. {
  2363. struct brcmf_console *c = &bus->console;
  2364. u8 line[CONSOLE_LINE_MAX], ch;
  2365. u32 n, idx, addr;
  2366. int rv;
  2367. /* Don't do anything until FWREADY updates console address */
  2368. if (bus->console_addr == 0)
  2369. return 0;
  2370. /* Read console log struct */
  2371. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2372. rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
  2373. sizeof(c->log_le));
  2374. if (rv < 0)
  2375. return rv;
  2376. /* Allocate console buffer (one time only) */
  2377. if (c->buf == NULL) {
  2378. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2379. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2380. if (c->buf == NULL)
  2381. return -ENOMEM;
  2382. }
  2383. idx = le32_to_cpu(c->log_le.idx);
  2384. /* Protect against corrupt value */
  2385. if (idx > c->bufsize)
  2386. return -EBADE;
  2387. /* Skip reading the console buffer if the index pointer
  2388. has not moved */
  2389. if (idx == c->last)
  2390. return 0;
  2391. /* Read the console buffer */
  2392. addr = le32_to_cpu(c->log_le.buf);
  2393. rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
  2394. if (rv < 0)
  2395. return rv;
  2396. while (c->last != idx) {
  2397. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2398. if (c->last == idx) {
  2399. /* This would output a partial line.
  2400. * Instead, back up
  2401. * the buffer pointer and output this
  2402. * line next time around.
  2403. */
  2404. if (c->last >= n)
  2405. c->last -= n;
  2406. else
  2407. c->last = c->bufsize - n;
  2408. goto break2;
  2409. }
  2410. ch = c->buf[c->last];
  2411. c->last = (c->last + 1) % c->bufsize;
  2412. if (ch == '\n')
  2413. break;
  2414. line[n] = ch;
  2415. }
  2416. if (n > 0) {
  2417. if (line[n - 1] == '\r')
  2418. n--;
  2419. line[n] = 0;
  2420. printk(KERN_DEBUG "CONSOLE: %s\n", line);
  2421. }
  2422. }
  2423. break2:
  2424. return 0;
  2425. }
  2426. #endif /* BCMDBG */
  2427. static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
  2428. {
  2429. int i;
  2430. int ret;
  2431. bus->ctrl_frame_stat = false;
  2432. ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
  2433. SDIO_FUNC_2, F2SYNC, frame, len);
  2434. if (ret < 0) {
  2435. /* On failure, abort the command and terminate the frame */
  2436. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2437. ret);
  2438. bus->tx_sderrs++;
  2439. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2440. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2441. SBSDIO_FUNC1_FRAMECTRL,
  2442. SFC_WF_TERM, NULL);
  2443. bus->f1regdata++;
  2444. for (i = 0; i < 3; i++) {
  2445. u8 hi, lo;
  2446. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2447. SBSDIO_FUNC1_WFRAMEBCHI,
  2448. NULL);
  2449. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2450. SBSDIO_FUNC1_WFRAMEBCLO,
  2451. NULL);
  2452. bus->f1regdata += 2;
  2453. if (hi == 0 && lo == 0)
  2454. break;
  2455. }
  2456. return ret;
  2457. }
  2458. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2459. return ret;
  2460. }
  2461. static int
  2462. brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
  2463. {
  2464. u8 *frame;
  2465. u16 len;
  2466. u32 swheader;
  2467. uint retries = 0;
  2468. u8 doff = 0;
  2469. int ret = -1;
  2470. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2471. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2472. struct brcmf_sdio *bus = sdiodev->bus;
  2473. brcmf_dbg(TRACE, "Enter\n");
  2474. /* Back the pointer to make a room for bus header */
  2475. frame = msg - SDPCM_HDRLEN;
  2476. len = (msglen += SDPCM_HDRLEN);
  2477. /* Add alignment padding (optional for ctl frames) */
  2478. doff = ((unsigned long)frame % BRCMF_SDALIGN);
  2479. if (doff) {
  2480. frame -= doff;
  2481. len += doff;
  2482. msglen += doff;
  2483. memset(frame, 0, doff + SDPCM_HDRLEN);
  2484. }
  2485. /* precondition: doff < BRCMF_SDALIGN */
  2486. doff += SDPCM_HDRLEN;
  2487. /* Round send length to next SDIO block */
  2488. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2489. u16 pad = bus->blocksize - (len % bus->blocksize);
  2490. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  2491. len += pad;
  2492. } else if (len % BRCMF_SDALIGN) {
  2493. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  2494. }
  2495. /* Satisfy length-alignment requirements */
  2496. if (len & (ALIGNMENT - 1))
  2497. len = roundup(len, ALIGNMENT);
  2498. /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
  2499. /* Need to lock here to protect txseq and SDIO tx calls */
  2500. down(&bus->sdsem);
  2501. bus_wake(bus);
  2502. /* Make sure backplane clock is on */
  2503. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2504. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  2505. *(__le16 *) frame = cpu_to_le16((u16) msglen);
  2506. *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
  2507. /* Software tag: channel, sequence number, data offset */
  2508. swheader =
  2509. ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
  2510. SDPCM_CHANNEL_MASK)
  2511. | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
  2512. SDPCM_DOFFSET_MASK);
  2513. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  2514. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  2515. if (!data_ok(bus)) {
  2516. brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
  2517. bus->tx_max, bus->tx_seq);
  2518. bus->ctrl_frame_stat = true;
  2519. /* Send from dpc */
  2520. bus->ctrl_frame_buf = frame;
  2521. bus->ctrl_frame_len = len;
  2522. brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
  2523. if (bus->ctrl_frame_stat == false) {
  2524. brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
  2525. ret = 0;
  2526. } else {
  2527. brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
  2528. ret = -1;
  2529. }
  2530. }
  2531. if (ret == -1) {
  2532. #ifdef BCMDBG
  2533. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  2534. printk(KERN_DEBUG "Tx Frame:\n");
  2535. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2536. frame, len);
  2537. } else if (BRCMF_HDRS_ON()) {
  2538. printk(KERN_DEBUG "TxHdr:\n");
  2539. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2540. frame, min_t(u16, len, 16));
  2541. }
  2542. #endif
  2543. do {
  2544. ret = brcmf_tx_frame(bus, frame, len);
  2545. } while (ret < 0 && retries++ < TXRETRIES);
  2546. }
  2547. if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
  2548. bus->activity = false;
  2549. brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
  2550. }
  2551. up(&bus->sdsem);
  2552. if (ret)
  2553. bus->tx_ctlerrs++;
  2554. else
  2555. bus->tx_ctlpkts++;
  2556. return ret ? -EIO : 0;
  2557. }
  2558. static int
  2559. brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
  2560. {
  2561. int timeleft;
  2562. uint rxlen = 0;
  2563. bool pending;
  2564. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2565. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2566. struct brcmf_sdio *bus = sdiodev->bus;
  2567. brcmf_dbg(TRACE, "Enter\n");
  2568. /* Wait until control frame is available */
  2569. timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2570. down(&bus->sdsem);
  2571. rxlen = bus->rxlen;
  2572. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2573. bus->rxlen = 0;
  2574. up(&bus->sdsem);
  2575. if (rxlen) {
  2576. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2577. rxlen, msglen);
  2578. } else if (timeleft == 0) {
  2579. brcmf_dbg(ERROR, "resumed on timeout\n");
  2580. } else if (pending == true) {
  2581. brcmf_dbg(CTL, "cancelled\n");
  2582. return -ERESTARTSYS;
  2583. } else {
  2584. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2585. }
  2586. if (rxlen)
  2587. bus->rx_ctlpkts++;
  2588. else
  2589. bus->rx_ctlerrs++;
  2590. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2591. }
  2592. static int brcmf_sdbrcm_downloadvars(struct brcmf_sdio *bus, void *arg, int len)
  2593. {
  2594. int bcmerror = 0;
  2595. brcmf_dbg(TRACE, "Enter\n");
  2596. /* Basic sanity checks */
  2597. if (bus->sdiodev->bus_if->drvr_up) {
  2598. bcmerror = -EISCONN;
  2599. goto err;
  2600. }
  2601. if (!len) {
  2602. bcmerror = -EOVERFLOW;
  2603. goto err;
  2604. }
  2605. /* Free the old ones and replace with passed variables */
  2606. kfree(bus->vars);
  2607. bus->vars = kmalloc(len, GFP_ATOMIC);
  2608. bus->varsz = bus->vars ? len : 0;
  2609. if (bus->vars == NULL) {
  2610. bcmerror = -ENOMEM;
  2611. goto err;
  2612. }
  2613. /* Copy the passed variables, which should include the
  2614. terminating double-null */
  2615. memcpy(bus->vars, arg, bus->varsz);
  2616. err:
  2617. return bcmerror;
  2618. }
  2619. static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
  2620. {
  2621. int bcmerror = 0;
  2622. u32 varsize;
  2623. u32 varaddr;
  2624. u8 *vbuffer;
  2625. u32 varsizew;
  2626. __le32 varsizew_le;
  2627. #ifdef BCMDBG
  2628. char *nvram_ularray;
  2629. #endif /* BCMDBG */
  2630. /* Even if there are no vars are to be written, we still
  2631. need to set the ramsize. */
  2632. varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
  2633. varaddr = (bus->ramsize - 4) - varsize;
  2634. if (bus->vars) {
  2635. vbuffer = kzalloc(varsize, GFP_ATOMIC);
  2636. if (!vbuffer)
  2637. return -ENOMEM;
  2638. memcpy(vbuffer, bus->vars, bus->varsz);
  2639. /* Write the vars list */
  2640. bcmerror =
  2641. brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
  2642. #ifdef BCMDBG
  2643. /* Verify NVRAM bytes */
  2644. brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
  2645. nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
  2646. if (!nvram_ularray)
  2647. return -ENOMEM;
  2648. /* Upload image to verify downloaded contents. */
  2649. memset(nvram_ularray, 0xaa, varsize);
  2650. /* Read the vars list to temp buffer for comparison */
  2651. bcmerror =
  2652. brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
  2653. varsize);
  2654. if (bcmerror) {
  2655. brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
  2656. bcmerror, varsize, varaddr);
  2657. }
  2658. /* Compare the org NVRAM with the one read from RAM */
  2659. if (memcmp(vbuffer, nvram_ularray, varsize))
  2660. brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
  2661. else
  2662. brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
  2663. kfree(nvram_ularray);
  2664. #endif /* BCMDBG */
  2665. kfree(vbuffer);
  2666. }
  2667. /* adjust to the user specified RAM */
  2668. brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
  2669. brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
  2670. varaddr, varsize);
  2671. varsize = ((bus->ramsize - 4) - varaddr);
  2672. /*
  2673. * Determine the length token:
  2674. * Varsize, converted to words, in lower 16-bits, checksum
  2675. * in upper 16-bits.
  2676. */
  2677. if (bcmerror) {
  2678. varsizew = 0;
  2679. varsizew_le = cpu_to_le32(0);
  2680. } else {
  2681. varsizew = varsize / 4;
  2682. varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
  2683. varsizew_le = cpu_to_le32(varsizew);
  2684. }
  2685. brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
  2686. varsize, varsizew);
  2687. /* Write the length token to the last word */
  2688. bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
  2689. (u8 *)&varsizew_le, 4);
  2690. return bcmerror;
  2691. }
  2692. static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
  2693. {
  2694. uint retries;
  2695. int bcmerror = 0;
  2696. struct chip_info *ci = bus->ci;
  2697. /* To enter download state, disable ARM and reset SOCRAM.
  2698. * To exit download state, simply reset ARM (default is RAM boot).
  2699. */
  2700. if (enter) {
  2701. bus->alp_only = true;
  2702. ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
  2703. ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
  2704. /* Clear the top bit of memory */
  2705. if (bus->ramsize) {
  2706. u32 zeros = 0;
  2707. brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
  2708. (u8 *)&zeros, 4);
  2709. }
  2710. } else {
  2711. if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
  2712. brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
  2713. bcmerror = -EBADE;
  2714. goto fail;
  2715. }
  2716. bcmerror = brcmf_sdbrcm_write_vars(bus);
  2717. if (bcmerror) {
  2718. brcmf_dbg(ERROR, "no vars written to RAM\n");
  2719. bcmerror = 0;
  2720. }
  2721. w_sdreg32(bus, 0xFFFFFFFF,
  2722. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2723. ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
  2724. /* Allow HT Clock now that the ARM is running. */
  2725. bus->alp_only = false;
  2726. bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD;
  2727. }
  2728. fail:
  2729. return bcmerror;
  2730. }
  2731. static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
  2732. {
  2733. if (bus->firmware->size < bus->fw_ptr + len)
  2734. len = bus->firmware->size - bus->fw_ptr;
  2735. memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
  2736. bus->fw_ptr += len;
  2737. return len;
  2738. }
  2739. static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
  2740. {
  2741. int offset = 0;
  2742. uint len;
  2743. u8 *memblock = NULL, *memptr;
  2744. int ret;
  2745. brcmf_dbg(INFO, "Enter\n");
  2746. ret = request_firmware(&bus->firmware, BRCMFMAC_FW_NAME,
  2747. &bus->sdiodev->func[2]->dev);
  2748. if (ret) {
  2749. brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
  2750. return ret;
  2751. }
  2752. bus->fw_ptr = 0;
  2753. memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
  2754. if (memblock == NULL) {
  2755. ret = -ENOMEM;
  2756. goto err;
  2757. }
  2758. if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
  2759. memptr += (BRCMF_SDALIGN -
  2760. ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
  2761. /* Download image */
  2762. while ((len =
  2763. brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
  2764. ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
  2765. if (ret) {
  2766. brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
  2767. ret, MEMBLOCK, offset);
  2768. goto err;
  2769. }
  2770. offset += MEMBLOCK;
  2771. }
  2772. err:
  2773. kfree(memblock);
  2774. release_firmware(bus->firmware);
  2775. bus->fw_ptr = 0;
  2776. return ret;
  2777. }
  2778. /*
  2779. * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
  2780. * and ending in a NUL.
  2781. * Removes carriage returns, empty lines, comment lines, and converts
  2782. * newlines to NULs.
  2783. * Shortens buffer as needed and pads with NULs. End of buffer is marked
  2784. * by two NULs.
  2785. */
  2786. static uint brcmf_process_nvram_vars(char *varbuf, uint len)
  2787. {
  2788. char *dp;
  2789. bool findNewline;
  2790. int column;
  2791. uint buf_len, n;
  2792. dp = varbuf;
  2793. findNewline = false;
  2794. column = 0;
  2795. for (n = 0; n < len; n++) {
  2796. if (varbuf[n] == 0)
  2797. break;
  2798. if (varbuf[n] == '\r')
  2799. continue;
  2800. if (findNewline && varbuf[n] != '\n')
  2801. continue;
  2802. findNewline = false;
  2803. if (varbuf[n] == '#') {
  2804. findNewline = true;
  2805. continue;
  2806. }
  2807. if (varbuf[n] == '\n') {
  2808. if (column == 0)
  2809. continue;
  2810. *dp++ = 0;
  2811. column = 0;
  2812. continue;
  2813. }
  2814. *dp++ = varbuf[n];
  2815. column++;
  2816. }
  2817. buf_len = dp - varbuf;
  2818. while (dp < varbuf + n)
  2819. *dp++ = 0;
  2820. return buf_len;
  2821. }
  2822. static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
  2823. {
  2824. uint len;
  2825. char *memblock = NULL;
  2826. char *bufp;
  2827. int ret;
  2828. ret = request_firmware(&bus->firmware, BRCMFMAC_NV_NAME,
  2829. &bus->sdiodev->func[2]->dev);
  2830. if (ret) {
  2831. brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
  2832. return ret;
  2833. }
  2834. bus->fw_ptr = 0;
  2835. memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
  2836. if (memblock == NULL) {
  2837. ret = -ENOMEM;
  2838. goto err;
  2839. }
  2840. len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
  2841. if (len > 0 && len < MEMBLOCK) {
  2842. bufp = (char *)memblock;
  2843. bufp[len] = 0;
  2844. len = brcmf_process_nvram_vars(bufp, len);
  2845. bufp += len;
  2846. *bufp++ = 0;
  2847. if (len)
  2848. ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
  2849. if (ret)
  2850. brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
  2851. } else {
  2852. brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
  2853. ret = -EIO;
  2854. }
  2855. err:
  2856. kfree(memblock);
  2857. release_firmware(bus->firmware);
  2858. bus->fw_ptr = 0;
  2859. return ret;
  2860. }
  2861. static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
  2862. {
  2863. int bcmerror = -1;
  2864. /* Keep arm in reset */
  2865. if (brcmf_sdbrcm_download_state(bus, true)) {
  2866. brcmf_dbg(ERROR, "error placing ARM core in reset\n");
  2867. goto err;
  2868. }
  2869. /* External image takes precedence if specified */
  2870. if (brcmf_sdbrcm_download_code_file(bus)) {
  2871. brcmf_dbg(ERROR, "dongle image file download failed\n");
  2872. goto err;
  2873. }
  2874. /* External nvram takes precedence if specified */
  2875. if (brcmf_sdbrcm_download_nvram(bus))
  2876. brcmf_dbg(ERROR, "dongle nvram file download failed\n");
  2877. /* Take arm out of reset */
  2878. if (brcmf_sdbrcm_download_state(bus, false)) {
  2879. brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
  2880. goto err;
  2881. }
  2882. bcmerror = 0;
  2883. err:
  2884. return bcmerror;
  2885. }
  2886. static bool
  2887. brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
  2888. {
  2889. bool ret;
  2890. /* Download the firmware */
  2891. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2892. ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
  2893. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2894. return ret;
  2895. }
  2896. static int brcmf_sdbrcm_bus_init(struct device *dev)
  2897. {
  2898. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2899. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2900. struct brcmf_sdio *bus = sdiodev->bus;
  2901. unsigned long timeout;
  2902. uint retries = 0;
  2903. u8 ready, enable;
  2904. int err, ret = 0;
  2905. u8 saveclk;
  2906. brcmf_dbg(TRACE, "Enter\n");
  2907. /* try to download image and nvram to the dongle */
  2908. if (bus_if->state == BRCMF_BUS_DOWN) {
  2909. if (!(brcmf_sdbrcm_download_firmware(bus)))
  2910. return -1;
  2911. }
  2912. if (!bus->sdiodev->bus_if->drvr)
  2913. return 0;
  2914. /* Start the watchdog timer */
  2915. bus->tickcnt = 0;
  2916. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  2917. down(&bus->sdsem);
  2918. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  2919. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2920. if (bus->clkstate != CLK_AVAIL)
  2921. goto exit;
  2922. /* Force clocks on backplane to be sure F2 interrupt propagates */
  2923. saveclk =
  2924. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2925. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2926. if (!err) {
  2927. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2928. SBSDIO_FUNC1_CHIPCLKCSR,
  2929. (saveclk | SBSDIO_FORCE_HT), &err);
  2930. }
  2931. if (err) {
  2932. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2933. goto exit;
  2934. }
  2935. /* Enable function 2 (frame transfers) */
  2936. w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
  2937. offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
  2938. enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
  2939. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2940. enable, NULL);
  2941. timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
  2942. ready = 0;
  2943. while (enable != ready) {
  2944. ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
  2945. SDIO_CCCR_IORx, NULL);
  2946. if (time_after(jiffies, timeout))
  2947. break;
  2948. else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
  2949. /* prevent busy waiting if it takes too long */
  2950. msleep_interruptible(20);
  2951. }
  2952. brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
  2953. /* If F2 successfully enabled, set core and enable interrupts */
  2954. if (ready == enable) {
  2955. /* Set up the interrupt mask and enable interrupts */
  2956. bus->hostintmask = HOSTINTMASK;
  2957. w_sdreg32(bus, bus->hostintmask,
  2958. offsetof(struct sdpcmd_regs, hostintmask), &retries);
  2959. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2960. SBSDIO_WATERMARK, 8, &err);
  2961. /* Set bus state according to enable result */
  2962. bus_if->state = BRCMF_BUS_DATA;
  2963. }
  2964. else {
  2965. /* Disable F2 again */
  2966. enable = SDIO_FUNC_ENABLE_1;
  2967. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
  2968. SDIO_CCCR_IOEx, enable, NULL);
  2969. }
  2970. /* Restore previous clock setting */
  2971. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2972. SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
  2973. /* If we didn't come up, turn off backplane clock */
  2974. if (bus_if->state != BRCMF_BUS_DATA)
  2975. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2976. exit:
  2977. up(&bus->sdsem);
  2978. return ret;
  2979. }
  2980. void brcmf_sdbrcm_isr(void *arg)
  2981. {
  2982. struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
  2983. brcmf_dbg(TRACE, "Enter\n");
  2984. if (!bus) {
  2985. brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
  2986. return;
  2987. }
  2988. if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
  2989. brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
  2990. return;
  2991. }
  2992. /* Count the interrupt call */
  2993. bus->intrcount++;
  2994. bus->ipend = true;
  2995. /* Shouldn't get this interrupt if we're sleeping? */
  2996. if (bus->sleeping) {
  2997. brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
  2998. return;
  2999. }
  3000. /* Disable additional interrupts (is this needed now)? */
  3001. if (!bus->intr)
  3002. brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
  3003. bus->dpc_sched = true;
  3004. if (bus->dpc_tsk)
  3005. complete(&bus->dpc_wait);
  3006. }
  3007. static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
  3008. {
  3009. #ifdef BCMDBG
  3010. struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
  3011. #endif /* BCMDBG */
  3012. brcmf_dbg(TIMER, "Enter\n");
  3013. /* Ignore the timer if simulating bus down */
  3014. if (bus->sleeping)
  3015. return false;
  3016. down(&bus->sdsem);
  3017. /* Poll period: check device if appropriate. */
  3018. if (bus->poll && (++bus->polltick >= bus->pollrate)) {
  3019. u32 intstatus = 0;
  3020. /* Reset poll tick */
  3021. bus->polltick = 0;
  3022. /* Check device if no interrupts */
  3023. if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
  3024. if (!bus->dpc_sched) {
  3025. u8 devpend;
  3026. devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
  3027. SDIO_FUNC_0, SDIO_CCCR_INTx,
  3028. NULL);
  3029. intstatus =
  3030. devpend & (INTR_STATUS_FUNC1 |
  3031. INTR_STATUS_FUNC2);
  3032. }
  3033. /* If there is something, make like the ISR and
  3034. schedule the DPC */
  3035. if (intstatus) {
  3036. bus->pollcnt++;
  3037. bus->ipend = true;
  3038. bus->dpc_sched = true;
  3039. if (bus->dpc_tsk)
  3040. complete(&bus->dpc_wait);
  3041. }
  3042. }
  3043. /* Update interrupt tracking */
  3044. bus->lastintrs = bus->intrcount;
  3045. }
  3046. #ifdef BCMDBG
  3047. /* Poll for console output periodically */
  3048. if (bus_if->state == BRCMF_BUS_DATA &&
  3049. bus->console_interval != 0) {
  3050. bus->console.count += BRCMF_WD_POLL_MS;
  3051. if (bus->console.count >= bus->console_interval) {
  3052. bus->console.count -= bus->console_interval;
  3053. /* Make sure backplane clock is on */
  3054. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3055. if (brcmf_sdbrcm_readconsole(bus) < 0)
  3056. /* stop on error */
  3057. bus->console_interval = 0;
  3058. }
  3059. }
  3060. #endif /* BCMDBG */
  3061. /* On idle timeout clear activity flag and/or turn off clock */
  3062. if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
  3063. if (++bus->idlecount >= bus->idletime) {
  3064. bus->idlecount = 0;
  3065. if (bus->activity) {
  3066. bus->activity = false;
  3067. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  3068. } else {
  3069. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3070. }
  3071. }
  3072. }
  3073. up(&bus->sdsem);
  3074. return bus->ipend;
  3075. }
  3076. static bool brcmf_sdbrcm_chipmatch(u16 chipid)
  3077. {
  3078. if (chipid == BCM4329_CHIP_ID)
  3079. return true;
  3080. if (chipid == BCM4330_CHIP_ID)
  3081. return true;
  3082. return false;
  3083. }
  3084. static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
  3085. {
  3086. brcmf_dbg(TRACE, "Enter\n");
  3087. kfree(bus->rxbuf);
  3088. bus->rxctl = bus->rxbuf = NULL;
  3089. bus->rxlen = 0;
  3090. kfree(bus->databuf);
  3091. bus->databuf = NULL;
  3092. }
  3093. static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
  3094. {
  3095. brcmf_dbg(TRACE, "Enter\n");
  3096. if (bus->sdiodev->bus_if->maxctl) {
  3097. bus->rxblen =
  3098. roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
  3099. ALIGNMENT) + BRCMF_SDALIGN;
  3100. bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
  3101. if (!(bus->rxbuf))
  3102. goto fail;
  3103. }
  3104. /* Allocate buffer to receive glomed packet */
  3105. bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
  3106. if (!(bus->databuf)) {
  3107. /* release rxbuf which was already located as above */
  3108. if (!bus->rxblen)
  3109. kfree(bus->rxbuf);
  3110. goto fail;
  3111. }
  3112. /* Align the buffer */
  3113. if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
  3114. bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
  3115. ((unsigned long)bus->databuf % BRCMF_SDALIGN));
  3116. else
  3117. bus->dataptr = bus->databuf;
  3118. return true;
  3119. fail:
  3120. return false;
  3121. }
  3122. static bool
  3123. brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
  3124. {
  3125. u8 clkctl = 0;
  3126. int err = 0;
  3127. int reg_addr;
  3128. u32 reg_val;
  3129. u8 idx;
  3130. bus->alp_only = true;
  3131. /* Return the window to backplane enumeration space for core access */
  3132. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
  3133. brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
  3134. #ifdef BCMDBG
  3135. printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
  3136. brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
  3137. #endif /* BCMDBG */
  3138. /*
  3139. * Force PLL off until brcmf_sdio_chip_attach()
  3140. * programs PLL control regs
  3141. */
  3142. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3143. SBSDIO_FUNC1_CHIPCLKCSR,
  3144. BRCMF_INIT_CLKCTL1, &err);
  3145. if (!err)
  3146. clkctl =
  3147. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3148. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3149. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3150. brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3151. err, BRCMF_INIT_CLKCTL1, clkctl);
  3152. goto fail;
  3153. }
  3154. if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
  3155. brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
  3156. goto fail;
  3157. }
  3158. if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
  3159. brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
  3160. goto fail;
  3161. }
  3162. brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
  3163. SDIO_DRIVE_STRENGTH);
  3164. /* Get info on the SOCRAM cores... */
  3165. bus->ramsize = bus->ci->ramsize;
  3166. if (!(bus->ramsize)) {
  3167. brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
  3168. goto fail;
  3169. }
  3170. /* Set core control so an SDIO reset does a backplane reset */
  3171. idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  3172. reg_addr = bus->ci->c_inf[idx].base +
  3173. offsetof(struct sdpcmd_regs, corecontrol);
  3174. reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
  3175. brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
  3176. reg_val | CC_BPRESEN);
  3177. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3178. /* Locate an appropriately-aligned portion of hdrbuf */
  3179. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3180. BRCMF_SDALIGN);
  3181. /* Set the poll and/or interrupt flags */
  3182. bus->intr = true;
  3183. bus->poll = false;
  3184. if (bus->poll)
  3185. bus->pollrate = 1;
  3186. return true;
  3187. fail:
  3188. return false;
  3189. }
  3190. static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
  3191. {
  3192. brcmf_dbg(TRACE, "Enter\n");
  3193. /* Disable F2 to clear any intermediate frame state on the dongle */
  3194. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3195. SDIO_FUNC_ENABLE_1, NULL);
  3196. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  3197. bus->sleeping = false;
  3198. bus->rxflow = false;
  3199. /* Done with backplane-dependent accesses, can drop clock... */
  3200. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3201. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3202. /* ...and initialize clock/power states */
  3203. bus->clkstate = CLK_SDONLY;
  3204. bus->idletime = BRCMF_IDLE_INTERVAL;
  3205. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3206. /* Query the F2 block size, set roundup accordingly */
  3207. bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
  3208. bus->roundup = min(max_roundup, bus->blocksize);
  3209. /* bus module does not support packet chaining */
  3210. bus->use_rxchain = false;
  3211. bus->sd_rxchain = false;
  3212. return true;
  3213. }
  3214. static int
  3215. brcmf_sdbrcm_watchdog_thread(void *data)
  3216. {
  3217. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3218. allow_signal(SIGTERM);
  3219. /* Run until signal received */
  3220. while (1) {
  3221. if (kthread_should_stop())
  3222. break;
  3223. if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
  3224. brcmf_sdbrcm_bus_watchdog(bus);
  3225. /* Count the tick for reference */
  3226. bus->tickcnt++;
  3227. } else
  3228. break;
  3229. }
  3230. return 0;
  3231. }
  3232. static void
  3233. brcmf_sdbrcm_watchdog(unsigned long data)
  3234. {
  3235. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3236. if (bus->watchdog_tsk) {
  3237. complete(&bus->watchdog_wait);
  3238. /* Reschedule the watchdog */
  3239. if (bus->wd_timer_valid)
  3240. mod_timer(&bus->timer,
  3241. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3242. }
  3243. }
  3244. static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
  3245. {
  3246. brcmf_dbg(TRACE, "Enter\n");
  3247. if (bus->ci) {
  3248. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3249. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3250. brcmf_sdio_chip_detach(&bus->ci);
  3251. if (bus->vars && bus->varsz)
  3252. kfree(bus->vars);
  3253. bus->vars = NULL;
  3254. }
  3255. brcmf_dbg(TRACE, "Disconnected\n");
  3256. }
  3257. /* Detach and free everything */
  3258. static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
  3259. {
  3260. brcmf_dbg(TRACE, "Enter\n");
  3261. if (bus) {
  3262. /* De-register interrupt handler */
  3263. brcmf_sdcard_intr_dereg(bus->sdiodev);
  3264. if (bus->sdiodev->bus_if->drvr) {
  3265. brcmf_detach(bus->sdiodev->dev);
  3266. brcmf_sdbrcm_release_dongle(bus);
  3267. }
  3268. brcmf_sdbrcm_release_malloc(bus);
  3269. kfree(bus);
  3270. }
  3271. brcmf_dbg(TRACE, "Disconnected\n");
  3272. }
  3273. void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
  3274. {
  3275. int ret;
  3276. struct brcmf_sdio *bus;
  3277. brcmf_dbg(TRACE, "Enter\n");
  3278. /* We make an assumption about address window mappings:
  3279. * regsva == SI_ENUM_BASE*/
  3280. /* Allocate private bus interface state */
  3281. bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
  3282. if (!bus)
  3283. goto fail;
  3284. bus->sdiodev = sdiodev;
  3285. sdiodev->bus = bus;
  3286. skb_queue_head_init(&bus->glom);
  3287. bus->txbound = BRCMF_TXBOUND;
  3288. bus->rxbound = BRCMF_RXBOUND;
  3289. bus->txminmax = BRCMF_TXMINMAX;
  3290. bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
  3291. bus->usebufpool = false; /* Use bufpool if allocated,
  3292. else use locally malloced rxbuf */
  3293. /* attempt to attach to the dongle */
  3294. if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
  3295. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
  3296. goto fail;
  3297. }
  3298. spin_lock_init(&bus->txqlock);
  3299. init_waitqueue_head(&bus->ctrl_wait);
  3300. init_waitqueue_head(&bus->dcmd_resp_wait);
  3301. /* Set up the watchdog timer */
  3302. init_timer(&bus->timer);
  3303. bus->timer.data = (unsigned long)bus;
  3304. bus->timer.function = brcmf_sdbrcm_watchdog;
  3305. /* Initialize thread based operation and lock */
  3306. sema_init(&bus->sdsem, 1);
  3307. /* Initialize watchdog thread */
  3308. init_completion(&bus->watchdog_wait);
  3309. bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
  3310. bus, "brcmf_watchdog");
  3311. if (IS_ERR(bus->watchdog_tsk)) {
  3312. printk(KERN_WARNING
  3313. "brcmf_watchdog thread failed to start\n");
  3314. bus->watchdog_tsk = NULL;
  3315. }
  3316. /* Initialize DPC thread */
  3317. init_completion(&bus->dpc_wait);
  3318. bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
  3319. bus, "brcmf_dpc");
  3320. if (IS_ERR(bus->dpc_tsk)) {
  3321. printk(KERN_WARNING
  3322. "brcmf_dpc thread failed to start\n");
  3323. bus->dpc_tsk = NULL;
  3324. }
  3325. /* Assign bus interface call back */
  3326. bus->sdiodev->bus_if->brcmf_bus_stop = brcmf_sdbrcm_bus_stop;
  3327. bus->sdiodev->bus_if->brcmf_bus_init = brcmf_sdbrcm_bus_init;
  3328. bus->sdiodev->bus_if->brcmf_bus_txdata = brcmf_sdbrcm_bus_txdata;
  3329. bus->sdiodev->bus_if->brcmf_bus_txctl = brcmf_sdbrcm_bus_txctl;
  3330. bus->sdiodev->bus_if->brcmf_bus_rxctl = brcmf_sdbrcm_bus_rxctl;
  3331. /* Attach to the brcmf/OS/network interface */
  3332. ret = brcmf_attach(SDPCM_RESERVE, bus->sdiodev->dev);
  3333. if (ret != 0) {
  3334. brcmf_dbg(ERROR, "brcmf_attach failed\n");
  3335. goto fail;
  3336. }
  3337. /* Allocate buffers */
  3338. if (!(brcmf_sdbrcm_probe_malloc(bus))) {
  3339. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
  3340. goto fail;
  3341. }
  3342. if (!(brcmf_sdbrcm_probe_init(bus))) {
  3343. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
  3344. goto fail;
  3345. }
  3346. /* Register interrupt callback, but mask it (not operational yet). */
  3347. brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
  3348. ret = brcmf_sdcard_intr_reg(bus->sdiodev);
  3349. if (ret != 0) {
  3350. brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
  3351. goto fail;
  3352. }
  3353. brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
  3354. brcmf_dbg(INFO, "completed!!\n");
  3355. /* if firmware path present try to download and bring up bus */
  3356. ret = brcmf_bus_start(bus->sdiodev->dev);
  3357. if (ret != 0) {
  3358. if (ret == -ENOLINK) {
  3359. brcmf_dbg(ERROR, "dongle is not responding\n");
  3360. goto fail;
  3361. }
  3362. }
  3363. /* add interface and open for business */
  3364. if (brcmf_add_if(bus->sdiodev->dev, 0, "wlan%d", NULL)) {
  3365. brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
  3366. goto fail;
  3367. }
  3368. return bus;
  3369. fail:
  3370. brcmf_sdbrcm_release(bus);
  3371. return NULL;
  3372. }
  3373. void brcmf_sdbrcm_disconnect(void *ptr)
  3374. {
  3375. struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
  3376. brcmf_dbg(TRACE, "Enter\n");
  3377. if (bus)
  3378. brcmf_sdbrcm_release(bus);
  3379. brcmf_dbg(TRACE, "Disconnected\n");
  3380. }
  3381. void
  3382. brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
  3383. {
  3384. /* Totally stop the timer */
  3385. if (!wdtick && bus->wd_timer_valid == true) {
  3386. del_timer_sync(&bus->timer);
  3387. bus->wd_timer_valid = false;
  3388. bus->save_ms = wdtick;
  3389. return;
  3390. }
  3391. /* don't start the wd until fw is loaded */
  3392. if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN)
  3393. return;
  3394. if (wdtick) {
  3395. if (bus->save_ms != BRCMF_WD_POLL_MS) {
  3396. if (bus->wd_timer_valid == true)
  3397. /* Stop timer and restart at new value */
  3398. del_timer_sync(&bus->timer);
  3399. /* Create timer again when watchdog period is
  3400. dynamically changed or in the first instance
  3401. */
  3402. bus->timer.expires =
  3403. jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
  3404. add_timer(&bus->timer);
  3405. } else {
  3406. /* Re arm the timer, at last watchdog period */
  3407. mod_timer(&bus->timer,
  3408. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3409. }
  3410. bus->wd_timer_valid = true;
  3411. bus->save_ms = wdtick;
  3412. }
  3413. }