phy_n.c 131 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. IEEE 802.11n PHY support
  4. Copyright (c) 2008 Michael Buesch <m@bues.ch>
  5. Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; see the file COPYING. If not, write to
  16. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  17. Boston, MA 02110-1301, USA.
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/slab.h>
  21. #include <linux/types.h>
  22. #include "b43.h"
  23. #include "phy_n.h"
  24. #include "tables_nphy.h"
  25. #include "radio_2055.h"
  26. #include "radio_2056.h"
  27. #include "main.h"
  28. struct nphy_txgains {
  29. u16 txgm[2];
  30. u16 pga[2];
  31. u16 pad[2];
  32. u16 ipa[2];
  33. };
  34. struct nphy_iqcal_params {
  35. u16 txgm;
  36. u16 pga;
  37. u16 pad;
  38. u16 ipa;
  39. u16 cal_gain;
  40. u16 ncorr[5];
  41. };
  42. struct nphy_iq_est {
  43. s32 iq0_prod;
  44. u32 i0_pwr;
  45. u32 q0_pwr;
  46. s32 iq1_prod;
  47. u32 i1_pwr;
  48. u32 q1_pwr;
  49. };
  50. enum b43_nphy_rf_sequence {
  51. B43_RFSEQ_RX2TX,
  52. B43_RFSEQ_TX2RX,
  53. B43_RFSEQ_RESET2RX,
  54. B43_RFSEQ_UPDATE_GAINH,
  55. B43_RFSEQ_UPDATE_GAINL,
  56. B43_RFSEQ_UPDATE_GAINU,
  57. };
  58. enum b43_nphy_rssi_type {
  59. B43_NPHY_RSSI_X = 0,
  60. B43_NPHY_RSSI_Y,
  61. B43_NPHY_RSSI_Z,
  62. B43_NPHY_RSSI_PWRDET,
  63. B43_NPHY_RSSI_TSSI_I,
  64. B43_NPHY_RSSI_TSSI_Q,
  65. B43_NPHY_RSSI_TBD,
  66. };
  67. static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  68. {
  69. enum ieee80211_band band = b43_current_band(dev->wl);
  70. return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  71. (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  72. }
  73. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
  74. static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
  75. {
  76. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  77. if (dev->phy.rev >= 6) {
  78. if (dev->dev->chip_id == 47162)
  79. return txpwrctrl_tx_gain_ipa_rev5;
  80. return txpwrctrl_tx_gain_ipa_rev6;
  81. } else if (dev->phy.rev >= 5) {
  82. return txpwrctrl_tx_gain_ipa_rev5;
  83. } else {
  84. return txpwrctrl_tx_gain_ipa;
  85. }
  86. } else {
  87. return txpwrctrl_tx_gain_ipa_5g;
  88. }
  89. }
  90. /**************************************************
  91. * RF (just without b43_nphy_rf_control_intc_override)
  92. **************************************************/
  93. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
  94. static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  95. enum b43_nphy_rf_sequence seq)
  96. {
  97. static const u16 trigger[] = {
  98. [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
  99. [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
  100. [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
  101. [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
  102. [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
  103. [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
  104. };
  105. int i;
  106. u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
  107. B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
  108. b43_phy_set(dev, B43_NPHY_RFSEQMODE,
  109. B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
  110. b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
  111. for (i = 0; i < 200; i++) {
  112. if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
  113. goto ok;
  114. msleep(1);
  115. }
  116. b43err(dev->wl, "RF sequence status timeout\n");
  117. ok:
  118. b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
  119. }
  120. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
  121. static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  122. u16 value, u8 core, bool off)
  123. {
  124. int i;
  125. u8 index = fls(field);
  126. u8 addr, en_addr, val_addr;
  127. /* we expect only one bit set */
  128. B43_WARN_ON(field & (~(1 << (index - 1))));
  129. if (dev->phy.rev >= 3) {
  130. const struct nphy_rf_control_override_rev3 *rf_ctrl;
  131. for (i = 0; i < 2; i++) {
  132. if (index == 0 || index == 16) {
  133. b43err(dev->wl,
  134. "Unsupported RF Ctrl Override call\n");
  135. return;
  136. }
  137. rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
  138. en_addr = B43_PHY_N((i == 0) ?
  139. rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
  140. val_addr = B43_PHY_N((i == 0) ?
  141. rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
  142. if (off) {
  143. b43_phy_mask(dev, en_addr, ~(field));
  144. b43_phy_mask(dev, val_addr,
  145. ~(rf_ctrl->val_mask));
  146. } else {
  147. if (core == 0 || ((1 << core) & i) != 0) {
  148. b43_phy_set(dev, en_addr, field);
  149. b43_phy_maskset(dev, val_addr,
  150. ~(rf_ctrl->val_mask),
  151. (value << rf_ctrl->val_shift));
  152. }
  153. }
  154. }
  155. } else {
  156. const struct nphy_rf_control_override_rev2 *rf_ctrl;
  157. if (off) {
  158. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
  159. value = 0;
  160. } else {
  161. b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
  162. }
  163. for (i = 0; i < 2; i++) {
  164. if (index <= 1 || index == 16) {
  165. b43err(dev->wl,
  166. "Unsupported RF Ctrl Override call\n");
  167. return;
  168. }
  169. if (index == 2 || index == 10 ||
  170. (index >= 13 && index <= 15)) {
  171. core = 1;
  172. }
  173. rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
  174. addr = B43_PHY_N((i == 0) ?
  175. rf_ctrl->addr0 : rf_ctrl->addr1);
  176. if ((core & (1 << i)) != 0)
  177. b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
  178. (value << rf_ctrl->shift));
  179. b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
  180. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  181. B43_NPHY_RFCTL_CMD_START);
  182. udelay(1);
  183. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
  184. }
  185. }
  186. }
  187. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
  188. static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  189. u16 value, u8 core)
  190. {
  191. u8 i, j;
  192. u16 reg, tmp, val;
  193. B43_WARN_ON(dev->phy.rev < 3);
  194. B43_WARN_ON(field > 4);
  195. for (i = 0; i < 2; i++) {
  196. if ((core == 1 && i == 1) || (core == 2 && !i))
  197. continue;
  198. reg = (i == 0) ?
  199. B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
  200. b43_phy_mask(dev, reg, 0xFBFF);
  201. switch (field) {
  202. case 0:
  203. b43_phy_write(dev, reg, 0);
  204. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  205. break;
  206. case 1:
  207. if (!i) {
  208. b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
  209. 0xFC3F, (value << 6));
  210. b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
  211. 0xFFFE, 1);
  212. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  213. B43_NPHY_RFCTL_CMD_START);
  214. for (j = 0; j < 100; j++) {
  215. if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
  216. j = 0;
  217. break;
  218. }
  219. udelay(10);
  220. }
  221. if (j)
  222. b43err(dev->wl,
  223. "intc override timeout\n");
  224. b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
  225. 0xFFFE);
  226. } else {
  227. b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
  228. 0xFC3F, (value << 6));
  229. b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
  230. 0xFFFE, 1);
  231. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  232. B43_NPHY_RFCTL_CMD_RXTX);
  233. for (j = 0; j < 100; j++) {
  234. if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
  235. j = 0;
  236. break;
  237. }
  238. udelay(10);
  239. }
  240. if (j)
  241. b43err(dev->wl,
  242. "intc override timeout\n");
  243. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
  244. 0xFFFE);
  245. }
  246. break;
  247. case 2:
  248. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  249. tmp = 0x0020;
  250. val = value << 5;
  251. } else {
  252. tmp = 0x0010;
  253. val = value << 4;
  254. }
  255. b43_phy_maskset(dev, reg, ~tmp, val);
  256. break;
  257. case 3:
  258. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  259. tmp = 0x0001;
  260. val = value;
  261. } else {
  262. tmp = 0x0004;
  263. val = value << 2;
  264. }
  265. b43_phy_maskset(dev, reg, ~tmp, val);
  266. break;
  267. case 4:
  268. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  269. tmp = 0x0002;
  270. val = value << 1;
  271. } else {
  272. tmp = 0x0008;
  273. val = value << 3;
  274. }
  275. b43_phy_maskset(dev, reg, ~tmp, val);
  276. break;
  277. }
  278. }
  279. }
  280. /**************************************************
  281. * Various PHY ops
  282. **************************************************/
  283. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
  284. static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
  285. const u16 *clip_st)
  286. {
  287. b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
  288. b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
  289. }
  290. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
  291. static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
  292. {
  293. clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
  294. clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
  295. }
  296. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
  297. static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
  298. {
  299. u16 tmp;
  300. if (dev->dev->core_rev == 16)
  301. b43_mac_suspend(dev);
  302. tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
  303. tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
  304. B43_NPHY_CLASSCTL_WAITEDEN);
  305. tmp &= ~mask;
  306. tmp |= (val & mask);
  307. b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
  308. if (dev->dev->core_rev == 16)
  309. b43_mac_enable(dev);
  310. return tmp;
  311. }
  312. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
  313. static void b43_nphy_reset_cca(struct b43_wldev *dev)
  314. {
  315. u16 bbcfg;
  316. b43_phy_force_clock(dev, 1);
  317. bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
  318. b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
  319. udelay(1);
  320. b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
  321. b43_phy_force_clock(dev, 0);
  322. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  323. }
  324. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
  325. static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
  326. {
  327. struct b43_phy *phy = &dev->phy;
  328. struct b43_phy_n *nphy = phy->n;
  329. if (enable) {
  330. static const u16 clip[] = { 0xFFFF, 0xFFFF };
  331. if (nphy->deaf_count++ == 0) {
  332. nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
  333. b43_nphy_classifier(dev, 0x7, 0);
  334. b43_nphy_read_clip_detection(dev, nphy->clip_state);
  335. b43_nphy_write_clip_detection(dev, clip);
  336. }
  337. b43_nphy_reset_cca(dev);
  338. } else {
  339. if (--nphy->deaf_count == 0) {
  340. b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
  341. b43_nphy_write_clip_detection(dev, nphy->clip_state);
  342. }
  343. }
  344. }
  345. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
  346. static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
  347. {
  348. struct b43_phy_n *nphy = dev->phy.n;
  349. u8 i;
  350. s16 tmp;
  351. u16 data[4];
  352. s16 gain[2];
  353. u16 minmax[2];
  354. static const u16 lna_gain[4] = { -2, 10, 19, 25 };
  355. if (nphy->hang_avoid)
  356. b43_nphy_stay_in_carrier_search(dev, 1);
  357. if (nphy->gain_boost) {
  358. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  359. gain[0] = 6;
  360. gain[1] = 6;
  361. } else {
  362. tmp = 40370 - 315 * dev->phy.channel;
  363. gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
  364. tmp = 23242 - 224 * dev->phy.channel;
  365. gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
  366. }
  367. } else {
  368. gain[0] = 0;
  369. gain[1] = 0;
  370. }
  371. for (i = 0; i < 2; i++) {
  372. if (nphy->elna_gain_config) {
  373. data[0] = 19 + gain[i];
  374. data[1] = 25 + gain[i];
  375. data[2] = 25 + gain[i];
  376. data[3] = 25 + gain[i];
  377. } else {
  378. data[0] = lna_gain[0] + gain[i];
  379. data[1] = lna_gain[1] + gain[i];
  380. data[2] = lna_gain[2] + gain[i];
  381. data[3] = lna_gain[3] + gain[i];
  382. }
  383. b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
  384. minmax[i] = 23 + gain[i];
  385. }
  386. b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
  387. minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
  388. b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
  389. minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
  390. if (nphy->hang_avoid)
  391. b43_nphy_stay_in_carrier_search(dev, 0);
  392. }
  393. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
  394. static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  395. u8 *events, u8 *delays, u8 length)
  396. {
  397. struct b43_phy_n *nphy = dev->phy.n;
  398. u8 i;
  399. u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
  400. u16 offset1 = cmd << 4;
  401. u16 offset2 = offset1 + 0x80;
  402. if (nphy->hang_avoid)
  403. b43_nphy_stay_in_carrier_search(dev, true);
  404. b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
  405. b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
  406. for (i = length; i < 16; i++) {
  407. b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
  408. b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
  409. }
  410. if (nphy->hang_avoid)
  411. b43_nphy_stay_in_carrier_search(dev, false);
  412. }
  413. /**************************************************
  414. * Radio 0x2056
  415. **************************************************/
  416. static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
  417. const struct b43_nphy_channeltab_entry_rev3 *e)
  418. {
  419. b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
  420. b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
  421. b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
  422. b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
  423. b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
  424. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
  425. e->radio_syn_pll_loopfilter1);
  426. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
  427. e->radio_syn_pll_loopfilter2);
  428. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
  429. e->radio_syn_pll_loopfilter3);
  430. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
  431. e->radio_syn_pll_loopfilter4);
  432. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
  433. e->radio_syn_pll_loopfilter5);
  434. b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
  435. e->radio_syn_reserved_addr27);
  436. b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
  437. e->radio_syn_reserved_addr28);
  438. b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
  439. e->radio_syn_reserved_addr29);
  440. b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
  441. e->radio_syn_logen_vcobuf1);
  442. b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
  443. b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
  444. b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
  445. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
  446. e->radio_rx0_lnaa_tune);
  447. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
  448. e->radio_rx0_lnag_tune);
  449. b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
  450. e->radio_tx0_intpaa_boost_tune);
  451. b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
  452. e->radio_tx0_intpag_boost_tune);
  453. b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
  454. e->radio_tx0_pada_boost_tune);
  455. b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
  456. e->radio_tx0_padg_boost_tune);
  457. b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
  458. e->radio_tx0_pgaa_boost_tune);
  459. b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
  460. e->radio_tx0_pgag_boost_tune);
  461. b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
  462. e->radio_tx0_mixa_boost_tune);
  463. b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
  464. e->radio_tx0_mixg_boost_tune);
  465. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
  466. e->radio_rx1_lnaa_tune);
  467. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
  468. e->radio_rx1_lnag_tune);
  469. b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
  470. e->radio_tx1_intpaa_boost_tune);
  471. b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
  472. e->radio_tx1_intpag_boost_tune);
  473. b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
  474. e->radio_tx1_pada_boost_tune);
  475. b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
  476. e->radio_tx1_padg_boost_tune);
  477. b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
  478. e->radio_tx1_pgaa_boost_tune);
  479. b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
  480. e->radio_tx1_pgag_boost_tune);
  481. b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
  482. e->radio_tx1_mixa_boost_tune);
  483. b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
  484. e->radio_tx1_mixg_boost_tune);
  485. }
  486. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
  487. static void b43_radio_2056_setup(struct b43_wldev *dev,
  488. const struct b43_nphy_channeltab_entry_rev3 *e)
  489. {
  490. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  491. enum ieee80211_band band = b43_current_band(dev->wl);
  492. u16 offset;
  493. u8 i;
  494. u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
  495. B43_WARN_ON(dev->phy.rev < 3);
  496. b43_chantab_radio_2056_upload(dev, e);
  497. b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
  498. if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
  499. b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  500. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
  501. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
  502. if (dev->dev->chip_id == 0x4716) {
  503. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
  504. b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
  505. } else {
  506. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
  507. b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
  508. }
  509. }
  510. if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
  511. b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  512. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
  513. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
  514. b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
  515. b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
  516. }
  517. if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
  518. for (i = 0; i < 2; i++) {
  519. offset = i ? B2056_TX1 : B2056_TX0;
  520. if (dev->phy.rev >= 5) {
  521. b43_radio_write(dev,
  522. offset | B2056_TX_PADG_IDAC, 0xcc);
  523. if (dev->dev->chip_id == 0x4716) {
  524. bias = 0x40;
  525. cbias = 0x45;
  526. pag_boost = 0x5;
  527. pgag_boost = 0x33;
  528. mixg_boost = 0x55;
  529. } else {
  530. bias = 0x25;
  531. cbias = 0x20;
  532. pag_boost = 0x4;
  533. pgag_boost = 0x03;
  534. mixg_boost = 0x65;
  535. }
  536. padg_boost = 0x77;
  537. b43_radio_write(dev,
  538. offset | B2056_TX_INTPAG_IMAIN_STAT,
  539. bias);
  540. b43_radio_write(dev,
  541. offset | B2056_TX_INTPAG_IAUX_STAT,
  542. bias);
  543. b43_radio_write(dev,
  544. offset | B2056_TX_INTPAG_CASCBIAS,
  545. cbias);
  546. b43_radio_write(dev,
  547. offset | B2056_TX_INTPAG_BOOST_TUNE,
  548. pag_boost);
  549. b43_radio_write(dev,
  550. offset | B2056_TX_PGAG_BOOST_TUNE,
  551. pgag_boost);
  552. b43_radio_write(dev,
  553. offset | B2056_TX_PADG_BOOST_TUNE,
  554. padg_boost);
  555. b43_radio_write(dev,
  556. offset | B2056_TX_MIXG_BOOST_TUNE,
  557. mixg_boost);
  558. } else {
  559. bias = dev->phy.is_40mhz ? 0x40 : 0x20;
  560. b43_radio_write(dev,
  561. offset | B2056_TX_INTPAG_IMAIN_STAT,
  562. bias);
  563. b43_radio_write(dev,
  564. offset | B2056_TX_INTPAG_IAUX_STAT,
  565. bias);
  566. b43_radio_write(dev,
  567. offset | B2056_TX_INTPAG_CASCBIAS,
  568. 0x30);
  569. }
  570. b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
  571. }
  572. } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
  573. /* TODO */
  574. }
  575. udelay(50);
  576. /* VCO calibration */
  577. b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
  578. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
  579. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
  580. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
  581. b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
  582. udelay(300);
  583. }
  584. static void b43_radio_init2056_pre(struct b43_wldev *dev)
  585. {
  586. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  587. ~B43_NPHY_RFCTL_CMD_CHIP0PU);
  588. /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
  589. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  590. B43_NPHY_RFCTL_CMD_OEPORFORCE);
  591. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  592. ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
  593. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  594. B43_NPHY_RFCTL_CMD_CHIP0PU);
  595. }
  596. static void b43_radio_init2056_post(struct b43_wldev *dev)
  597. {
  598. b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
  599. b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
  600. b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
  601. msleep(1);
  602. b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
  603. b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
  604. b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
  605. /*
  606. if (nphy->init_por)
  607. Call Radio 2056 Recalibrate
  608. */
  609. }
  610. /*
  611. * Initialize a Broadcom 2056 N-radio
  612. * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
  613. */
  614. static void b43_radio_init2056(struct b43_wldev *dev)
  615. {
  616. b43_radio_init2056_pre(dev);
  617. b2056_upload_inittabs(dev, 0, 0);
  618. b43_radio_init2056_post(dev);
  619. }
  620. /**************************************************
  621. * Radio 0x2055
  622. **************************************************/
  623. static void b43_chantab_radio_upload(struct b43_wldev *dev,
  624. const struct b43_nphy_channeltab_entry_rev2 *e)
  625. {
  626. b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
  627. b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  628. b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  629. b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  630. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  631. b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  632. b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  633. b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  634. b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  635. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  636. b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  637. b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  638. b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  639. b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  640. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  641. b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  642. b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  643. b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  644. b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  645. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  646. b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  647. b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  648. b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  649. b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  650. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  651. b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  652. b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  653. }
  654. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
  655. static void b43_radio_2055_setup(struct b43_wldev *dev,
  656. const struct b43_nphy_channeltab_entry_rev2 *e)
  657. {
  658. B43_WARN_ON(dev->phy.rev >= 3);
  659. b43_chantab_radio_upload(dev, e);
  660. udelay(50);
  661. b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
  662. b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
  663. b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  664. b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
  665. udelay(300);
  666. }
  667. static void b43_radio_init2055_pre(struct b43_wldev *dev)
  668. {
  669. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  670. ~B43_NPHY_RFCTL_CMD_PORFORCE);
  671. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  672. B43_NPHY_RFCTL_CMD_CHIP0PU |
  673. B43_NPHY_RFCTL_CMD_OEPORFORCE);
  674. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  675. B43_NPHY_RFCTL_CMD_PORFORCE);
  676. }
  677. static void b43_radio_init2055_post(struct b43_wldev *dev)
  678. {
  679. struct b43_phy_n *nphy = dev->phy.n;
  680. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  681. int i;
  682. u16 val;
  683. bool workaround = false;
  684. if (sprom->revision < 4)
  685. workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
  686. && dev->dev->board_type == 0x46D
  687. && dev->dev->board_rev >= 0x41);
  688. else
  689. workaround =
  690. !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
  691. b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
  692. if (workaround) {
  693. b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
  694. b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
  695. }
  696. b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
  697. b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
  698. b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
  699. b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
  700. b43_radio_set(dev, B2055_CAL_MISC, 0x1);
  701. msleep(1);
  702. b43_radio_set(dev, B2055_CAL_MISC, 0x40);
  703. for (i = 0; i < 200; i++) {
  704. val = b43_radio_read(dev, B2055_CAL_COUT2);
  705. if (val & 0x80) {
  706. i = 0;
  707. break;
  708. }
  709. udelay(10);
  710. }
  711. if (i)
  712. b43err(dev->wl, "radio post init timeout\n");
  713. b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
  714. b43_switch_channel(dev, dev->phy.channel);
  715. b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
  716. b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
  717. b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
  718. b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
  719. b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
  720. b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
  721. if (!nphy->gain_boost) {
  722. b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
  723. b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
  724. } else {
  725. b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
  726. b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
  727. }
  728. udelay(2);
  729. }
  730. /*
  731. * Initialize a Broadcom 2055 N-radio
  732. * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
  733. */
  734. static void b43_radio_init2055(struct b43_wldev *dev)
  735. {
  736. b43_radio_init2055_pre(dev);
  737. if (b43_status(dev) < B43_STAT_INITIALIZED) {
  738. /* Follow wl, not specs. Do not force uploading all regs */
  739. b2055_upload_inittab(dev, 0, 0);
  740. } else {
  741. bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
  742. b2055_upload_inittab(dev, ghz5, 0);
  743. }
  744. b43_radio_init2055_post(dev);
  745. }
  746. /**************************************************
  747. * Samples
  748. **************************************************/
  749. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
  750. static int b43_nphy_load_samples(struct b43_wldev *dev,
  751. struct b43_c32 *samples, u16 len) {
  752. struct b43_phy_n *nphy = dev->phy.n;
  753. u16 i;
  754. u32 *data;
  755. data = kzalloc(len * sizeof(u32), GFP_KERNEL);
  756. if (!data) {
  757. b43err(dev->wl, "allocation for samples loading failed\n");
  758. return -ENOMEM;
  759. }
  760. if (nphy->hang_avoid)
  761. b43_nphy_stay_in_carrier_search(dev, 1);
  762. for (i = 0; i < len; i++) {
  763. data[i] = (samples[i].i & 0x3FF << 10);
  764. data[i] |= samples[i].q & 0x3FF;
  765. }
  766. b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
  767. kfree(data);
  768. if (nphy->hang_avoid)
  769. b43_nphy_stay_in_carrier_search(dev, 0);
  770. return 0;
  771. }
  772. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
  773. static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
  774. bool test)
  775. {
  776. int i;
  777. u16 bw, len, rot, angle;
  778. struct b43_c32 *samples;
  779. bw = (dev->phy.is_40mhz) ? 40 : 20;
  780. len = bw << 3;
  781. if (test) {
  782. if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
  783. bw = 82;
  784. else
  785. bw = 80;
  786. if (dev->phy.is_40mhz)
  787. bw <<= 1;
  788. len = bw << 1;
  789. }
  790. samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
  791. if (!samples) {
  792. b43err(dev->wl, "allocation for samples generation failed\n");
  793. return 0;
  794. }
  795. rot = (((freq * 36) / bw) << 16) / 100;
  796. angle = 0;
  797. for (i = 0; i < len; i++) {
  798. samples[i] = b43_cordic(angle);
  799. angle += rot;
  800. samples[i].q = CORDIC_CONVERT(samples[i].q * max);
  801. samples[i].i = CORDIC_CONVERT(samples[i].i * max);
  802. }
  803. i = b43_nphy_load_samples(dev, samples, len);
  804. kfree(samples);
  805. return (i < 0) ? 0 : len;
  806. }
  807. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
  808. static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
  809. u16 wait, bool iqmode, bool dac_test)
  810. {
  811. struct b43_phy_n *nphy = dev->phy.n;
  812. int i;
  813. u16 seq_mode;
  814. u32 tmp;
  815. if (nphy->hang_avoid)
  816. b43_nphy_stay_in_carrier_search(dev, true);
  817. if ((nphy->bb_mult_save & 0x80000000) == 0) {
  818. tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
  819. nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
  820. }
  821. if (!dev->phy.is_40mhz)
  822. tmp = 0x6464;
  823. else
  824. tmp = 0x4747;
  825. b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
  826. if (nphy->hang_avoid)
  827. b43_nphy_stay_in_carrier_search(dev, false);
  828. b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
  829. if (loops != 0xFFFF)
  830. b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
  831. else
  832. b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
  833. b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
  834. seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
  835. b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
  836. if (iqmode) {
  837. b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
  838. b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
  839. } else {
  840. if (dac_test)
  841. b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
  842. else
  843. b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
  844. }
  845. for (i = 0; i < 100; i++) {
  846. if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
  847. i = 0;
  848. break;
  849. }
  850. udelay(10);
  851. }
  852. if (i)
  853. b43err(dev->wl, "run samples timeout\n");
  854. b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
  855. }
  856. /**************************************************
  857. * RSSI
  858. **************************************************/
  859. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
  860. static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
  861. s8 offset, u8 core, u8 rail,
  862. enum b43_nphy_rssi_type type)
  863. {
  864. u16 tmp;
  865. bool core1or5 = (core == 1) || (core == 5);
  866. bool core2or5 = (core == 2) || (core == 5);
  867. offset = clamp_val(offset, -32, 31);
  868. tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
  869. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
  870. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
  871. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
  872. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
  873. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
  874. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
  875. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
  876. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
  877. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
  878. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
  879. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
  880. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
  881. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
  882. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
  883. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
  884. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
  885. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
  886. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
  887. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
  888. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
  889. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
  890. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
  891. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
  892. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
  893. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
  894. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
  895. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
  896. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
  897. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
  898. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
  899. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
  900. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
  901. if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
  902. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
  903. if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
  904. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
  905. if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
  906. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
  907. if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
  908. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
  909. if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
  910. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
  911. if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
  912. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
  913. if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
  914. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
  915. if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
  916. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
  917. }
  918. static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
  919. {
  920. u8 i;
  921. u16 reg, val;
  922. if (code == 0) {
  923. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
  924. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
  925. b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
  926. b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
  927. b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
  928. b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
  929. b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
  930. b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
  931. } else {
  932. for (i = 0; i < 2; i++) {
  933. if ((code == 1 && i == 1) || (code == 2 && !i))
  934. continue;
  935. reg = (i == 0) ?
  936. B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
  937. b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
  938. if (type < 3) {
  939. reg = (i == 0) ?
  940. B43_NPHY_AFECTL_C1 :
  941. B43_NPHY_AFECTL_C2;
  942. b43_phy_maskset(dev, reg, 0xFCFF, 0);
  943. reg = (i == 0) ?
  944. B43_NPHY_RFCTL_LUT_TRSW_UP1 :
  945. B43_NPHY_RFCTL_LUT_TRSW_UP2;
  946. b43_phy_maskset(dev, reg, 0xFFC3, 0);
  947. if (type == 0)
  948. val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
  949. else if (type == 1)
  950. val = 16;
  951. else
  952. val = 32;
  953. b43_phy_set(dev, reg, val);
  954. reg = (i == 0) ?
  955. B43_NPHY_TXF_40CO_B1S0 :
  956. B43_NPHY_TXF_40CO_B32S1;
  957. b43_phy_set(dev, reg, 0x0020);
  958. } else {
  959. if (type == 6)
  960. val = 0x0100;
  961. else if (type == 3)
  962. val = 0x0200;
  963. else
  964. val = 0x0300;
  965. reg = (i == 0) ?
  966. B43_NPHY_AFECTL_C1 :
  967. B43_NPHY_AFECTL_C2;
  968. b43_phy_maskset(dev, reg, 0xFCFF, val);
  969. b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
  970. if (type != 3 && type != 6) {
  971. enum ieee80211_band band =
  972. b43_current_band(dev->wl);
  973. if (b43_nphy_ipa(dev))
  974. val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
  975. else
  976. val = 0x11;
  977. reg = (i == 0) ? 0x2000 : 0x3000;
  978. reg |= B2055_PADDRV;
  979. b43_radio_write16(dev, reg, val);
  980. reg = (i == 0) ?
  981. B43_NPHY_AFECTL_OVER1 :
  982. B43_NPHY_AFECTL_OVER;
  983. b43_phy_set(dev, reg, 0x0200);
  984. }
  985. }
  986. }
  987. }
  988. }
  989. static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
  990. {
  991. u16 val;
  992. if (type < 3)
  993. val = 0;
  994. else if (type == 6)
  995. val = 1;
  996. else if (type == 3)
  997. val = 2;
  998. else
  999. val = 3;
  1000. val = (val << 12) | (val << 14);
  1001. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
  1002. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
  1003. if (type < 3) {
  1004. b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
  1005. (type + 1) << 4);
  1006. b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
  1007. (type + 1) << 4);
  1008. }
  1009. if (code == 0) {
  1010. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
  1011. if (type < 3) {
  1012. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  1013. ~(B43_NPHY_RFCTL_CMD_RXEN |
  1014. B43_NPHY_RFCTL_CMD_CORESEL));
  1015. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
  1016. ~(0x1 << 12 |
  1017. 0x1 << 5 |
  1018. 0x1 << 1 |
  1019. 0x1));
  1020. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  1021. ~B43_NPHY_RFCTL_CMD_START);
  1022. udelay(20);
  1023. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
  1024. }
  1025. } else {
  1026. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
  1027. if (type < 3) {
  1028. b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
  1029. ~(B43_NPHY_RFCTL_CMD_RXEN |
  1030. B43_NPHY_RFCTL_CMD_CORESEL),
  1031. (B43_NPHY_RFCTL_CMD_RXEN |
  1032. code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
  1033. b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
  1034. (0x1 << 12 |
  1035. 0x1 << 5 |
  1036. 0x1 << 1 |
  1037. 0x1));
  1038. b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
  1039. B43_NPHY_RFCTL_CMD_START);
  1040. udelay(20);
  1041. b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
  1042. }
  1043. }
  1044. }
  1045. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
  1046. static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
  1047. {
  1048. if (dev->phy.rev >= 3)
  1049. b43_nphy_rev3_rssi_select(dev, code, type);
  1050. else
  1051. b43_nphy_rev2_rssi_select(dev, code, type);
  1052. }
  1053. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
  1054. static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
  1055. {
  1056. int i;
  1057. for (i = 0; i < 2; i++) {
  1058. if (type == 2) {
  1059. if (i == 0) {
  1060. b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
  1061. 0xFC, buf[0]);
  1062. b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
  1063. 0xFC, buf[1]);
  1064. } else {
  1065. b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
  1066. 0xFC, buf[2 * i]);
  1067. b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
  1068. 0xFC, buf[2 * i + 1]);
  1069. }
  1070. } else {
  1071. if (i == 0)
  1072. b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
  1073. 0xF3, buf[0] << 2);
  1074. else
  1075. b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
  1076. 0xF3, buf[2 * i + 1] << 2);
  1077. }
  1078. }
  1079. }
  1080. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
  1081. static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
  1082. u8 nsamp)
  1083. {
  1084. int i;
  1085. int out;
  1086. u16 save_regs_phy[9];
  1087. u16 s[2];
  1088. if (dev->phy.rev >= 3) {
  1089. save_regs_phy[0] = b43_phy_read(dev,
  1090. B43_NPHY_RFCTL_LUT_TRSW_UP1);
  1091. save_regs_phy[1] = b43_phy_read(dev,
  1092. B43_NPHY_RFCTL_LUT_TRSW_UP2);
  1093. save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  1094. save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  1095. save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
  1096. save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  1097. save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
  1098. save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
  1099. save_regs_phy[8] = 0;
  1100. } else {
  1101. save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  1102. save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  1103. save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  1104. save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
  1105. save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
  1106. save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
  1107. save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
  1108. save_regs_phy[7] = 0;
  1109. save_regs_phy[8] = 0;
  1110. }
  1111. b43_nphy_rssi_select(dev, 5, type);
  1112. if (dev->phy.rev < 2) {
  1113. save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
  1114. b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
  1115. }
  1116. for (i = 0; i < 4; i++)
  1117. buf[i] = 0;
  1118. for (i = 0; i < nsamp; i++) {
  1119. if (dev->phy.rev < 2) {
  1120. s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
  1121. s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
  1122. } else {
  1123. s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
  1124. s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
  1125. }
  1126. buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
  1127. buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
  1128. buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
  1129. buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
  1130. }
  1131. out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
  1132. (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
  1133. if (dev->phy.rev < 2)
  1134. b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
  1135. if (dev->phy.rev >= 3) {
  1136. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
  1137. save_regs_phy[0]);
  1138. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
  1139. save_regs_phy[1]);
  1140. b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
  1141. b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
  1142. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
  1143. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
  1144. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
  1145. b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
  1146. } else {
  1147. b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
  1148. b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
  1149. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
  1150. b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
  1151. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
  1152. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
  1153. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
  1154. }
  1155. return out;
  1156. }
  1157. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
  1158. static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
  1159. {
  1160. int i, j;
  1161. u8 state[4];
  1162. u8 code, val;
  1163. u16 class, override;
  1164. u8 regs_save_radio[2];
  1165. u16 regs_save_phy[2];
  1166. s8 offset[4];
  1167. u8 core;
  1168. u8 rail;
  1169. u16 clip_state[2];
  1170. u16 clip_off[2] = { 0xFFFF, 0xFFFF };
  1171. s32 results_min[4] = { };
  1172. u8 vcm_final[4] = { };
  1173. s32 results[4][4] = { };
  1174. s32 miniq[4][2] = { };
  1175. if (type == 2) {
  1176. code = 0;
  1177. val = 6;
  1178. } else if (type < 2) {
  1179. code = 25;
  1180. val = 4;
  1181. } else {
  1182. B43_WARN_ON(1);
  1183. return;
  1184. }
  1185. class = b43_nphy_classifier(dev, 0, 0);
  1186. b43_nphy_classifier(dev, 7, 4);
  1187. b43_nphy_read_clip_detection(dev, clip_state);
  1188. b43_nphy_write_clip_detection(dev, clip_off);
  1189. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  1190. override = 0x140;
  1191. else
  1192. override = 0x110;
  1193. regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  1194. regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
  1195. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
  1196. b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
  1197. regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  1198. regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
  1199. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
  1200. b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
  1201. state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
  1202. state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
  1203. b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
  1204. b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
  1205. state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
  1206. state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
  1207. b43_nphy_rssi_select(dev, 5, type);
  1208. b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
  1209. b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
  1210. for (i = 0; i < 4; i++) {
  1211. u8 tmp[4];
  1212. for (j = 0; j < 4; j++)
  1213. tmp[j] = i;
  1214. if (type != 1)
  1215. b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
  1216. b43_nphy_poll_rssi(dev, type, results[i], 8);
  1217. if (type < 2)
  1218. for (j = 0; j < 2; j++)
  1219. miniq[i][j] = min(results[i][2 * j],
  1220. results[i][2 * j + 1]);
  1221. }
  1222. for (i = 0; i < 4; i++) {
  1223. s32 mind = 40;
  1224. u8 minvcm = 0;
  1225. s32 minpoll = 249;
  1226. s32 curr;
  1227. for (j = 0; j < 4; j++) {
  1228. if (type == 2)
  1229. curr = abs(results[j][i]);
  1230. else
  1231. curr = abs(miniq[j][i / 2] - code * 8);
  1232. if (curr < mind) {
  1233. mind = curr;
  1234. minvcm = j;
  1235. }
  1236. if (results[j][i] < minpoll)
  1237. minpoll = results[j][i];
  1238. }
  1239. results_min[i] = minpoll;
  1240. vcm_final[i] = minvcm;
  1241. }
  1242. if (type != 1)
  1243. b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
  1244. for (i = 0; i < 4; i++) {
  1245. offset[i] = (code * 8) - results[vcm_final[i]][i];
  1246. if (offset[i] < 0)
  1247. offset[i] = -((abs(offset[i]) + 4) / 8);
  1248. else
  1249. offset[i] = (offset[i] + 4) / 8;
  1250. if (results_min[i] == 248)
  1251. offset[i] = code - 32;
  1252. core = (i / 2) ? 2 : 1;
  1253. rail = (i % 2) ? 1 : 0;
  1254. b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
  1255. type);
  1256. }
  1257. b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
  1258. b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
  1259. switch (state[2]) {
  1260. case 1:
  1261. b43_nphy_rssi_select(dev, 1, 2);
  1262. break;
  1263. case 4:
  1264. b43_nphy_rssi_select(dev, 1, 0);
  1265. break;
  1266. case 2:
  1267. b43_nphy_rssi_select(dev, 1, 1);
  1268. break;
  1269. default:
  1270. b43_nphy_rssi_select(dev, 1, 1);
  1271. break;
  1272. }
  1273. switch (state[3]) {
  1274. case 1:
  1275. b43_nphy_rssi_select(dev, 2, 2);
  1276. break;
  1277. case 4:
  1278. b43_nphy_rssi_select(dev, 2, 0);
  1279. break;
  1280. default:
  1281. b43_nphy_rssi_select(dev, 2, 1);
  1282. break;
  1283. }
  1284. b43_nphy_rssi_select(dev, 0, type);
  1285. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
  1286. b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
  1287. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
  1288. b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
  1289. b43_nphy_classifier(dev, 7, class);
  1290. b43_nphy_write_clip_detection(dev, clip_state);
  1291. /* Specs don't say about reset here, but it makes wl and b43 dumps
  1292. identical, it really seems wl performs this */
  1293. b43_nphy_reset_cca(dev);
  1294. }
  1295. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
  1296. static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
  1297. {
  1298. /* TODO */
  1299. }
  1300. /*
  1301. * RSSI Calibration
  1302. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
  1303. */
  1304. static void b43_nphy_rssi_cal(struct b43_wldev *dev)
  1305. {
  1306. if (dev->phy.rev >= 3) {
  1307. b43_nphy_rev3_rssi_cal(dev);
  1308. } else {
  1309. b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
  1310. b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
  1311. b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
  1312. }
  1313. }
  1314. /**************************************************
  1315. * Workarounds
  1316. **************************************************/
  1317. static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
  1318. {
  1319. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  1320. bool ghz5;
  1321. bool ext_lna;
  1322. u16 rssi_gain;
  1323. struct nphy_gain_ctl_workaround_entry *e;
  1324. u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
  1325. u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
  1326. /* Prepare values */
  1327. ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
  1328. & B43_NPHY_BANDCTL_5GHZ;
  1329. ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
  1330. e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
  1331. if (ghz5 && dev->phy.rev >= 5)
  1332. rssi_gain = 0x90;
  1333. else
  1334. rssi_gain = 0x50;
  1335. b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
  1336. /* Set Clip 2 detect */
  1337. b43_phy_set(dev, B43_NPHY_C1_CGAINI,
  1338. B43_NPHY_C1_CGAINI_CL2DETECT);
  1339. b43_phy_set(dev, B43_NPHY_C2_CGAINI,
  1340. B43_NPHY_C2_CGAINI_CL2DETECT);
  1341. b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
  1342. 0x17);
  1343. b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
  1344. 0x17);
  1345. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
  1346. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
  1347. b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
  1348. b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
  1349. b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
  1350. rssi_gain);
  1351. b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
  1352. rssi_gain);
  1353. b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
  1354. 0x17);
  1355. b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
  1356. 0x17);
  1357. b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
  1358. b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
  1359. b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
  1360. b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
  1361. b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
  1362. b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
  1363. b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
  1364. b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
  1365. b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
  1366. b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
  1367. b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
  1368. b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
  1369. b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
  1370. b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
  1371. b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
  1372. b43_phy_write(dev, 0x2A7, e->init_gain);
  1373. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
  1374. e->rfseq_init);
  1375. b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
  1376. /* TODO: check defines. Do not match variables names */
  1377. b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
  1378. b43_phy_write(dev, 0x2A9, e->cliphi_gain);
  1379. b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
  1380. b43_phy_write(dev, 0x2AB, e->clipmd_gain);
  1381. b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
  1382. b43_phy_write(dev, 0x2AD, e->cliplo_gain);
  1383. b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
  1384. b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
  1385. b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
  1386. b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
  1387. b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
  1388. b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
  1389. ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
  1390. b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
  1391. ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
  1392. b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
  1393. }
  1394. static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
  1395. {
  1396. struct b43_phy_n *nphy = dev->phy.n;
  1397. u8 i, j;
  1398. u8 code;
  1399. u16 tmp;
  1400. u8 rfseq_events[3] = { 6, 8, 7 };
  1401. u8 rfseq_delays[3] = { 10, 30, 1 };
  1402. /* Set Clip 2 detect */
  1403. b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
  1404. b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
  1405. /* Set narrowband clip threshold */
  1406. b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
  1407. b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
  1408. if (!dev->phy.is_40mhz) {
  1409. /* Set dwell lengths */
  1410. b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
  1411. b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
  1412. b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
  1413. b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
  1414. }
  1415. /* Set wideband clip 2 threshold */
  1416. b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
  1417. ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
  1418. b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
  1419. ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
  1420. if (!dev->phy.is_40mhz) {
  1421. b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
  1422. ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
  1423. b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
  1424. ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
  1425. b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
  1426. ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
  1427. b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
  1428. ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
  1429. }
  1430. b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
  1431. if (nphy->gain_boost) {
  1432. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
  1433. dev->phy.is_40mhz)
  1434. code = 4;
  1435. else
  1436. code = 5;
  1437. } else {
  1438. code = dev->phy.is_40mhz ? 6 : 7;
  1439. }
  1440. /* Set HPVGA2 index */
  1441. b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
  1442. code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
  1443. b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
  1444. code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
  1445. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
  1446. /* specs say about 2 loops, but wl does 4 */
  1447. for (i = 0; i < 4; i++)
  1448. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
  1449. b43_nphy_adjust_lna_gain_table(dev);
  1450. if (nphy->elna_gain_config) {
  1451. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
  1452. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
  1453. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1454. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1455. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1456. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
  1457. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
  1458. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1459. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1460. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
  1461. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
  1462. /* specs say about 2 loops, but wl does 4 */
  1463. for (i = 0; i < 4; i++)
  1464. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  1465. (code << 8 | 0x74));
  1466. }
  1467. if (dev->phy.rev == 2) {
  1468. for (i = 0; i < 4; i++) {
  1469. b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
  1470. (0x0400 * i) + 0x0020);
  1471. for (j = 0; j < 21; j++) {
  1472. tmp = j * (i < 2 ? 3 : 1);
  1473. b43_phy_write(dev,
  1474. B43_NPHY_TABLE_DATALO, tmp);
  1475. }
  1476. }
  1477. }
  1478. b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
  1479. b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
  1480. ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
  1481. 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
  1482. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  1483. b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
  1484. }
  1485. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
  1486. static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
  1487. {
  1488. if (dev->phy.rev >= 3)
  1489. b43_nphy_gain_ctl_workarounds_rev3plus(dev);
  1490. else
  1491. b43_nphy_gain_ctl_workarounds_rev1_2(dev);
  1492. }
  1493. static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
  1494. {
  1495. struct b43_phy_n *nphy = dev->phy.n;
  1496. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  1497. /* TX to RX */
  1498. u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
  1499. u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
  1500. /* RX to TX */
  1501. u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
  1502. 0x1F };
  1503. u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
  1504. u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
  1505. u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
  1506. u16 tmp16;
  1507. u32 tmp32;
  1508. b43_phy_write(dev, 0x23f, 0x1f8);
  1509. b43_phy_write(dev, 0x240, 0x1f8);
  1510. tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
  1511. tmp32 &= 0xffffff;
  1512. b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
  1513. b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
  1514. b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
  1515. b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
  1516. b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
  1517. b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
  1518. b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
  1519. b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
  1520. b43_phy_write(dev, 0x2AE, 0x000C);
  1521. /* TX to RX */
  1522. b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
  1523. ARRAY_SIZE(tx2rx_events));
  1524. /* RX to TX */
  1525. if (b43_nphy_ipa(dev))
  1526. b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
  1527. rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
  1528. if (nphy->hw_phyrxchain != 3 &&
  1529. nphy->hw_phyrxchain != nphy->hw_phytxchain) {
  1530. if (b43_nphy_ipa(dev)) {
  1531. rx2tx_delays[5] = 59;
  1532. rx2tx_delays[6] = 1;
  1533. rx2tx_events[7] = 0x1F;
  1534. }
  1535. b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
  1536. ARRAY_SIZE(rx2tx_events));
  1537. }
  1538. tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
  1539. 0x2 : 0x9C40;
  1540. b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
  1541. b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
  1542. b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
  1543. b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
  1544. b43_nphy_gain_ctl_workarounds(dev);
  1545. b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
  1546. b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
  1547. /* TODO */
  1548. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
  1549. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
  1550. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
  1551. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
  1552. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
  1553. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
  1554. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
  1555. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
  1556. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
  1557. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
  1558. b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
  1559. b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
  1560. /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
  1561. if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
  1562. b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
  1563. (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
  1564. b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
  1565. tmp32 = 0x00088888;
  1566. else
  1567. tmp32 = 0x88888888;
  1568. b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
  1569. b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
  1570. b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
  1571. if (dev->phy.rev == 4 &&
  1572. b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  1573. b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
  1574. 0x70);
  1575. b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
  1576. 0x70);
  1577. }
  1578. b43_phy_write(dev, 0x224, 0x03eb);
  1579. b43_phy_write(dev, 0x225, 0x03eb);
  1580. b43_phy_write(dev, 0x226, 0x0341);
  1581. b43_phy_write(dev, 0x227, 0x0341);
  1582. b43_phy_write(dev, 0x228, 0x042b);
  1583. b43_phy_write(dev, 0x229, 0x042b);
  1584. b43_phy_write(dev, 0x22a, 0x0381);
  1585. b43_phy_write(dev, 0x22b, 0x0381);
  1586. b43_phy_write(dev, 0x22c, 0x042b);
  1587. b43_phy_write(dev, 0x22d, 0x042b);
  1588. b43_phy_write(dev, 0x22e, 0x0381);
  1589. b43_phy_write(dev, 0x22f, 0x0381);
  1590. }
  1591. static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
  1592. {
  1593. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  1594. struct b43_phy *phy = &dev->phy;
  1595. struct b43_phy_n *nphy = phy->n;
  1596. u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
  1597. u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
  1598. u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
  1599. u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
  1600. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
  1601. nphy->band5g_pwrgain) {
  1602. b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
  1603. b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
  1604. } else {
  1605. b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
  1606. b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
  1607. }
  1608. b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
  1609. b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
  1610. b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
  1611. b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
  1612. if (dev->phy.rev < 2) {
  1613. b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
  1614. b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
  1615. b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
  1616. b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
  1617. b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
  1618. b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
  1619. }
  1620. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
  1621. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
  1622. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
  1623. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
  1624. if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
  1625. dev->dev->board_type == 0x8B) {
  1626. delays1[0] = 0x1;
  1627. delays1[5] = 0x14;
  1628. }
  1629. b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
  1630. b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
  1631. b43_nphy_gain_ctl_workarounds(dev);
  1632. if (dev->phy.rev < 2) {
  1633. if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
  1634. b43_hf_write(dev, b43_hf_read(dev) |
  1635. B43_HF_MLADVW);
  1636. } else if (dev->phy.rev == 2) {
  1637. b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
  1638. b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
  1639. }
  1640. if (dev->phy.rev < 2)
  1641. b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
  1642. ~B43_NPHY_SCRAM_SIGCTL_SCM);
  1643. /* Set phase track alpha and beta */
  1644. b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
  1645. b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
  1646. b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
  1647. b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
  1648. b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
  1649. b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
  1650. b43_phy_mask(dev, B43_NPHY_PIL_DW1,
  1651. ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
  1652. b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
  1653. b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
  1654. b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
  1655. if (dev->phy.rev == 2)
  1656. b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
  1657. B43_NPHY_FINERX2_CGC_DECGC);
  1658. }
  1659. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
  1660. static void b43_nphy_workarounds(struct b43_wldev *dev)
  1661. {
  1662. struct b43_phy *phy = &dev->phy;
  1663. struct b43_phy_n *nphy = phy->n;
  1664. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  1665. b43_nphy_classifier(dev, 1, 0);
  1666. else
  1667. b43_nphy_classifier(dev, 1, 1);
  1668. if (nphy->hang_avoid)
  1669. b43_nphy_stay_in_carrier_search(dev, 1);
  1670. b43_phy_set(dev, B43_NPHY_IQFLIP,
  1671. B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
  1672. if (dev->phy.rev >= 3)
  1673. b43_nphy_workarounds_rev3plus(dev);
  1674. else
  1675. b43_nphy_workarounds_rev1_2(dev);
  1676. if (nphy->hang_avoid)
  1677. b43_nphy_stay_in_carrier_search(dev, 0);
  1678. }
  1679. /**************************************************
  1680. * Tx and Rx
  1681. **************************************************/
  1682. void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  1683. {//TODO
  1684. }
  1685. static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  1686. {//TODO
  1687. }
  1688. static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  1689. bool ignore_tssi)
  1690. {//TODO
  1691. return B43_TXPWR_RES_DONE;
  1692. }
  1693. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
  1694. static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
  1695. {
  1696. struct b43_phy_n *nphy = dev->phy.n;
  1697. u8 i;
  1698. u16 bmask, val, tmp;
  1699. enum ieee80211_band band = b43_current_band(dev->wl);
  1700. if (nphy->hang_avoid)
  1701. b43_nphy_stay_in_carrier_search(dev, 1);
  1702. nphy->txpwrctrl = enable;
  1703. if (!enable) {
  1704. if (dev->phy.rev >= 3 &&
  1705. (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
  1706. (B43_NPHY_TXPCTL_CMD_COEFF |
  1707. B43_NPHY_TXPCTL_CMD_HWPCTLEN |
  1708. B43_NPHY_TXPCTL_CMD_PCTLEN))) {
  1709. /* We disable enabled TX pwr ctl, save it's state */
  1710. nphy->tx_pwr_idx[0] = b43_phy_read(dev,
  1711. B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
  1712. nphy->tx_pwr_idx[1] = b43_phy_read(dev,
  1713. B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
  1714. }
  1715. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
  1716. for (i = 0; i < 84; i++)
  1717. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
  1718. b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
  1719. for (i = 0; i < 84; i++)
  1720. b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
  1721. tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
  1722. if (dev->phy.rev >= 3)
  1723. tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
  1724. b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
  1725. if (dev->phy.rev >= 3) {
  1726. b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
  1727. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
  1728. } else {
  1729. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
  1730. }
  1731. if (dev->phy.rev == 2)
  1732. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
  1733. ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
  1734. else if (dev->phy.rev < 2)
  1735. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
  1736. ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
  1737. if (dev->phy.rev < 2 && dev->phy.is_40mhz)
  1738. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
  1739. } else {
  1740. b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
  1741. nphy->adj_pwr_tbl);
  1742. b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
  1743. nphy->adj_pwr_tbl);
  1744. bmask = B43_NPHY_TXPCTL_CMD_COEFF |
  1745. B43_NPHY_TXPCTL_CMD_HWPCTLEN;
  1746. /* wl does useless check for "enable" param here */
  1747. val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
  1748. if (dev->phy.rev >= 3) {
  1749. bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
  1750. if (val)
  1751. val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
  1752. }
  1753. b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
  1754. if (band == IEEE80211_BAND_5GHZ) {
  1755. b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
  1756. ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
  1757. if (dev->phy.rev > 1)
  1758. b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
  1759. ~B43_NPHY_TXPCTL_INIT_PIDXI1,
  1760. 0x64);
  1761. }
  1762. if (dev->phy.rev >= 3) {
  1763. if (nphy->tx_pwr_idx[0] != 128 &&
  1764. nphy->tx_pwr_idx[1] != 128) {
  1765. /* Recover TX pwr ctl state */
  1766. b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
  1767. ~B43_NPHY_TXPCTL_CMD_INIT,
  1768. nphy->tx_pwr_idx[0]);
  1769. if (dev->phy.rev > 1)
  1770. b43_phy_maskset(dev,
  1771. B43_NPHY_TXPCTL_INIT,
  1772. ~0xff, nphy->tx_pwr_idx[1]);
  1773. }
  1774. }
  1775. if (dev->phy.rev >= 3) {
  1776. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
  1777. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
  1778. } else {
  1779. b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
  1780. }
  1781. if (dev->phy.rev == 2)
  1782. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
  1783. else if (dev->phy.rev < 2)
  1784. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
  1785. if (dev->phy.rev < 2 && dev->phy.is_40mhz)
  1786. b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
  1787. if (b43_nphy_ipa(dev)) {
  1788. b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
  1789. b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
  1790. }
  1791. }
  1792. if (nphy->hang_avoid)
  1793. b43_nphy_stay_in_carrier_search(dev, 0);
  1794. }
  1795. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
  1796. static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
  1797. {
  1798. struct b43_phy_n *nphy = dev->phy.n;
  1799. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  1800. u8 txpi[2], bbmult, i;
  1801. u16 tmp, radio_gain, dac_gain;
  1802. u16 freq = dev->phy.channel_freq;
  1803. u32 txgain;
  1804. /* u32 gaintbl; rev3+ */
  1805. if (nphy->hang_avoid)
  1806. b43_nphy_stay_in_carrier_search(dev, 1);
  1807. if (dev->phy.rev >= 7) {
  1808. txpi[0] = txpi[1] = 30;
  1809. } else if (dev->phy.rev >= 3) {
  1810. txpi[0] = 40;
  1811. txpi[1] = 40;
  1812. } else if (sprom->revision < 4) {
  1813. txpi[0] = 72;
  1814. txpi[1] = 72;
  1815. } else {
  1816. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  1817. txpi[0] = sprom->txpid2g[0];
  1818. txpi[1] = sprom->txpid2g[1];
  1819. } else if (freq >= 4900 && freq < 5100) {
  1820. txpi[0] = sprom->txpid5gl[0];
  1821. txpi[1] = sprom->txpid5gl[1];
  1822. } else if (freq >= 5100 && freq < 5500) {
  1823. txpi[0] = sprom->txpid5g[0];
  1824. txpi[1] = sprom->txpid5g[1];
  1825. } else if (freq >= 5500) {
  1826. txpi[0] = sprom->txpid5gh[0];
  1827. txpi[1] = sprom->txpid5gh[1];
  1828. } else {
  1829. txpi[0] = 91;
  1830. txpi[1] = 91;
  1831. }
  1832. }
  1833. if (dev->phy.rev < 7 &&
  1834. (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
  1835. txpi[0] = txpi[1] = 91;
  1836. /*
  1837. for (i = 0; i < 2; i++) {
  1838. nphy->txpwrindex[i].index_internal = txpi[i];
  1839. nphy->txpwrindex[i].index_internal_save = txpi[i];
  1840. }
  1841. */
  1842. for (i = 0; i < 2; i++) {
  1843. if (dev->phy.rev >= 3) {
  1844. if (b43_nphy_ipa(dev)) {
  1845. txgain = *(b43_nphy_get_ipa_gain_table(dev) +
  1846. txpi[i]);
  1847. } else if (b43_current_band(dev->wl) ==
  1848. IEEE80211_BAND_5GHZ) {
  1849. /* FIXME: use 5GHz tables */
  1850. txgain =
  1851. b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
  1852. } else {
  1853. if (dev->phy.rev >= 5 &&
  1854. sprom->fem.ghz5.extpa_gain == 3)
  1855. ; /* FIXME: 5GHz_txgain_HiPwrEPA */
  1856. txgain =
  1857. b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
  1858. }
  1859. radio_gain = (txgain >> 16) & 0x1FFFF;
  1860. } else {
  1861. txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
  1862. radio_gain = (txgain >> 16) & 0x1FFF;
  1863. }
  1864. if (dev->phy.rev >= 7)
  1865. dac_gain = (txgain >> 8) & 0x7;
  1866. else
  1867. dac_gain = (txgain >> 8) & 0x3F;
  1868. bbmult = txgain & 0xFF;
  1869. if (dev->phy.rev >= 3) {
  1870. if (i == 0)
  1871. b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
  1872. else
  1873. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
  1874. } else {
  1875. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
  1876. }
  1877. if (i == 0)
  1878. b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
  1879. else
  1880. b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
  1881. b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
  1882. tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
  1883. if (i == 0)
  1884. tmp = (tmp & 0x00FF) | (bbmult << 8);
  1885. else
  1886. tmp = (tmp & 0xFF00) | bbmult;
  1887. b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
  1888. if (b43_nphy_ipa(dev)) {
  1889. u32 tmp32;
  1890. u16 reg = (i == 0) ?
  1891. B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
  1892. tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
  1893. 576 + txpi[i]));
  1894. b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
  1895. b43_phy_set(dev, reg, 0x4);
  1896. }
  1897. }
  1898. b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
  1899. if (nphy->hang_avoid)
  1900. b43_nphy_stay_in_carrier_search(dev, 0);
  1901. }
  1902. static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
  1903. {
  1904. struct b43_phy *phy = &dev->phy;
  1905. const u32 *table = NULL;
  1906. #if 0
  1907. TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
  1908. u32 rfpwr_offset;
  1909. u8 pga_gain;
  1910. int i;
  1911. #endif
  1912. if (phy->rev >= 3) {
  1913. if (b43_nphy_ipa(dev)) {
  1914. table = b43_nphy_get_ipa_gain_table(dev);
  1915. } else {
  1916. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  1917. if (phy->rev == 3)
  1918. table = b43_ntab_tx_gain_rev3_5ghz;
  1919. if (phy->rev == 4)
  1920. table = b43_ntab_tx_gain_rev4_5ghz;
  1921. else
  1922. table = b43_ntab_tx_gain_rev5plus_5ghz;
  1923. } else {
  1924. table = b43_ntab_tx_gain_rev3plus_2ghz;
  1925. }
  1926. }
  1927. } else {
  1928. table = b43_ntab_tx_gain_rev0_1_2;
  1929. }
  1930. b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
  1931. b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
  1932. if (phy->rev >= 3) {
  1933. #if 0
  1934. nphy->gmval = (table[0] >> 16) & 0x7000;
  1935. for (i = 0; i < 128; i++) {
  1936. pga_gain = (table[i] >> 24) & 0xF;
  1937. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  1938. rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
  1939. else
  1940. rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
  1941. b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
  1942. rfpwr_offset);
  1943. b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
  1944. rfpwr_offset);
  1945. }
  1946. #endif
  1947. }
  1948. }
  1949. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
  1950. static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
  1951. {
  1952. struct b43_phy_n *nphy = dev->phy.n;
  1953. enum ieee80211_band band;
  1954. u16 tmp;
  1955. if (!enable) {
  1956. nphy->rfctrl_intc1_save = b43_phy_read(dev,
  1957. B43_NPHY_RFCTL_INTC1);
  1958. nphy->rfctrl_intc2_save = b43_phy_read(dev,
  1959. B43_NPHY_RFCTL_INTC2);
  1960. band = b43_current_band(dev->wl);
  1961. if (dev->phy.rev >= 3) {
  1962. if (band == IEEE80211_BAND_5GHZ)
  1963. tmp = 0x600;
  1964. else
  1965. tmp = 0x480;
  1966. } else {
  1967. if (band == IEEE80211_BAND_5GHZ)
  1968. tmp = 0x180;
  1969. else
  1970. tmp = 0x120;
  1971. }
  1972. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
  1973. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
  1974. } else {
  1975. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
  1976. nphy->rfctrl_intc1_save);
  1977. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
  1978. nphy->rfctrl_intc2_save);
  1979. }
  1980. }
  1981. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
  1982. static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
  1983. {
  1984. u16 tmp;
  1985. if (dev->phy.rev >= 3) {
  1986. if (b43_nphy_ipa(dev)) {
  1987. tmp = 4;
  1988. b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
  1989. (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
  1990. }
  1991. tmp = 1;
  1992. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
  1993. (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
  1994. }
  1995. }
  1996. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
  1997. static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
  1998. {
  1999. struct b43_phy_n *nphy = dev->phy.n;
  2000. bool override = false;
  2001. u16 chain = 0x33;
  2002. if (nphy->txrx_chain == 0) {
  2003. chain = 0x11;
  2004. override = true;
  2005. } else if (nphy->txrx_chain == 1) {
  2006. chain = 0x22;
  2007. override = true;
  2008. }
  2009. b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
  2010. ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
  2011. chain);
  2012. if (override)
  2013. b43_phy_set(dev, B43_NPHY_RFSEQMODE,
  2014. B43_NPHY_RFSEQMODE_CAOVER);
  2015. else
  2016. b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
  2017. ~B43_NPHY_RFSEQMODE_CAOVER);
  2018. }
  2019. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
  2020. static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
  2021. u16 samps, u8 time, bool wait)
  2022. {
  2023. int i;
  2024. u16 tmp;
  2025. b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
  2026. b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
  2027. if (wait)
  2028. b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
  2029. else
  2030. b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
  2031. b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
  2032. for (i = 1000; i; i--) {
  2033. tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
  2034. if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
  2035. est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
  2036. b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
  2037. est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
  2038. b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
  2039. est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
  2040. b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
  2041. est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
  2042. b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
  2043. est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
  2044. b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
  2045. est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
  2046. b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
  2047. return;
  2048. }
  2049. udelay(10);
  2050. }
  2051. memset(est, 0, sizeof(*est));
  2052. }
  2053. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
  2054. static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
  2055. struct b43_phy_n_iq_comp *pcomp)
  2056. {
  2057. if (write) {
  2058. b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
  2059. b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
  2060. b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
  2061. b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
  2062. } else {
  2063. pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
  2064. pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
  2065. pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
  2066. pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
  2067. }
  2068. }
  2069. #if 0
  2070. /* Ready but not used anywhere */
  2071. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
  2072. static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
  2073. {
  2074. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  2075. b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
  2076. if (core == 0) {
  2077. b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
  2078. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
  2079. } else {
  2080. b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
  2081. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
  2082. }
  2083. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
  2084. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
  2085. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
  2086. b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
  2087. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
  2088. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
  2089. b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
  2090. b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
  2091. }
  2092. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
  2093. static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
  2094. {
  2095. u8 rxval, txval;
  2096. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  2097. regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
  2098. if (core == 0) {
  2099. regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  2100. regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
  2101. } else {
  2102. regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  2103. regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  2104. }
  2105. regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  2106. regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  2107. regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
  2108. regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
  2109. regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
  2110. regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
  2111. regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
  2112. regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
  2113. b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
  2114. b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
  2115. b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
  2116. ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
  2117. ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
  2118. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
  2119. ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
  2120. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
  2121. (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
  2122. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
  2123. (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
  2124. if (core == 0) {
  2125. b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
  2126. b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
  2127. } else {
  2128. b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
  2129. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
  2130. }
  2131. b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
  2132. b43_nphy_rf_control_override(dev, 8, 0, 3, false);
  2133. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
  2134. if (core == 0) {
  2135. rxval = 1;
  2136. txval = 8;
  2137. } else {
  2138. rxval = 4;
  2139. txval = 2;
  2140. }
  2141. b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
  2142. b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
  2143. }
  2144. #endif
  2145. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
  2146. static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
  2147. {
  2148. int i;
  2149. s32 iq;
  2150. u32 ii;
  2151. u32 qq;
  2152. int iq_nbits, qq_nbits;
  2153. int arsh, brsh;
  2154. u16 tmp, a, b;
  2155. struct nphy_iq_est est;
  2156. struct b43_phy_n_iq_comp old;
  2157. struct b43_phy_n_iq_comp new = { };
  2158. bool error = false;
  2159. if (mask == 0)
  2160. return;
  2161. b43_nphy_rx_iq_coeffs(dev, false, &old);
  2162. b43_nphy_rx_iq_coeffs(dev, true, &new);
  2163. b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
  2164. new = old;
  2165. for (i = 0; i < 2; i++) {
  2166. if (i == 0 && (mask & 1)) {
  2167. iq = est.iq0_prod;
  2168. ii = est.i0_pwr;
  2169. qq = est.q0_pwr;
  2170. } else if (i == 1 && (mask & 2)) {
  2171. iq = est.iq1_prod;
  2172. ii = est.i1_pwr;
  2173. qq = est.q1_pwr;
  2174. } else {
  2175. continue;
  2176. }
  2177. if (ii + qq < 2) {
  2178. error = true;
  2179. break;
  2180. }
  2181. iq_nbits = fls(abs(iq));
  2182. qq_nbits = fls(qq);
  2183. arsh = iq_nbits - 20;
  2184. if (arsh >= 0) {
  2185. a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
  2186. tmp = ii >> arsh;
  2187. } else {
  2188. a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
  2189. tmp = ii << -arsh;
  2190. }
  2191. if (tmp == 0) {
  2192. error = true;
  2193. break;
  2194. }
  2195. a /= tmp;
  2196. brsh = qq_nbits - 11;
  2197. if (brsh >= 0) {
  2198. b = (qq << (31 - qq_nbits));
  2199. tmp = ii >> brsh;
  2200. } else {
  2201. b = (qq << (31 - qq_nbits));
  2202. tmp = ii << -brsh;
  2203. }
  2204. if (tmp == 0) {
  2205. error = true;
  2206. break;
  2207. }
  2208. b = int_sqrt(b / tmp - a * a) - (1 << 10);
  2209. if (i == 0 && (mask & 0x1)) {
  2210. if (dev->phy.rev >= 3) {
  2211. new.a0 = a & 0x3FF;
  2212. new.b0 = b & 0x3FF;
  2213. } else {
  2214. new.a0 = b & 0x3FF;
  2215. new.b0 = a & 0x3FF;
  2216. }
  2217. } else if (i == 1 && (mask & 0x2)) {
  2218. if (dev->phy.rev >= 3) {
  2219. new.a1 = a & 0x3FF;
  2220. new.b1 = b & 0x3FF;
  2221. } else {
  2222. new.a1 = b & 0x3FF;
  2223. new.b1 = a & 0x3FF;
  2224. }
  2225. }
  2226. }
  2227. if (error)
  2228. new = old;
  2229. b43_nphy_rx_iq_coeffs(dev, true, &new);
  2230. }
  2231. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
  2232. static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
  2233. {
  2234. u16 array[4];
  2235. b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
  2236. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
  2237. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
  2238. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
  2239. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
  2240. }
  2241. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
  2242. static void b43_nphy_stop_playback(struct b43_wldev *dev)
  2243. {
  2244. struct b43_phy_n *nphy = dev->phy.n;
  2245. u16 tmp;
  2246. if (nphy->hang_avoid)
  2247. b43_nphy_stay_in_carrier_search(dev, 1);
  2248. tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
  2249. if (tmp & 0x1)
  2250. b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
  2251. else if (tmp & 0x2)
  2252. b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
  2253. b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
  2254. if (nphy->bb_mult_save & 0x80000000) {
  2255. tmp = nphy->bb_mult_save & 0xFFFF;
  2256. b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
  2257. nphy->bb_mult_save = 0;
  2258. }
  2259. if (nphy->hang_avoid)
  2260. b43_nphy_stay_in_carrier_search(dev, 0);
  2261. }
  2262. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
  2263. static void b43_nphy_spur_workaround(struct b43_wldev *dev)
  2264. {
  2265. struct b43_phy_n *nphy = dev->phy.n;
  2266. u8 channel = dev->phy.channel;
  2267. int tone[2] = { 57, 58 };
  2268. u32 noise[2] = { 0x3FF, 0x3FF };
  2269. B43_WARN_ON(dev->phy.rev < 3);
  2270. if (nphy->hang_avoid)
  2271. b43_nphy_stay_in_carrier_search(dev, 1);
  2272. if (nphy->gband_spurwar_en) {
  2273. /* TODO: N PHY Adjust Analog Pfbw (7) */
  2274. if (channel == 11 && dev->phy.is_40mhz)
  2275. ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
  2276. else
  2277. ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
  2278. /* TODO: N PHY Adjust CRS Min Power (0x1E) */
  2279. }
  2280. if (nphy->aband_spurwar_en) {
  2281. if (channel == 54) {
  2282. tone[0] = 0x20;
  2283. noise[0] = 0x25F;
  2284. } else if (channel == 38 || channel == 102 || channel == 118) {
  2285. if (0 /* FIXME */) {
  2286. tone[0] = 0x20;
  2287. noise[0] = 0x21F;
  2288. } else {
  2289. tone[0] = 0;
  2290. noise[0] = 0;
  2291. }
  2292. } else if (channel == 134) {
  2293. tone[0] = 0x20;
  2294. noise[0] = 0x21F;
  2295. } else if (channel == 151) {
  2296. tone[0] = 0x10;
  2297. noise[0] = 0x23F;
  2298. } else if (channel == 153 || channel == 161) {
  2299. tone[0] = 0x30;
  2300. noise[0] = 0x23F;
  2301. } else {
  2302. tone[0] = 0;
  2303. noise[0] = 0;
  2304. }
  2305. if (!tone[0] && !noise[0])
  2306. ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
  2307. else
  2308. ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
  2309. }
  2310. if (nphy->hang_avoid)
  2311. b43_nphy_stay_in_carrier_search(dev, 0);
  2312. }
  2313. /*
  2314. * Transmits a known value for LO calibration
  2315. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
  2316. */
  2317. static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
  2318. bool iqmode, bool dac_test)
  2319. {
  2320. u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
  2321. if (samp == 0)
  2322. return -1;
  2323. b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
  2324. return 0;
  2325. }
  2326. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
  2327. static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
  2328. {
  2329. struct b43_phy_n *nphy = dev->phy.n;
  2330. int i, j;
  2331. u32 tmp;
  2332. u32 cur_real, cur_imag, real_part, imag_part;
  2333. u16 buffer[7];
  2334. if (nphy->hang_avoid)
  2335. b43_nphy_stay_in_carrier_search(dev, true);
  2336. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
  2337. for (i = 0; i < 2; i++) {
  2338. tmp = ((buffer[i * 2] & 0x3FF) << 10) |
  2339. (buffer[i * 2 + 1] & 0x3FF);
  2340. b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
  2341. (((i + 26) << 10) | 320));
  2342. for (j = 0; j < 128; j++) {
  2343. b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
  2344. ((tmp >> 16) & 0xFFFF));
  2345. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  2346. (tmp & 0xFFFF));
  2347. }
  2348. }
  2349. for (i = 0; i < 2; i++) {
  2350. tmp = buffer[5 + i];
  2351. real_part = (tmp >> 8) & 0xFF;
  2352. imag_part = (tmp & 0xFF);
  2353. b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
  2354. (((i + 26) << 10) | 448));
  2355. if (dev->phy.rev >= 3) {
  2356. cur_real = real_part;
  2357. cur_imag = imag_part;
  2358. tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
  2359. }
  2360. for (j = 0; j < 128; j++) {
  2361. if (dev->phy.rev < 3) {
  2362. cur_real = (real_part * loscale[j] + 128) >> 8;
  2363. cur_imag = (imag_part * loscale[j] + 128) >> 8;
  2364. tmp = ((cur_real & 0xFF) << 8) |
  2365. (cur_imag & 0xFF);
  2366. }
  2367. b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
  2368. ((tmp >> 16) & 0xFFFF));
  2369. b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
  2370. (tmp & 0xFFFF));
  2371. }
  2372. }
  2373. if (dev->phy.rev >= 3) {
  2374. b43_shm_write16(dev, B43_SHM_SHARED,
  2375. B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
  2376. b43_shm_write16(dev, B43_SHM_SHARED,
  2377. B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
  2378. }
  2379. if (nphy->hang_avoid)
  2380. b43_nphy_stay_in_carrier_search(dev, false);
  2381. }
  2382. /*
  2383. * Restore RSSI Calibration
  2384. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
  2385. */
  2386. static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
  2387. {
  2388. struct b43_phy_n *nphy = dev->phy.n;
  2389. u16 *rssical_radio_regs = NULL;
  2390. u16 *rssical_phy_regs = NULL;
  2391. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2392. if (!nphy->rssical_chanspec_2G.center_freq)
  2393. return;
  2394. rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
  2395. rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
  2396. } else {
  2397. if (!nphy->rssical_chanspec_5G.center_freq)
  2398. return;
  2399. rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
  2400. rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
  2401. }
  2402. /* TODO use some definitions */
  2403. b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
  2404. b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
  2405. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
  2406. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
  2407. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
  2408. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
  2409. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
  2410. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
  2411. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
  2412. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
  2413. b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
  2414. b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
  2415. b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
  2416. b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
  2417. }
  2418. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
  2419. static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
  2420. {
  2421. struct b43_phy_n *nphy = dev->phy.n;
  2422. u16 *save = nphy->tx_rx_cal_radio_saveregs;
  2423. u16 tmp;
  2424. u8 offset, i;
  2425. if (dev->phy.rev >= 3) {
  2426. for (i = 0; i < 2; i++) {
  2427. tmp = (i == 0) ? 0x2000 : 0x3000;
  2428. offset = i * 11;
  2429. save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
  2430. save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
  2431. save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
  2432. save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
  2433. save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
  2434. save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
  2435. save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
  2436. save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
  2437. save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
  2438. save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
  2439. save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
  2440. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  2441. b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
  2442. b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
  2443. b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
  2444. b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
  2445. b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
  2446. if (nphy->ipa5g_on) {
  2447. b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
  2448. b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
  2449. } else {
  2450. b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
  2451. b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
  2452. }
  2453. b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
  2454. } else {
  2455. b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
  2456. b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
  2457. b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
  2458. b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
  2459. b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
  2460. b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
  2461. if (nphy->ipa2g_on) {
  2462. b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
  2463. b43_radio_write16(dev, tmp | B2055_XOCTL2,
  2464. (dev->phy.rev < 5) ? 0x11 : 0x01);
  2465. } else {
  2466. b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
  2467. b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
  2468. }
  2469. }
  2470. b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
  2471. b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
  2472. b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
  2473. }
  2474. } else {
  2475. save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
  2476. b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
  2477. save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
  2478. b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
  2479. save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
  2480. b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
  2481. save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
  2482. b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
  2483. save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
  2484. save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
  2485. if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
  2486. B43_NPHY_BANDCTL_5GHZ)) {
  2487. b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
  2488. b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
  2489. } else {
  2490. b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
  2491. b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
  2492. }
  2493. if (dev->phy.rev < 2) {
  2494. b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
  2495. b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
  2496. } else {
  2497. b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
  2498. b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
  2499. }
  2500. }
  2501. }
  2502. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
  2503. static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
  2504. struct nphy_txgains target,
  2505. struct nphy_iqcal_params *params)
  2506. {
  2507. int i, j, indx;
  2508. u16 gain;
  2509. if (dev->phy.rev >= 3) {
  2510. params->txgm = target.txgm[core];
  2511. params->pga = target.pga[core];
  2512. params->pad = target.pad[core];
  2513. params->ipa = target.ipa[core];
  2514. params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
  2515. (params->pad << 4) | (params->ipa);
  2516. for (j = 0; j < 5; j++)
  2517. params->ncorr[j] = 0x79;
  2518. } else {
  2519. gain = (target.pad[core]) | (target.pga[core] << 4) |
  2520. (target.txgm[core] << 8);
  2521. indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
  2522. 1 : 0;
  2523. for (i = 0; i < 9; i++)
  2524. if (tbl_iqcal_gainparams[indx][i][0] == gain)
  2525. break;
  2526. i = min(i, 8);
  2527. params->txgm = tbl_iqcal_gainparams[indx][i][1];
  2528. params->pga = tbl_iqcal_gainparams[indx][i][2];
  2529. params->pad = tbl_iqcal_gainparams[indx][i][3];
  2530. params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
  2531. (params->pad << 2);
  2532. for (j = 0; j < 4; j++)
  2533. params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
  2534. }
  2535. }
  2536. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
  2537. static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
  2538. {
  2539. struct b43_phy_n *nphy = dev->phy.n;
  2540. int i;
  2541. u16 scale, entry;
  2542. u16 tmp = nphy->txcal_bbmult;
  2543. if (core == 0)
  2544. tmp >>= 8;
  2545. tmp &= 0xff;
  2546. for (i = 0; i < 18; i++) {
  2547. scale = (ladder_lo[i].percent * tmp) / 100;
  2548. entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
  2549. b43_ntab_write(dev, B43_NTAB16(15, i), entry);
  2550. scale = (ladder_iq[i].percent * tmp) / 100;
  2551. entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
  2552. b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
  2553. }
  2554. }
  2555. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
  2556. static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
  2557. {
  2558. int i;
  2559. for (i = 0; i < 15; i++)
  2560. b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
  2561. tbl_tx_filter_coef_rev4[2][i]);
  2562. }
  2563. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
  2564. static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
  2565. {
  2566. int i, j;
  2567. /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
  2568. static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
  2569. for (i = 0; i < 3; i++)
  2570. for (j = 0; j < 15; j++)
  2571. b43_phy_write(dev, B43_PHY_N(offset[i] + j),
  2572. tbl_tx_filter_coef_rev4[i][j]);
  2573. if (dev->phy.is_40mhz) {
  2574. for (j = 0; j < 15; j++)
  2575. b43_phy_write(dev, B43_PHY_N(offset[0] + j),
  2576. tbl_tx_filter_coef_rev4[3][j]);
  2577. } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
  2578. for (j = 0; j < 15; j++)
  2579. b43_phy_write(dev, B43_PHY_N(offset[0] + j),
  2580. tbl_tx_filter_coef_rev4[5][j]);
  2581. }
  2582. if (dev->phy.channel == 14)
  2583. for (j = 0; j < 15; j++)
  2584. b43_phy_write(dev, B43_PHY_N(offset[0] + j),
  2585. tbl_tx_filter_coef_rev4[6][j]);
  2586. }
  2587. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
  2588. static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
  2589. {
  2590. struct b43_phy_n *nphy = dev->phy.n;
  2591. u16 curr_gain[2];
  2592. struct nphy_txgains target;
  2593. const u32 *table = NULL;
  2594. if (!nphy->txpwrctrl) {
  2595. int i;
  2596. if (nphy->hang_avoid)
  2597. b43_nphy_stay_in_carrier_search(dev, true);
  2598. b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
  2599. if (nphy->hang_avoid)
  2600. b43_nphy_stay_in_carrier_search(dev, false);
  2601. for (i = 0; i < 2; ++i) {
  2602. if (dev->phy.rev >= 3) {
  2603. target.ipa[i] = curr_gain[i] & 0x000F;
  2604. target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
  2605. target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
  2606. target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
  2607. } else {
  2608. target.ipa[i] = curr_gain[i] & 0x0003;
  2609. target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
  2610. target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
  2611. target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
  2612. }
  2613. }
  2614. } else {
  2615. int i;
  2616. u16 index[2];
  2617. index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
  2618. B43_NPHY_TXPCTL_STAT_BIDX) >>
  2619. B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
  2620. index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
  2621. B43_NPHY_TXPCTL_STAT_BIDX) >>
  2622. B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
  2623. for (i = 0; i < 2; ++i) {
  2624. if (dev->phy.rev >= 3) {
  2625. enum ieee80211_band band =
  2626. b43_current_band(dev->wl);
  2627. if (b43_nphy_ipa(dev)) {
  2628. table = b43_nphy_get_ipa_gain_table(dev);
  2629. } else {
  2630. if (band == IEEE80211_BAND_5GHZ) {
  2631. if (dev->phy.rev == 3)
  2632. table = b43_ntab_tx_gain_rev3_5ghz;
  2633. else if (dev->phy.rev == 4)
  2634. table = b43_ntab_tx_gain_rev4_5ghz;
  2635. else
  2636. table = b43_ntab_tx_gain_rev5plus_5ghz;
  2637. } else {
  2638. table = b43_ntab_tx_gain_rev3plus_2ghz;
  2639. }
  2640. }
  2641. target.ipa[i] = (table[index[i]] >> 16) & 0xF;
  2642. target.pad[i] = (table[index[i]] >> 20) & 0xF;
  2643. target.pga[i] = (table[index[i]] >> 24) & 0xF;
  2644. target.txgm[i] = (table[index[i]] >> 28) & 0xF;
  2645. } else {
  2646. table = b43_ntab_tx_gain_rev0_1_2;
  2647. target.ipa[i] = (table[index[i]] >> 16) & 0x3;
  2648. target.pad[i] = (table[index[i]] >> 18) & 0x3;
  2649. target.pga[i] = (table[index[i]] >> 20) & 0x7;
  2650. target.txgm[i] = (table[index[i]] >> 23) & 0x7;
  2651. }
  2652. }
  2653. }
  2654. return target;
  2655. }
  2656. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
  2657. static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
  2658. {
  2659. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  2660. if (dev->phy.rev >= 3) {
  2661. b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
  2662. b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
  2663. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
  2664. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
  2665. b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
  2666. b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
  2667. b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
  2668. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
  2669. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
  2670. b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
  2671. b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
  2672. b43_nphy_reset_cca(dev);
  2673. } else {
  2674. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
  2675. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
  2676. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
  2677. b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
  2678. b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
  2679. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
  2680. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
  2681. }
  2682. }
  2683. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
  2684. static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
  2685. {
  2686. u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
  2687. u16 tmp;
  2688. regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
  2689. regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
  2690. if (dev->phy.rev >= 3) {
  2691. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
  2692. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
  2693. tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
  2694. regs[2] = tmp;
  2695. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
  2696. tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  2697. regs[3] = tmp;
  2698. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
  2699. regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
  2700. b43_phy_mask(dev, B43_NPHY_BBCFG,
  2701. ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
  2702. tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
  2703. regs[5] = tmp;
  2704. b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
  2705. tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
  2706. regs[6] = tmp;
  2707. b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
  2708. regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  2709. regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  2710. b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
  2711. b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
  2712. b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
  2713. regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
  2714. regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
  2715. b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
  2716. b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
  2717. } else {
  2718. b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
  2719. b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
  2720. tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  2721. regs[2] = tmp;
  2722. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
  2723. tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
  2724. regs[3] = tmp;
  2725. tmp |= 0x2000;
  2726. b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
  2727. tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
  2728. regs[4] = tmp;
  2729. tmp |= 0x2000;
  2730. b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
  2731. regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
  2732. regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
  2733. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  2734. tmp = 0x0180;
  2735. else
  2736. tmp = 0x0120;
  2737. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
  2738. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
  2739. }
  2740. }
  2741. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
  2742. static void b43_nphy_save_cal(struct b43_wldev *dev)
  2743. {
  2744. struct b43_phy_n *nphy = dev->phy.n;
  2745. struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
  2746. u16 *txcal_radio_regs = NULL;
  2747. struct b43_chanspec *iqcal_chanspec;
  2748. u16 *table = NULL;
  2749. if (nphy->hang_avoid)
  2750. b43_nphy_stay_in_carrier_search(dev, 1);
  2751. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2752. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
  2753. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
  2754. iqcal_chanspec = &nphy->iqcal_chanspec_2G;
  2755. table = nphy->cal_cache.txcal_coeffs_2G;
  2756. } else {
  2757. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
  2758. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
  2759. iqcal_chanspec = &nphy->iqcal_chanspec_5G;
  2760. table = nphy->cal_cache.txcal_coeffs_5G;
  2761. }
  2762. b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
  2763. /* TODO use some definitions */
  2764. if (dev->phy.rev >= 3) {
  2765. txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
  2766. txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
  2767. txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
  2768. txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
  2769. txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
  2770. txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
  2771. txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
  2772. txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
  2773. } else {
  2774. txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
  2775. txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
  2776. txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
  2777. txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
  2778. }
  2779. iqcal_chanspec->center_freq = dev->phy.channel_freq;
  2780. iqcal_chanspec->channel_type = dev->phy.channel_type;
  2781. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
  2782. if (nphy->hang_avoid)
  2783. b43_nphy_stay_in_carrier_search(dev, 0);
  2784. }
  2785. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
  2786. static void b43_nphy_restore_cal(struct b43_wldev *dev)
  2787. {
  2788. struct b43_phy_n *nphy = dev->phy.n;
  2789. u16 coef[4];
  2790. u16 *loft = NULL;
  2791. u16 *table = NULL;
  2792. int i;
  2793. u16 *txcal_radio_regs = NULL;
  2794. struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
  2795. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2796. if (!nphy->iqcal_chanspec_2G.center_freq)
  2797. return;
  2798. table = nphy->cal_cache.txcal_coeffs_2G;
  2799. loft = &nphy->cal_cache.txcal_coeffs_2G[5];
  2800. } else {
  2801. if (!nphy->iqcal_chanspec_5G.center_freq)
  2802. return;
  2803. table = nphy->cal_cache.txcal_coeffs_5G;
  2804. loft = &nphy->cal_cache.txcal_coeffs_5G[5];
  2805. }
  2806. b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
  2807. for (i = 0; i < 4; i++) {
  2808. if (dev->phy.rev >= 3)
  2809. table[i] = coef[i];
  2810. else
  2811. coef[i] = 0;
  2812. }
  2813. b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
  2814. b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
  2815. b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
  2816. if (dev->phy.rev < 2)
  2817. b43_nphy_tx_iq_workaround(dev);
  2818. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  2819. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
  2820. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
  2821. } else {
  2822. txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
  2823. rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
  2824. }
  2825. /* TODO use some definitions */
  2826. if (dev->phy.rev >= 3) {
  2827. b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
  2828. b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
  2829. b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
  2830. b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
  2831. b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
  2832. b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
  2833. b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
  2834. b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
  2835. } else {
  2836. b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
  2837. b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
  2838. b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
  2839. b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
  2840. }
  2841. b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
  2842. }
  2843. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
  2844. static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
  2845. struct nphy_txgains target,
  2846. bool full, bool mphase)
  2847. {
  2848. struct b43_phy_n *nphy = dev->phy.n;
  2849. int i;
  2850. int error = 0;
  2851. int freq;
  2852. bool avoid = false;
  2853. u8 length;
  2854. u16 tmp, core, type, count, max, numb, last = 0, cmd;
  2855. const u16 *table;
  2856. bool phy6or5x;
  2857. u16 buffer[11];
  2858. u16 diq_start = 0;
  2859. u16 save[2];
  2860. u16 gain[2];
  2861. struct nphy_iqcal_params params[2];
  2862. bool updated[2] = { };
  2863. b43_nphy_stay_in_carrier_search(dev, true);
  2864. if (dev->phy.rev >= 4) {
  2865. avoid = nphy->hang_avoid;
  2866. nphy->hang_avoid = 0;
  2867. }
  2868. b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
  2869. for (i = 0; i < 2; i++) {
  2870. b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
  2871. gain[i] = params[i].cal_gain;
  2872. }
  2873. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
  2874. b43_nphy_tx_cal_radio_setup(dev);
  2875. b43_nphy_tx_cal_phy_setup(dev);
  2876. phy6or5x = dev->phy.rev >= 6 ||
  2877. (dev->phy.rev == 5 && nphy->ipa2g_on &&
  2878. b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
  2879. if (phy6or5x) {
  2880. if (dev->phy.is_40mhz) {
  2881. b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
  2882. tbl_tx_iqlo_cal_loft_ladder_40);
  2883. b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
  2884. tbl_tx_iqlo_cal_iqimb_ladder_40);
  2885. } else {
  2886. b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
  2887. tbl_tx_iqlo_cal_loft_ladder_20);
  2888. b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
  2889. tbl_tx_iqlo_cal_iqimb_ladder_20);
  2890. }
  2891. }
  2892. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
  2893. if (!dev->phy.is_40mhz)
  2894. freq = 2500;
  2895. else
  2896. freq = 5000;
  2897. if (nphy->mphase_cal_phase_id > 2)
  2898. b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
  2899. 0xFFFF, 0, true, false);
  2900. else
  2901. error = b43_nphy_tx_tone(dev, freq, 250, true, false);
  2902. if (error == 0) {
  2903. if (nphy->mphase_cal_phase_id > 2) {
  2904. table = nphy->mphase_txcal_bestcoeffs;
  2905. length = 11;
  2906. if (dev->phy.rev < 3)
  2907. length -= 2;
  2908. } else {
  2909. if (!full && nphy->txiqlocal_coeffsvalid) {
  2910. table = nphy->txiqlocal_bestc;
  2911. length = 11;
  2912. if (dev->phy.rev < 3)
  2913. length -= 2;
  2914. } else {
  2915. full = true;
  2916. if (dev->phy.rev >= 3) {
  2917. table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
  2918. length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
  2919. } else {
  2920. table = tbl_tx_iqlo_cal_startcoefs;
  2921. length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
  2922. }
  2923. }
  2924. }
  2925. b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
  2926. if (full) {
  2927. if (dev->phy.rev >= 3)
  2928. max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
  2929. else
  2930. max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
  2931. } else {
  2932. if (dev->phy.rev >= 3)
  2933. max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
  2934. else
  2935. max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
  2936. }
  2937. if (mphase) {
  2938. count = nphy->mphase_txcal_cmdidx;
  2939. numb = min(max,
  2940. (u16)(count + nphy->mphase_txcal_numcmds));
  2941. } else {
  2942. count = 0;
  2943. numb = max;
  2944. }
  2945. for (; count < numb; count++) {
  2946. if (full) {
  2947. if (dev->phy.rev >= 3)
  2948. cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
  2949. else
  2950. cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
  2951. } else {
  2952. if (dev->phy.rev >= 3)
  2953. cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
  2954. else
  2955. cmd = tbl_tx_iqlo_cal_cmds_recal[count];
  2956. }
  2957. core = (cmd & 0x3000) >> 12;
  2958. type = (cmd & 0x0F00) >> 8;
  2959. if (phy6or5x && updated[core] == 0) {
  2960. b43_nphy_update_tx_cal_ladder(dev, core);
  2961. updated[core] = 1;
  2962. }
  2963. tmp = (params[core].ncorr[type] << 8) | 0x66;
  2964. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
  2965. if (type == 1 || type == 3 || type == 4) {
  2966. buffer[0] = b43_ntab_read(dev,
  2967. B43_NTAB16(15, 69 + core));
  2968. diq_start = buffer[0];
  2969. buffer[0] = 0;
  2970. b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
  2971. 0);
  2972. }
  2973. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
  2974. for (i = 0; i < 2000; i++) {
  2975. tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
  2976. if (tmp & 0xC000)
  2977. break;
  2978. udelay(10);
  2979. }
  2980. b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
  2981. buffer);
  2982. b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
  2983. buffer);
  2984. if (type == 1 || type == 3 || type == 4)
  2985. buffer[0] = diq_start;
  2986. }
  2987. if (mphase)
  2988. nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
  2989. last = (dev->phy.rev < 3) ? 6 : 7;
  2990. if (!mphase || nphy->mphase_cal_phase_id == last) {
  2991. b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
  2992. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
  2993. if (dev->phy.rev < 3) {
  2994. buffer[0] = 0;
  2995. buffer[1] = 0;
  2996. buffer[2] = 0;
  2997. buffer[3] = 0;
  2998. }
  2999. b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
  3000. buffer);
  3001. b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
  3002. buffer);
  3003. b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
  3004. buffer);
  3005. b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
  3006. buffer);
  3007. length = 11;
  3008. if (dev->phy.rev < 3)
  3009. length -= 2;
  3010. b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
  3011. nphy->txiqlocal_bestc);
  3012. nphy->txiqlocal_coeffsvalid = true;
  3013. nphy->txiqlocal_chanspec.center_freq =
  3014. dev->phy.channel_freq;
  3015. nphy->txiqlocal_chanspec.channel_type =
  3016. dev->phy.channel_type;
  3017. } else {
  3018. length = 11;
  3019. if (dev->phy.rev < 3)
  3020. length -= 2;
  3021. b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
  3022. nphy->mphase_txcal_bestcoeffs);
  3023. }
  3024. b43_nphy_stop_playback(dev);
  3025. b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
  3026. }
  3027. b43_nphy_tx_cal_phy_cleanup(dev);
  3028. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
  3029. if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
  3030. b43_nphy_tx_iq_workaround(dev);
  3031. if (dev->phy.rev >= 4)
  3032. nphy->hang_avoid = avoid;
  3033. b43_nphy_stay_in_carrier_search(dev, false);
  3034. return error;
  3035. }
  3036. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
  3037. static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
  3038. {
  3039. struct b43_phy_n *nphy = dev->phy.n;
  3040. u8 i;
  3041. u16 buffer[7];
  3042. bool equal = true;
  3043. if (!nphy->txiqlocal_coeffsvalid ||
  3044. nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
  3045. nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
  3046. return;
  3047. b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
  3048. for (i = 0; i < 4; i++) {
  3049. if (buffer[i] != nphy->txiqlocal_bestc[i]) {
  3050. equal = false;
  3051. break;
  3052. }
  3053. }
  3054. if (!equal) {
  3055. b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
  3056. nphy->txiqlocal_bestc);
  3057. for (i = 0; i < 4; i++)
  3058. buffer[i] = 0;
  3059. b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
  3060. buffer);
  3061. b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
  3062. &nphy->txiqlocal_bestc[5]);
  3063. b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
  3064. &nphy->txiqlocal_bestc[5]);
  3065. }
  3066. }
  3067. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
  3068. static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
  3069. struct nphy_txgains target, u8 type, bool debug)
  3070. {
  3071. struct b43_phy_n *nphy = dev->phy.n;
  3072. int i, j, index;
  3073. u8 rfctl[2];
  3074. u8 afectl_core;
  3075. u16 tmp[6];
  3076. u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
  3077. u32 real, imag;
  3078. enum ieee80211_band band;
  3079. u8 use;
  3080. u16 cur_hpf;
  3081. u16 lna[3] = { 3, 3, 1 };
  3082. u16 hpf1[3] = { 7, 2, 0 };
  3083. u16 hpf2[3] = { 2, 0, 0 };
  3084. u32 power[3] = { };
  3085. u16 gain_save[2];
  3086. u16 cal_gain[2];
  3087. struct nphy_iqcal_params cal_params[2];
  3088. struct nphy_iq_est est;
  3089. int ret = 0;
  3090. bool playtone = true;
  3091. int desired = 13;
  3092. b43_nphy_stay_in_carrier_search(dev, 1);
  3093. if (dev->phy.rev < 2)
  3094. b43_nphy_reapply_tx_cal_coeffs(dev);
  3095. b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
  3096. for (i = 0; i < 2; i++) {
  3097. b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
  3098. cal_gain[i] = cal_params[i].cal_gain;
  3099. }
  3100. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
  3101. for (i = 0; i < 2; i++) {
  3102. if (i == 0) {
  3103. rfctl[0] = B43_NPHY_RFCTL_INTC1;
  3104. rfctl[1] = B43_NPHY_RFCTL_INTC2;
  3105. afectl_core = B43_NPHY_AFECTL_C1;
  3106. } else {
  3107. rfctl[0] = B43_NPHY_RFCTL_INTC2;
  3108. rfctl[1] = B43_NPHY_RFCTL_INTC1;
  3109. afectl_core = B43_NPHY_AFECTL_C2;
  3110. }
  3111. tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
  3112. tmp[2] = b43_phy_read(dev, afectl_core);
  3113. tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
  3114. tmp[4] = b43_phy_read(dev, rfctl[0]);
  3115. tmp[5] = b43_phy_read(dev, rfctl[1]);
  3116. b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
  3117. ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
  3118. ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
  3119. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
  3120. (1 - i));
  3121. b43_phy_set(dev, afectl_core, 0x0006);
  3122. b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
  3123. band = b43_current_band(dev->wl);
  3124. if (nphy->rxcalparams & 0xFF000000) {
  3125. if (band == IEEE80211_BAND_5GHZ)
  3126. b43_phy_write(dev, rfctl[0], 0x140);
  3127. else
  3128. b43_phy_write(dev, rfctl[0], 0x110);
  3129. } else {
  3130. if (band == IEEE80211_BAND_5GHZ)
  3131. b43_phy_write(dev, rfctl[0], 0x180);
  3132. else
  3133. b43_phy_write(dev, rfctl[0], 0x120);
  3134. }
  3135. if (band == IEEE80211_BAND_5GHZ)
  3136. b43_phy_write(dev, rfctl[1], 0x148);
  3137. else
  3138. b43_phy_write(dev, rfctl[1], 0x114);
  3139. if (nphy->rxcalparams & 0x10000) {
  3140. b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
  3141. (i + 1));
  3142. b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
  3143. (2 - i));
  3144. }
  3145. for (j = 0; j < 4; j++) {
  3146. if (j < 3) {
  3147. cur_lna = lna[j];
  3148. cur_hpf1 = hpf1[j];
  3149. cur_hpf2 = hpf2[j];
  3150. } else {
  3151. if (power[1] > 10000) {
  3152. use = 1;
  3153. cur_hpf = cur_hpf1;
  3154. index = 2;
  3155. } else {
  3156. if (power[0] > 10000) {
  3157. use = 1;
  3158. cur_hpf = cur_hpf1;
  3159. index = 1;
  3160. } else {
  3161. index = 0;
  3162. use = 2;
  3163. cur_hpf = cur_hpf2;
  3164. }
  3165. }
  3166. cur_lna = lna[index];
  3167. cur_hpf1 = hpf1[index];
  3168. cur_hpf2 = hpf2[index];
  3169. cur_hpf += desired - hweight32(power[index]);
  3170. cur_hpf = clamp_val(cur_hpf, 0, 10);
  3171. if (use == 1)
  3172. cur_hpf1 = cur_hpf;
  3173. else
  3174. cur_hpf2 = cur_hpf;
  3175. }
  3176. tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
  3177. (cur_lna << 2));
  3178. b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
  3179. false);
  3180. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3181. b43_nphy_stop_playback(dev);
  3182. if (playtone) {
  3183. ret = b43_nphy_tx_tone(dev, 4000,
  3184. (nphy->rxcalparams & 0xFFFF),
  3185. false, false);
  3186. playtone = false;
  3187. } else {
  3188. b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
  3189. false, false);
  3190. }
  3191. if (ret == 0) {
  3192. if (j < 3) {
  3193. b43_nphy_rx_iq_est(dev, &est, 1024, 32,
  3194. false);
  3195. if (i == 0) {
  3196. real = est.i0_pwr;
  3197. imag = est.q0_pwr;
  3198. } else {
  3199. real = est.i1_pwr;
  3200. imag = est.q1_pwr;
  3201. }
  3202. power[i] = ((real + imag) / 1024) + 1;
  3203. } else {
  3204. b43_nphy_calc_rx_iq_comp(dev, 1 << i);
  3205. }
  3206. b43_nphy_stop_playback(dev);
  3207. }
  3208. if (ret != 0)
  3209. break;
  3210. }
  3211. b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
  3212. b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
  3213. b43_phy_write(dev, rfctl[1], tmp[5]);
  3214. b43_phy_write(dev, rfctl[0], tmp[4]);
  3215. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
  3216. b43_phy_write(dev, afectl_core, tmp[2]);
  3217. b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
  3218. if (ret != 0)
  3219. break;
  3220. }
  3221. b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
  3222. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3223. b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
  3224. b43_nphy_stay_in_carrier_search(dev, 0);
  3225. return ret;
  3226. }
  3227. static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
  3228. struct nphy_txgains target, u8 type, bool debug)
  3229. {
  3230. return -1;
  3231. }
  3232. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
  3233. static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
  3234. struct nphy_txgains target, u8 type, bool debug)
  3235. {
  3236. if (dev->phy.rev >= 3)
  3237. return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
  3238. else
  3239. return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
  3240. }
  3241. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
  3242. static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
  3243. {
  3244. struct b43_phy *phy = &dev->phy;
  3245. struct b43_phy_n *nphy = phy->n;
  3246. /* u16 buf[16]; it's rev3+ */
  3247. nphy->phyrxchain = mask;
  3248. if (0 /* FIXME clk */)
  3249. return;
  3250. b43_mac_suspend(dev);
  3251. if (nphy->hang_avoid)
  3252. b43_nphy_stay_in_carrier_search(dev, true);
  3253. b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
  3254. (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
  3255. if ((mask & 0x3) != 0x3) {
  3256. b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
  3257. if (dev->phy.rev >= 3) {
  3258. /* TODO */
  3259. }
  3260. } else {
  3261. b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
  3262. if (dev->phy.rev >= 3) {
  3263. /* TODO */
  3264. }
  3265. }
  3266. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3267. if (nphy->hang_avoid)
  3268. b43_nphy_stay_in_carrier_search(dev, false);
  3269. b43_mac_enable(dev);
  3270. }
  3271. /**************************************************
  3272. * N-PHY init
  3273. **************************************************/
  3274. /*
  3275. * Upload the N-PHY tables.
  3276. * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
  3277. */
  3278. static void b43_nphy_tables_init(struct b43_wldev *dev)
  3279. {
  3280. if (dev->phy.rev < 3)
  3281. b43_nphy_rev0_1_2_tables_init(dev);
  3282. else
  3283. b43_nphy_rev3plus_tables_init(dev);
  3284. }
  3285. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
  3286. static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
  3287. {
  3288. u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
  3289. mimocfg |= B43_NPHY_MIMOCFG_AUTO;
  3290. if (preamble == 1)
  3291. mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
  3292. else
  3293. mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
  3294. b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
  3295. }
  3296. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
  3297. static void b43_nphy_bphy_init(struct b43_wldev *dev)
  3298. {
  3299. unsigned int i;
  3300. u16 val;
  3301. val = 0x1E1F;
  3302. for (i = 0; i < 16; i++) {
  3303. b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
  3304. val -= 0x202;
  3305. }
  3306. val = 0x3E3F;
  3307. for (i = 0; i < 16; i++) {
  3308. b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
  3309. val -= 0x202;
  3310. }
  3311. b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
  3312. }
  3313. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
  3314. static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
  3315. {
  3316. if (dev->phy.rev >= 3) {
  3317. if (!init)
  3318. return;
  3319. if (0 /* FIXME */) {
  3320. b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
  3321. b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
  3322. b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
  3323. b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
  3324. }
  3325. } else {
  3326. b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
  3327. b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
  3328. switch (dev->dev->bus_type) {
  3329. #ifdef CONFIG_B43_BCMA
  3330. case B43_BUS_BCMA:
  3331. bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
  3332. 0xFC00, 0xFC00);
  3333. break;
  3334. #endif
  3335. #ifdef CONFIG_B43_SSB
  3336. case B43_BUS_SSB:
  3337. ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
  3338. 0xFC00, 0xFC00);
  3339. break;
  3340. #endif
  3341. }
  3342. b43_write32(dev, B43_MMIO_MACCTL,
  3343. b43_read32(dev, B43_MMIO_MACCTL) &
  3344. ~B43_MACCTL_GPOUTSMSK);
  3345. b43_write16(dev, B43_MMIO_GPIO_MASK,
  3346. b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
  3347. b43_write16(dev, B43_MMIO_GPIO_CONTROL,
  3348. b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
  3349. if (init) {
  3350. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
  3351. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
  3352. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
  3353. b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
  3354. }
  3355. }
  3356. }
  3357. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
  3358. int b43_phy_initn(struct b43_wldev *dev)
  3359. {
  3360. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  3361. struct b43_phy *phy = &dev->phy;
  3362. struct b43_phy_n *nphy = phy->n;
  3363. u8 tx_pwr_state;
  3364. struct nphy_txgains target;
  3365. u16 tmp;
  3366. enum ieee80211_band tmp2;
  3367. bool do_rssi_cal;
  3368. u16 clip[2];
  3369. bool do_cal = false;
  3370. if ((dev->phy.rev >= 3) &&
  3371. (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
  3372. (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
  3373. switch (dev->dev->bus_type) {
  3374. #ifdef CONFIG_B43_BCMA
  3375. case B43_BUS_BCMA:
  3376. bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
  3377. BCMA_CC_CHIPCTL, 0x40);
  3378. break;
  3379. #endif
  3380. #ifdef CONFIG_B43_SSB
  3381. case B43_BUS_SSB:
  3382. chipco_set32(&dev->dev->sdev->bus->chipco,
  3383. SSB_CHIPCO_CHIPCTL, 0x40);
  3384. break;
  3385. #endif
  3386. }
  3387. }
  3388. nphy->deaf_count = 0;
  3389. b43_nphy_tables_init(dev);
  3390. nphy->crsminpwr_adjusted = false;
  3391. nphy->noisevars_adjusted = false;
  3392. /* Clear all overrides */
  3393. if (dev->phy.rev >= 3) {
  3394. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
  3395. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
  3396. b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
  3397. b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
  3398. } else {
  3399. b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
  3400. }
  3401. b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
  3402. b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
  3403. if (dev->phy.rev < 6) {
  3404. b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
  3405. b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
  3406. }
  3407. b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
  3408. ~(B43_NPHY_RFSEQMODE_CAOVER |
  3409. B43_NPHY_RFSEQMODE_TROVER));
  3410. if (dev->phy.rev >= 3)
  3411. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
  3412. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
  3413. if (dev->phy.rev <= 2) {
  3414. tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
  3415. b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
  3416. ~B43_NPHY_BPHY_CTL3_SCALE,
  3417. tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
  3418. }
  3419. b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
  3420. b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
  3421. if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
  3422. (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
  3423. dev->dev->board_type == 0x8B))
  3424. b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
  3425. else
  3426. b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
  3427. b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
  3428. b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
  3429. b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
  3430. b43_nphy_update_mimo_config(dev, nphy->preamble_override);
  3431. b43_nphy_update_txrx_chain(dev);
  3432. if (phy->rev < 2) {
  3433. b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
  3434. b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
  3435. }
  3436. tmp2 = b43_current_band(dev->wl);
  3437. if (b43_nphy_ipa(dev)) {
  3438. b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
  3439. b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
  3440. nphy->papd_epsilon_offset[0] << 7);
  3441. b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
  3442. b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
  3443. nphy->papd_epsilon_offset[1] << 7);
  3444. b43_nphy_int_pa_set_tx_dig_filters(dev);
  3445. } else if (phy->rev >= 5) {
  3446. b43_nphy_ext_pa_set_tx_dig_filters(dev);
  3447. }
  3448. b43_nphy_workarounds(dev);
  3449. /* Reset CCA, in init code it differs a little from standard way */
  3450. b43_phy_force_clock(dev, 1);
  3451. tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
  3452. b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
  3453. b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
  3454. b43_phy_force_clock(dev, 0);
  3455. b43_mac_phy_clock_set(dev, true);
  3456. b43_nphy_pa_override(dev, false);
  3457. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
  3458. b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
  3459. b43_nphy_pa_override(dev, true);
  3460. b43_nphy_classifier(dev, 0, 0);
  3461. b43_nphy_read_clip_detection(dev, clip);
  3462. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3463. b43_nphy_bphy_init(dev);
  3464. tx_pwr_state = nphy->txpwrctrl;
  3465. b43_nphy_tx_power_ctrl(dev, false);
  3466. b43_nphy_tx_power_fix(dev);
  3467. /* TODO N PHY TX Power Control Idle TSSI */
  3468. /* TODO N PHY TX Power Control Setup */
  3469. b43_nphy_tx_gain_table_upload(dev);
  3470. if (nphy->phyrxchain != 3)
  3471. b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
  3472. if (nphy->mphase_cal_phase_id > 0)
  3473. ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
  3474. do_rssi_cal = false;
  3475. if (phy->rev >= 3) {
  3476. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3477. do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
  3478. else
  3479. do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
  3480. if (do_rssi_cal)
  3481. b43_nphy_rssi_cal(dev);
  3482. else
  3483. b43_nphy_restore_rssi_cal(dev);
  3484. } else {
  3485. b43_nphy_rssi_cal(dev);
  3486. }
  3487. if (!((nphy->measure_hold & 0x6) != 0)) {
  3488. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3489. do_cal = !nphy->iqcal_chanspec_2G.center_freq;
  3490. else
  3491. do_cal = !nphy->iqcal_chanspec_5G.center_freq;
  3492. if (nphy->mute)
  3493. do_cal = false;
  3494. if (do_cal) {
  3495. target = b43_nphy_get_tx_gains(dev);
  3496. if (nphy->antsel_type == 2)
  3497. b43_nphy_superswitch_init(dev, true);
  3498. if (nphy->perical != 2) {
  3499. b43_nphy_rssi_cal(dev);
  3500. if (phy->rev >= 3) {
  3501. nphy->cal_orig_pwr_idx[0] =
  3502. nphy->txpwrindex[0].index_internal;
  3503. nphy->cal_orig_pwr_idx[1] =
  3504. nphy->txpwrindex[1].index_internal;
  3505. /* TODO N PHY Pre Calibrate TX Gain */
  3506. target = b43_nphy_get_tx_gains(dev);
  3507. }
  3508. if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
  3509. if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
  3510. b43_nphy_save_cal(dev);
  3511. } else if (nphy->mphase_cal_phase_id == 0)
  3512. ;/* N PHY Periodic Calibration with arg 3 */
  3513. } else {
  3514. b43_nphy_restore_cal(dev);
  3515. }
  3516. }
  3517. b43_nphy_tx_pwr_ctrl_coef_setup(dev);
  3518. b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
  3519. b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
  3520. b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
  3521. if (phy->rev >= 3 && phy->rev <= 6)
  3522. b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
  3523. b43_nphy_tx_lp_fbw(dev);
  3524. if (phy->rev >= 3)
  3525. b43_nphy_spur_workaround(dev);
  3526. return 0;
  3527. }
  3528. /**************************************************
  3529. * Channel switching ops.
  3530. **************************************************/
  3531. static void b43_chantab_phy_upload(struct b43_wldev *dev,
  3532. const struct b43_phy_n_sfo_cfg *e)
  3533. {
  3534. b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
  3535. b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
  3536. b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
  3537. b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
  3538. b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
  3539. b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
  3540. }
  3541. /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
  3542. static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
  3543. {
  3544. struct bcma_drv_cc __maybe_unused *cc;
  3545. u32 __maybe_unused pmu_ctl;
  3546. switch (dev->dev->bus_type) {
  3547. #ifdef CONFIG_B43_BCMA
  3548. case B43_BUS_BCMA:
  3549. cc = &dev->dev->bdev->bus->drv_cc;
  3550. if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
  3551. if (avoid) {
  3552. bcma_chipco_pll_write(cc, 0x0, 0x11500010);
  3553. bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
  3554. bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
  3555. bcma_chipco_pll_write(cc, 0x3, 0x00000000);
  3556. bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
  3557. bcma_chipco_pll_write(cc, 0x5, 0x88888815);
  3558. } else {
  3559. bcma_chipco_pll_write(cc, 0x0, 0x11100010);
  3560. bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
  3561. bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
  3562. bcma_chipco_pll_write(cc, 0x3, 0x00000000);
  3563. bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
  3564. bcma_chipco_pll_write(cc, 0x5, 0x88888815);
  3565. }
  3566. pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
  3567. } else if (dev->dev->chip_id == 0x4716) {
  3568. if (avoid) {
  3569. bcma_chipco_pll_write(cc, 0x0, 0x11500060);
  3570. bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
  3571. bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
  3572. bcma_chipco_pll_write(cc, 0x3, 0x00000000);
  3573. bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
  3574. bcma_chipco_pll_write(cc, 0x5, 0x88888815);
  3575. } else {
  3576. bcma_chipco_pll_write(cc, 0x0, 0x11100060);
  3577. bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
  3578. bcma_chipco_pll_write(cc, 0x2, 0x03000000);
  3579. bcma_chipco_pll_write(cc, 0x3, 0x00000000);
  3580. bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
  3581. bcma_chipco_pll_write(cc, 0x5, 0x88888815);
  3582. }
  3583. pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
  3584. BCMA_CC_PMU_CTL_NOILPONW;
  3585. } else if (dev->dev->chip_id == 0x4322 ||
  3586. dev->dev->chip_id == 0x4340 ||
  3587. dev->dev->chip_id == 0x4341) {
  3588. bcma_chipco_pll_write(cc, 0x0, 0x11100070);
  3589. bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
  3590. bcma_chipco_pll_write(cc, 0x5, 0x88888854);
  3591. if (avoid)
  3592. bcma_chipco_pll_write(cc, 0x2, 0x05201828);
  3593. else
  3594. bcma_chipco_pll_write(cc, 0x2, 0x05001828);
  3595. pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
  3596. } else {
  3597. return;
  3598. }
  3599. bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
  3600. break;
  3601. #endif
  3602. #ifdef CONFIG_B43_SSB
  3603. case B43_BUS_SSB:
  3604. /* FIXME */
  3605. break;
  3606. #endif
  3607. }
  3608. }
  3609. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
  3610. static void b43_nphy_channel_setup(struct b43_wldev *dev,
  3611. const struct b43_phy_n_sfo_cfg *e,
  3612. struct ieee80211_channel *new_channel)
  3613. {
  3614. struct b43_phy *phy = &dev->phy;
  3615. struct b43_phy_n *nphy = dev->phy.n;
  3616. int ch = new_channel->hw_value;
  3617. u16 old_band_5ghz;
  3618. u32 tmp32;
  3619. old_band_5ghz =
  3620. b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
  3621. if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
  3622. tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
  3623. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
  3624. b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
  3625. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
  3626. b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
  3627. } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
  3628. b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
  3629. tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
  3630. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
  3631. b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
  3632. b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
  3633. }
  3634. b43_chantab_phy_upload(dev, e);
  3635. if (new_channel->hw_value == 14) {
  3636. b43_nphy_classifier(dev, 2, 0);
  3637. b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
  3638. } else {
  3639. b43_nphy_classifier(dev, 2, 2);
  3640. if (new_channel->band == IEEE80211_BAND_2GHZ)
  3641. b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
  3642. }
  3643. if (!nphy->txpwrctrl)
  3644. b43_nphy_tx_power_fix(dev);
  3645. if (dev->phy.rev < 3)
  3646. b43_nphy_adjust_lna_gain_table(dev);
  3647. b43_nphy_tx_lp_fbw(dev);
  3648. if (dev->phy.rev >= 3 &&
  3649. dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
  3650. bool avoid = false;
  3651. if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
  3652. avoid = true;
  3653. } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
  3654. if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
  3655. avoid = true;
  3656. } else { /* 40MHz */
  3657. if (nphy->aband_spurwar_en &&
  3658. (ch == 38 || ch == 102 || ch == 118))
  3659. avoid = dev->dev->chip_id == 0x4716;
  3660. }
  3661. b43_nphy_pmu_spur_avoid(dev, avoid);
  3662. if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
  3663. dev->dev->chip_id == 43225) {
  3664. b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
  3665. avoid ? 0x5341 : 0x8889);
  3666. b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
  3667. }
  3668. if (dev->phy.rev == 3 || dev->phy.rev == 4)
  3669. ; /* TODO: reset PLL */
  3670. if (avoid)
  3671. b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
  3672. else
  3673. b43_phy_mask(dev, B43_NPHY_BBCFG,
  3674. ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
  3675. b43_nphy_reset_cca(dev);
  3676. /* wl sets useless phy_isspuravoid here */
  3677. }
  3678. b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
  3679. if (phy->rev >= 3)
  3680. b43_nphy_spur_workaround(dev);
  3681. }
  3682. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
  3683. static int b43_nphy_set_channel(struct b43_wldev *dev,
  3684. struct ieee80211_channel *channel,
  3685. enum nl80211_channel_type channel_type)
  3686. {
  3687. struct b43_phy *phy = &dev->phy;
  3688. const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
  3689. const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
  3690. u8 tmp;
  3691. if (dev->phy.rev >= 3) {
  3692. tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
  3693. channel->center_freq);
  3694. if (!tabent_r3)
  3695. return -ESRCH;
  3696. } else {
  3697. tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
  3698. channel->hw_value);
  3699. if (!tabent_r2)
  3700. return -ESRCH;
  3701. }
  3702. /* Channel is set later in common code, but we need to set it on our
  3703. own to let this function's subcalls work properly. */
  3704. phy->channel = channel->hw_value;
  3705. phy->channel_freq = channel->center_freq;
  3706. if (b43_channel_type_is_40mhz(phy->channel_type) !=
  3707. b43_channel_type_is_40mhz(channel_type))
  3708. ; /* TODO: BMAC BW Set (channel_type) */
  3709. if (channel_type == NL80211_CHAN_HT40PLUS)
  3710. b43_phy_set(dev, B43_NPHY_RXCTL,
  3711. B43_NPHY_RXCTL_BSELU20);
  3712. else if (channel_type == NL80211_CHAN_HT40MINUS)
  3713. b43_phy_mask(dev, B43_NPHY_RXCTL,
  3714. ~B43_NPHY_RXCTL_BSELU20);
  3715. if (dev->phy.rev >= 3) {
  3716. tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
  3717. b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
  3718. b43_radio_2056_setup(dev, tabent_r3);
  3719. b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
  3720. } else {
  3721. tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
  3722. b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
  3723. b43_radio_2055_setup(dev, tabent_r2);
  3724. b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
  3725. }
  3726. return 0;
  3727. }
  3728. /**************************************************
  3729. * Basic PHY ops.
  3730. **************************************************/
  3731. static int b43_nphy_op_allocate(struct b43_wldev *dev)
  3732. {
  3733. struct b43_phy_n *nphy;
  3734. nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
  3735. if (!nphy)
  3736. return -ENOMEM;
  3737. dev->phy.n = nphy;
  3738. return 0;
  3739. }
  3740. static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
  3741. {
  3742. struct b43_phy *phy = &dev->phy;
  3743. struct b43_phy_n *nphy = phy->n;
  3744. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  3745. memset(nphy, 0, sizeof(*nphy));
  3746. nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
  3747. nphy->spur_avoid = (phy->rev >= 3) ?
  3748. B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
  3749. nphy->gain_boost = true; /* this way we follow wl, assume it is true */
  3750. nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
  3751. nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
  3752. nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
  3753. /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
  3754. * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
  3755. nphy->tx_pwr_idx[0] = 128;
  3756. nphy->tx_pwr_idx[1] = 128;
  3757. /* Hardware TX power control and 5GHz power gain */
  3758. nphy->txpwrctrl = false;
  3759. nphy->pwg_gain_5ghz = false;
  3760. if (dev->phy.rev >= 3 ||
  3761. (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
  3762. (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
  3763. nphy->txpwrctrl = true;
  3764. nphy->pwg_gain_5ghz = true;
  3765. } else if (sprom->revision >= 4) {
  3766. if (dev->phy.rev >= 2 &&
  3767. (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
  3768. nphy->txpwrctrl = true;
  3769. #ifdef CONFIG_B43_SSB
  3770. if (dev->dev->bus_type == B43_BUS_SSB &&
  3771. dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
  3772. struct pci_dev *pdev =
  3773. dev->dev->sdev->bus->host_pci;
  3774. if (pdev->device == 0x4328 ||
  3775. pdev->device == 0x432a)
  3776. nphy->pwg_gain_5ghz = true;
  3777. }
  3778. #endif
  3779. } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
  3780. nphy->pwg_gain_5ghz = true;
  3781. }
  3782. }
  3783. if (dev->phy.rev >= 3) {
  3784. nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
  3785. nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
  3786. }
  3787. }
  3788. static void b43_nphy_op_free(struct b43_wldev *dev)
  3789. {
  3790. struct b43_phy *phy = &dev->phy;
  3791. struct b43_phy_n *nphy = phy->n;
  3792. kfree(nphy);
  3793. phy->n = NULL;
  3794. }
  3795. static int b43_nphy_op_init(struct b43_wldev *dev)
  3796. {
  3797. return b43_phy_initn(dev);
  3798. }
  3799. static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
  3800. {
  3801. #if B43_DEBUG
  3802. if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
  3803. /* OFDM registers are onnly available on A/G-PHYs */
  3804. b43err(dev->wl, "Invalid OFDM PHY access at "
  3805. "0x%04X on N-PHY\n", offset);
  3806. dump_stack();
  3807. }
  3808. if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
  3809. /* Ext-G registers are only available on G-PHYs */
  3810. b43err(dev->wl, "Invalid EXT-G PHY access at "
  3811. "0x%04X on N-PHY\n", offset);
  3812. dump_stack();
  3813. }
  3814. #endif /* B43_DEBUG */
  3815. }
  3816. static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
  3817. {
  3818. check_phyreg(dev, reg);
  3819. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  3820. return b43_read16(dev, B43_MMIO_PHY_DATA);
  3821. }
  3822. static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
  3823. {
  3824. check_phyreg(dev, reg);
  3825. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  3826. b43_write16(dev, B43_MMIO_PHY_DATA, value);
  3827. }
  3828. static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
  3829. u16 set)
  3830. {
  3831. check_phyreg(dev, reg);
  3832. b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
  3833. b43_write16(dev, B43_MMIO_PHY_DATA,
  3834. (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
  3835. }
  3836. static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
  3837. {
  3838. /* Register 1 is a 32-bit register. */
  3839. B43_WARN_ON(reg == 1);
  3840. /* N-PHY needs 0x100 for read access */
  3841. reg |= 0x100;
  3842. b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
  3843. return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
  3844. }
  3845. static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
  3846. {
  3847. /* Register 1 is a 32-bit register. */
  3848. B43_WARN_ON(reg == 1);
  3849. b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
  3850. b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
  3851. }
  3852. /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
  3853. static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
  3854. bool blocked)
  3855. {
  3856. if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
  3857. b43err(dev->wl, "MAC not suspended\n");
  3858. if (blocked) {
  3859. b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
  3860. ~B43_NPHY_RFCTL_CMD_CHIP0PU);
  3861. if (dev->phy.rev >= 3) {
  3862. b43_radio_mask(dev, 0x09, ~0x2);
  3863. b43_radio_write(dev, 0x204D, 0);
  3864. b43_radio_write(dev, 0x2053, 0);
  3865. b43_radio_write(dev, 0x2058, 0);
  3866. b43_radio_write(dev, 0x205E, 0);
  3867. b43_radio_mask(dev, 0x2062, ~0xF0);
  3868. b43_radio_write(dev, 0x2064, 0);
  3869. b43_radio_write(dev, 0x304D, 0);
  3870. b43_radio_write(dev, 0x3053, 0);
  3871. b43_radio_write(dev, 0x3058, 0);
  3872. b43_radio_write(dev, 0x305E, 0);
  3873. b43_radio_mask(dev, 0x3062, ~0xF0);
  3874. b43_radio_write(dev, 0x3064, 0);
  3875. }
  3876. } else {
  3877. if (dev->phy.rev >= 3) {
  3878. b43_radio_init2056(dev);
  3879. b43_switch_channel(dev, dev->phy.channel);
  3880. } else {
  3881. b43_radio_init2055(dev);
  3882. }
  3883. }
  3884. }
  3885. /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
  3886. static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
  3887. {
  3888. u16 override = on ? 0x0 : 0x7FFF;
  3889. u16 core = on ? 0xD : 0x00FD;
  3890. if (dev->phy.rev >= 3) {
  3891. if (on) {
  3892. b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
  3893. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
  3894. b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
  3895. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
  3896. } else {
  3897. b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
  3898. b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
  3899. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
  3900. b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
  3901. }
  3902. } else {
  3903. b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
  3904. }
  3905. }
  3906. static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
  3907. unsigned int new_channel)
  3908. {
  3909. struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
  3910. enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
  3911. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  3912. if ((new_channel < 1) || (new_channel > 14))
  3913. return -EINVAL;
  3914. } else {
  3915. if (new_channel > 200)
  3916. return -EINVAL;
  3917. }
  3918. return b43_nphy_set_channel(dev, channel, channel_type);
  3919. }
  3920. static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
  3921. {
  3922. if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  3923. return 1;
  3924. return 36;
  3925. }
  3926. const struct b43_phy_operations b43_phyops_n = {
  3927. .allocate = b43_nphy_op_allocate,
  3928. .free = b43_nphy_op_free,
  3929. .prepare_structs = b43_nphy_op_prepare_structs,
  3930. .init = b43_nphy_op_init,
  3931. .phy_read = b43_nphy_op_read,
  3932. .phy_write = b43_nphy_op_write,
  3933. .phy_maskset = b43_nphy_op_maskset,
  3934. .radio_read = b43_nphy_op_radio_read,
  3935. .radio_write = b43_nphy_op_radio_write,
  3936. .software_rfkill = b43_nphy_op_software_rfkill,
  3937. .switch_analog = b43_nphy_op_switch_analog,
  3938. .switch_channel = b43_nphy_op_switch_channel,
  3939. .get_default_chan = b43_nphy_op_get_default_chan,
  3940. .recalc_txpower = b43_nphy_op_recalc_txpower,
  3941. .adjust_txpower = b43_nphy_op_adjust_txpower,
  3942. };