qla3xxx.c 102 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968
  1. /*
  2. * QLogic QLA3xxx NIC HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla3xxx for copyright and licensing details.
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/types.h>
  11. #include <linux/module.h>
  12. #include <linux/list.h>
  13. #include <linux/pci.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/sched.h>
  16. #include <linux/slab.h>
  17. #include <linux/dmapool.h>
  18. #include <linux/mempool.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/kthread.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/errno.h>
  23. #include <linux/ioport.h>
  24. #include <linux/ip.h>
  25. #include <linux/in.h>
  26. #include <linux/if_arp.h>
  27. #include <linux/if_ether.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/skbuff.h>
  32. #include <linux/rtnetlink.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/delay.h>
  35. #include <linux/mm.h>
  36. #include <linux/prefetch.h>
  37. #include "qla3xxx.h"
  38. #define DRV_NAME "qla3xxx"
  39. #define DRV_STRING "QLogic ISP3XXX Network Driver"
  40. #define DRV_VERSION "v2.03.00-k5"
  41. static const char ql3xxx_driver_name[] = DRV_NAME;
  42. static const char ql3xxx_driver_version[] = DRV_VERSION;
  43. #define TIMED_OUT_MSG \
  44. "Timed out waiting for management port to get free before issuing command\n"
  45. MODULE_AUTHOR("QLogic Corporation");
  46. MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  47. MODULE_LICENSE("GPL");
  48. MODULE_VERSION(DRV_VERSION);
  49. static const u32 default_msg
  50. = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  51. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  52. static int debug = -1; /* defaults above */
  53. module_param(debug, int, 0);
  54. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  55. static int msi;
  56. module_param(msi, int, 0);
  57. MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  58. static DEFINE_PCI_DEVICE_TABLE(ql3xxx_pci_tbl) = {
  59. {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  60. {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  61. /* required last entry */
  62. {0,}
  63. };
  64. MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  65. /*
  66. * These are the known PHY's which are used
  67. */
  68. enum PHY_DEVICE_TYPE {
  69. PHY_TYPE_UNKNOWN = 0,
  70. PHY_VITESSE_VSC8211,
  71. PHY_AGERE_ET1011C,
  72. MAX_PHY_DEV_TYPES
  73. };
  74. struct PHY_DEVICE_INFO {
  75. const enum PHY_DEVICE_TYPE phyDevice;
  76. const u32 phyIdOUI;
  77. const u16 phyIdModel;
  78. const char *name;
  79. };
  80. static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
  81. {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
  82. {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
  83. {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
  84. };
  85. /*
  86. * Caller must take hw_lock.
  87. */
  88. static int ql_sem_spinlock(struct ql3_adapter *qdev,
  89. u32 sem_mask, u32 sem_bits)
  90. {
  91. struct ql3xxx_port_registers __iomem *port_regs =
  92. qdev->mem_map_registers;
  93. u32 value;
  94. unsigned int seconds = 3;
  95. do {
  96. writel((sem_mask | sem_bits),
  97. &port_regs->CommonRegs.semaphoreReg);
  98. value = readl(&port_regs->CommonRegs.semaphoreReg);
  99. if ((value & (sem_mask >> 16)) == sem_bits)
  100. return 0;
  101. ssleep(1);
  102. } while (--seconds);
  103. return -1;
  104. }
  105. static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
  106. {
  107. struct ql3xxx_port_registers __iomem *port_regs =
  108. qdev->mem_map_registers;
  109. writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
  110. readl(&port_regs->CommonRegs.semaphoreReg);
  111. }
  112. static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
  113. {
  114. struct ql3xxx_port_registers __iomem *port_regs =
  115. qdev->mem_map_registers;
  116. u32 value;
  117. writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
  118. value = readl(&port_regs->CommonRegs.semaphoreReg);
  119. return ((value & (sem_mask >> 16)) == sem_bits);
  120. }
  121. /*
  122. * Caller holds hw_lock.
  123. */
  124. static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
  125. {
  126. int i = 0;
  127. while (i < 10) {
  128. if (i)
  129. ssleep(1);
  130. if (ql_sem_lock(qdev,
  131. QL_DRVR_SEM_MASK,
  132. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
  133. * 2) << 1)) {
  134. netdev_printk(KERN_DEBUG, qdev->ndev,
  135. "driver lock acquired\n");
  136. return 1;
  137. }
  138. }
  139. netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
  140. return 0;
  141. }
  142. static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
  143. {
  144. struct ql3xxx_port_registers __iomem *port_regs =
  145. qdev->mem_map_registers;
  146. writel(((ISP_CONTROL_NP_MASK << 16) | page),
  147. &port_regs->CommonRegs.ispControlStatus);
  148. readl(&port_regs->CommonRegs.ispControlStatus);
  149. qdev->current_page = page;
  150. }
  151. static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
  152. {
  153. u32 value;
  154. unsigned long hw_flags;
  155. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  156. value = readl(reg);
  157. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  158. return value;
  159. }
  160. static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
  161. {
  162. return readl(reg);
  163. }
  164. static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
  165. {
  166. u32 value;
  167. unsigned long hw_flags;
  168. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  169. if (qdev->current_page != 0)
  170. ql_set_register_page(qdev, 0);
  171. value = readl(reg);
  172. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  173. return value;
  174. }
  175. static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
  176. {
  177. if (qdev->current_page != 0)
  178. ql_set_register_page(qdev, 0);
  179. return readl(reg);
  180. }
  181. static void ql_write_common_reg_l(struct ql3_adapter *qdev,
  182. u32 __iomem *reg, u32 value)
  183. {
  184. unsigned long hw_flags;
  185. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  186. writel(value, reg);
  187. readl(reg);
  188. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  189. }
  190. static void ql_write_common_reg(struct ql3_adapter *qdev,
  191. u32 __iomem *reg, u32 value)
  192. {
  193. writel(value, reg);
  194. readl(reg);
  195. }
  196. static void ql_write_nvram_reg(struct ql3_adapter *qdev,
  197. u32 __iomem *reg, u32 value)
  198. {
  199. writel(value, reg);
  200. readl(reg);
  201. udelay(1);
  202. }
  203. static void ql_write_page0_reg(struct ql3_adapter *qdev,
  204. u32 __iomem *reg, u32 value)
  205. {
  206. if (qdev->current_page != 0)
  207. ql_set_register_page(qdev, 0);
  208. writel(value, reg);
  209. readl(reg);
  210. }
  211. /*
  212. * Caller holds hw_lock. Only called during init.
  213. */
  214. static void ql_write_page1_reg(struct ql3_adapter *qdev,
  215. u32 __iomem *reg, u32 value)
  216. {
  217. if (qdev->current_page != 1)
  218. ql_set_register_page(qdev, 1);
  219. writel(value, reg);
  220. readl(reg);
  221. }
  222. /*
  223. * Caller holds hw_lock. Only called during init.
  224. */
  225. static void ql_write_page2_reg(struct ql3_adapter *qdev,
  226. u32 __iomem *reg, u32 value)
  227. {
  228. if (qdev->current_page != 2)
  229. ql_set_register_page(qdev, 2);
  230. writel(value, reg);
  231. readl(reg);
  232. }
  233. static void ql_disable_interrupts(struct ql3_adapter *qdev)
  234. {
  235. struct ql3xxx_port_registers __iomem *port_regs =
  236. qdev->mem_map_registers;
  237. ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
  238. (ISP_IMR_ENABLE_INT << 16));
  239. }
  240. static void ql_enable_interrupts(struct ql3_adapter *qdev)
  241. {
  242. struct ql3xxx_port_registers __iomem *port_regs =
  243. qdev->mem_map_registers;
  244. ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
  245. ((0xff << 16) | ISP_IMR_ENABLE_INT));
  246. }
  247. static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
  248. struct ql_rcv_buf_cb *lrg_buf_cb)
  249. {
  250. dma_addr_t map;
  251. int err;
  252. lrg_buf_cb->next = NULL;
  253. if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
  254. qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
  255. } else {
  256. qdev->lrg_buf_free_tail->next = lrg_buf_cb;
  257. qdev->lrg_buf_free_tail = lrg_buf_cb;
  258. }
  259. if (!lrg_buf_cb->skb) {
  260. lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
  261. qdev->lrg_buffer_len);
  262. if (unlikely(!lrg_buf_cb->skb)) {
  263. netdev_err(qdev->ndev, "failed netdev_alloc_skb()\n");
  264. qdev->lrg_buf_skb_check++;
  265. } else {
  266. /*
  267. * We save some space to copy the ethhdr from first
  268. * buffer
  269. */
  270. skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
  271. map = pci_map_single(qdev->pdev,
  272. lrg_buf_cb->skb->data,
  273. qdev->lrg_buffer_len -
  274. QL_HEADER_SPACE,
  275. PCI_DMA_FROMDEVICE);
  276. err = pci_dma_mapping_error(qdev->pdev, map);
  277. if (err) {
  278. netdev_err(qdev->ndev,
  279. "PCI mapping failed with error: %d\n",
  280. err);
  281. dev_kfree_skb(lrg_buf_cb->skb);
  282. lrg_buf_cb->skb = NULL;
  283. qdev->lrg_buf_skb_check++;
  284. return;
  285. }
  286. lrg_buf_cb->buf_phy_addr_low =
  287. cpu_to_le32(LS_64BITS(map));
  288. lrg_buf_cb->buf_phy_addr_high =
  289. cpu_to_le32(MS_64BITS(map));
  290. dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
  291. dma_unmap_len_set(lrg_buf_cb, maplen,
  292. qdev->lrg_buffer_len -
  293. QL_HEADER_SPACE);
  294. }
  295. }
  296. qdev->lrg_buf_free_count++;
  297. }
  298. static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
  299. *qdev)
  300. {
  301. struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
  302. if (lrg_buf_cb != NULL) {
  303. qdev->lrg_buf_free_head = lrg_buf_cb->next;
  304. if (qdev->lrg_buf_free_head == NULL)
  305. qdev->lrg_buf_free_tail = NULL;
  306. qdev->lrg_buf_free_count--;
  307. }
  308. return lrg_buf_cb;
  309. }
  310. static u32 addrBits = EEPROM_NO_ADDR_BITS;
  311. static u32 dataBits = EEPROM_NO_DATA_BITS;
  312. static void fm93c56a_deselect(struct ql3_adapter *qdev);
  313. static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
  314. unsigned short *value);
  315. /*
  316. * Caller holds hw_lock.
  317. */
  318. static void fm93c56a_select(struct ql3_adapter *qdev)
  319. {
  320. struct ql3xxx_port_registers __iomem *port_regs =
  321. qdev->mem_map_registers;
  322. __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
  323. qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
  324. ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
  325. ql_write_nvram_reg(qdev, spir,
  326. ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
  327. }
  328. /*
  329. * Caller holds hw_lock.
  330. */
  331. static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
  332. {
  333. int i;
  334. u32 mask;
  335. u32 dataBit;
  336. u32 previousBit;
  337. struct ql3xxx_port_registers __iomem *port_regs =
  338. qdev->mem_map_registers;
  339. __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
  340. /* Clock in a zero, then do the start bit */
  341. ql_write_nvram_reg(qdev, spir,
  342. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  343. AUBURN_EEPROM_DO_1));
  344. ql_write_nvram_reg(qdev, spir,
  345. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  346. AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
  347. ql_write_nvram_reg(qdev, spir,
  348. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  349. AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
  350. mask = 1 << (FM93C56A_CMD_BITS - 1);
  351. /* Force the previous data bit to be different */
  352. previousBit = 0xffff;
  353. for (i = 0; i < FM93C56A_CMD_BITS; i++) {
  354. dataBit = (cmd & mask)
  355. ? AUBURN_EEPROM_DO_1
  356. : AUBURN_EEPROM_DO_0;
  357. if (previousBit != dataBit) {
  358. /* If the bit changed, change the DO state to match */
  359. ql_write_nvram_reg(qdev, spir,
  360. (ISP_NVRAM_MASK |
  361. qdev->eeprom_cmd_data | dataBit));
  362. previousBit = dataBit;
  363. }
  364. ql_write_nvram_reg(qdev, spir,
  365. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  366. dataBit | AUBURN_EEPROM_CLK_RISE));
  367. ql_write_nvram_reg(qdev, spir,
  368. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  369. dataBit | AUBURN_EEPROM_CLK_FALL));
  370. cmd = cmd << 1;
  371. }
  372. mask = 1 << (addrBits - 1);
  373. /* Force the previous data bit to be different */
  374. previousBit = 0xffff;
  375. for (i = 0; i < addrBits; i++) {
  376. dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
  377. : AUBURN_EEPROM_DO_0;
  378. if (previousBit != dataBit) {
  379. /*
  380. * If the bit changed, then change the DO state to
  381. * match
  382. */
  383. ql_write_nvram_reg(qdev, spir,
  384. (ISP_NVRAM_MASK |
  385. qdev->eeprom_cmd_data | dataBit));
  386. previousBit = dataBit;
  387. }
  388. ql_write_nvram_reg(qdev, spir,
  389. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  390. dataBit | AUBURN_EEPROM_CLK_RISE));
  391. ql_write_nvram_reg(qdev, spir,
  392. (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  393. dataBit | AUBURN_EEPROM_CLK_FALL));
  394. eepromAddr = eepromAddr << 1;
  395. }
  396. }
  397. /*
  398. * Caller holds hw_lock.
  399. */
  400. static void fm93c56a_deselect(struct ql3_adapter *qdev)
  401. {
  402. struct ql3xxx_port_registers __iomem *port_regs =
  403. qdev->mem_map_registers;
  404. __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
  405. qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
  406. ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
  407. }
  408. /*
  409. * Caller holds hw_lock.
  410. */
  411. static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
  412. {
  413. int i;
  414. u32 data = 0;
  415. u32 dataBit;
  416. struct ql3xxx_port_registers __iomem *port_regs =
  417. qdev->mem_map_registers;
  418. __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
  419. /* Read the data bits */
  420. /* The first bit is a dummy. Clock right over it. */
  421. for (i = 0; i < dataBits; i++) {
  422. ql_write_nvram_reg(qdev, spir,
  423. ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  424. AUBURN_EEPROM_CLK_RISE);
  425. ql_write_nvram_reg(qdev, spir,
  426. ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  427. AUBURN_EEPROM_CLK_FALL);
  428. dataBit = (ql_read_common_reg(qdev, spir) &
  429. AUBURN_EEPROM_DI_1) ? 1 : 0;
  430. data = (data << 1) | dataBit;
  431. }
  432. *value = (u16)data;
  433. }
  434. /*
  435. * Caller holds hw_lock.
  436. */
  437. static void eeprom_readword(struct ql3_adapter *qdev,
  438. u32 eepromAddr, unsigned short *value)
  439. {
  440. fm93c56a_select(qdev);
  441. fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
  442. fm93c56a_datain(qdev, value);
  443. fm93c56a_deselect(qdev);
  444. }
  445. static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
  446. {
  447. __le16 *p = (__le16 *)ndev->dev_addr;
  448. p[0] = cpu_to_le16(addr[0]);
  449. p[1] = cpu_to_le16(addr[1]);
  450. p[2] = cpu_to_le16(addr[2]);
  451. }
  452. static int ql_get_nvram_params(struct ql3_adapter *qdev)
  453. {
  454. u16 *pEEPROMData;
  455. u16 checksum = 0;
  456. u32 index;
  457. unsigned long hw_flags;
  458. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  459. pEEPROMData = (u16 *)&qdev->nvram_data;
  460. qdev->eeprom_cmd_data = 0;
  461. if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
  462. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  463. 2) << 10)) {
  464. pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
  465. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  466. return -1;
  467. }
  468. for (index = 0; index < EEPROM_SIZE; index++) {
  469. eeprom_readword(qdev, index, pEEPROMData);
  470. checksum += *pEEPROMData;
  471. pEEPROMData++;
  472. }
  473. ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
  474. if (checksum != 0) {
  475. netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
  476. checksum);
  477. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  478. return -1;
  479. }
  480. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  481. return checksum;
  482. }
  483. static const u32 PHYAddr[2] = {
  484. PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
  485. };
  486. static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
  487. {
  488. struct ql3xxx_port_registers __iomem *port_regs =
  489. qdev->mem_map_registers;
  490. u32 temp;
  491. int count = 1000;
  492. while (count) {
  493. temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
  494. if (!(temp & MAC_MII_STATUS_BSY))
  495. return 0;
  496. udelay(10);
  497. count--;
  498. }
  499. return -1;
  500. }
  501. static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
  502. {
  503. struct ql3xxx_port_registers __iomem *port_regs =
  504. qdev->mem_map_registers;
  505. u32 scanControl;
  506. if (qdev->numPorts > 1) {
  507. /* Auto scan will cycle through multiple ports */
  508. scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
  509. } else {
  510. scanControl = MAC_MII_CONTROL_SC;
  511. }
  512. /*
  513. * Scan register 1 of PHY/PETBI,
  514. * Set up to scan both devices
  515. * The autoscan starts from the first register, completes
  516. * the last one before rolling over to the first
  517. */
  518. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  519. PHYAddr[0] | MII_SCAN_REGISTER);
  520. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  521. (scanControl) |
  522. ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
  523. }
  524. static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
  525. {
  526. u8 ret;
  527. struct ql3xxx_port_registers __iomem *port_regs =
  528. qdev->mem_map_registers;
  529. /* See if scan mode is enabled before we turn it off */
  530. if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
  531. (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
  532. /* Scan is enabled */
  533. ret = 1;
  534. } else {
  535. /* Scan is disabled */
  536. ret = 0;
  537. }
  538. /*
  539. * When disabling scan mode you must first change the MII register
  540. * address
  541. */
  542. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  543. PHYAddr[0] | MII_SCAN_REGISTER);
  544. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  545. ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
  546. MAC_MII_CONTROL_RC) << 16));
  547. return ret;
  548. }
  549. static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
  550. u16 regAddr, u16 value, u32 phyAddr)
  551. {
  552. struct ql3xxx_port_registers __iomem *port_regs =
  553. qdev->mem_map_registers;
  554. u8 scanWasEnabled;
  555. scanWasEnabled = ql_mii_disable_scan_mode(qdev);
  556. if (ql_wait_for_mii_ready(qdev)) {
  557. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  558. return -1;
  559. }
  560. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  561. phyAddr | regAddr);
  562. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
  563. /* Wait for write to complete 9/10/04 SJP */
  564. if (ql_wait_for_mii_ready(qdev)) {
  565. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  566. return -1;
  567. }
  568. if (scanWasEnabled)
  569. ql_mii_enable_scan_mode(qdev);
  570. return 0;
  571. }
  572. static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
  573. u16 *value, u32 phyAddr)
  574. {
  575. struct ql3xxx_port_registers __iomem *port_regs =
  576. qdev->mem_map_registers;
  577. u8 scanWasEnabled;
  578. u32 temp;
  579. scanWasEnabled = ql_mii_disable_scan_mode(qdev);
  580. if (ql_wait_for_mii_ready(qdev)) {
  581. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  582. return -1;
  583. }
  584. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  585. phyAddr | regAddr);
  586. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  587. (MAC_MII_CONTROL_RC << 16));
  588. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  589. (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
  590. /* Wait for the read to complete */
  591. if (ql_wait_for_mii_ready(qdev)) {
  592. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  593. return -1;
  594. }
  595. temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
  596. *value = (u16) temp;
  597. if (scanWasEnabled)
  598. ql_mii_enable_scan_mode(qdev);
  599. return 0;
  600. }
  601. static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
  602. {
  603. struct ql3xxx_port_registers __iomem *port_regs =
  604. qdev->mem_map_registers;
  605. ql_mii_disable_scan_mode(qdev);
  606. if (ql_wait_for_mii_ready(qdev)) {
  607. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  608. return -1;
  609. }
  610. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  611. qdev->PHYAddr | regAddr);
  612. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
  613. /* Wait for write to complete. */
  614. if (ql_wait_for_mii_ready(qdev)) {
  615. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  616. return -1;
  617. }
  618. ql_mii_enable_scan_mode(qdev);
  619. return 0;
  620. }
  621. static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
  622. {
  623. u32 temp;
  624. struct ql3xxx_port_registers __iomem *port_regs =
  625. qdev->mem_map_registers;
  626. ql_mii_disable_scan_mode(qdev);
  627. if (ql_wait_for_mii_ready(qdev)) {
  628. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  629. return -1;
  630. }
  631. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  632. qdev->PHYAddr | regAddr);
  633. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  634. (MAC_MII_CONTROL_RC << 16));
  635. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  636. (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
  637. /* Wait for the read to complete */
  638. if (ql_wait_for_mii_ready(qdev)) {
  639. netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
  640. return -1;
  641. }
  642. temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
  643. *value = (u16) temp;
  644. ql_mii_enable_scan_mode(qdev);
  645. return 0;
  646. }
  647. static void ql_petbi_reset(struct ql3_adapter *qdev)
  648. {
  649. ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
  650. }
  651. static void ql_petbi_start_neg(struct ql3_adapter *qdev)
  652. {
  653. u16 reg;
  654. /* Enable Auto-negotiation sense */
  655. ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
  656. reg |= PETBI_TBI_AUTO_SENSE;
  657. ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
  658. ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
  659. PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
  660. ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
  661. PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
  662. PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
  663. }
  664. static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
  665. {
  666. ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
  667. PHYAddr[qdev->mac_index]);
  668. }
  669. static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
  670. {
  671. u16 reg;
  672. /* Enable Auto-negotiation sense */
  673. ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
  674. PHYAddr[qdev->mac_index]);
  675. reg |= PETBI_TBI_AUTO_SENSE;
  676. ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
  677. PHYAddr[qdev->mac_index]);
  678. ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
  679. PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
  680. PHYAddr[qdev->mac_index]);
  681. ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
  682. PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
  683. PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
  684. PHYAddr[qdev->mac_index]);
  685. }
  686. static void ql_petbi_init(struct ql3_adapter *qdev)
  687. {
  688. ql_petbi_reset(qdev);
  689. ql_petbi_start_neg(qdev);
  690. }
  691. static void ql_petbi_init_ex(struct ql3_adapter *qdev)
  692. {
  693. ql_petbi_reset_ex(qdev);
  694. ql_petbi_start_neg_ex(qdev);
  695. }
  696. static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
  697. {
  698. u16 reg;
  699. if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
  700. return 0;
  701. return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
  702. }
  703. static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
  704. {
  705. netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
  706. /* power down device bit 11 = 1 */
  707. ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
  708. /* enable diagnostic mode bit 2 = 1 */
  709. ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
  710. /* 1000MB amplitude adjust (see Agere errata) */
  711. ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
  712. /* 1000MB amplitude adjust (see Agere errata) */
  713. ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
  714. /* 100MB amplitude adjust (see Agere errata) */
  715. ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
  716. /* 100MB amplitude adjust (see Agere errata) */
  717. ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
  718. /* 10MB amplitude adjust (see Agere errata) */
  719. ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
  720. /* 10MB amplitude adjust (see Agere errata) */
  721. ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
  722. /* point to hidden reg 0x2806 */
  723. ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
  724. /* Write new PHYAD w/bit 5 set */
  725. ql_mii_write_reg_ex(qdev, 0x11,
  726. 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
  727. /*
  728. * Disable diagnostic mode bit 2 = 0
  729. * Power up device bit 11 = 0
  730. * Link up (on) and activity (blink)
  731. */
  732. ql_mii_write_reg(qdev, 0x12, 0x840a);
  733. ql_mii_write_reg(qdev, 0x00, 0x1140);
  734. ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
  735. }
  736. static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
  737. u16 phyIdReg0, u16 phyIdReg1)
  738. {
  739. enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
  740. u32 oui;
  741. u16 model;
  742. int i;
  743. if (phyIdReg0 == 0xffff)
  744. return result;
  745. if (phyIdReg1 == 0xffff)
  746. return result;
  747. /* oui is split between two registers */
  748. oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
  749. model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
  750. /* Scan table for this PHY */
  751. for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
  752. if ((oui == PHY_DEVICES[i].phyIdOUI) &&
  753. (model == PHY_DEVICES[i].phyIdModel)) {
  754. netdev_info(qdev->ndev, "Phy: %s\n",
  755. PHY_DEVICES[i].name);
  756. result = PHY_DEVICES[i].phyDevice;
  757. break;
  758. }
  759. }
  760. return result;
  761. }
  762. static int ql_phy_get_speed(struct ql3_adapter *qdev)
  763. {
  764. u16 reg;
  765. switch (qdev->phyType) {
  766. case PHY_AGERE_ET1011C: {
  767. if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
  768. return 0;
  769. reg = (reg >> 8) & 3;
  770. break;
  771. }
  772. default:
  773. if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
  774. return 0;
  775. reg = (((reg & 0x18) >> 3) & 3);
  776. }
  777. switch (reg) {
  778. case 2:
  779. return SPEED_1000;
  780. case 1:
  781. return SPEED_100;
  782. case 0:
  783. return SPEED_10;
  784. default:
  785. return -1;
  786. }
  787. }
  788. static int ql_is_full_dup(struct ql3_adapter *qdev)
  789. {
  790. u16 reg;
  791. switch (qdev->phyType) {
  792. case PHY_AGERE_ET1011C: {
  793. if (ql_mii_read_reg(qdev, 0x1A, &reg))
  794. return 0;
  795. return ((reg & 0x0080) && (reg & 0x1000)) != 0;
  796. }
  797. case PHY_VITESSE_VSC8211:
  798. default: {
  799. if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
  800. return 0;
  801. return (reg & PHY_AUX_DUPLEX_STAT) != 0;
  802. }
  803. }
  804. }
  805. static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
  806. {
  807. u16 reg;
  808. if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
  809. return 0;
  810. return (reg & PHY_NEG_PAUSE) != 0;
  811. }
  812. static int PHY_Setup(struct ql3_adapter *qdev)
  813. {
  814. u16 reg1;
  815. u16 reg2;
  816. bool agereAddrChangeNeeded = false;
  817. u32 miiAddr = 0;
  818. int err;
  819. /* Determine the PHY we are using by reading the ID's */
  820. err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
  821. if (err != 0) {
  822. netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
  823. return err;
  824. }
  825. err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
  826. if (err != 0) {
  827. netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
  828. return err;
  829. }
  830. /* Check if we have a Agere PHY */
  831. if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
  832. /* Determine which MII address we should be using
  833. determined by the index of the card */
  834. if (qdev->mac_index == 0)
  835. miiAddr = MII_AGERE_ADDR_1;
  836. else
  837. miiAddr = MII_AGERE_ADDR_2;
  838. err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
  839. if (err != 0) {
  840. netdev_err(qdev->ndev,
  841. "Could not read from reg PHY_ID_0_REG after Agere detected\n");
  842. return err;
  843. }
  844. err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
  845. if (err != 0) {
  846. netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
  847. return err;
  848. }
  849. /* We need to remember to initialize the Agere PHY */
  850. agereAddrChangeNeeded = true;
  851. }
  852. /* Determine the particular PHY we have on board to apply
  853. PHY specific initializations */
  854. qdev->phyType = getPhyType(qdev, reg1, reg2);
  855. if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
  856. /* need this here so address gets changed */
  857. phyAgereSpecificInit(qdev, miiAddr);
  858. } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
  859. netdev_err(qdev->ndev, "PHY is unknown\n");
  860. return -EIO;
  861. }
  862. return 0;
  863. }
  864. /*
  865. * Caller holds hw_lock.
  866. */
  867. static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
  868. {
  869. struct ql3xxx_port_registers __iomem *port_regs =
  870. qdev->mem_map_registers;
  871. u32 value;
  872. if (enable)
  873. value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
  874. else
  875. value = (MAC_CONFIG_REG_PE << 16);
  876. if (qdev->mac_index)
  877. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  878. else
  879. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  880. }
  881. /*
  882. * Caller holds hw_lock.
  883. */
  884. static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
  885. {
  886. struct ql3xxx_port_registers __iomem *port_regs =
  887. qdev->mem_map_registers;
  888. u32 value;
  889. if (enable)
  890. value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
  891. else
  892. value = (MAC_CONFIG_REG_SR << 16);
  893. if (qdev->mac_index)
  894. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  895. else
  896. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  897. }
  898. /*
  899. * Caller holds hw_lock.
  900. */
  901. static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
  902. {
  903. struct ql3xxx_port_registers __iomem *port_regs =
  904. qdev->mem_map_registers;
  905. u32 value;
  906. if (enable)
  907. value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
  908. else
  909. value = (MAC_CONFIG_REG_GM << 16);
  910. if (qdev->mac_index)
  911. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  912. else
  913. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  914. }
  915. /*
  916. * Caller holds hw_lock.
  917. */
  918. static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
  919. {
  920. struct ql3xxx_port_registers __iomem *port_regs =
  921. qdev->mem_map_registers;
  922. u32 value;
  923. if (enable)
  924. value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
  925. else
  926. value = (MAC_CONFIG_REG_FD << 16);
  927. if (qdev->mac_index)
  928. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  929. else
  930. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  931. }
  932. /*
  933. * Caller holds hw_lock.
  934. */
  935. static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
  936. {
  937. struct ql3xxx_port_registers __iomem *port_regs =
  938. qdev->mem_map_registers;
  939. u32 value;
  940. if (enable)
  941. value =
  942. ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
  943. ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
  944. else
  945. value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
  946. if (qdev->mac_index)
  947. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  948. else
  949. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  950. }
  951. /*
  952. * Caller holds hw_lock.
  953. */
  954. static int ql_is_fiber(struct ql3_adapter *qdev)
  955. {
  956. struct ql3xxx_port_registers __iomem *port_regs =
  957. qdev->mem_map_registers;
  958. u32 bitToCheck = 0;
  959. u32 temp;
  960. switch (qdev->mac_index) {
  961. case 0:
  962. bitToCheck = PORT_STATUS_SM0;
  963. break;
  964. case 1:
  965. bitToCheck = PORT_STATUS_SM1;
  966. break;
  967. }
  968. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  969. return (temp & bitToCheck) != 0;
  970. }
  971. static int ql_is_auto_cfg(struct ql3_adapter *qdev)
  972. {
  973. u16 reg;
  974. ql_mii_read_reg(qdev, 0x00, &reg);
  975. return (reg & 0x1000) != 0;
  976. }
  977. /*
  978. * Caller holds hw_lock.
  979. */
  980. static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
  981. {
  982. struct ql3xxx_port_registers __iomem *port_regs =
  983. qdev->mem_map_registers;
  984. u32 bitToCheck = 0;
  985. u32 temp;
  986. switch (qdev->mac_index) {
  987. case 0:
  988. bitToCheck = PORT_STATUS_AC0;
  989. break;
  990. case 1:
  991. bitToCheck = PORT_STATUS_AC1;
  992. break;
  993. }
  994. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  995. if (temp & bitToCheck) {
  996. netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
  997. return 1;
  998. }
  999. netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
  1000. return 0;
  1001. }
  1002. /*
  1003. * ql_is_neg_pause() returns 1 if pause was negotiated to be on
  1004. */
  1005. static int ql_is_neg_pause(struct ql3_adapter *qdev)
  1006. {
  1007. if (ql_is_fiber(qdev))
  1008. return ql_is_petbi_neg_pause(qdev);
  1009. else
  1010. return ql_is_phy_neg_pause(qdev);
  1011. }
  1012. static int ql_auto_neg_error(struct ql3_adapter *qdev)
  1013. {
  1014. struct ql3xxx_port_registers __iomem *port_regs =
  1015. qdev->mem_map_registers;
  1016. u32 bitToCheck = 0;
  1017. u32 temp;
  1018. switch (qdev->mac_index) {
  1019. case 0:
  1020. bitToCheck = PORT_STATUS_AE0;
  1021. break;
  1022. case 1:
  1023. bitToCheck = PORT_STATUS_AE1;
  1024. break;
  1025. }
  1026. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  1027. return (temp & bitToCheck) != 0;
  1028. }
  1029. static u32 ql_get_link_speed(struct ql3_adapter *qdev)
  1030. {
  1031. if (ql_is_fiber(qdev))
  1032. return SPEED_1000;
  1033. else
  1034. return ql_phy_get_speed(qdev);
  1035. }
  1036. static int ql_is_link_full_dup(struct ql3_adapter *qdev)
  1037. {
  1038. if (ql_is_fiber(qdev))
  1039. return 1;
  1040. else
  1041. return ql_is_full_dup(qdev);
  1042. }
  1043. /*
  1044. * Caller holds hw_lock.
  1045. */
  1046. static int ql_link_down_detect(struct ql3_adapter *qdev)
  1047. {
  1048. struct ql3xxx_port_registers __iomem *port_regs =
  1049. qdev->mem_map_registers;
  1050. u32 bitToCheck = 0;
  1051. u32 temp;
  1052. switch (qdev->mac_index) {
  1053. case 0:
  1054. bitToCheck = ISP_CONTROL_LINK_DN_0;
  1055. break;
  1056. case 1:
  1057. bitToCheck = ISP_CONTROL_LINK_DN_1;
  1058. break;
  1059. }
  1060. temp =
  1061. ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
  1062. return (temp & bitToCheck) != 0;
  1063. }
  1064. /*
  1065. * Caller holds hw_lock.
  1066. */
  1067. static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
  1068. {
  1069. struct ql3xxx_port_registers __iomem *port_regs =
  1070. qdev->mem_map_registers;
  1071. switch (qdev->mac_index) {
  1072. case 0:
  1073. ql_write_common_reg(qdev,
  1074. &port_regs->CommonRegs.ispControlStatus,
  1075. (ISP_CONTROL_LINK_DN_0) |
  1076. (ISP_CONTROL_LINK_DN_0 << 16));
  1077. break;
  1078. case 1:
  1079. ql_write_common_reg(qdev,
  1080. &port_regs->CommonRegs.ispControlStatus,
  1081. (ISP_CONTROL_LINK_DN_1) |
  1082. (ISP_CONTROL_LINK_DN_1 << 16));
  1083. break;
  1084. default:
  1085. return 1;
  1086. }
  1087. return 0;
  1088. }
  1089. /*
  1090. * Caller holds hw_lock.
  1091. */
  1092. static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
  1093. {
  1094. struct ql3xxx_port_registers __iomem *port_regs =
  1095. qdev->mem_map_registers;
  1096. u32 bitToCheck = 0;
  1097. u32 temp;
  1098. switch (qdev->mac_index) {
  1099. case 0:
  1100. bitToCheck = PORT_STATUS_F1_ENABLED;
  1101. break;
  1102. case 1:
  1103. bitToCheck = PORT_STATUS_F3_ENABLED;
  1104. break;
  1105. default:
  1106. break;
  1107. }
  1108. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  1109. if (temp & bitToCheck) {
  1110. netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
  1111. "not link master\n");
  1112. return 0;
  1113. }
  1114. netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
  1115. return 1;
  1116. }
  1117. static void ql_phy_reset_ex(struct ql3_adapter *qdev)
  1118. {
  1119. ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
  1120. PHYAddr[qdev->mac_index]);
  1121. }
  1122. static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
  1123. {
  1124. u16 reg;
  1125. u16 portConfiguration;
  1126. if (qdev->phyType == PHY_AGERE_ET1011C)
  1127. ql_mii_write_reg(qdev, 0x13, 0x0000);
  1128. /* turn off external loopback */
  1129. if (qdev->mac_index == 0)
  1130. portConfiguration =
  1131. qdev->nvram_data.macCfg_port0.portConfiguration;
  1132. else
  1133. portConfiguration =
  1134. qdev->nvram_data.macCfg_port1.portConfiguration;
  1135. /* Some HBA's in the field are set to 0 and they need to
  1136. be reinterpreted with a default value */
  1137. if (portConfiguration == 0)
  1138. portConfiguration = PORT_CONFIG_DEFAULT;
  1139. /* Set the 1000 advertisements */
  1140. ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
  1141. PHYAddr[qdev->mac_index]);
  1142. reg &= ~PHY_GIG_ALL_PARAMS;
  1143. if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
  1144. if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
  1145. reg |= PHY_GIG_ADV_1000F;
  1146. else
  1147. reg |= PHY_GIG_ADV_1000H;
  1148. }
  1149. ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
  1150. PHYAddr[qdev->mac_index]);
  1151. /* Set the 10/100 & pause negotiation advertisements */
  1152. ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
  1153. PHYAddr[qdev->mac_index]);
  1154. reg &= ~PHY_NEG_ALL_PARAMS;
  1155. if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
  1156. reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
  1157. if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
  1158. if (portConfiguration & PORT_CONFIG_100MB_SPEED)
  1159. reg |= PHY_NEG_ADV_100F;
  1160. if (portConfiguration & PORT_CONFIG_10MB_SPEED)
  1161. reg |= PHY_NEG_ADV_10F;
  1162. }
  1163. if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
  1164. if (portConfiguration & PORT_CONFIG_100MB_SPEED)
  1165. reg |= PHY_NEG_ADV_100H;
  1166. if (portConfiguration & PORT_CONFIG_10MB_SPEED)
  1167. reg |= PHY_NEG_ADV_10H;
  1168. }
  1169. if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
  1170. reg |= 1;
  1171. ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
  1172. PHYAddr[qdev->mac_index]);
  1173. ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
  1174. ql_mii_write_reg_ex(qdev, CONTROL_REG,
  1175. reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
  1176. PHYAddr[qdev->mac_index]);
  1177. }
  1178. static void ql_phy_init_ex(struct ql3_adapter *qdev)
  1179. {
  1180. ql_phy_reset_ex(qdev);
  1181. PHY_Setup(qdev);
  1182. ql_phy_start_neg_ex(qdev);
  1183. }
  1184. /*
  1185. * Caller holds hw_lock.
  1186. */
  1187. static u32 ql_get_link_state(struct ql3_adapter *qdev)
  1188. {
  1189. struct ql3xxx_port_registers __iomem *port_regs =
  1190. qdev->mem_map_registers;
  1191. u32 bitToCheck = 0;
  1192. u32 temp, linkState;
  1193. switch (qdev->mac_index) {
  1194. case 0:
  1195. bitToCheck = PORT_STATUS_UP0;
  1196. break;
  1197. case 1:
  1198. bitToCheck = PORT_STATUS_UP1;
  1199. break;
  1200. }
  1201. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  1202. if (temp & bitToCheck)
  1203. linkState = LS_UP;
  1204. else
  1205. linkState = LS_DOWN;
  1206. return linkState;
  1207. }
  1208. static int ql_port_start(struct ql3_adapter *qdev)
  1209. {
  1210. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1211. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1212. 2) << 7)) {
  1213. netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
  1214. return -1;
  1215. }
  1216. if (ql_is_fiber(qdev)) {
  1217. ql_petbi_init(qdev);
  1218. } else {
  1219. /* Copper port */
  1220. ql_phy_init_ex(qdev);
  1221. }
  1222. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1223. return 0;
  1224. }
  1225. static int ql_finish_auto_neg(struct ql3_adapter *qdev)
  1226. {
  1227. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1228. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1229. 2) << 7))
  1230. return -1;
  1231. if (!ql_auto_neg_error(qdev)) {
  1232. if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
  1233. /* configure the MAC */
  1234. netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
  1235. "Configuring link\n");
  1236. ql_mac_cfg_soft_reset(qdev, 1);
  1237. ql_mac_cfg_gig(qdev,
  1238. (ql_get_link_speed
  1239. (qdev) ==
  1240. SPEED_1000));
  1241. ql_mac_cfg_full_dup(qdev,
  1242. ql_is_link_full_dup
  1243. (qdev));
  1244. ql_mac_cfg_pause(qdev,
  1245. ql_is_neg_pause
  1246. (qdev));
  1247. ql_mac_cfg_soft_reset(qdev, 0);
  1248. /* enable the MAC */
  1249. netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
  1250. "Enabling mac\n");
  1251. ql_mac_enable(qdev, 1);
  1252. }
  1253. qdev->port_link_state = LS_UP;
  1254. netif_start_queue(qdev->ndev);
  1255. netif_carrier_on(qdev->ndev);
  1256. netif_info(qdev, link, qdev->ndev,
  1257. "Link is up at %d Mbps, %s duplex\n",
  1258. ql_get_link_speed(qdev),
  1259. ql_is_link_full_dup(qdev) ? "full" : "half");
  1260. } else { /* Remote error detected */
  1261. if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
  1262. netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
  1263. "Remote error detected. Calling ql_port_start()\n");
  1264. /*
  1265. * ql_port_start() is shared code and needs
  1266. * to lock the PHY on it's own.
  1267. */
  1268. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1269. if (ql_port_start(qdev)) /* Restart port */
  1270. return -1;
  1271. return 0;
  1272. }
  1273. }
  1274. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1275. return 0;
  1276. }
  1277. static void ql_link_state_machine_work(struct work_struct *work)
  1278. {
  1279. struct ql3_adapter *qdev =
  1280. container_of(work, struct ql3_adapter, link_state_work.work);
  1281. u32 curr_link_state;
  1282. unsigned long hw_flags;
  1283. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1284. curr_link_state = ql_get_link_state(qdev);
  1285. if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
  1286. netif_info(qdev, link, qdev->ndev,
  1287. "Reset in progress, skip processing link state\n");
  1288. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1289. /* Restart timer on 2 second interval. */
  1290. mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
  1291. return;
  1292. }
  1293. switch (qdev->port_link_state) {
  1294. default:
  1295. if (test_bit(QL_LINK_MASTER, &qdev->flags))
  1296. ql_port_start(qdev);
  1297. qdev->port_link_state = LS_DOWN;
  1298. /* Fall Through */
  1299. case LS_DOWN:
  1300. if (curr_link_state == LS_UP) {
  1301. netif_info(qdev, link, qdev->ndev, "Link is up\n");
  1302. if (ql_is_auto_neg_complete(qdev))
  1303. ql_finish_auto_neg(qdev);
  1304. if (qdev->port_link_state == LS_UP)
  1305. ql_link_down_detect_clear(qdev);
  1306. qdev->port_link_state = LS_UP;
  1307. }
  1308. break;
  1309. case LS_UP:
  1310. /*
  1311. * See if the link is currently down or went down and came
  1312. * back up
  1313. */
  1314. if (curr_link_state == LS_DOWN) {
  1315. netif_info(qdev, link, qdev->ndev, "Link is down\n");
  1316. qdev->port_link_state = LS_DOWN;
  1317. }
  1318. if (ql_link_down_detect(qdev))
  1319. qdev->port_link_state = LS_DOWN;
  1320. break;
  1321. }
  1322. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1323. /* Restart timer on 2 second interval. */
  1324. mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
  1325. }
  1326. /*
  1327. * Caller must take hw_lock and QL_PHY_GIO_SEM.
  1328. */
  1329. static void ql_get_phy_owner(struct ql3_adapter *qdev)
  1330. {
  1331. if (ql_this_adapter_controls_port(qdev))
  1332. set_bit(QL_LINK_MASTER, &qdev->flags);
  1333. else
  1334. clear_bit(QL_LINK_MASTER, &qdev->flags);
  1335. }
  1336. /*
  1337. * Caller must take hw_lock and QL_PHY_GIO_SEM.
  1338. */
  1339. static void ql_init_scan_mode(struct ql3_adapter *qdev)
  1340. {
  1341. ql_mii_enable_scan_mode(qdev);
  1342. if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
  1343. if (ql_this_adapter_controls_port(qdev))
  1344. ql_petbi_init_ex(qdev);
  1345. } else {
  1346. if (ql_this_adapter_controls_port(qdev))
  1347. ql_phy_init_ex(qdev);
  1348. }
  1349. }
  1350. /*
  1351. * MII_Setup needs to be called before taking the PHY out of reset
  1352. * so that the management interface clock speed can be set properly.
  1353. * It would be better if we had a way to disable MDC until after the
  1354. * PHY is out of reset, but we don't have that capability.
  1355. */
  1356. static int ql_mii_setup(struct ql3_adapter *qdev)
  1357. {
  1358. u32 reg;
  1359. struct ql3xxx_port_registers __iomem *port_regs =
  1360. qdev->mem_map_registers;
  1361. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1362. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1363. 2) << 7))
  1364. return -1;
  1365. if (qdev->device_id == QL3032_DEVICE_ID)
  1366. ql_write_page0_reg(qdev,
  1367. &port_regs->macMIIMgmtControlReg, 0x0f00000);
  1368. /* Divide 125MHz clock by 28 to meet PHY timing requirements */
  1369. reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
  1370. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  1371. reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
  1372. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1373. return 0;
  1374. }
  1375. #define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
  1376. SUPPORTED_FIBRE | \
  1377. SUPPORTED_Autoneg)
  1378. #define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
  1379. SUPPORTED_10baseT_Full | \
  1380. SUPPORTED_100baseT_Half | \
  1381. SUPPORTED_100baseT_Full | \
  1382. SUPPORTED_1000baseT_Half | \
  1383. SUPPORTED_1000baseT_Full | \
  1384. SUPPORTED_Autoneg | \
  1385. SUPPORTED_TP) \
  1386. static u32 ql_supported_modes(struct ql3_adapter *qdev)
  1387. {
  1388. if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
  1389. return SUPPORTED_OPTICAL_MODES;
  1390. return SUPPORTED_TP_MODES;
  1391. }
  1392. static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
  1393. {
  1394. int status;
  1395. unsigned long hw_flags;
  1396. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1397. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1398. (QL_RESOURCE_BITS_BASE_CODE |
  1399. (qdev->mac_index) * 2) << 7)) {
  1400. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1401. return 0;
  1402. }
  1403. status = ql_is_auto_cfg(qdev);
  1404. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1405. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1406. return status;
  1407. }
  1408. static u32 ql_get_speed(struct ql3_adapter *qdev)
  1409. {
  1410. u32 status;
  1411. unsigned long hw_flags;
  1412. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1413. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1414. (QL_RESOURCE_BITS_BASE_CODE |
  1415. (qdev->mac_index) * 2) << 7)) {
  1416. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1417. return 0;
  1418. }
  1419. status = ql_get_link_speed(qdev);
  1420. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1421. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1422. return status;
  1423. }
  1424. static int ql_get_full_dup(struct ql3_adapter *qdev)
  1425. {
  1426. int status;
  1427. unsigned long hw_flags;
  1428. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1429. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1430. (QL_RESOURCE_BITS_BASE_CODE |
  1431. (qdev->mac_index) * 2) << 7)) {
  1432. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1433. return 0;
  1434. }
  1435. status = ql_is_link_full_dup(qdev);
  1436. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1437. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1438. return status;
  1439. }
  1440. static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
  1441. {
  1442. struct ql3_adapter *qdev = netdev_priv(ndev);
  1443. ecmd->transceiver = XCVR_INTERNAL;
  1444. ecmd->supported = ql_supported_modes(qdev);
  1445. if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
  1446. ecmd->port = PORT_FIBRE;
  1447. } else {
  1448. ecmd->port = PORT_TP;
  1449. ecmd->phy_address = qdev->PHYAddr;
  1450. }
  1451. ecmd->advertising = ql_supported_modes(qdev);
  1452. ecmd->autoneg = ql_get_auto_cfg_status(qdev);
  1453. ethtool_cmd_speed_set(ecmd, ql_get_speed(qdev));
  1454. ecmd->duplex = ql_get_full_dup(qdev);
  1455. return 0;
  1456. }
  1457. static void ql_get_drvinfo(struct net_device *ndev,
  1458. struct ethtool_drvinfo *drvinfo)
  1459. {
  1460. struct ql3_adapter *qdev = netdev_priv(ndev);
  1461. strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
  1462. strncpy(drvinfo->version, ql3xxx_driver_version, 32);
  1463. strncpy(drvinfo->fw_version, "N/A", 32);
  1464. strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
  1465. drvinfo->regdump_len = 0;
  1466. drvinfo->eedump_len = 0;
  1467. }
  1468. static u32 ql_get_msglevel(struct net_device *ndev)
  1469. {
  1470. struct ql3_adapter *qdev = netdev_priv(ndev);
  1471. return qdev->msg_enable;
  1472. }
  1473. static void ql_set_msglevel(struct net_device *ndev, u32 value)
  1474. {
  1475. struct ql3_adapter *qdev = netdev_priv(ndev);
  1476. qdev->msg_enable = value;
  1477. }
  1478. static void ql_get_pauseparam(struct net_device *ndev,
  1479. struct ethtool_pauseparam *pause)
  1480. {
  1481. struct ql3_adapter *qdev = netdev_priv(ndev);
  1482. struct ql3xxx_port_registers __iomem *port_regs =
  1483. qdev->mem_map_registers;
  1484. u32 reg;
  1485. if (qdev->mac_index == 0)
  1486. reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
  1487. else
  1488. reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
  1489. pause->autoneg = ql_get_auto_cfg_status(qdev);
  1490. pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
  1491. pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
  1492. }
  1493. static const struct ethtool_ops ql3xxx_ethtool_ops = {
  1494. .get_settings = ql_get_settings,
  1495. .get_drvinfo = ql_get_drvinfo,
  1496. .get_link = ethtool_op_get_link,
  1497. .get_msglevel = ql_get_msglevel,
  1498. .set_msglevel = ql_set_msglevel,
  1499. .get_pauseparam = ql_get_pauseparam,
  1500. };
  1501. static int ql_populate_free_queue(struct ql3_adapter *qdev)
  1502. {
  1503. struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
  1504. dma_addr_t map;
  1505. int err;
  1506. while (lrg_buf_cb) {
  1507. if (!lrg_buf_cb->skb) {
  1508. lrg_buf_cb->skb =
  1509. netdev_alloc_skb(qdev->ndev,
  1510. qdev->lrg_buffer_len);
  1511. if (unlikely(!lrg_buf_cb->skb)) {
  1512. netdev_printk(KERN_DEBUG, qdev->ndev,
  1513. "Failed netdev_alloc_skb()\n");
  1514. break;
  1515. } else {
  1516. /*
  1517. * We save some space to copy the ethhdr from
  1518. * first buffer
  1519. */
  1520. skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
  1521. map = pci_map_single(qdev->pdev,
  1522. lrg_buf_cb->skb->data,
  1523. qdev->lrg_buffer_len -
  1524. QL_HEADER_SPACE,
  1525. PCI_DMA_FROMDEVICE);
  1526. err = pci_dma_mapping_error(qdev->pdev, map);
  1527. if (err) {
  1528. netdev_err(qdev->ndev,
  1529. "PCI mapping failed with error: %d\n",
  1530. err);
  1531. dev_kfree_skb(lrg_buf_cb->skb);
  1532. lrg_buf_cb->skb = NULL;
  1533. break;
  1534. }
  1535. lrg_buf_cb->buf_phy_addr_low =
  1536. cpu_to_le32(LS_64BITS(map));
  1537. lrg_buf_cb->buf_phy_addr_high =
  1538. cpu_to_le32(MS_64BITS(map));
  1539. dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
  1540. dma_unmap_len_set(lrg_buf_cb, maplen,
  1541. qdev->lrg_buffer_len -
  1542. QL_HEADER_SPACE);
  1543. --qdev->lrg_buf_skb_check;
  1544. if (!qdev->lrg_buf_skb_check)
  1545. return 1;
  1546. }
  1547. }
  1548. lrg_buf_cb = lrg_buf_cb->next;
  1549. }
  1550. return 0;
  1551. }
  1552. /*
  1553. * Caller holds hw_lock.
  1554. */
  1555. static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
  1556. {
  1557. struct ql3xxx_port_registers __iomem *port_regs =
  1558. qdev->mem_map_registers;
  1559. if (qdev->small_buf_release_cnt >= 16) {
  1560. while (qdev->small_buf_release_cnt >= 16) {
  1561. qdev->small_buf_q_producer_index++;
  1562. if (qdev->small_buf_q_producer_index ==
  1563. NUM_SBUFQ_ENTRIES)
  1564. qdev->small_buf_q_producer_index = 0;
  1565. qdev->small_buf_release_cnt -= 8;
  1566. }
  1567. wmb();
  1568. writel(qdev->small_buf_q_producer_index,
  1569. &port_regs->CommonRegs.rxSmallQProducerIndex);
  1570. }
  1571. }
  1572. /*
  1573. * Caller holds hw_lock.
  1574. */
  1575. static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
  1576. {
  1577. struct bufq_addr_element *lrg_buf_q_ele;
  1578. int i;
  1579. struct ql_rcv_buf_cb *lrg_buf_cb;
  1580. struct ql3xxx_port_registers __iomem *port_regs =
  1581. qdev->mem_map_registers;
  1582. if ((qdev->lrg_buf_free_count >= 8) &&
  1583. (qdev->lrg_buf_release_cnt >= 16)) {
  1584. if (qdev->lrg_buf_skb_check)
  1585. if (!ql_populate_free_queue(qdev))
  1586. return;
  1587. lrg_buf_q_ele = qdev->lrg_buf_next_free;
  1588. while ((qdev->lrg_buf_release_cnt >= 16) &&
  1589. (qdev->lrg_buf_free_count >= 8)) {
  1590. for (i = 0; i < 8; i++) {
  1591. lrg_buf_cb =
  1592. ql_get_from_lrg_buf_free_list(qdev);
  1593. lrg_buf_q_ele->addr_high =
  1594. lrg_buf_cb->buf_phy_addr_high;
  1595. lrg_buf_q_ele->addr_low =
  1596. lrg_buf_cb->buf_phy_addr_low;
  1597. lrg_buf_q_ele++;
  1598. qdev->lrg_buf_release_cnt--;
  1599. }
  1600. qdev->lrg_buf_q_producer_index++;
  1601. if (qdev->lrg_buf_q_producer_index ==
  1602. qdev->num_lbufq_entries)
  1603. qdev->lrg_buf_q_producer_index = 0;
  1604. if (qdev->lrg_buf_q_producer_index ==
  1605. (qdev->num_lbufq_entries - 1)) {
  1606. lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
  1607. }
  1608. }
  1609. wmb();
  1610. qdev->lrg_buf_next_free = lrg_buf_q_ele;
  1611. writel(qdev->lrg_buf_q_producer_index,
  1612. &port_regs->CommonRegs.rxLargeQProducerIndex);
  1613. }
  1614. }
  1615. static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
  1616. struct ob_mac_iocb_rsp *mac_rsp)
  1617. {
  1618. struct ql_tx_buf_cb *tx_cb;
  1619. int i;
  1620. int retval = 0;
  1621. if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
  1622. netdev_warn(qdev->ndev,
  1623. "Frame too short but it was padded and sent\n");
  1624. }
  1625. tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
  1626. /* Check the transmit response flags for any errors */
  1627. if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
  1628. netdev_err(qdev->ndev,
  1629. "Frame too short to be legal, frame not sent\n");
  1630. qdev->ndev->stats.tx_errors++;
  1631. retval = -EIO;
  1632. goto frame_not_sent;
  1633. }
  1634. if (tx_cb->seg_count == 0) {
  1635. netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
  1636. mac_rsp->transaction_id);
  1637. qdev->ndev->stats.tx_errors++;
  1638. retval = -EIO;
  1639. goto invalid_seg_count;
  1640. }
  1641. pci_unmap_single(qdev->pdev,
  1642. dma_unmap_addr(&tx_cb->map[0], mapaddr),
  1643. dma_unmap_len(&tx_cb->map[0], maplen),
  1644. PCI_DMA_TODEVICE);
  1645. tx_cb->seg_count--;
  1646. if (tx_cb->seg_count) {
  1647. for (i = 1; i < tx_cb->seg_count; i++) {
  1648. pci_unmap_page(qdev->pdev,
  1649. dma_unmap_addr(&tx_cb->map[i],
  1650. mapaddr),
  1651. dma_unmap_len(&tx_cb->map[i], maplen),
  1652. PCI_DMA_TODEVICE);
  1653. }
  1654. }
  1655. qdev->ndev->stats.tx_packets++;
  1656. qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
  1657. frame_not_sent:
  1658. dev_kfree_skb_irq(tx_cb->skb);
  1659. tx_cb->skb = NULL;
  1660. invalid_seg_count:
  1661. atomic_inc(&qdev->tx_count);
  1662. }
  1663. static void ql_get_sbuf(struct ql3_adapter *qdev)
  1664. {
  1665. if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
  1666. qdev->small_buf_index = 0;
  1667. qdev->small_buf_release_cnt++;
  1668. }
  1669. static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
  1670. {
  1671. struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
  1672. lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
  1673. qdev->lrg_buf_release_cnt++;
  1674. if (++qdev->lrg_buf_index == qdev->num_large_buffers)
  1675. qdev->lrg_buf_index = 0;
  1676. return lrg_buf_cb;
  1677. }
  1678. /*
  1679. * The difference between 3022 and 3032 for inbound completions:
  1680. * 3022 uses two buffers per completion. The first buffer contains
  1681. * (some) header info, the second the remainder of the headers plus
  1682. * the data. For this chip we reserve some space at the top of the
  1683. * receive buffer so that the header info in buffer one can be
  1684. * prepended to the buffer two. Buffer two is the sent up while
  1685. * buffer one is returned to the hardware to be reused.
  1686. * 3032 receives all of it's data and headers in one buffer for a
  1687. * simpler process. 3032 also supports checksum verification as
  1688. * can be seen in ql_process_macip_rx_intr().
  1689. */
  1690. static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
  1691. struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
  1692. {
  1693. struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
  1694. struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
  1695. struct sk_buff *skb;
  1696. u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
  1697. /*
  1698. * Get the inbound address list (small buffer).
  1699. */
  1700. ql_get_sbuf(qdev);
  1701. if (qdev->device_id == QL3022_DEVICE_ID)
  1702. lrg_buf_cb1 = ql_get_lbuf(qdev);
  1703. /* start of second buffer */
  1704. lrg_buf_cb2 = ql_get_lbuf(qdev);
  1705. skb = lrg_buf_cb2->skb;
  1706. qdev->ndev->stats.rx_packets++;
  1707. qdev->ndev->stats.rx_bytes += length;
  1708. skb_put(skb, length);
  1709. pci_unmap_single(qdev->pdev,
  1710. dma_unmap_addr(lrg_buf_cb2, mapaddr),
  1711. dma_unmap_len(lrg_buf_cb2, maplen),
  1712. PCI_DMA_FROMDEVICE);
  1713. prefetch(skb->data);
  1714. skb_checksum_none_assert(skb);
  1715. skb->protocol = eth_type_trans(skb, qdev->ndev);
  1716. netif_receive_skb(skb);
  1717. lrg_buf_cb2->skb = NULL;
  1718. if (qdev->device_id == QL3022_DEVICE_ID)
  1719. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
  1720. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
  1721. }
  1722. static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
  1723. struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
  1724. {
  1725. struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
  1726. struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
  1727. struct sk_buff *skb1 = NULL, *skb2;
  1728. struct net_device *ndev = qdev->ndev;
  1729. u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
  1730. u16 size = 0;
  1731. /*
  1732. * Get the inbound address list (small buffer).
  1733. */
  1734. ql_get_sbuf(qdev);
  1735. if (qdev->device_id == QL3022_DEVICE_ID) {
  1736. /* start of first buffer on 3022 */
  1737. lrg_buf_cb1 = ql_get_lbuf(qdev);
  1738. skb1 = lrg_buf_cb1->skb;
  1739. size = ETH_HLEN;
  1740. if (*((u16 *) skb1->data) != 0xFFFF)
  1741. size += VLAN_ETH_HLEN - ETH_HLEN;
  1742. }
  1743. /* start of second buffer */
  1744. lrg_buf_cb2 = ql_get_lbuf(qdev);
  1745. skb2 = lrg_buf_cb2->skb;
  1746. skb_put(skb2, length); /* Just the second buffer length here. */
  1747. pci_unmap_single(qdev->pdev,
  1748. dma_unmap_addr(lrg_buf_cb2, mapaddr),
  1749. dma_unmap_len(lrg_buf_cb2, maplen),
  1750. PCI_DMA_FROMDEVICE);
  1751. prefetch(skb2->data);
  1752. skb_checksum_none_assert(skb2);
  1753. if (qdev->device_id == QL3022_DEVICE_ID) {
  1754. /*
  1755. * Copy the ethhdr from first buffer to second. This
  1756. * is necessary for 3022 IP completions.
  1757. */
  1758. skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
  1759. skb_push(skb2, size), size);
  1760. } else {
  1761. u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
  1762. if (checksum &
  1763. (IB_IP_IOCB_RSP_3032_ICE |
  1764. IB_IP_IOCB_RSP_3032_CE)) {
  1765. netdev_err(ndev,
  1766. "%s: Bad checksum for this %s packet, checksum = %x\n",
  1767. __func__,
  1768. ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
  1769. "TCP" : "UDP"), checksum);
  1770. } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
  1771. (checksum & IB_IP_IOCB_RSP_3032_UDP &&
  1772. !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
  1773. skb2->ip_summed = CHECKSUM_UNNECESSARY;
  1774. }
  1775. }
  1776. skb2->protocol = eth_type_trans(skb2, qdev->ndev);
  1777. netif_receive_skb(skb2);
  1778. ndev->stats.rx_packets++;
  1779. ndev->stats.rx_bytes += length;
  1780. lrg_buf_cb2->skb = NULL;
  1781. if (qdev->device_id == QL3022_DEVICE_ID)
  1782. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
  1783. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
  1784. }
  1785. static int ql_tx_rx_clean(struct ql3_adapter *qdev,
  1786. int *tx_cleaned, int *rx_cleaned, int work_to_do)
  1787. {
  1788. struct net_rsp_iocb *net_rsp;
  1789. struct net_device *ndev = qdev->ndev;
  1790. int work_done = 0;
  1791. /* While there are entries in the completion queue. */
  1792. while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
  1793. qdev->rsp_consumer_index) && (work_done < work_to_do)) {
  1794. net_rsp = qdev->rsp_current;
  1795. rmb();
  1796. /*
  1797. * Fix 4032 chip's undocumented "feature" where bit-8 is set
  1798. * if the inbound completion is for a VLAN.
  1799. */
  1800. if (qdev->device_id == QL3032_DEVICE_ID)
  1801. net_rsp->opcode &= 0x7f;
  1802. switch (net_rsp->opcode) {
  1803. case OPCODE_OB_MAC_IOCB_FN0:
  1804. case OPCODE_OB_MAC_IOCB_FN2:
  1805. ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
  1806. net_rsp);
  1807. (*tx_cleaned)++;
  1808. break;
  1809. case OPCODE_IB_MAC_IOCB:
  1810. case OPCODE_IB_3032_MAC_IOCB:
  1811. ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
  1812. net_rsp);
  1813. (*rx_cleaned)++;
  1814. break;
  1815. case OPCODE_IB_IP_IOCB:
  1816. case OPCODE_IB_3032_IP_IOCB:
  1817. ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
  1818. net_rsp);
  1819. (*rx_cleaned)++;
  1820. break;
  1821. default: {
  1822. u32 *tmp = (u32 *)net_rsp;
  1823. netdev_err(ndev,
  1824. "Hit default case, not handled!\n"
  1825. " dropping the packet, opcode = %x\n"
  1826. "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
  1827. net_rsp->opcode,
  1828. (unsigned long int)tmp[0],
  1829. (unsigned long int)tmp[1],
  1830. (unsigned long int)tmp[2],
  1831. (unsigned long int)tmp[3]);
  1832. }
  1833. }
  1834. qdev->rsp_consumer_index++;
  1835. if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
  1836. qdev->rsp_consumer_index = 0;
  1837. qdev->rsp_current = qdev->rsp_q_virt_addr;
  1838. } else {
  1839. qdev->rsp_current++;
  1840. }
  1841. work_done = *tx_cleaned + *rx_cleaned;
  1842. }
  1843. return work_done;
  1844. }
  1845. static int ql_poll(struct napi_struct *napi, int budget)
  1846. {
  1847. struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
  1848. int rx_cleaned = 0, tx_cleaned = 0;
  1849. unsigned long hw_flags;
  1850. struct ql3xxx_port_registers __iomem *port_regs =
  1851. qdev->mem_map_registers;
  1852. ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
  1853. if (tx_cleaned + rx_cleaned != budget) {
  1854. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1855. __napi_complete(napi);
  1856. ql_update_small_bufq_prod_index(qdev);
  1857. ql_update_lrg_bufq_prod_index(qdev);
  1858. writel(qdev->rsp_consumer_index,
  1859. &port_regs->CommonRegs.rspQConsumerIndex);
  1860. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1861. ql_enable_interrupts(qdev);
  1862. }
  1863. return tx_cleaned + rx_cleaned;
  1864. }
  1865. static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
  1866. {
  1867. struct net_device *ndev = dev_id;
  1868. struct ql3_adapter *qdev = netdev_priv(ndev);
  1869. struct ql3xxx_port_registers __iomem *port_regs =
  1870. qdev->mem_map_registers;
  1871. u32 value;
  1872. int handled = 1;
  1873. u32 var;
  1874. value = ql_read_common_reg_l(qdev,
  1875. &port_regs->CommonRegs.ispControlStatus);
  1876. if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
  1877. spin_lock(&qdev->adapter_lock);
  1878. netif_stop_queue(qdev->ndev);
  1879. netif_carrier_off(qdev->ndev);
  1880. ql_disable_interrupts(qdev);
  1881. qdev->port_link_state = LS_DOWN;
  1882. set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
  1883. if (value & ISP_CONTROL_FE) {
  1884. /*
  1885. * Chip Fatal Error.
  1886. */
  1887. var =
  1888. ql_read_page0_reg_l(qdev,
  1889. &port_regs->PortFatalErrStatus);
  1890. netdev_warn(ndev,
  1891. "Resetting chip. PortFatalErrStatus register = 0x%x\n",
  1892. var);
  1893. set_bit(QL_RESET_START, &qdev->flags) ;
  1894. } else {
  1895. /*
  1896. * Soft Reset Requested.
  1897. */
  1898. set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
  1899. netdev_err(ndev,
  1900. "Another function issued a reset to the chip. ISR value = %x\n",
  1901. value);
  1902. }
  1903. queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
  1904. spin_unlock(&qdev->adapter_lock);
  1905. } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
  1906. ql_disable_interrupts(qdev);
  1907. if (likely(napi_schedule_prep(&qdev->napi)))
  1908. __napi_schedule(&qdev->napi);
  1909. } else
  1910. return IRQ_NONE;
  1911. return IRQ_RETVAL(handled);
  1912. }
  1913. /*
  1914. * Get the total number of segments needed for the given number of fragments.
  1915. * This is necessary because outbound address lists (OAL) will be used when
  1916. * more than two frags are given. Each address list has 5 addr/len pairs.
  1917. * The 5th pair in each OAL is used to point to the next OAL if more frags
  1918. * are coming. That is why the frags:segment count ratio is not linear.
  1919. */
  1920. static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
  1921. {
  1922. if (qdev->device_id == QL3022_DEVICE_ID)
  1923. return 1;
  1924. if (frags <= 2)
  1925. return frags + 1;
  1926. else if (frags <= 6)
  1927. return frags + 2;
  1928. else if (frags <= 10)
  1929. return frags + 3;
  1930. else if (frags <= 14)
  1931. return frags + 4;
  1932. else if (frags <= 18)
  1933. return frags + 5;
  1934. return -1;
  1935. }
  1936. static void ql_hw_csum_setup(const struct sk_buff *skb,
  1937. struct ob_mac_iocb_req *mac_iocb_ptr)
  1938. {
  1939. const struct iphdr *ip = ip_hdr(skb);
  1940. mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
  1941. mac_iocb_ptr->ip_hdr_len = ip->ihl;
  1942. if (ip->protocol == IPPROTO_TCP) {
  1943. mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
  1944. OB_3032MAC_IOCB_REQ_IC;
  1945. } else {
  1946. mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
  1947. OB_3032MAC_IOCB_REQ_IC;
  1948. }
  1949. }
  1950. /*
  1951. * Map the buffers for this transmit.
  1952. * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
  1953. */
  1954. static int ql_send_map(struct ql3_adapter *qdev,
  1955. struct ob_mac_iocb_req *mac_iocb_ptr,
  1956. struct ql_tx_buf_cb *tx_cb,
  1957. struct sk_buff *skb)
  1958. {
  1959. struct oal *oal;
  1960. struct oal_entry *oal_entry;
  1961. int len = skb_headlen(skb);
  1962. dma_addr_t map;
  1963. int err;
  1964. int completed_segs, i;
  1965. int seg_cnt, seg = 0;
  1966. int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
  1967. seg_cnt = tx_cb->seg_count;
  1968. /*
  1969. * Map the skb buffer first.
  1970. */
  1971. map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1972. err = pci_dma_mapping_error(qdev->pdev, map);
  1973. if (err) {
  1974. netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
  1975. err);
  1976. return NETDEV_TX_BUSY;
  1977. }
  1978. oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
  1979. oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
  1980. oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
  1981. oal_entry->len = cpu_to_le32(len);
  1982. dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
  1983. dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
  1984. seg++;
  1985. if (seg_cnt == 1) {
  1986. /* Terminate the last segment. */
  1987. oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
  1988. return NETDEV_TX_OK;
  1989. }
  1990. oal = tx_cb->oal;
  1991. for (completed_segs = 0;
  1992. completed_segs < frag_cnt;
  1993. completed_segs++, seg++) {
  1994. skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
  1995. oal_entry++;
  1996. /*
  1997. * Check for continuation requirements.
  1998. * It's strange but necessary.
  1999. * Continuation entry points to outbound address list.
  2000. */
  2001. if ((seg == 2 && seg_cnt > 3) ||
  2002. (seg == 7 && seg_cnt > 8) ||
  2003. (seg == 12 && seg_cnt > 13) ||
  2004. (seg == 17 && seg_cnt > 18)) {
  2005. map = pci_map_single(qdev->pdev, oal,
  2006. sizeof(struct oal),
  2007. PCI_DMA_TODEVICE);
  2008. err = pci_dma_mapping_error(qdev->pdev, map);
  2009. if (err) {
  2010. netdev_err(qdev->ndev,
  2011. "PCI mapping outbound address list with error: %d\n",
  2012. err);
  2013. goto map_error;
  2014. }
  2015. oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
  2016. oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
  2017. oal_entry->len = cpu_to_le32(sizeof(struct oal) |
  2018. OAL_CONT_ENTRY);
  2019. dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
  2020. dma_unmap_len_set(&tx_cb->map[seg], maplen,
  2021. sizeof(struct oal));
  2022. oal_entry = (struct oal_entry *)oal;
  2023. oal++;
  2024. seg++;
  2025. }
  2026. map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
  2027. DMA_TO_DEVICE);
  2028. err = dma_mapping_error(&qdev->pdev->dev, map);
  2029. if (err) {
  2030. netdev_err(qdev->ndev,
  2031. "PCI mapping frags failed with error: %d\n",
  2032. err);
  2033. goto map_error;
  2034. }
  2035. oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
  2036. oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
  2037. oal_entry->len = cpu_to_le32(skb_frag_size(frag));
  2038. dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
  2039. dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
  2040. }
  2041. /* Terminate the last segment. */
  2042. oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
  2043. return NETDEV_TX_OK;
  2044. map_error:
  2045. /* A PCI mapping failed and now we will need to back out
  2046. * We need to traverse through the oal's and associated pages which
  2047. * have been mapped and now we must unmap them to clean up properly
  2048. */
  2049. seg = 1;
  2050. oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
  2051. oal = tx_cb->oal;
  2052. for (i = 0; i < completed_segs; i++, seg++) {
  2053. oal_entry++;
  2054. /*
  2055. * Check for continuation requirements.
  2056. * It's strange but necessary.
  2057. */
  2058. if ((seg == 2 && seg_cnt > 3) ||
  2059. (seg == 7 && seg_cnt > 8) ||
  2060. (seg == 12 && seg_cnt > 13) ||
  2061. (seg == 17 && seg_cnt > 18)) {
  2062. pci_unmap_single(qdev->pdev,
  2063. dma_unmap_addr(&tx_cb->map[seg], mapaddr),
  2064. dma_unmap_len(&tx_cb->map[seg], maplen),
  2065. PCI_DMA_TODEVICE);
  2066. oal++;
  2067. seg++;
  2068. }
  2069. pci_unmap_page(qdev->pdev,
  2070. dma_unmap_addr(&tx_cb->map[seg], mapaddr),
  2071. dma_unmap_len(&tx_cb->map[seg], maplen),
  2072. PCI_DMA_TODEVICE);
  2073. }
  2074. pci_unmap_single(qdev->pdev,
  2075. dma_unmap_addr(&tx_cb->map[0], mapaddr),
  2076. dma_unmap_addr(&tx_cb->map[0], maplen),
  2077. PCI_DMA_TODEVICE);
  2078. return NETDEV_TX_BUSY;
  2079. }
  2080. /*
  2081. * The difference between 3022 and 3032 sends:
  2082. * 3022 only supports a simple single segment transmission.
  2083. * 3032 supports checksumming and scatter/gather lists (fragments).
  2084. * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
  2085. * in the IOCB plus a chain of outbound address lists (OAL) that
  2086. * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
  2087. * will be used to point to an OAL when more ALP entries are required.
  2088. * The IOCB is always the top of the chain followed by one or more
  2089. * OALs (when necessary).
  2090. */
  2091. static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
  2092. struct net_device *ndev)
  2093. {
  2094. struct ql3_adapter *qdev = netdev_priv(ndev);
  2095. struct ql3xxx_port_registers __iomem *port_regs =
  2096. qdev->mem_map_registers;
  2097. struct ql_tx_buf_cb *tx_cb;
  2098. u32 tot_len = skb->len;
  2099. struct ob_mac_iocb_req *mac_iocb_ptr;
  2100. if (unlikely(atomic_read(&qdev->tx_count) < 2))
  2101. return NETDEV_TX_BUSY;
  2102. tx_cb = &qdev->tx_buf[qdev->req_producer_index];
  2103. tx_cb->seg_count = ql_get_seg_count(qdev,
  2104. skb_shinfo(skb)->nr_frags);
  2105. if (tx_cb->seg_count == -1) {
  2106. netdev_err(ndev, "%s: invalid segment count!\n", __func__);
  2107. return NETDEV_TX_OK;
  2108. }
  2109. mac_iocb_ptr = tx_cb->queue_entry;
  2110. memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
  2111. mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
  2112. mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
  2113. mac_iocb_ptr->flags |= qdev->mb_bit_mask;
  2114. mac_iocb_ptr->transaction_id = qdev->req_producer_index;
  2115. mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
  2116. tx_cb->skb = skb;
  2117. if (qdev->device_id == QL3032_DEVICE_ID &&
  2118. skb->ip_summed == CHECKSUM_PARTIAL)
  2119. ql_hw_csum_setup(skb, mac_iocb_ptr);
  2120. if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
  2121. netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
  2122. return NETDEV_TX_BUSY;
  2123. }
  2124. wmb();
  2125. qdev->req_producer_index++;
  2126. if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
  2127. qdev->req_producer_index = 0;
  2128. wmb();
  2129. ql_write_common_reg_l(qdev,
  2130. &port_regs->CommonRegs.reqQProducerIndex,
  2131. qdev->req_producer_index);
  2132. netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
  2133. "tx queued, slot %d, len %d\n",
  2134. qdev->req_producer_index, skb->len);
  2135. atomic_dec(&qdev->tx_count);
  2136. return NETDEV_TX_OK;
  2137. }
  2138. static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
  2139. {
  2140. qdev->req_q_size =
  2141. (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
  2142. qdev->req_q_virt_addr =
  2143. pci_alloc_consistent(qdev->pdev,
  2144. (size_t) qdev->req_q_size,
  2145. &qdev->req_q_phy_addr);
  2146. if ((qdev->req_q_virt_addr == NULL) ||
  2147. LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
  2148. netdev_err(qdev->ndev, "reqQ failed\n");
  2149. return -ENOMEM;
  2150. }
  2151. qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
  2152. qdev->rsp_q_virt_addr =
  2153. pci_alloc_consistent(qdev->pdev,
  2154. (size_t) qdev->rsp_q_size,
  2155. &qdev->rsp_q_phy_addr);
  2156. if ((qdev->rsp_q_virt_addr == NULL) ||
  2157. LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
  2158. netdev_err(qdev->ndev, "rspQ allocation failed\n");
  2159. pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
  2160. qdev->req_q_virt_addr,
  2161. qdev->req_q_phy_addr);
  2162. return -ENOMEM;
  2163. }
  2164. set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
  2165. return 0;
  2166. }
  2167. static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
  2168. {
  2169. if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
  2170. netdev_info(qdev->ndev, "Already done\n");
  2171. return;
  2172. }
  2173. pci_free_consistent(qdev->pdev,
  2174. qdev->req_q_size,
  2175. qdev->req_q_virt_addr, qdev->req_q_phy_addr);
  2176. qdev->req_q_virt_addr = NULL;
  2177. pci_free_consistent(qdev->pdev,
  2178. qdev->rsp_q_size,
  2179. qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
  2180. qdev->rsp_q_virt_addr = NULL;
  2181. clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
  2182. }
  2183. static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
  2184. {
  2185. /* Create Large Buffer Queue */
  2186. qdev->lrg_buf_q_size =
  2187. qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
  2188. if (qdev->lrg_buf_q_size < PAGE_SIZE)
  2189. qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
  2190. else
  2191. qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
  2192. qdev->lrg_buf =
  2193. kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),
  2194. GFP_KERNEL);
  2195. if (qdev->lrg_buf == NULL) {
  2196. netdev_err(qdev->ndev, "qdev->lrg_buf alloc failed\n");
  2197. return -ENOMEM;
  2198. }
  2199. qdev->lrg_buf_q_alloc_virt_addr =
  2200. pci_alloc_consistent(qdev->pdev,
  2201. qdev->lrg_buf_q_alloc_size,
  2202. &qdev->lrg_buf_q_alloc_phy_addr);
  2203. if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
  2204. netdev_err(qdev->ndev, "lBufQ failed\n");
  2205. return -ENOMEM;
  2206. }
  2207. qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
  2208. qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
  2209. /* Create Small Buffer Queue */
  2210. qdev->small_buf_q_size =
  2211. NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
  2212. if (qdev->small_buf_q_size < PAGE_SIZE)
  2213. qdev->small_buf_q_alloc_size = PAGE_SIZE;
  2214. else
  2215. qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
  2216. qdev->small_buf_q_alloc_virt_addr =
  2217. pci_alloc_consistent(qdev->pdev,
  2218. qdev->small_buf_q_alloc_size,
  2219. &qdev->small_buf_q_alloc_phy_addr);
  2220. if (qdev->small_buf_q_alloc_virt_addr == NULL) {
  2221. netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
  2222. pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
  2223. qdev->lrg_buf_q_alloc_virt_addr,
  2224. qdev->lrg_buf_q_alloc_phy_addr);
  2225. return -ENOMEM;
  2226. }
  2227. qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
  2228. qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
  2229. set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
  2230. return 0;
  2231. }
  2232. static void ql_free_buffer_queues(struct ql3_adapter *qdev)
  2233. {
  2234. if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
  2235. netdev_info(qdev->ndev, "Already done\n");
  2236. return;
  2237. }
  2238. kfree(qdev->lrg_buf);
  2239. pci_free_consistent(qdev->pdev,
  2240. qdev->lrg_buf_q_alloc_size,
  2241. qdev->lrg_buf_q_alloc_virt_addr,
  2242. qdev->lrg_buf_q_alloc_phy_addr);
  2243. qdev->lrg_buf_q_virt_addr = NULL;
  2244. pci_free_consistent(qdev->pdev,
  2245. qdev->small_buf_q_alloc_size,
  2246. qdev->small_buf_q_alloc_virt_addr,
  2247. qdev->small_buf_q_alloc_phy_addr);
  2248. qdev->small_buf_q_virt_addr = NULL;
  2249. clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
  2250. }
  2251. static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
  2252. {
  2253. int i;
  2254. struct bufq_addr_element *small_buf_q_entry;
  2255. /* Currently we allocate on one of memory and use it for smallbuffers */
  2256. qdev->small_buf_total_size =
  2257. (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
  2258. QL_SMALL_BUFFER_SIZE);
  2259. qdev->small_buf_virt_addr =
  2260. pci_alloc_consistent(qdev->pdev,
  2261. qdev->small_buf_total_size,
  2262. &qdev->small_buf_phy_addr);
  2263. if (qdev->small_buf_virt_addr == NULL) {
  2264. netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
  2265. return -ENOMEM;
  2266. }
  2267. qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
  2268. qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
  2269. small_buf_q_entry = qdev->small_buf_q_virt_addr;
  2270. /* Initialize the small buffer queue. */
  2271. for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
  2272. small_buf_q_entry->addr_high =
  2273. cpu_to_le32(qdev->small_buf_phy_addr_high);
  2274. small_buf_q_entry->addr_low =
  2275. cpu_to_le32(qdev->small_buf_phy_addr_low +
  2276. (i * QL_SMALL_BUFFER_SIZE));
  2277. small_buf_q_entry++;
  2278. }
  2279. qdev->small_buf_index = 0;
  2280. set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
  2281. return 0;
  2282. }
  2283. static void ql_free_small_buffers(struct ql3_adapter *qdev)
  2284. {
  2285. if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
  2286. netdev_info(qdev->ndev, "Already done\n");
  2287. return;
  2288. }
  2289. if (qdev->small_buf_virt_addr != NULL) {
  2290. pci_free_consistent(qdev->pdev,
  2291. qdev->small_buf_total_size,
  2292. qdev->small_buf_virt_addr,
  2293. qdev->small_buf_phy_addr);
  2294. qdev->small_buf_virt_addr = NULL;
  2295. }
  2296. }
  2297. static void ql_free_large_buffers(struct ql3_adapter *qdev)
  2298. {
  2299. int i = 0;
  2300. struct ql_rcv_buf_cb *lrg_buf_cb;
  2301. for (i = 0; i < qdev->num_large_buffers; i++) {
  2302. lrg_buf_cb = &qdev->lrg_buf[i];
  2303. if (lrg_buf_cb->skb) {
  2304. dev_kfree_skb(lrg_buf_cb->skb);
  2305. pci_unmap_single(qdev->pdev,
  2306. dma_unmap_addr(lrg_buf_cb, mapaddr),
  2307. dma_unmap_len(lrg_buf_cb, maplen),
  2308. PCI_DMA_FROMDEVICE);
  2309. memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
  2310. } else {
  2311. break;
  2312. }
  2313. }
  2314. }
  2315. static void ql_init_large_buffers(struct ql3_adapter *qdev)
  2316. {
  2317. int i;
  2318. struct ql_rcv_buf_cb *lrg_buf_cb;
  2319. struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
  2320. for (i = 0; i < qdev->num_large_buffers; i++) {
  2321. lrg_buf_cb = &qdev->lrg_buf[i];
  2322. buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
  2323. buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
  2324. buf_addr_ele++;
  2325. }
  2326. qdev->lrg_buf_index = 0;
  2327. qdev->lrg_buf_skb_check = 0;
  2328. }
  2329. static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
  2330. {
  2331. int i;
  2332. struct ql_rcv_buf_cb *lrg_buf_cb;
  2333. struct sk_buff *skb;
  2334. dma_addr_t map;
  2335. int err;
  2336. for (i = 0; i < qdev->num_large_buffers; i++) {
  2337. skb = netdev_alloc_skb(qdev->ndev,
  2338. qdev->lrg_buffer_len);
  2339. if (unlikely(!skb)) {
  2340. /* Better luck next round */
  2341. netdev_err(qdev->ndev,
  2342. "large buff alloc failed for %d bytes at index %d\n",
  2343. qdev->lrg_buffer_len * 2, i);
  2344. ql_free_large_buffers(qdev);
  2345. return -ENOMEM;
  2346. } else {
  2347. lrg_buf_cb = &qdev->lrg_buf[i];
  2348. memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
  2349. lrg_buf_cb->index = i;
  2350. lrg_buf_cb->skb = skb;
  2351. /*
  2352. * We save some space to copy the ethhdr from first
  2353. * buffer
  2354. */
  2355. skb_reserve(skb, QL_HEADER_SPACE);
  2356. map = pci_map_single(qdev->pdev,
  2357. skb->data,
  2358. qdev->lrg_buffer_len -
  2359. QL_HEADER_SPACE,
  2360. PCI_DMA_FROMDEVICE);
  2361. err = pci_dma_mapping_error(qdev->pdev, map);
  2362. if (err) {
  2363. netdev_err(qdev->ndev,
  2364. "PCI mapping failed with error: %d\n",
  2365. err);
  2366. ql_free_large_buffers(qdev);
  2367. return -ENOMEM;
  2368. }
  2369. dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
  2370. dma_unmap_len_set(lrg_buf_cb, maplen,
  2371. qdev->lrg_buffer_len -
  2372. QL_HEADER_SPACE);
  2373. lrg_buf_cb->buf_phy_addr_low =
  2374. cpu_to_le32(LS_64BITS(map));
  2375. lrg_buf_cb->buf_phy_addr_high =
  2376. cpu_to_le32(MS_64BITS(map));
  2377. }
  2378. }
  2379. return 0;
  2380. }
  2381. static void ql_free_send_free_list(struct ql3_adapter *qdev)
  2382. {
  2383. struct ql_tx_buf_cb *tx_cb;
  2384. int i;
  2385. tx_cb = &qdev->tx_buf[0];
  2386. for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
  2387. kfree(tx_cb->oal);
  2388. tx_cb->oal = NULL;
  2389. tx_cb++;
  2390. }
  2391. }
  2392. static int ql_create_send_free_list(struct ql3_adapter *qdev)
  2393. {
  2394. struct ql_tx_buf_cb *tx_cb;
  2395. int i;
  2396. struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
  2397. /* Create free list of transmit buffers */
  2398. for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
  2399. tx_cb = &qdev->tx_buf[i];
  2400. tx_cb->skb = NULL;
  2401. tx_cb->queue_entry = req_q_curr;
  2402. req_q_curr++;
  2403. tx_cb->oal = kmalloc(512, GFP_KERNEL);
  2404. if (tx_cb->oal == NULL)
  2405. return -1;
  2406. }
  2407. return 0;
  2408. }
  2409. static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
  2410. {
  2411. if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
  2412. qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
  2413. qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
  2414. } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
  2415. /*
  2416. * Bigger buffers, so less of them.
  2417. */
  2418. qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
  2419. qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
  2420. } else {
  2421. netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
  2422. qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
  2423. return -ENOMEM;
  2424. }
  2425. qdev->num_large_buffers =
  2426. qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
  2427. qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
  2428. qdev->max_frame_size =
  2429. (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
  2430. /*
  2431. * First allocate a page of shared memory and use it for shadow
  2432. * locations of Network Request Queue Consumer Address Register and
  2433. * Network Completion Queue Producer Index Register
  2434. */
  2435. qdev->shadow_reg_virt_addr =
  2436. pci_alloc_consistent(qdev->pdev,
  2437. PAGE_SIZE, &qdev->shadow_reg_phy_addr);
  2438. if (qdev->shadow_reg_virt_addr != NULL) {
  2439. qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
  2440. qdev->req_consumer_index_phy_addr_high =
  2441. MS_64BITS(qdev->shadow_reg_phy_addr);
  2442. qdev->req_consumer_index_phy_addr_low =
  2443. LS_64BITS(qdev->shadow_reg_phy_addr);
  2444. qdev->prsp_producer_index =
  2445. (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
  2446. qdev->rsp_producer_index_phy_addr_high =
  2447. qdev->req_consumer_index_phy_addr_high;
  2448. qdev->rsp_producer_index_phy_addr_low =
  2449. qdev->req_consumer_index_phy_addr_low + 8;
  2450. } else {
  2451. netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
  2452. return -ENOMEM;
  2453. }
  2454. if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
  2455. netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
  2456. goto err_req_rsp;
  2457. }
  2458. if (ql_alloc_buffer_queues(qdev) != 0) {
  2459. netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
  2460. goto err_buffer_queues;
  2461. }
  2462. if (ql_alloc_small_buffers(qdev) != 0) {
  2463. netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
  2464. goto err_small_buffers;
  2465. }
  2466. if (ql_alloc_large_buffers(qdev) != 0) {
  2467. netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
  2468. goto err_small_buffers;
  2469. }
  2470. /* Initialize the large buffer queue. */
  2471. ql_init_large_buffers(qdev);
  2472. if (ql_create_send_free_list(qdev))
  2473. goto err_free_list;
  2474. qdev->rsp_current = qdev->rsp_q_virt_addr;
  2475. return 0;
  2476. err_free_list:
  2477. ql_free_send_free_list(qdev);
  2478. err_small_buffers:
  2479. ql_free_buffer_queues(qdev);
  2480. err_buffer_queues:
  2481. ql_free_net_req_rsp_queues(qdev);
  2482. err_req_rsp:
  2483. pci_free_consistent(qdev->pdev,
  2484. PAGE_SIZE,
  2485. qdev->shadow_reg_virt_addr,
  2486. qdev->shadow_reg_phy_addr);
  2487. return -ENOMEM;
  2488. }
  2489. static void ql_free_mem_resources(struct ql3_adapter *qdev)
  2490. {
  2491. ql_free_send_free_list(qdev);
  2492. ql_free_large_buffers(qdev);
  2493. ql_free_small_buffers(qdev);
  2494. ql_free_buffer_queues(qdev);
  2495. ql_free_net_req_rsp_queues(qdev);
  2496. if (qdev->shadow_reg_virt_addr != NULL) {
  2497. pci_free_consistent(qdev->pdev,
  2498. PAGE_SIZE,
  2499. qdev->shadow_reg_virt_addr,
  2500. qdev->shadow_reg_phy_addr);
  2501. qdev->shadow_reg_virt_addr = NULL;
  2502. }
  2503. }
  2504. static int ql_init_misc_registers(struct ql3_adapter *qdev)
  2505. {
  2506. struct ql3xxx_local_ram_registers __iomem *local_ram =
  2507. (void __iomem *)qdev->mem_map_registers;
  2508. if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
  2509. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  2510. 2) << 4))
  2511. return -1;
  2512. ql_write_page2_reg(qdev,
  2513. &local_ram->bufletSize, qdev->nvram_data.bufletSize);
  2514. ql_write_page2_reg(qdev,
  2515. &local_ram->maxBufletCount,
  2516. qdev->nvram_data.bufletCount);
  2517. ql_write_page2_reg(qdev,
  2518. &local_ram->freeBufletThresholdLow,
  2519. (qdev->nvram_data.tcpWindowThreshold25 << 16) |
  2520. (qdev->nvram_data.tcpWindowThreshold0));
  2521. ql_write_page2_reg(qdev,
  2522. &local_ram->freeBufletThresholdHigh,
  2523. qdev->nvram_data.tcpWindowThreshold50);
  2524. ql_write_page2_reg(qdev,
  2525. &local_ram->ipHashTableBase,
  2526. (qdev->nvram_data.ipHashTableBaseHi << 16) |
  2527. qdev->nvram_data.ipHashTableBaseLo);
  2528. ql_write_page2_reg(qdev,
  2529. &local_ram->ipHashTableCount,
  2530. qdev->nvram_data.ipHashTableSize);
  2531. ql_write_page2_reg(qdev,
  2532. &local_ram->tcpHashTableBase,
  2533. (qdev->nvram_data.tcpHashTableBaseHi << 16) |
  2534. qdev->nvram_data.tcpHashTableBaseLo);
  2535. ql_write_page2_reg(qdev,
  2536. &local_ram->tcpHashTableCount,
  2537. qdev->nvram_data.tcpHashTableSize);
  2538. ql_write_page2_reg(qdev,
  2539. &local_ram->ncbBase,
  2540. (qdev->nvram_data.ncbTableBaseHi << 16) |
  2541. qdev->nvram_data.ncbTableBaseLo);
  2542. ql_write_page2_reg(qdev,
  2543. &local_ram->maxNcbCount,
  2544. qdev->nvram_data.ncbTableSize);
  2545. ql_write_page2_reg(qdev,
  2546. &local_ram->drbBase,
  2547. (qdev->nvram_data.drbTableBaseHi << 16) |
  2548. qdev->nvram_data.drbTableBaseLo);
  2549. ql_write_page2_reg(qdev,
  2550. &local_ram->maxDrbCount,
  2551. qdev->nvram_data.drbTableSize);
  2552. ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
  2553. return 0;
  2554. }
  2555. static int ql_adapter_initialize(struct ql3_adapter *qdev)
  2556. {
  2557. u32 value;
  2558. struct ql3xxx_port_registers __iomem *port_regs =
  2559. qdev->mem_map_registers;
  2560. __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
  2561. struct ql3xxx_host_memory_registers __iomem *hmem_regs =
  2562. (void __iomem *)port_regs;
  2563. u32 delay = 10;
  2564. int status = 0;
  2565. unsigned long hw_flags = 0;
  2566. if (ql_mii_setup(qdev))
  2567. return -1;
  2568. /* Bring out PHY out of reset */
  2569. ql_write_common_reg(qdev, spir,
  2570. (ISP_SERIAL_PORT_IF_WE |
  2571. (ISP_SERIAL_PORT_IF_WE << 16)));
  2572. /* Give the PHY time to come out of reset. */
  2573. mdelay(100);
  2574. qdev->port_link_state = LS_DOWN;
  2575. netif_carrier_off(qdev->ndev);
  2576. /* V2 chip fix for ARS-39168. */
  2577. ql_write_common_reg(qdev, spir,
  2578. (ISP_SERIAL_PORT_IF_SDE |
  2579. (ISP_SERIAL_PORT_IF_SDE << 16)));
  2580. /* Request Queue Registers */
  2581. *((u32 *)(qdev->preq_consumer_index)) = 0;
  2582. atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
  2583. qdev->req_producer_index = 0;
  2584. ql_write_page1_reg(qdev,
  2585. &hmem_regs->reqConsumerIndexAddrHigh,
  2586. qdev->req_consumer_index_phy_addr_high);
  2587. ql_write_page1_reg(qdev,
  2588. &hmem_regs->reqConsumerIndexAddrLow,
  2589. qdev->req_consumer_index_phy_addr_low);
  2590. ql_write_page1_reg(qdev,
  2591. &hmem_regs->reqBaseAddrHigh,
  2592. MS_64BITS(qdev->req_q_phy_addr));
  2593. ql_write_page1_reg(qdev,
  2594. &hmem_regs->reqBaseAddrLow,
  2595. LS_64BITS(qdev->req_q_phy_addr));
  2596. ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
  2597. /* Response Queue Registers */
  2598. *((__le16 *) (qdev->prsp_producer_index)) = 0;
  2599. qdev->rsp_consumer_index = 0;
  2600. qdev->rsp_current = qdev->rsp_q_virt_addr;
  2601. ql_write_page1_reg(qdev,
  2602. &hmem_regs->rspProducerIndexAddrHigh,
  2603. qdev->rsp_producer_index_phy_addr_high);
  2604. ql_write_page1_reg(qdev,
  2605. &hmem_regs->rspProducerIndexAddrLow,
  2606. qdev->rsp_producer_index_phy_addr_low);
  2607. ql_write_page1_reg(qdev,
  2608. &hmem_regs->rspBaseAddrHigh,
  2609. MS_64BITS(qdev->rsp_q_phy_addr));
  2610. ql_write_page1_reg(qdev,
  2611. &hmem_regs->rspBaseAddrLow,
  2612. LS_64BITS(qdev->rsp_q_phy_addr));
  2613. ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
  2614. /* Large Buffer Queue */
  2615. ql_write_page1_reg(qdev,
  2616. &hmem_regs->rxLargeQBaseAddrHigh,
  2617. MS_64BITS(qdev->lrg_buf_q_phy_addr));
  2618. ql_write_page1_reg(qdev,
  2619. &hmem_regs->rxLargeQBaseAddrLow,
  2620. LS_64BITS(qdev->lrg_buf_q_phy_addr));
  2621. ql_write_page1_reg(qdev,
  2622. &hmem_regs->rxLargeQLength,
  2623. qdev->num_lbufq_entries);
  2624. ql_write_page1_reg(qdev,
  2625. &hmem_regs->rxLargeBufferLength,
  2626. qdev->lrg_buffer_len);
  2627. /* Small Buffer Queue */
  2628. ql_write_page1_reg(qdev,
  2629. &hmem_regs->rxSmallQBaseAddrHigh,
  2630. MS_64BITS(qdev->small_buf_q_phy_addr));
  2631. ql_write_page1_reg(qdev,
  2632. &hmem_regs->rxSmallQBaseAddrLow,
  2633. LS_64BITS(qdev->small_buf_q_phy_addr));
  2634. ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
  2635. ql_write_page1_reg(qdev,
  2636. &hmem_regs->rxSmallBufferLength,
  2637. QL_SMALL_BUFFER_SIZE);
  2638. qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
  2639. qdev->small_buf_release_cnt = 8;
  2640. qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
  2641. qdev->lrg_buf_release_cnt = 8;
  2642. qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
  2643. qdev->small_buf_index = 0;
  2644. qdev->lrg_buf_index = 0;
  2645. qdev->lrg_buf_free_count = 0;
  2646. qdev->lrg_buf_free_head = NULL;
  2647. qdev->lrg_buf_free_tail = NULL;
  2648. ql_write_common_reg(qdev,
  2649. &port_regs->CommonRegs.
  2650. rxSmallQProducerIndex,
  2651. qdev->small_buf_q_producer_index);
  2652. ql_write_common_reg(qdev,
  2653. &port_regs->CommonRegs.
  2654. rxLargeQProducerIndex,
  2655. qdev->lrg_buf_q_producer_index);
  2656. /*
  2657. * Find out if the chip has already been initialized. If it has, then
  2658. * we skip some of the initialization.
  2659. */
  2660. clear_bit(QL_LINK_MASTER, &qdev->flags);
  2661. value = ql_read_page0_reg(qdev, &port_regs->portStatus);
  2662. if ((value & PORT_STATUS_IC) == 0) {
  2663. /* Chip has not been configured yet, so let it rip. */
  2664. if (ql_init_misc_registers(qdev)) {
  2665. status = -1;
  2666. goto out;
  2667. }
  2668. value = qdev->nvram_data.tcpMaxWindowSize;
  2669. ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
  2670. value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
  2671. if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
  2672. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
  2673. * 2) << 13)) {
  2674. status = -1;
  2675. goto out;
  2676. }
  2677. ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
  2678. ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
  2679. (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
  2680. 16) | (INTERNAL_CHIP_SD |
  2681. INTERNAL_CHIP_WE)));
  2682. ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
  2683. }
  2684. if (qdev->mac_index)
  2685. ql_write_page0_reg(qdev,
  2686. &port_regs->mac1MaxFrameLengthReg,
  2687. qdev->max_frame_size);
  2688. else
  2689. ql_write_page0_reg(qdev,
  2690. &port_regs->mac0MaxFrameLengthReg,
  2691. qdev->max_frame_size);
  2692. if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  2693. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  2694. 2) << 7)) {
  2695. status = -1;
  2696. goto out;
  2697. }
  2698. PHY_Setup(qdev);
  2699. ql_init_scan_mode(qdev);
  2700. ql_get_phy_owner(qdev);
  2701. /* Load the MAC Configuration */
  2702. /* Program lower 32 bits of the MAC address */
  2703. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  2704. (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
  2705. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  2706. ((qdev->ndev->dev_addr[2] << 24)
  2707. | (qdev->ndev->dev_addr[3] << 16)
  2708. | (qdev->ndev->dev_addr[4] << 8)
  2709. | qdev->ndev->dev_addr[5]));
  2710. /* Program top 16 bits of the MAC address */
  2711. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  2712. ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
  2713. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  2714. ((qdev->ndev->dev_addr[0] << 8)
  2715. | qdev->ndev->dev_addr[1]));
  2716. /* Enable Primary MAC */
  2717. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  2718. ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
  2719. MAC_ADDR_INDIRECT_PTR_REG_PE));
  2720. /* Clear Primary and Secondary IP addresses */
  2721. ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
  2722. ((IP_ADDR_INDEX_REG_MASK << 16) |
  2723. (qdev->mac_index << 2)));
  2724. ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
  2725. ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
  2726. ((IP_ADDR_INDEX_REG_MASK << 16) |
  2727. ((qdev->mac_index << 2) + 1)));
  2728. ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
  2729. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  2730. /* Indicate Configuration Complete */
  2731. ql_write_page0_reg(qdev,
  2732. &port_regs->portControl,
  2733. ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
  2734. do {
  2735. value = ql_read_page0_reg(qdev, &port_regs->portStatus);
  2736. if (value & PORT_STATUS_IC)
  2737. break;
  2738. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2739. msleep(500);
  2740. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  2741. } while (--delay);
  2742. if (delay == 0) {
  2743. netdev_err(qdev->ndev, "Hw Initialization timeout\n");
  2744. status = -1;
  2745. goto out;
  2746. }
  2747. /* Enable Ethernet Function */
  2748. if (qdev->device_id == QL3032_DEVICE_ID) {
  2749. value =
  2750. (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
  2751. QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
  2752. QL3032_PORT_CONTROL_ET);
  2753. ql_write_page0_reg(qdev, &port_regs->functionControl,
  2754. ((value << 16) | value));
  2755. } else {
  2756. value =
  2757. (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
  2758. PORT_CONTROL_HH);
  2759. ql_write_page0_reg(qdev, &port_regs->portControl,
  2760. ((value << 16) | value));
  2761. }
  2762. out:
  2763. return status;
  2764. }
  2765. /*
  2766. * Caller holds hw_lock.
  2767. */
  2768. static int ql_adapter_reset(struct ql3_adapter *qdev)
  2769. {
  2770. struct ql3xxx_port_registers __iomem *port_regs =
  2771. qdev->mem_map_registers;
  2772. int status = 0;
  2773. u16 value;
  2774. int max_wait_time;
  2775. set_bit(QL_RESET_ACTIVE, &qdev->flags);
  2776. clear_bit(QL_RESET_DONE, &qdev->flags);
  2777. /*
  2778. * Issue soft reset to chip.
  2779. */
  2780. netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
  2781. ql_write_common_reg(qdev,
  2782. &port_regs->CommonRegs.ispControlStatus,
  2783. ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
  2784. /* Wait 3 seconds for reset to complete. */
  2785. netdev_printk(KERN_DEBUG, qdev->ndev,
  2786. "Wait 10 milliseconds for reset to complete\n");
  2787. /* Wait until the firmware tells us the Soft Reset is done */
  2788. max_wait_time = 5;
  2789. do {
  2790. value =
  2791. ql_read_common_reg(qdev,
  2792. &port_regs->CommonRegs.ispControlStatus);
  2793. if ((value & ISP_CONTROL_SR) == 0)
  2794. break;
  2795. ssleep(1);
  2796. } while ((--max_wait_time));
  2797. /*
  2798. * Also, make sure that the Network Reset Interrupt bit has been
  2799. * cleared after the soft reset has taken place.
  2800. */
  2801. value =
  2802. ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
  2803. if (value & ISP_CONTROL_RI) {
  2804. netdev_printk(KERN_DEBUG, qdev->ndev,
  2805. "clearing RI after reset\n");
  2806. ql_write_common_reg(qdev,
  2807. &port_regs->CommonRegs.
  2808. ispControlStatus,
  2809. ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
  2810. }
  2811. if (max_wait_time == 0) {
  2812. /* Issue Force Soft Reset */
  2813. ql_write_common_reg(qdev,
  2814. &port_regs->CommonRegs.
  2815. ispControlStatus,
  2816. ((ISP_CONTROL_FSR << 16) |
  2817. ISP_CONTROL_FSR));
  2818. /*
  2819. * Wait until the firmware tells us the Force Soft Reset is
  2820. * done
  2821. */
  2822. max_wait_time = 5;
  2823. do {
  2824. value = ql_read_common_reg(qdev,
  2825. &port_regs->CommonRegs.
  2826. ispControlStatus);
  2827. if ((value & ISP_CONTROL_FSR) == 0)
  2828. break;
  2829. ssleep(1);
  2830. } while ((--max_wait_time));
  2831. }
  2832. if (max_wait_time == 0)
  2833. status = 1;
  2834. clear_bit(QL_RESET_ACTIVE, &qdev->flags);
  2835. set_bit(QL_RESET_DONE, &qdev->flags);
  2836. return status;
  2837. }
  2838. static void ql_set_mac_info(struct ql3_adapter *qdev)
  2839. {
  2840. struct ql3xxx_port_registers __iomem *port_regs =
  2841. qdev->mem_map_registers;
  2842. u32 value, port_status;
  2843. u8 func_number;
  2844. /* Get the function number */
  2845. value =
  2846. ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
  2847. func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
  2848. port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
  2849. switch (value & ISP_CONTROL_FN_MASK) {
  2850. case ISP_CONTROL_FN0_NET:
  2851. qdev->mac_index = 0;
  2852. qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
  2853. qdev->mb_bit_mask = FN0_MA_BITS_MASK;
  2854. qdev->PHYAddr = PORT0_PHY_ADDRESS;
  2855. if (port_status & PORT_STATUS_SM0)
  2856. set_bit(QL_LINK_OPTICAL, &qdev->flags);
  2857. else
  2858. clear_bit(QL_LINK_OPTICAL, &qdev->flags);
  2859. break;
  2860. case ISP_CONTROL_FN1_NET:
  2861. qdev->mac_index = 1;
  2862. qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
  2863. qdev->mb_bit_mask = FN1_MA_BITS_MASK;
  2864. qdev->PHYAddr = PORT1_PHY_ADDRESS;
  2865. if (port_status & PORT_STATUS_SM1)
  2866. set_bit(QL_LINK_OPTICAL, &qdev->flags);
  2867. else
  2868. clear_bit(QL_LINK_OPTICAL, &qdev->flags);
  2869. break;
  2870. case ISP_CONTROL_FN0_SCSI:
  2871. case ISP_CONTROL_FN1_SCSI:
  2872. default:
  2873. netdev_printk(KERN_DEBUG, qdev->ndev,
  2874. "Invalid function number, ispControlStatus = 0x%x\n",
  2875. value);
  2876. break;
  2877. }
  2878. qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
  2879. }
  2880. static void ql_display_dev_info(struct net_device *ndev)
  2881. {
  2882. struct ql3_adapter *qdev = netdev_priv(ndev);
  2883. struct pci_dev *pdev = qdev->pdev;
  2884. netdev_info(ndev,
  2885. "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
  2886. DRV_NAME, qdev->index, qdev->chip_rev_id,
  2887. qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
  2888. qdev->pci_slot);
  2889. netdev_info(ndev, "%s Interface\n",
  2890. test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
  2891. /*
  2892. * Print PCI bus width/type.
  2893. */
  2894. netdev_info(ndev, "Bus interface is %s %s\n",
  2895. ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
  2896. ((qdev->pci_x) ? "PCI-X" : "PCI"));
  2897. netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
  2898. qdev->mem_map_registers);
  2899. netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
  2900. netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
  2901. }
  2902. static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
  2903. {
  2904. struct net_device *ndev = qdev->ndev;
  2905. int retval = 0;
  2906. netif_stop_queue(ndev);
  2907. netif_carrier_off(ndev);
  2908. clear_bit(QL_ADAPTER_UP, &qdev->flags);
  2909. clear_bit(QL_LINK_MASTER, &qdev->flags);
  2910. ql_disable_interrupts(qdev);
  2911. free_irq(qdev->pdev->irq, ndev);
  2912. if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
  2913. netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
  2914. clear_bit(QL_MSI_ENABLED, &qdev->flags);
  2915. pci_disable_msi(qdev->pdev);
  2916. }
  2917. del_timer_sync(&qdev->adapter_timer);
  2918. napi_disable(&qdev->napi);
  2919. if (do_reset) {
  2920. int soft_reset;
  2921. unsigned long hw_flags;
  2922. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  2923. if (ql_wait_for_drvr_lock(qdev)) {
  2924. soft_reset = ql_adapter_reset(qdev);
  2925. if (soft_reset) {
  2926. netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
  2927. qdev->index);
  2928. }
  2929. netdev_err(ndev,
  2930. "Releasing driver lock via chip reset\n");
  2931. } else {
  2932. netdev_err(ndev,
  2933. "Could not acquire driver lock to do reset!\n");
  2934. retval = -1;
  2935. }
  2936. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2937. }
  2938. ql_free_mem_resources(qdev);
  2939. return retval;
  2940. }
  2941. static int ql_adapter_up(struct ql3_adapter *qdev)
  2942. {
  2943. struct net_device *ndev = qdev->ndev;
  2944. int err;
  2945. unsigned long irq_flags = IRQF_SHARED;
  2946. unsigned long hw_flags;
  2947. if (ql_alloc_mem_resources(qdev)) {
  2948. netdev_err(ndev, "Unable to allocate buffers\n");
  2949. return -ENOMEM;
  2950. }
  2951. if (qdev->msi) {
  2952. if (pci_enable_msi(qdev->pdev)) {
  2953. netdev_err(ndev,
  2954. "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
  2955. qdev->msi = 0;
  2956. } else {
  2957. netdev_info(ndev, "MSI Enabled...\n");
  2958. set_bit(QL_MSI_ENABLED, &qdev->flags);
  2959. irq_flags &= ~IRQF_SHARED;
  2960. }
  2961. }
  2962. err = request_irq(qdev->pdev->irq, ql3xxx_isr,
  2963. irq_flags, ndev->name, ndev);
  2964. if (err) {
  2965. netdev_err(ndev,
  2966. "Failed to reserve interrupt %d - already in use\n",
  2967. qdev->pdev->irq);
  2968. goto err_irq;
  2969. }
  2970. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  2971. err = ql_wait_for_drvr_lock(qdev);
  2972. if (err) {
  2973. err = ql_adapter_initialize(qdev);
  2974. if (err) {
  2975. netdev_err(ndev, "Unable to initialize adapter\n");
  2976. goto err_init;
  2977. }
  2978. netdev_err(ndev, "Releasing driver lock\n");
  2979. ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
  2980. } else {
  2981. netdev_err(ndev, "Could not acquire driver lock\n");
  2982. goto err_lock;
  2983. }
  2984. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2985. set_bit(QL_ADAPTER_UP, &qdev->flags);
  2986. mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
  2987. napi_enable(&qdev->napi);
  2988. ql_enable_interrupts(qdev);
  2989. return 0;
  2990. err_init:
  2991. ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
  2992. err_lock:
  2993. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2994. free_irq(qdev->pdev->irq, ndev);
  2995. err_irq:
  2996. if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
  2997. netdev_info(ndev, "calling pci_disable_msi()\n");
  2998. clear_bit(QL_MSI_ENABLED, &qdev->flags);
  2999. pci_disable_msi(qdev->pdev);
  3000. }
  3001. return err;
  3002. }
  3003. static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
  3004. {
  3005. if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
  3006. netdev_err(qdev->ndev,
  3007. "Driver up/down cycle failed, closing device\n");
  3008. rtnl_lock();
  3009. dev_close(qdev->ndev);
  3010. rtnl_unlock();
  3011. return -1;
  3012. }
  3013. return 0;
  3014. }
  3015. static int ql3xxx_close(struct net_device *ndev)
  3016. {
  3017. struct ql3_adapter *qdev = netdev_priv(ndev);
  3018. /*
  3019. * Wait for device to recover from a reset.
  3020. * (Rarely happens, but possible.)
  3021. */
  3022. while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
  3023. msleep(50);
  3024. ql_adapter_down(qdev, QL_DO_RESET);
  3025. return 0;
  3026. }
  3027. static int ql3xxx_open(struct net_device *ndev)
  3028. {
  3029. struct ql3_adapter *qdev = netdev_priv(ndev);
  3030. return ql_adapter_up(qdev);
  3031. }
  3032. static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
  3033. {
  3034. struct ql3_adapter *qdev = netdev_priv(ndev);
  3035. struct ql3xxx_port_registers __iomem *port_regs =
  3036. qdev->mem_map_registers;
  3037. struct sockaddr *addr = p;
  3038. unsigned long hw_flags;
  3039. if (netif_running(ndev))
  3040. return -EBUSY;
  3041. if (!is_valid_ether_addr(addr->sa_data))
  3042. return -EADDRNOTAVAIL;
  3043. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  3044. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  3045. /* Program lower 32 bits of the MAC address */
  3046. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  3047. (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
  3048. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  3049. ((ndev->dev_addr[2] << 24) | (ndev->
  3050. dev_addr[3] << 16) |
  3051. (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
  3052. /* Program top 16 bits of the MAC address */
  3053. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  3054. ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
  3055. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  3056. ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
  3057. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  3058. return 0;
  3059. }
  3060. static void ql3xxx_tx_timeout(struct net_device *ndev)
  3061. {
  3062. struct ql3_adapter *qdev = netdev_priv(ndev);
  3063. netdev_err(ndev, "Resetting...\n");
  3064. /*
  3065. * Stop the queues, we've got a problem.
  3066. */
  3067. netif_stop_queue(ndev);
  3068. /*
  3069. * Wake up the worker to process this event.
  3070. */
  3071. queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
  3072. }
  3073. static void ql_reset_work(struct work_struct *work)
  3074. {
  3075. struct ql3_adapter *qdev =
  3076. container_of(work, struct ql3_adapter, reset_work.work);
  3077. struct net_device *ndev = qdev->ndev;
  3078. u32 value;
  3079. struct ql_tx_buf_cb *tx_cb;
  3080. int max_wait_time, i;
  3081. struct ql3xxx_port_registers __iomem *port_regs =
  3082. qdev->mem_map_registers;
  3083. unsigned long hw_flags;
  3084. if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
  3085. clear_bit(QL_LINK_MASTER, &qdev->flags);
  3086. /*
  3087. * Loop through the active list and return the skb.
  3088. */
  3089. for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
  3090. int j;
  3091. tx_cb = &qdev->tx_buf[i];
  3092. if (tx_cb->skb) {
  3093. netdev_printk(KERN_DEBUG, ndev,
  3094. "Freeing lost SKB\n");
  3095. pci_unmap_single(qdev->pdev,
  3096. dma_unmap_addr(&tx_cb->map[0],
  3097. mapaddr),
  3098. dma_unmap_len(&tx_cb->map[0], maplen),
  3099. PCI_DMA_TODEVICE);
  3100. for (j = 1; j < tx_cb->seg_count; j++) {
  3101. pci_unmap_page(qdev->pdev,
  3102. dma_unmap_addr(&tx_cb->map[j],
  3103. mapaddr),
  3104. dma_unmap_len(&tx_cb->map[j],
  3105. maplen),
  3106. PCI_DMA_TODEVICE);
  3107. }
  3108. dev_kfree_skb(tx_cb->skb);
  3109. tx_cb->skb = NULL;
  3110. }
  3111. }
  3112. netdev_err(ndev, "Clearing NRI after reset\n");
  3113. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  3114. ql_write_common_reg(qdev,
  3115. &port_regs->CommonRegs.
  3116. ispControlStatus,
  3117. ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
  3118. /*
  3119. * Wait the for Soft Reset to Complete.
  3120. */
  3121. max_wait_time = 10;
  3122. do {
  3123. value = ql_read_common_reg(qdev,
  3124. &port_regs->CommonRegs.
  3125. ispControlStatus);
  3126. if ((value & ISP_CONTROL_SR) == 0) {
  3127. netdev_printk(KERN_DEBUG, ndev,
  3128. "reset completed\n");
  3129. break;
  3130. }
  3131. if (value & ISP_CONTROL_RI) {
  3132. netdev_printk(KERN_DEBUG, ndev,
  3133. "clearing NRI after reset\n");
  3134. ql_write_common_reg(qdev,
  3135. &port_regs->
  3136. CommonRegs.
  3137. ispControlStatus,
  3138. ((ISP_CONTROL_RI <<
  3139. 16) | ISP_CONTROL_RI));
  3140. }
  3141. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  3142. ssleep(1);
  3143. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  3144. } while (--max_wait_time);
  3145. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  3146. if (value & ISP_CONTROL_SR) {
  3147. /*
  3148. * Set the reset flags and clear the board again.
  3149. * Nothing else to do...
  3150. */
  3151. netdev_err(ndev,
  3152. "Timed out waiting for reset to complete\n");
  3153. netdev_err(ndev, "Do a reset\n");
  3154. clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
  3155. clear_bit(QL_RESET_START, &qdev->flags);
  3156. ql_cycle_adapter(qdev, QL_DO_RESET);
  3157. return;
  3158. }
  3159. clear_bit(QL_RESET_ACTIVE, &qdev->flags);
  3160. clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
  3161. clear_bit(QL_RESET_START, &qdev->flags);
  3162. ql_cycle_adapter(qdev, QL_NO_RESET);
  3163. }
  3164. }
  3165. static void ql_tx_timeout_work(struct work_struct *work)
  3166. {
  3167. struct ql3_adapter *qdev =
  3168. container_of(work, struct ql3_adapter, tx_timeout_work.work);
  3169. ql_cycle_adapter(qdev, QL_DO_RESET);
  3170. }
  3171. static void ql_get_board_info(struct ql3_adapter *qdev)
  3172. {
  3173. struct ql3xxx_port_registers __iomem *port_regs =
  3174. qdev->mem_map_registers;
  3175. u32 value;
  3176. value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
  3177. qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
  3178. if (value & PORT_STATUS_64)
  3179. qdev->pci_width = 64;
  3180. else
  3181. qdev->pci_width = 32;
  3182. if (value & PORT_STATUS_X)
  3183. qdev->pci_x = 1;
  3184. else
  3185. qdev->pci_x = 0;
  3186. qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
  3187. }
  3188. static void ql3xxx_timer(unsigned long ptr)
  3189. {
  3190. struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
  3191. queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
  3192. }
  3193. static const struct net_device_ops ql3xxx_netdev_ops = {
  3194. .ndo_open = ql3xxx_open,
  3195. .ndo_start_xmit = ql3xxx_send,
  3196. .ndo_stop = ql3xxx_close,
  3197. .ndo_change_mtu = eth_change_mtu,
  3198. .ndo_validate_addr = eth_validate_addr,
  3199. .ndo_set_mac_address = ql3xxx_set_mac_address,
  3200. .ndo_tx_timeout = ql3xxx_tx_timeout,
  3201. };
  3202. static int __devinit ql3xxx_probe(struct pci_dev *pdev,
  3203. const struct pci_device_id *pci_entry)
  3204. {
  3205. struct net_device *ndev = NULL;
  3206. struct ql3_adapter *qdev = NULL;
  3207. static int cards_found;
  3208. int uninitialized_var(pci_using_dac), err;
  3209. err = pci_enable_device(pdev);
  3210. if (err) {
  3211. pr_err("%s cannot enable PCI device\n", pci_name(pdev));
  3212. goto err_out;
  3213. }
  3214. err = pci_request_regions(pdev, DRV_NAME);
  3215. if (err) {
  3216. pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
  3217. goto err_out_disable_pdev;
  3218. }
  3219. pci_set_master(pdev);
  3220. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  3221. pci_using_dac = 1;
  3222. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  3223. } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
  3224. pci_using_dac = 0;
  3225. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3226. }
  3227. if (err) {
  3228. pr_err("%s no usable DMA configuration\n", pci_name(pdev));
  3229. goto err_out_free_regions;
  3230. }
  3231. ndev = alloc_etherdev(sizeof(struct ql3_adapter));
  3232. if (!ndev) {
  3233. pr_err("%s could not alloc etherdev\n", pci_name(pdev));
  3234. err = -ENOMEM;
  3235. goto err_out_free_regions;
  3236. }
  3237. SET_NETDEV_DEV(ndev, &pdev->dev);
  3238. pci_set_drvdata(pdev, ndev);
  3239. qdev = netdev_priv(ndev);
  3240. qdev->index = cards_found;
  3241. qdev->ndev = ndev;
  3242. qdev->pdev = pdev;
  3243. qdev->device_id = pci_entry->device;
  3244. qdev->port_link_state = LS_DOWN;
  3245. if (msi)
  3246. qdev->msi = 1;
  3247. qdev->msg_enable = netif_msg_init(debug, default_msg);
  3248. if (pci_using_dac)
  3249. ndev->features |= NETIF_F_HIGHDMA;
  3250. if (qdev->device_id == QL3032_DEVICE_ID)
  3251. ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  3252. qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
  3253. if (!qdev->mem_map_registers) {
  3254. pr_err("%s: cannot map device registers\n", pci_name(pdev));
  3255. err = -EIO;
  3256. goto err_out_free_ndev;
  3257. }
  3258. spin_lock_init(&qdev->adapter_lock);
  3259. spin_lock_init(&qdev->hw_lock);
  3260. /* Set driver entry points */
  3261. ndev->netdev_ops = &ql3xxx_netdev_ops;
  3262. SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
  3263. ndev->watchdog_timeo = 5 * HZ;
  3264. netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
  3265. ndev->irq = pdev->irq;
  3266. /* make sure the EEPROM is good */
  3267. if (ql_get_nvram_params(qdev)) {
  3268. pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
  3269. __func__, qdev->index);
  3270. err = -EIO;
  3271. goto err_out_iounmap;
  3272. }
  3273. ql_set_mac_info(qdev);
  3274. /* Validate and set parameters */
  3275. if (qdev->mac_index) {
  3276. ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
  3277. ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
  3278. } else {
  3279. ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
  3280. ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
  3281. }
  3282. memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
  3283. ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
  3284. /* Record PCI bus information. */
  3285. ql_get_board_info(qdev);
  3286. /*
  3287. * Set the Maximum Memory Read Byte Count value. We do this to handle
  3288. * jumbo frames.
  3289. */
  3290. if (qdev->pci_x)
  3291. pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
  3292. err = register_netdev(ndev);
  3293. if (err) {
  3294. pr_err("%s: cannot register net device\n", pci_name(pdev));
  3295. goto err_out_iounmap;
  3296. }
  3297. /* we're going to reset, so assume we have no link for now */
  3298. netif_carrier_off(ndev);
  3299. netif_stop_queue(ndev);
  3300. qdev->workqueue = create_singlethread_workqueue(ndev->name);
  3301. INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
  3302. INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
  3303. INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
  3304. init_timer(&qdev->adapter_timer);
  3305. qdev->adapter_timer.function = ql3xxx_timer;
  3306. qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
  3307. qdev->adapter_timer.data = (unsigned long)qdev;
  3308. if (!cards_found) {
  3309. pr_alert("%s\n", DRV_STRING);
  3310. pr_alert("Driver name: %s, Version: %s\n",
  3311. DRV_NAME, DRV_VERSION);
  3312. }
  3313. ql_display_dev_info(ndev);
  3314. cards_found++;
  3315. return 0;
  3316. err_out_iounmap:
  3317. iounmap(qdev->mem_map_registers);
  3318. err_out_free_ndev:
  3319. free_netdev(ndev);
  3320. err_out_free_regions:
  3321. pci_release_regions(pdev);
  3322. err_out_disable_pdev:
  3323. pci_disable_device(pdev);
  3324. pci_set_drvdata(pdev, NULL);
  3325. err_out:
  3326. return err;
  3327. }
  3328. static void __devexit ql3xxx_remove(struct pci_dev *pdev)
  3329. {
  3330. struct net_device *ndev = pci_get_drvdata(pdev);
  3331. struct ql3_adapter *qdev = netdev_priv(ndev);
  3332. unregister_netdev(ndev);
  3333. ql_disable_interrupts(qdev);
  3334. if (qdev->workqueue) {
  3335. cancel_delayed_work(&qdev->reset_work);
  3336. cancel_delayed_work(&qdev->tx_timeout_work);
  3337. destroy_workqueue(qdev->workqueue);
  3338. qdev->workqueue = NULL;
  3339. }
  3340. iounmap(qdev->mem_map_registers);
  3341. pci_release_regions(pdev);
  3342. pci_set_drvdata(pdev, NULL);
  3343. free_netdev(ndev);
  3344. }
  3345. static struct pci_driver ql3xxx_driver = {
  3346. .name = DRV_NAME,
  3347. .id_table = ql3xxx_pci_tbl,
  3348. .probe = ql3xxx_probe,
  3349. .remove = __devexit_p(ql3xxx_remove),
  3350. };
  3351. static int __init ql3xxx_init_module(void)
  3352. {
  3353. return pci_register_driver(&ql3xxx_driver);
  3354. }
  3355. static void __exit ql3xxx_exit(void)
  3356. {
  3357. pci_unregister_driver(&ql3xxx_driver);
  3358. }
  3359. module_init(ql3xxx_init_module);
  3360. module_exit(ql3xxx_exit);