iwl3945-base.c 231 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-commands.h"
  47. #include "iwl-3945.h"
  48. #include "iwl-3945-fh.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-core.h"
  51. #include "iwl-dev.h"
  52. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  53. struct iwl3945_tx_queue *txq);
  54. /******************************************************************************
  55. *
  56. * module boiler plate
  57. *
  58. ******************************************************************************/
  59. /* module parameters */
  60. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  61. static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  62. static int iwl3945_param_disable; /* def: 0 = enable radio */
  63. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  64. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWL39_VERSION "1.2.26k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  83. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  84. #define DRV_VERSION IWL39_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  95. * DMA services
  96. *
  97. * Theory of operation
  98. *
  99. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  100. * of buffer descriptors, each of which points to one or more data buffers for
  101. * the device to read from or fill. Driver and device exchange status of each
  102. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  103. * entries in each circular buffer, to protect against confusing empty and full
  104. * queue states.
  105. *
  106. * The device reads or writes the data in the queues via the device's several
  107. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  108. *
  109. * For Tx queue, there are low mark and high mark limits. If, after queuing
  110. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  111. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  112. * Tx queue resumed.
  113. *
  114. * The 3945 operates with six queues: One receive queue, one transmit queue
  115. * (#4) for sending commands to the device firmware, and four transmit queues
  116. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  117. ***************************************************/
  118. int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
  119. {
  120. return q->write_ptr > q->read_ptr ?
  121. (i >= q->read_ptr && i < q->write_ptr) :
  122. !(i < q->read_ptr && i >= q->write_ptr);
  123. }
  124. /**
  125. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  126. */
  127. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl_queue *q,
  128. int count, int slots_num, u32 id)
  129. {
  130. q->n_bd = count;
  131. q->n_window = slots_num;
  132. q->id = id;
  133. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  134. * and iwl_queue_dec_wrap are broken. */
  135. BUG_ON(!is_power_of_2(count));
  136. /* slots_num must be power-of-two size, otherwise
  137. * get_cmd_index is broken. */
  138. BUG_ON(!is_power_of_2(slots_num));
  139. q->low_mark = q->n_window / 4;
  140. if (q->low_mark < 4)
  141. q->low_mark = 4;
  142. q->high_mark = q->n_window / 8;
  143. if (q->high_mark < 2)
  144. q->high_mark = 2;
  145. q->write_ptr = q->read_ptr = 0;
  146. return 0;
  147. }
  148. /**
  149. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  150. */
  151. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  152. struct iwl3945_tx_queue *txq, u32 id)
  153. {
  154. struct pci_dev *dev = priv->pci_dev;
  155. /* Driver private data, only for Tx (not command) queues,
  156. * not shared with device. */
  157. if (id != IWL_CMD_QUEUE_NUM) {
  158. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  159. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  160. if (!txq->txb) {
  161. IWL_ERROR("kmalloc for auxiliary BD "
  162. "structures failed\n");
  163. goto error;
  164. }
  165. } else
  166. txq->txb = NULL;
  167. /* Circular buffer of transmit frame descriptors (TFDs),
  168. * shared with device */
  169. txq->bd = pci_alloc_consistent(dev,
  170. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  171. &txq->q.dma_addr);
  172. if (!txq->bd) {
  173. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  174. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  175. goto error;
  176. }
  177. txq->q.id = id;
  178. return 0;
  179. error:
  180. kfree(txq->txb);
  181. txq->txb = NULL;
  182. return -ENOMEM;
  183. }
  184. /**
  185. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  186. */
  187. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  188. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  189. {
  190. struct pci_dev *dev = priv->pci_dev;
  191. int len;
  192. int rc = 0;
  193. /*
  194. * Alloc buffer array for commands (Tx or other types of commands).
  195. * For the command queue (#4), allocate command space + one big
  196. * command for scan, since scan command is very huge; the system will
  197. * not have two scans at the same time, so only one is needed.
  198. * For data Tx queues (all other queues), no super-size command
  199. * space is needed.
  200. */
  201. len = sizeof(struct iwl3945_cmd) * slots_num;
  202. if (txq_id == IWL_CMD_QUEUE_NUM)
  203. len += IWL_MAX_SCAN_SIZE;
  204. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  205. if (!txq->cmd)
  206. return -ENOMEM;
  207. /* Alloc driver data array and TFD circular buffer */
  208. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  209. if (rc) {
  210. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  211. return -ENOMEM;
  212. }
  213. txq->need_update = 0;
  214. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  215. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  216. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  217. /* Initialize queue high/low-water, head/tail indexes */
  218. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  219. /* Tell device where to find queue, enable DMA channel. */
  220. iwl3945_hw_tx_queue_init(priv, txq);
  221. return 0;
  222. }
  223. /**
  224. * iwl3945_tx_queue_free - Deallocate DMA queue.
  225. * @txq: Transmit queue to deallocate.
  226. *
  227. * Empty queue by removing and destroying all BD's.
  228. * Free all buffers.
  229. * 0-fill, but do not free "txq" descriptor structure.
  230. */
  231. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  232. {
  233. struct iwl_queue *q = &txq->q;
  234. struct pci_dev *dev = priv->pci_dev;
  235. int len;
  236. if (q->n_bd == 0)
  237. return;
  238. /* first, empty all BD's */
  239. for (; q->write_ptr != q->read_ptr;
  240. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  241. iwl3945_hw_txq_free_tfd(priv, txq);
  242. len = sizeof(struct iwl3945_cmd) * q->n_window;
  243. if (q->id == IWL_CMD_QUEUE_NUM)
  244. len += IWL_MAX_SCAN_SIZE;
  245. /* De-alloc array of command/tx buffers */
  246. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  247. /* De-alloc circular buffer of TFDs */
  248. if (txq->q.n_bd)
  249. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  250. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  251. /* De-alloc array of per-TFD driver data */
  252. kfree(txq->txb);
  253. txq->txb = NULL;
  254. /* 0-fill queue descriptor structure */
  255. memset(txq, 0, sizeof(*txq));
  256. }
  257. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  258. /*************** STATION TABLE MANAGEMENT ****
  259. * mac80211 should be examined to determine if sta_info is duplicating
  260. * the functionality provided here
  261. */
  262. /**************************************************************/
  263. #if 0 /* temporary disable till we add real remove station */
  264. /**
  265. * iwl3945_remove_station - Remove driver's knowledge of station.
  266. *
  267. * NOTE: This does not remove station from device's station table.
  268. */
  269. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  270. {
  271. int index = IWL_INVALID_STATION;
  272. int i;
  273. unsigned long flags;
  274. spin_lock_irqsave(&priv->sta_lock, flags);
  275. if (is_ap)
  276. index = IWL_AP_ID;
  277. else if (is_broadcast_ether_addr(addr))
  278. index = priv->hw_setting.bcast_sta_id;
  279. else
  280. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  281. if (priv->stations[i].used &&
  282. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  283. addr)) {
  284. index = i;
  285. break;
  286. }
  287. if (unlikely(index == IWL_INVALID_STATION))
  288. goto out;
  289. if (priv->stations[index].used) {
  290. priv->stations[index].used = 0;
  291. priv->num_stations--;
  292. }
  293. BUG_ON(priv->num_stations < 0);
  294. out:
  295. spin_unlock_irqrestore(&priv->sta_lock, flags);
  296. return 0;
  297. }
  298. #endif
  299. /**
  300. * iwl3945_clear_stations_table - Clear the driver's station table
  301. *
  302. * NOTE: This does not clear or otherwise alter the device's station table.
  303. */
  304. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  305. {
  306. unsigned long flags;
  307. spin_lock_irqsave(&priv->sta_lock, flags);
  308. priv->num_stations = 0;
  309. memset(priv->stations, 0, sizeof(priv->stations));
  310. spin_unlock_irqrestore(&priv->sta_lock, flags);
  311. }
  312. /**
  313. * iwl3945_add_station - Add station to station tables in driver and device
  314. */
  315. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  316. {
  317. int i;
  318. int index = IWL_INVALID_STATION;
  319. struct iwl3945_station_entry *station;
  320. unsigned long flags_spin;
  321. u8 rate;
  322. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  323. if (is_ap)
  324. index = IWL_AP_ID;
  325. else if (is_broadcast_ether_addr(addr))
  326. index = priv->hw_setting.bcast_sta_id;
  327. else
  328. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  329. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  330. addr)) {
  331. index = i;
  332. break;
  333. }
  334. if (!priv->stations[i].used &&
  335. index == IWL_INVALID_STATION)
  336. index = i;
  337. }
  338. /* These two conditions has the same outcome but keep them separate
  339. since they have different meaning */
  340. if (unlikely(index == IWL_INVALID_STATION)) {
  341. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  342. return index;
  343. }
  344. if (priv->stations[index].used &&
  345. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  346. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  347. return index;
  348. }
  349. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  350. station = &priv->stations[index];
  351. station->used = 1;
  352. priv->num_stations++;
  353. /* Set up the REPLY_ADD_STA command to send to device */
  354. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  355. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  356. station->sta.mode = 0;
  357. station->sta.sta.sta_id = index;
  358. station->sta.station_flags = 0;
  359. if (priv->band == IEEE80211_BAND_5GHZ)
  360. rate = IWL_RATE_6M_PLCP;
  361. else
  362. rate = IWL_RATE_1M_PLCP;
  363. /* Turn on both antennas for the station... */
  364. station->sta.rate_n_flags =
  365. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  366. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  367. /* Add station to device's station table */
  368. iwl3945_send_add_station(priv, &station->sta, flags);
  369. return index;
  370. }
  371. /*************** DRIVER STATUS FUNCTIONS *****/
  372. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  373. {
  374. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  375. * set but EXIT_PENDING is not */
  376. return test_bit(STATUS_READY, &priv->status) &&
  377. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  378. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  379. }
  380. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  381. {
  382. return test_bit(STATUS_ALIVE, &priv->status);
  383. }
  384. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  385. {
  386. return test_bit(STATUS_INIT, &priv->status);
  387. }
  388. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  389. {
  390. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  391. }
  392. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  393. {
  394. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  395. }
  396. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  397. {
  398. return iwl3945_is_rfkill_hw(priv) ||
  399. iwl3945_is_rfkill_sw(priv);
  400. }
  401. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  402. {
  403. if (iwl3945_is_rfkill(priv))
  404. return 0;
  405. return iwl3945_is_ready(priv);
  406. }
  407. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  408. #define IWL_CMD(x) case x: return #x
  409. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  410. /**
  411. * iwl3945_enqueue_hcmd - enqueue a uCode command
  412. * @priv: device private data point
  413. * @cmd: a point to the ucode command structure
  414. *
  415. * The function returns < 0 values to indicate the operation is
  416. * failed. On success, it turns the index (> 0) of command in the
  417. * command queue.
  418. */
  419. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  420. {
  421. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  422. struct iwl_queue *q = &txq->q;
  423. struct iwl3945_tfd_frame *tfd;
  424. u32 *control_flags;
  425. struct iwl3945_cmd *out_cmd;
  426. u32 idx;
  427. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  428. dma_addr_t phys_addr;
  429. int pad;
  430. u16 count;
  431. int ret;
  432. unsigned long flags;
  433. /* If any of the command structures end up being larger than
  434. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  435. * we will need to increase the size of the TFD entries */
  436. BUG_ON((fix_size > TFD39_MAX_PAYLOAD_SIZE) &&
  437. !(cmd->meta.flags & CMD_SIZE_HUGE));
  438. if (iwl3945_is_rfkill(priv)) {
  439. IWL_DEBUG_INFO("Not sending command - RF KILL");
  440. return -EIO;
  441. }
  442. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  443. IWL_ERROR("No space for Tx\n");
  444. return -ENOSPC;
  445. }
  446. spin_lock_irqsave(&priv->hcmd_lock, flags);
  447. tfd = &txq->bd[q->write_ptr];
  448. memset(tfd, 0, sizeof(*tfd));
  449. control_flags = (u32 *) tfd;
  450. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  451. out_cmd = &txq->cmd[idx];
  452. out_cmd->hdr.cmd = cmd->id;
  453. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  454. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  455. /* At this point, the out_cmd now has all of the incoming cmd
  456. * information */
  457. out_cmd->hdr.flags = 0;
  458. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  459. INDEX_TO_SEQ(q->write_ptr));
  460. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  461. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  462. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  463. offsetof(struct iwl3945_cmd, hdr);
  464. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  465. pad = U32_PAD(cmd->len);
  466. count = TFD_CTL_COUNT_GET(*control_flags);
  467. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  468. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  469. "%d bytes at %d[%d]:%d\n",
  470. get_cmd_string(out_cmd->hdr.cmd),
  471. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  472. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  473. txq->need_update = 1;
  474. /* Increment and update queue's write index */
  475. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  476. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  477. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  478. return ret ? ret : idx;
  479. }
  480. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  481. {
  482. int ret;
  483. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  484. /* An asynchronous command can not expect an SKB to be set. */
  485. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  486. /* An asynchronous command MUST have a callback. */
  487. BUG_ON(!cmd->meta.u.callback);
  488. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  489. return -EBUSY;
  490. ret = iwl3945_enqueue_hcmd(priv, cmd);
  491. if (ret < 0) {
  492. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  493. get_cmd_string(cmd->id), ret);
  494. return ret;
  495. }
  496. return 0;
  497. }
  498. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  499. {
  500. int cmd_idx;
  501. int ret;
  502. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  503. /* A synchronous command can not have a callback set. */
  504. BUG_ON(cmd->meta.u.callback != NULL);
  505. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  506. IWL_ERROR("Error sending %s: Already sending a host command\n",
  507. get_cmd_string(cmd->id));
  508. ret = -EBUSY;
  509. goto out;
  510. }
  511. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  512. if (cmd->meta.flags & CMD_WANT_SKB)
  513. cmd->meta.source = &cmd->meta;
  514. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  515. if (cmd_idx < 0) {
  516. ret = cmd_idx;
  517. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  518. get_cmd_string(cmd->id), ret);
  519. goto out;
  520. }
  521. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  522. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  523. HOST_COMPLETE_TIMEOUT);
  524. if (!ret) {
  525. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  526. IWL_ERROR("Error sending %s: time out after %dms.\n",
  527. get_cmd_string(cmd->id),
  528. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  529. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  530. ret = -ETIMEDOUT;
  531. goto cancel;
  532. }
  533. }
  534. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  535. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  536. get_cmd_string(cmd->id));
  537. ret = -ECANCELED;
  538. goto fail;
  539. }
  540. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  541. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  542. get_cmd_string(cmd->id));
  543. ret = -EIO;
  544. goto fail;
  545. }
  546. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  547. IWL_ERROR("Error: Response NULL in '%s'\n",
  548. get_cmd_string(cmd->id));
  549. ret = -EIO;
  550. goto cancel;
  551. }
  552. ret = 0;
  553. goto out;
  554. cancel:
  555. if (cmd->meta.flags & CMD_WANT_SKB) {
  556. struct iwl3945_cmd *qcmd;
  557. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  558. * TX cmd queue. Otherwise in case the cmd comes
  559. * in later, it will possibly set an invalid
  560. * address (cmd->meta.source). */
  561. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  562. qcmd->meta.flags &= ~CMD_WANT_SKB;
  563. }
  564. fail:
  565. if (cmd->meta.u.skb) {
  566. dev_kfree_skb_any(cmd->meta.u.skb);
  567. cmd->meta.u.skb = NULL;
  568. }
  569. out:
  570. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  571. return ret;
  572. }
  573. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  574. {
  575. if (cmd->meta.flags & CMD_ASYNC)
  576. return iwl3945_send_cmd_async(priv, cmd);
  577. return iwl3945_send_cmd_sync(priv, cmd);
  578. }
  579. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  580. {
  581. struct iwl3945_host_cmd cmd = {
  582. .id = id,
  583. .len = len,
  584. .data = data,
  585. };
  586. return iwl3945_send_cmd_sync(priv, &cmd);
  587. }
  588. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  589. {
  590. struct iwl3945_host_cmd cmd = {
  591. .id = id,
  592. .len = sizeof(val),
  593. .data = &val,
  594. };
  595. return iwl3945_send_cmd_sync(priv, &cmd);
  596. }
  597. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  598. {
  599. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  600. }
  601. /**
  602. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  603. * @band: 2.4 or 5 GHz band
  604. * @channel: Any channel valid for the requested band
  605. * In addition to setting the staging RXON, priv->band is also set.
  606. *
  607. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  608. * in the staging RXON flag structure based on the band
  609. */
  610. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  611. enum ieee80211_band band,
  612. u16 channel)
  613. {
  614. if (!iwl3945_get_channel_info(priv, band, channel)) {
  615. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  616. channel, band);
  617. return -EINVAL;
  618. }
  619. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  620. (priv->band == band))
  621. return 0;
  622. priv->staging_rxon.channel = cpu_to_le16(channel);
  623. if (band == IEEE80211_BAND_5GHZ)
  624. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  625. else
  626. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  627. priv->band = band;
  628. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  629. return 0;
  630. }
  631. /**
  632. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  633. *
  634. * NOTE: This is really only useful during development and can eventually
  635. * be #ifdef'd out once the driver is stable and folks aren't actively
  636. * making changes
  637. */
  638. static int iwl3945_check_rxon_cmd(struct iwl3945_priv *priv)
  639. {
  640. int error = 0;
  641. int counter = 1;
  642. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  643. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  644. error |= le32_to_cpu(rxon->flags &
  645. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  646. RXON_FLG_RADAR_DETECT_MSK));
  647. if (error)
  648. IWL_WARNING("check 24G fields %d | %d\n",
  649. counter++, error);
  650. } else {
  651. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  652. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  653. if (error)
  654. IWL_WARNING("check 52 fields %d | %d\n",
  655. counter++, error);
  656. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  657. if (error)
  658. IWL_WARNING("check 52 CCK %d | %d\n",
  659. counter++, error);
  660. }
  661. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  662. if (error)
  663. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  664. /* make sure basic rates 6Mbps and 1Mbps are supported */
  665. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  666. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  667. if (error)
  668. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  669. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  670. if (error)
  671. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  672. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  673. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  674. if (error)
  675. IWL_WARNING("check CCK and short slot %d | %d\n",
  676. counter++, error);
  677. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  678. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  679. if (error)
  680. IWL_WARNING("check CCK & auto detect %d | %d\n",
  681. counter++, error);
  682. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  683. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  684. if (error)
  685. IWL_WARNING("check TGG and auto detect %d | %d\n",
  686. counter++, error);
  687. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  688. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  689. RXON_FLG_ANT_A_MSK)) == 0);
  690. if (error)
  691. IWL_WARNING("check antenna %d %d\n", counter++, error);
  692. if (error)
  693. IWL_WARNING("Tuning to channel %d\n",
  694. le16_to_cpu(rxon->channel));
  695. if (error) {
  696. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  697. return -1;
  698. }
  699. return 0;
  700. }
  701. /**
  702. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  703. * @priv: staging_rxon is compared to active_rxon
  704. *
  705. * If the RXON structure is changing enough to require a new tune,
  706. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  707. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  708. */
  709. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  710. {
  711. /* These items are only settable from the full RXON command */
  712. if (!(iwl3945_is_associated(priv)) ||
  713. compare_ether_addr(priv->staging_rxon.bssid_addr,
  714. priv->active_rxon.bssid_addr) ||
  715. compare_ether_addr(priv->staging_rxon.node_addr,
  716. priv->active_rxon.node_addr) ||
  717. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  718. priv->active_rxon.wlap_bssid_addr) ||
  719. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  720. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  721. (priv->staging_rxon.air_propagation !=
  722. priv->active_rxon.air_propagation) ||
  723. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  724. return 1;
  725. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  726. * be updated with the RXON_ASSOC command -- however only some
  727. * flag transitions are allowed using RXON_ASSOC */
  728. /* Check if we are not switching bands */
  729. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  730. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  731. return 1;
  732. /* Check if we are switching association toggle */
  733. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  734. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  735. return 1;
  736. return 0;
  737. }
  738. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  739. {
  740. int rc = 0;
  741. struct iwl_rx_packet *res = NULL;
  742. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  743. struct iwl3945_host_cmd cmd = {
  744. .id = REPLY_RXON_ASSOC,
  745. .len = sizeof(rxon_assoc),
  746. .meta.flags = CMD_WANT_SKB,
  747. .data = &rxon_assoc,
  748. };
  749. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  750. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  751. if ((rxon1->flags == rxon2->flags) &&
  752. (rxon1->filter_flags == rxon2->filter_flags) &&
  753. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  754. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  755. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  756. return 0;
  757. }
  758. rxon_assoc.flags = priv->staging_rxon.flags;
  759. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  760. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  761. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  762. rxon_assoc.reserved = 0;
  763. rc = iwl3945_send_cmd_sync(priv, &cmd);
  764. if (rc)
  765. return rc;
  766. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  767. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  768. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  769. rc = -EIO;
  770. }
  771. priv->alloc_rxb_skb--;
  772. dev_kfree_skb_any(cmd.meta.u.skb);
  773. return rc;
  774. }
  775. /**
  776. * iwl3945_commit_rxon - commit staging_rxon to hardware
  777. *
  778. * The RXON command in staging_rxon is committed to the hardware and
  779. * the active_rxon structure is updated with the new data. This
  780. * function correctly transitions out of the RXON_ASSOC_MSK state if
  781. * a HW tune is required based on the RXON structure changes.
  782. */
  783. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  784. {
  785. /* cast away the const for active_rxon in this function */
  786. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  787. int rc = 0;
  788. if (!iwl3945_is_alive(priv))
  789. return -1;
  790. /* always get timestamp with Rx frame */
  791. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  792. /* select antenna */
  793. priv->staging_rxon.flags &=
  794. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  795. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  796. rc = iwl3945_check_rxon_cmd(priv);
  797. if (rc) {
  798. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  799. return -EINVAL;
  800. }
  801. /* If we don't need to send a full RXON, we can use
  802. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  803. * and other flags for the current radio configuration. */
  804. if (!iwl3945_full_rxon_required(priv)) {
  805. rc = iwl3945_send_rxon_assoc(priv);
  806. if (rc) {
  807. IWL_ERROR("Error setting RXON_ASSOC "
  808. "configuration (%d).\n", rc);
  809. return rc;
  810. }
  811. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  812. return 0;
  813. }
  814. /* If we are currently associated and the new config requires
  815. * an RXON_ASSOC and the new config wants the associated mask enabled,
  816. * we must clear the associated from the active configuration
  817. * before we apply the new config */
  818. if (iwl3945_is_associated(priv) &&
  819. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  820. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  821. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  822. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  823. sizeof(struct iwl3945_rxon_cmd),
  824. &priv->active_rxon);
  825. /* If the mask clearing failed then we set
  826. * active_rxon back to what it was previously */
  827. if (rc) {
  828. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  829. IWL_ERROR("Error clearing ASSOC_MSK on current "
  830. "configuration (%d).\n", rc);
  831. return rc;
  832. }
  833. }
  834. IWL_DEBUG_INFO("Sending RXON\n"
  835. "* with%s RXON_FILTER_ASSOC_MSK\n"
  836. "* channel = %d\n"
  837. "* bssid = %pM\n",
  838. ((priv->staging_rxon.filter_flags &
  839. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  840. le16_to_cpu(priv->staging_rxon.channel),
  841. priv->staging_rxon.bssid_addr);
  842. /* Apply the new configuration */
  843. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  844. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  845. if (rc) {
  846. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  847. return rc;
  848. }
  849. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  850. iwl3945_clear_stations_table(priv);
  851. /* If we issue a new RXON command which required a tune then we must
  852. * send a new TXPOWER command or we won't be able to Tx any frames */
  853. rc = iwl3945_hw_reg_send_txpower(priv);
  854. if (rc) {
  855. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  856. return rc;
  857. }
  858. /* Add the broadcast address so we can send broadcast frames */
  859. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  860. IWL_INVALID_STATION) {
  861. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  862. return -EIO;
  863. }
  864. /* If we have set the ASSOC_MSK and we are in BSS mode then
  865. * add the IWL_AP_ID to the station rate table */
  866. if (iwl3945_is_associated(priv) &&
  867. (priv->iw_mode == NL80211_IFTYPE_STATION))
  868. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  869. == IWL_INVALID_STATION) {
  870. IWL_ERROR("Error adding AP address for transmit.\n");
  871. return -EIO;
  872. }
  873. /* Init the hardware's rate fallback order based on the band */
  874. rc = iwl3945_init_hw_rate_table(priv);
  875. if (rc) {
  876. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  877. return -EIO;
  878. }
  879. return 0;
  880. }
  881. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  882. {
  883. struct iwl_bt_cmd bt_cmd = {
  884. .flags = 3,
  885. .lead_time = 0xAA,
  886. .max_kill = 1,
  887. .kill_ack_mask = 0,
  888. .kill_cts_mask = 0,
  889. };
  890. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  891. sizeof(bt_cmd), &bt_cmd);
  892. }
  893. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  894. {
  895. int rc = 0;
  896. struct iwl_rx_packet *res;
  897. struct iwl3945_host_cmd cmd = {
  898. .id = REPLY_SCAN_ABORT_CMD,
  899. .meta.flags = CMD_WANT_SKB,
  900. };
  901. /* If there isn't a scan actively going on in the hardware
  902. * then we are in between scan bands and not actually
  903. * actively scanning, so don't send the abort command */
  904. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  905. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  906. return 0;
  907. }
  908. rc = iwl3945_send_cmd_sync(priv, &cmd);
  909. if (rc) {
  910. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  911. return rc;
  912. }
  913. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  914. if (res->u.status != CAN_ABORT_STATUS) {
  915. /* The scan abort will return 1 for success or
  916. * 2 for "failure". A failure condition can be
  917. * due to simply not being in an active scan which
  918. * can occur if we send the scan abort before we
  919. * the microcode has notified us that a scan is
  920. * completed. */
  921. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  922. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  923. clear_bit(STATUS_SCAN_HW, &priv->status);
  924. }
  925. dev_kfree_skb_any(cmd.meta.u.skb);
  926. return rc;
  927. }
  928. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  929. struct iwl3945_cmd *cmd,
  930. struct sk_buff *skb)
  931. {
  932. return 1;
  933. }
  934. /*
  935. * CARD_STATE_CMD
  936. *
  937. * Use: Sets the device's internal card state to enable, disable, or halt
  938. *
  939. * When in the 'enable' state the card operates as normal.
  940. * When in the 'disable' state, the card enters into a low power mode.
  941. * When in the 'halt' state, the card is shut down and must be fully
  942. * restarted to come back on.
  943. */
  944. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  945. {
  946. struct iwl3945_host_cmd cmd = {
  947. .id = REPLY_CARD_STATE_CMD,
  948. .len = sizeof(u32),
  949. .data = &flags,
  950. .meta.flags = meta_flag,
  951. };
  952. if (meta_flag & CMD_ASYNC)
  953. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  954. return iwl3945_send_cmd(priv, &cmd);
  955. }
  956. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  957. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  958. {
  959. struct iwl_rx_packet *res = NULL;
  960. if (!skb) {
  961. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  962. return 1;
  963. }
  964. res = (struct iwl_rx_packet *)skb->data;
  965. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  966. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  967. res->hdr.flags);
  968. return 1;
  969. }
  970. switch (res->u.add_sta.status) {
  971. case ADD_STA_SUCCESS_MSK:
  972. break;
  973. default:
  974. break;
  975. }
  976. /* We didn't cache the SKB; let the caller free it */
  977. return 1;
  978. }
  979. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  980. struct iwl3945_addsta_cmd *sta, u8 flags)
  981. {
  982. struct iwl_rx_packet *res = NULL;
  983. int rc = 0;
  984. struct iwl3945_host_cmd cmd = {
  985. .id = REPLY_ADD_STA,
  986. .len = sizeof(struct iwl3945_addsta_cmd),
  987. .meta.flags = flags,
  988. .data = sta,
  989. };
  990. if (flags & CMD_ASYNC)
  991. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  992. else
  993. cmd.meta.flags |= CMD_WANT_SKB;
  994. rc = iwl3945_send_cmd(priv, &cmd);
  995. if (rc || (flags & CMD_ASYNC))
  996. return rc;
  997. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  998. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  999. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1000. res->hdr.flags);
  1001. rc = -EIO;
  1002. }
  1003. if (rc == 0) {
  1004. switch (res->u.add_sta.status) {
  1005. case ADD_STA_SUCCESS_MSK:
  1006. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1007. break;
  1008. default:
  1009. rc = -EIO;
  1010. IWL_WARNING("REPLY_ADD_STA failed\n");
  1011. break;
  1012. }
  1013. }
  1014. priv->alloc_rxb_skb--;
  1015. dev_kfree_skb_any(cmd.meta.u.skb);
  1016. return rc;
  1017. }
  1018. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1019. struct ieee80211_key_conf *keyconf,
  1020. u8 sta_id)
  1021. {
  1022. unsigned long flags;
  1023. __le16 key_flags = 0;
  1024. switch (keyconf->alg) {
  1025. case ALG_CCMP:
  1026. key_flags |= STA_KEY_FLG_CCMP;
  1027. key_flags |= cpu_to_le16(
  1028. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1029. key_flags &= ~STA_KEY_FLG_INVALID;
  1030. break;
  1031. case ALG_TKIP:
  1032. case ALG_WEP:
  1033. default:
  1034. return -EINVAL;
  1035. }
  1036. spin_lock_irqsave(&priv->sta_lock, flags);
  1037. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1038. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1039. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1040. keyconf->keylen);
  1041. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1042. keyconf->keylen);
  1043. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1044. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1045. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1046. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1047. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1048. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1049. return 0;
  1050. }
  1051. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1052. {
  1053. unsigned long flags;
  1054. spin_lock_irqsave(&priv->sta_lock, flags);
  1055. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1056. memset(&priv->stations[sta_id].sta.key, 0,
  1057. sizeof(struct iwl4965_keyinfo));
  1058. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1059. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1060. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1061. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1062. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1063. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1064. return 0;
  1065. }
  1066. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1067. {
  1068. struct list_head *element;
  1069. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1070. priv->frames_count);
  1071. while (!list_empty(&priv->free_frames)) {
  1072. element = priv->free_frames.next;
  1073. list_del(element);
  1074. kfree(list_entry(element, struct iwl3945_frame, list));
  1075. priv->frames_count--;
  1076. }
  1077. if (priv->frames_count) {
  1078. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1079. priv->frames_count);
  1080. priv->frames_count = 0;
  1081. }
  1082. }
  1083. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1084. {
  1085. struct iwl3945_frame *frame;
  1086. struct list_head *element;
  1087. if (list_empty(&priv->free_frames)) {
  1088. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1089. if (!frame) {
  1090. IWL_ERROR("Could not allocate frame!\n");
  1091. return NULL;
  1092. }
  1093. priv->frames_count++;
  1094. return frame;
  1095. }
  1096. element = priv->free_frames.next;
  1097. list_del(element);
  1098. return list_entry(element, struct iwl3945_frame, list);
  1099. }
  1100. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1101. {
  1102. memset(frame, 0, sizeof(*frame));
  1103. list_add(&frame->list, &priv->free_frames);
  1104. }
  1105. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1106. struct ieee80211_hdr *hdr,
  1107. int left)
  1108. {
  1109. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1110. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1111. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1112. return 0;
  1113. if (priv->ibss_beacon->len > left)
  1114. return 0;
  1115. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1116. return priv->ibss_beacon->len;
  1117. }
  1118. static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
  1119. {
  1120. u8 i;
  1121. int rate_mask;
  1122. /* Set rate mask*/
  1123. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1124. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1125. else
  1126. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1127. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1128. i = iwl3945_rates[i].next_ieee) {
  1129. if (rate_mask & (1 << i))
  1130. return iwl3945_rates[i].plcp;
  1131. }
  1132. /* No valid rate was found. Assign the lowest one */
  1133. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1134. return IWL_RATE_1M_PLCP;
  1135. else
  1136. return IWL_RATE_6M_PLCP;
  1137. }
  1138. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1139. {
  1140. struct iwl3945_frame *frame;
  1141. unsigned int frame_size;
  1142. int rc;
  1143. u8 rate;
  1144. frame = iwl3945_get_free_frame(priv);
  1145. if (!frame) {
  1146. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1147. "command.\n");
  1148. return -ENOMEM;
  1149. }
  1150. rate = iwl3945_rate_get_lowest_plcp(priv);
  1151. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1152. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1153. &frame->u.cmd[0]);
  1154. iwl3945_free_frame(priv, frame);
  1155. return rc;
  1156. }
  1157. /******************************************************************************
  1158. *
  1159. * EEPROM related functions
  1160. *
  1161. ******************************************************************************/
  1162. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1163. {
  1164. memcpy(mac, priv->eeprom.mac_address, 6);
  1165. }
  1166. /*
  1167. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1168. * embedded controller) as EEPROM reader; each read is a series of pulses
  1169. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1170. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1171. * simply claims ownership, which should be safe when this function is called
  1172. * (i.e. before loading uCode!).
  1173. */
  1174. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1175. {
  1176. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1177. return 0;
  1178. }
  1179. /**
  1180. * iwl3945_eeprom_init - read EEPROM contents
  1181. *
  1182. * Load the EEPROM contents from adapter into priv->eeprom
  1183. *
  1184. * NOTE: This routine uses the non-debug IO access functions.
  1185. */
  1186. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1187. {
  1188. u16 *e = (u16 *)&priv->eeprom;
  1189. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1190. int sz = sizeof(priv->eeprom);
  1191. int ret;
  1192. u16 addr;
  1193. /* The EEPROM structure has several padding buffers within it
  1194. * and when adding new EEPROM maps is subject to programmer errors
  1195. * which may be very difficult to identify without explicitly
  1196. * checking the resulting size of the eeprom map. */
  1197. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1198. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1199. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1200. return -ENOENT;
  1201. }
  1202. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1203. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1204. if (ret < 0) {
  1205. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1206. return -ENOENT;
  1207. }
  1208. /* eeprom is an array of 16bit values */
  1209. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1210. u32 r;
  1211. _iwl3945_write32(priv, CSR_EEPROM_REG,
  1212. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1213. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1214. ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
  1215. CSR_EEPROM_REG_READ_VALID_MSK,
  1216. IWL_EEPROM_ACCESS_TIMEOUT);
  1217. if (ret < 0) {
  1218. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1219. return ret;
  1220. }
  1221. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1222. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1223. }
  1224. return 0;
  1225. }
  1226. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1227. {
  1228. if (priv->hw_setting.shared_virt)
  1229. pci_free_consistent(priv->pci_dev,
  1230. sizeof(struct iwl3945_shared),
  1231. priv->hw_setting.shared_virt,
  1232. priv->hw_setting.shared_phys);
  1233. }
  1234. /**
  1235. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1236. *
  1237. * return : set the bit for each supported rate insert in ie
  1238. */
  1239. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1240. u16 basic_rate, int *left)
  1241. {
  1242. u16 ret_rates = 0, bit;
  1243. int i;
  1244. u8 *cnt = ie;
  1245. u8 *rates = ie + 1;
  1246. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1247. if (bit & supported_rate) {
  1248. ret_rates |= bit;
  1249. rates[*cnt] = iwl3945_rates[i].ieee |
  1250. ((bit & basic_rate) ? 0x80 : 0x00);
  1251. (*cnt)++;
  1252. (*left)--;
  1253. if ((*left <= 0) ||
  1254. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1255. break;
  1256. }
  1257. }
  1258. return ret_rates;
  1259. }
  1260. /**
  1261. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1262. */
  1263. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1264. struct ieee80211_mgmt *frame,
  1265. int left)
  1266. {
  1267. int len = 0;
  1268. u8 *pos = NULL;
  1269. u16 active_rates, ret_rates, cck_rates;
  1270. /* Make sure there is enough space for the probe request,
  1271. * two mandatory IEs and the data */
  1272. left -= 24;
  1273. if (left < 0)
  1274. return 0;
  1275. len += 24;
  1276. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1277. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1278. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1279. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1280. frame->seq_ctrl = 0;
  1281. /* fill in our indirect SSID IE */
  1282. /* ...next IE... */
  1283. left -= 2;
  1284. if (left < 0)
  1285. return 0;
  1286. len += 2;
  1287. pos = &(frame->u.probe_req.variable[0]);
  1288. *pos++ = WLAN_EID_SSID;
  1289. *pos++ = 0;
  1290. /* fill in supported rate */
  1291. /* ...next IE... */
  1292. left -= 2;
  1293. if (left < 0)
  1294. return 0;
  1295. /* ... fill it in... */
  1296. *pos++ = WLAN_EID_SUPP_RATES;
  1297. *pos = 0;
  1298. priv->active_rate = priv->rates_mask;
  1299. active_rates = priv->active_rate;
  1300. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1301. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1302. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1303. priv->active_rate_basic, &left);
  1304. active_rates &= ~ret_rates;
  1305. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1306. priv->active_rate_basic, &left);
  1307. active_rates &= ~ret_rates;
  1308. len += 2 + *pos;
  1309. pos += (*pos) + 1;
  1310. if (active_rates == 0)
  1311. goto fill_end;
  1312. /* fill in supported extended rate */
  1313. /* ...next IE... */
  1314. left -= 2;
  1315. if (left < 0)
  1316. return 0;
  1317. /* ... fill it in... */
  1318. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1319. *pos = 0;
  1320. iwl3945_supported_rate_to_ie(pos, active_rates,
  1321. priv->active_rate_basic, &left);
  1322. if (*pos > 0)
  1323. len += 2 + *pos;
  1324. fill_end:
  1325. return (u16)len;
  1326. }
  1327. /*
  1328. * QoS support
  1329. */
  1330. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1331. struct iwl_qosparam_cmd *qos)
  1332. {
  1333. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1334. sizeof(struct iwl_qosparam_cmd), qos);
  1335. }
  1336. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1337. {
  1338. u16 cw_min = 15;
  1339. u16 cw_max = 1023;
  1340. u8 aifs = 2;
  1341. u8 is_legacy = 0;
  1342. unsigned long flags;
  1343. int i;
  1344. spin_lock_irqsave(&priv->lock, flags);
  1345. priv->qos_data.qos_active = 0;
  1346. /* QoS always active in AP and ADHOC mode
  1347. * In STA mode wait for association
  1348. */
  1349. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1350. priv->iw_mode == NL80211_IFTYPE_AP)
  1351. priv->qos_data.qos_active = 1;
  1352. else
  1353. priv->qos_data.qos_active = 0;
  1354. /* check for legacy mode */
  1355. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  1356. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  1357. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  1358. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  1359. cw_min = 31;
  1360. is_legacy = 1;
  1361. }
  1362. if (priv->qos_data.qos_active)
  1363. aifs = 3;
  1364. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1365. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1366. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1367. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1368. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1369. if (priv->qos_data.qos_active) {
  1370. i = 1;
  1371. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1372. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1373. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1374. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1375. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1376. i = 2;
  1377. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1378. cpu_to_le16((cw_min + 1) / 2 - 1);
  1379. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1380. cpu_to_le16(cw_max);
  1381. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1382. if (is_legacy)
  1383. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1384. cpu_to_le16(6016);
  1385. else
  1386. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1387. cpu_to_le16(3008);
  1388. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1389. i = 3;
  1390. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1391. cpu_to_le16((cw_min + 1) / 4 - 1);
  1392. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1393. cpu_to_le16((cw_max + 1) / 2 - 1);
  1394. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1395. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1396. if (is_legacy)
  1397. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1398. cpu_to_le16(3264);
  1399. else
  1400. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1401. cpu_to_le16(1504);
  1402. } else {
  1403. for (i = 1; i < 4; i++) {
  1404. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1405. cpu_to_le16(cw_min);
  1406. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1407. cpu_to_le16(cw_max);
  1408. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1409. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1410. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1411. }
  1412. }
  1413. IWL_DEBUG_QOS("set QoS to default \n");
  1414. spin_unlock_irqrestore(&priv->lock, flags);
  1415. }
  1416. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1417. {
  1418. unsigned long flags;
  1419. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1420. return;
  1421. spin_lock_irqsave(&priv->lock, flags);
  1422. priv->qos_data.def_qos_parm.qos_flags = 0;
  1423. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1424. !priv->qos_data.qos_cap.q_AP.txop_request)
  1425. priv->qos_data.def_qos_parm.qos_flags |=
  1426. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1427. if (priv->qos_data.qos_active)
  1428. priv->qos_data.def_qos_parm.qos_flags |=
  1429. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1430. spin_unlock_irqrestore(&priv->lock, flags);
  1431. if (force || iwl3945_is_associated(priv)) {
  1432. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1433. priv->qos_data.qos_active);
  1434. iwl3945_send_qos_params_command(priv,
  1435. &(priv->qos_data.def_qos_parm));
  1436. }
  1437. }
  1438. /*
  1439. * Power management (not Tx power!) functions
  1440. */
  1441. #define MSEC_TO_USEC 1024
  1442. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1443. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1444. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1445. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1446. __constant_cpu_to_le32(X1), \
  1447. __constant_cpu_to_le32(X2), \
  1448. __constant_cpu_to_le32(X3), \
  1449. __constant_cpu_to_le32(X4)}
  1450. /* default power management (not Tx power) table values */
  1451. /* for TIM 0-10 */
  1452. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1453. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1454. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1455. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1456. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1457. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1458. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1459. };
  1460. /* for TIM > 10 */
  1461. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1462. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1463. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1464. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1465. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1466. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1467. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1468. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1469. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1470. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1471. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1472. };
  1473. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1474. {
  1475. int rc = 0, i;
  1476. struct iwl3945_power_mgr *pow_data;
  1477. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1478. u16 pci_pm;
  1479. IWL_DEBUG_POWER("Initialize power \n");
  1480. pow_data = &(priv->power_data);
  1481. memset(pow_data, 0, sizeof(*pow_data));
  1482. pow_data->active_index = IWL_POWER_RANGE_0;
  1483. pow_data->dtim_val = 0xffff;
  1484. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1485. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1486. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1487. if (rc != 0)
  1488. return 0;
  1489. else {
  1490. struct iwl_powertable_cmd *cmd;
  1491. IWL_DEBUG_POWER("adjust power command flags\n");
  1492. for (i = 0; i < IWL39_POWER_AC; i++) {
  1493. cmd = &pow_data->pwr_range_0[i].cmd;
  1494. if (pci_pm & 0x1)
  1495. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1496. else
  1497. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1498. }
  1499. }
  1500. return rc;
  1501. }
  1502. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1503. struct iwl_powertable_cmd *cmd, u32 mode)
  1504. {
  1505. int rc = 0, i;
  1506. u8 skip;
  1507. u32 max_sleep = 0;
  1508. struct iwl_power_vec_entry *range;
  1509. u8 period = 0;
  1510. struct iwl3945_power_mgr *pow_data;
  1511. if (mode > IWL_POWER_INDEX_5) {
  1512. IWL_DEBUG_POWER("Error invalid power mode \n");
  1513. return -1;
  1514. }
  1515. pow_data = &(priv->power_data);
  1516. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1517. range = &pow_data->pwr_range_0[0];
  1518. else
  1519. range = &pow_data->pwr_range_1[1];
  1520. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1521. #ifdef IWL_MAC80211_DISABLE
  1522. if (priv->assoc_network != NULL) {
  1523. unsigned long flags;
  1524. period = priv->assoc_network->tim.tim_period;
  1525. }
  1526. #endif /*IWL_MAC80211_DISABLE */
  1527. skip = range[mode].no_dtim;
  1528. if (period == 0) {
  1529. period = 1;
  1530. skip = 0;
  1531. }
  1532. if (skip == 0) {
  1533. max_sleep = period;
  1534. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1535. } else {
  1536. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1537. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1538. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1539. }
  1540. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1541. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1542. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1543. }
  1544. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1545. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1546. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1547. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1548. le32_to_cpu(cmd->sleep_interval[0]),
  1549. le32_to_cpu(cmd->sleep_interval[1]),
  1550. le32_to_cpu(cmd->sleep_interval[2]),
  1551. le32_to_cpu(cmd->sleep_interval[3]),
  1552. le32_to_cpu(cmd->sleep_interval[4]));
  1553. return rc;
  1554. }
  1555. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1556. {
  1557. u32 uninitialized_var(final_mode);
  1558. int rc;
  1559. struct iwl_powertable_cmd cmd;
  1560. /* If on battery, set to 3,
  1561. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1562. * else user level */
  1563. switch (mode) {
  1564. case IWL39_POWER_BATTERY:
  1565. final_mode = IWL_POWER_INDEX_3;
  1566. break;
  1567. case IWL39_POWER_AC:
  1568. final_mode = IWL_POWER_MODE_CAM;
  1569. break;
  1570. default:
  1571. final_mode = mode;
  1572. break;
  1573. }
  1574. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1575. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1576. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1577. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1578. if (final_mode == IWL_POWER_MODE_CAM)
  1579. clear_bit(STATUS_POWER_PMI, &priv->status);
  1580. else
  1581. set_bit(STATUS_POWER_PMI, &priv->status);
  1582. return rc;
  1583. }
  1584. /**
  1585. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1586. *
  1587. * NOTE: priv->mutex is not required before calling this function
  1588. */
  1589. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1590. {
  1591. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1592. clear_bit(STATUS_SCANNING, &priv->status);
  1593. return 0;
  1594. }
  1595. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1596. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1597. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1598. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1599. queue_work(priv->workqueue, &priv->abort_scan);
  1600. } else
  1601. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1602. return test_bit(STATUS_SCANNING, &priv->status);
  1603. }
  1604. return 0;
  1605. }
  1606. /**
  1607. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1608. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1609. *
  1610. * NOTE: priv->mutex must be held before calling this function
  1611. */
  1612. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1613. {
  1614. unsigned long now = jiffies;
  1615. int ret;
  1616. ret = iwl3945_scan_cancel(priv);
  1617. if (ret && ms) {
  1618. mutex_unlock(&priv->mutex);
  1619. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1620. test_bit(STATUS_SCANNING, &priv->status))
  1621. msleep(1);
  1622. mutex_lock(&priv->mutex);
  1623. return test_bit(STATUS_SCANNING, &priv->status);
  1624. }
  1625. return ret;
  1626. }
  1627. #define MAX_UCODE_BEACON_INTERVAL 1024
  1628. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1629. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1630. {
  1631. u16 new_val = 0;
  1632. u16 beacon_factor = 0;
  1633. beacon_factor =
  1634. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1635. / MAX_UCODE_BEACON_INTERVAL;
  1636. new_val = beacon_val / beacon_factor;
  1637. return cpu_to_le16(new_val);
  1638. }
  1639. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1640. {
  1641. u64 interval_tm_unit;
  1642. u64 tsf, result;
  1643. unsigned long flags;
  1644. struct ieee80211_conf *conf = NULL;
  1645. u16 beacon_int = 0;
  1646. conf = ieee80211_get_hw_conf(priv->hw);
  1647. spin_lock_irqsave(&priv->lock, flags);
  1648. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1649. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1650. tsf = priv->timestamp;
  1651. beacon_int = priv->beacon_int;
  1652. spin_unlock_irqrestore(&priv->lock, flags);
  1653. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1654. if (beacon_int == 0) {
  1655. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1656. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1657. } else {
  1658. priv->rxon_timing.beacon_interval =
  1659. cpu_to_le16(beacon_int);
  1660. priv->rxon_timing.beacon_interval =
  1661. iwl3945_adjust_beacon_interval(
  1662. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1663. }
  1664. priv->rxon_timing.atim_window = 0;
  1665. } else {
  1666. priv->rxon_timing.beacon_interval =
  1667. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1668. /* TODO: we need to get atim_window from upper stack
  1669. * for now we set to 0 */
  1670. priv->rxon_timing.atim_window = 0;
  1671. }
  1672. interval_tm_unit =
  1673. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1674. result = do_div(tsf, interval_tm_unit);
  1675. priv->rxon_timing.beacon_init_val =
  1676. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1677. IWL_DEBUG_ASSOC
  1678. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1679. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1680. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1681. le16_to_cpu(priv->rxon_timing.atim_window));
  1682. }
  1683. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1684. {
  1685. if (!iwl3945_is_ready_rf(priv)) {
  1686. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1687. return -EIO;
  1688. }
  1689. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1690. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1691. return -EAGAIN;
  1692. }
  1693. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1694. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1695. "Queuing.\n");
  1696. return -EAGAIN;
  1697. }
  1698. IWL_DEBUG_INFO("Starting scan...\n");
  1699. if (priv->cfg->sku & IWL_SKU_G)
  1700. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1701. if (priv->cfg->sku & IWL_SKU_A)
  1702. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1703. set_bit(STATUS_SCANNING, &priv->status);
  1704. priv->scan_start = jiffies;
  1705. priv->scan_pass_start = priv->scan_start;
  1706. queue_work(priv->workqueue, &priv->request_scan);
  1707. return 0;
  1708. }
  1709. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1710. {
  1711. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1712. if (hw_decrypt)
  1713. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1714. else
  1715. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1716. return 0;
  1717. }
  1718. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1719. enum ieee80211_band band)
  1720. {
  1721. if (band == IEEE80211_BAND_5GHZ) {
  1722. priv->staging_rxon.flags &=
  1723. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1724. | RXON_FLG_CCK_MSK);
  1725. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1726. } else {
  1727. /* Copied from iwl3945_bg_post_associate() */
  1728. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1729. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1730. else
  1731. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1732. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1733. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1734. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1735. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1736. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1737. }
  1738. }
  1739. /*
  1740. * initialize rxon structure with default values from eeprom
  1741. */
  1742. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
  1743. int mode)
  1744. {
  1745. const struct iwl_channel_info *ch_info;
  1746. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1747. switch (mode) {
  1748. case NL80211_IFTYPE_AP:
  1749. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1750. break;
  1751. case NL80211_IFTYPE_STATION:
  1752. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1753. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1754. break;
  1755. case NL80211_IFTYPE_ADHOC:
  1756. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1757. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1758. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1759. RXON_FILTER_ACCEPT_GRP_MSK;
  1760. break;
  1761. case NL80211_IFTYPE_MONITOR:
  1762. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1763. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1764. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1765. break;
  1766. default:
  1767. IWL_ERROR("Unsupported interface type %d\n", mode);
  1768. break;
  1769. }
  1770. #if 0
  1771. /* TODO: Figure out when short_preamble would be set and cache from
  1772. * that */
  1773. if (!hw_to_local(priv->hw)->short_preamble)
  1774. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1775. else
  1776. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1777. #endif
  1778. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1779. le16_to_cpu(priv->active_rxon.channel));
  1780. if (!ch_info)
  1781. ch_info = &priv->channel_info[0];
  1782. /*
  1783. * in some case A channels are all non IBSS
  1784. * in this case force B/G channel
  1785. */
  1786. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1787. ch_info = &priv->channel_info[0];
  1788. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1789. if (is_channel_a_band(ch_info))
  1790. priv->band = IEEE80211_BAND_5GHZ;
  1791. else
  1792. priv->band = IEEE80211_BAND_2GHZ;
  1793. iwl3945_set_flags_for_phymode(priv, priv->band);
  1794. priv->staging_rxon.ofdm_basic_rates =
  1795. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1796. priv->staging_rxon.cck_basic_rates =
  1797. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1798. }
  1799. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1800. {
  1801. if (mode == NL80211_IFTYPE_ADHOC) {
  1802. const struct iwl_channel_info *ch_info;
  1803. ch_info = iwl3945_get_channel_info(priv,
  1804. priv->band,
  1805. le16_to_cpu(priv->staging_rxon.channel));
  1806. if (!ch_info || !is_channel_ibss(ch_info)) {
  1807. IWL_ERROR("channel %d not IBSS channel\n",
  1808. le16_to_cpu(priv->staging_rxon.channel));
  1809. return -EINVAL;
  1810. }
  1811. }
  1812. iwl3945_connection_init_rx_config(priv, mode);
  1813. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1814. iwl3945_clear_stations_table(priv);
  1815. /* don't commit rxon if rf-kill is on*/
  1816. if (!iwl3945_is_ready_rf(priv))
  1817. return -EAGAIN;
  1818. cancel_delayed_work(&priv->scan_check);
  1819. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1820. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1821. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1822. return -EAGAIN;
  1823. }
  1824. iwl3945_commit_rxon(priv);
  1825. return 0;
  1826. }
  1827. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1828. struct ieee80211_tx_info *info,
  1829. struct iwl3945_cmd *cmd,
  1830. struct sk_buff *skb_frag,
  1831. int last_frag)
  1832. {
  1833. struct iwl3945_hw_key *keyinfo =
  1834. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1835. switch (keyinfo->alg) {
  1836. case ALG_CCMP:
  1837. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1838. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1839. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1840. break;
  1841. case ALG_TKIP:
  1842. #if 0
  1843. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1844. if (last_frag)
  1845. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1846. 8);
  1847. else
  1848. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1849. #endif
  1850. break;
  1851. case ALG_WEP:
  1852. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1853. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1854. if (keyinfo->keylen == 13)
  1855. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1856. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1857. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1858. "with key %d\n", info->control.hw_key->hw_key_idx);
  1859. break;
  1860. default:
  1861. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1862. break;
  1863. }
  1864. }
  1865. /*
  1866. * handle build REPLY_TX command notification.
  1867. */
  1868. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1869. struct iwl3945_cmd *cmd,
  1870. struct ieee80211_tx_info *info,
  1871. struct ieee80211_hdr *hdr,
  1872. int is_unicast, u8 std_id)
  1873. {
  1874. __le16 fc = hdr->frame_control;
  1875. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1876. u8 rc_flags = info->control.rates[0].flags;
  1877. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1878. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1879. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1880. if (ieee80211_is_mgmt(fc))
  1881. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1882. if (ieee80211_is_probe_resp(fc) &&
  1883. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1884. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1885. } else {
  1886. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1887. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1888. }
  1889. cmd->cmd.tx.sta_id = std_id;
  1890. if (ieee80211_has_morefrags(fc))
  1891. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1892. if (ieee80211_is_data_qos(fc)) {
  1893. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1894. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1895. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1896. } else {
  1897. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1898. }
  1899. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1900. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1901. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1902. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1903. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1904. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1905. }
  1906. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1907. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1908. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1909. if (ieee80211_is_mgmt(fc)) {
  1910. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1911. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1912. else
  1913. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1914. } else {
  1915. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1916. #ifdef CONFIG_IWL3945_LEDS
  1917. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1918. #endif
  1919. }
  1920. cmd->cmd.tx.driver_txop = 0;
  1921. cmd->cmd.tx.tx_flags = tx_flags;
  1922. cmd->cmd.tx.next_frame_len = 0;
  1923. }
  1924. /**
  1925. * iwl3945_get_sta_id - Find station's index within station table
  1926. */
  1927. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  1928. {
  1929. int sta_id;
  1930. u16 fc = le16_to_cpu(hdr->frame_control);
  1931. /* If this frame is broadcast or management, use broadcast station id */
  1932. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1933. is_multicast_ether_addr(hdr->addr1))
  1934. return priv->hw_setting.bcast_sta_id;
  1935. switch (priv->iw_mode) {
  1936. /* If we are a client station in a BSS network, use the special
  1937. * AP station entry (that's the only station we communicate with) */
  1938. case NL80211_IFTYPE_STATION:
  1939. return IWL_AP_ID;
  1940. /* If we are an AP, then find the station, or use BCAST */
  1941. case NL80211_IFTYPE_AP:
  1942. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1943. if (sta_id != IWL_INVALID_STATION)
  1944. return sta_id;
  1945. return priv->hw_setting.bcast_sta_id;
  1946. /* If this frame is going out to an IBSS network, find the station,
  1947. * or create a new station table entry */
  1948. case NL80211_IFTYPE_ADHOC: {
  1949. /* Create new station table entry */
  1950. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1951. if (sta_id != IWL_INVALID_STATION)
  1952. return sta_id;
  1953. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1954. if (sta_id != IWL_INVALID_STATION)
  1955. return sta_id;
  1956. IWL_DEBUG_DROP("Station %pM not in station map. "
  1957. "Defaulting to broadcast...\n",
  1958. hdr->addr1);
  1959. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1960. return priv->hw_setting.bcast_sta_id;
  1961. }
  1962. /* If we are in monitor mode, use BCAST. This is required for
  1963. * packet injection. */
  1964. case NL80211_IFTYPE_MONITOR:
  1965. return priv->hw_setting.bcast_sta_id;
  1966. default:
  1967. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  1968. return priv->hw_setting.bcast_sta_id;
  1969. }
  1970. }
  1971. /*
  1972. * start REPLY_TX command process
  1973. */
  1974. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  1975. {
  1976. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1977. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1978. struct iwl3945_tfd_frame *tfd;
  1979. u32 *control_flags;
  1980. int txq_id = skb_get_queue_mapping(skb);
  1981. struct iwl3945_tx_queue *txq = NULL;
  1982. struct iwl_queue *q = NULL;
  1983. dma_addr_t phys_addr;
  1984. dma_addr_t txcmd_phys;
  1985. struct iwl3945_cmd *out_cmd = NULL;
  1986. u16 len, idx, len_org, hdr_len;
  1987. u8 id;
  1988. u8 unicast;
  1989. u8 sta_id;
  1990. u8 tid = 0;
  1991. u16 seq_number = 0;
  1992. __le16 fc;
  1993. u8 wait_write_ptr = 0;
  1994. u8 *qc = NULL;
  1995. unsigned long flags;
  1996. int rc;
  1997. spin_lock_irqsave(&priv->lock, flags);
  1998. if (iwl3945_is_rfkill(priv)) {
  1999. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2000. goto drop_unlock;
  2001. }
  2002. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2003. IWL_ERROR("ERROR: No TX rate available.\n");
  2004. goto drop_unlock;
  2005. }
  2006. unicast = !is_multicast_ether_addr(hdr->addr1);
  2007. id = 0;
  2008. fc = hdr->frame_control;
  2009. #ifdef CONFIG_IWL3945_DEBUG
  2010. if (ieee80211_is_auth(fc))
  2011. IWL_DEBUG_TX("Sending AUTH frame\n");
  2012. else if (ieee80211_is_assoc_req(fc))
  2013. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2014. else if (ieee80211_is_reassoc_req(fc))
  2015. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2016. #endif
  2017. /* drop all data frame if we are not associated */
  2018. if (ieee80211_is_data(fc) &&
  2019. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2020. (!iwl3945_is_associated(priv) ||
  2021. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2022. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2023. goto drop_unlock;
  2024. }
  2025. spin_unlock_irqrestore(&priv->lock, flags);
  2026. hdr_len = ieee80211_hdrlen(fc);
  2027. /* Find (or create) index into station table for destination station */
  2028. sta_id = iwl3945_get_sta_id(priv, hdr);
  2029. if (sta_id == IWL_INVALID_STATION) {
  2030. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  2031. hdr->addr1);
  2032. goto drop;
  2033. }
  2034. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2035. if (ieee80211_is_data_qos(fc)) {
  2036. qc = ieee80211_get_qos_ctl(hdr);
  2037. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2038. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2039. IEEE80211_SCTL_SEQ;
  2040. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2041. (hdr->seq_ctrl &
  2042. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2043. seq_number += 0x10;
  2044. }
  2045. /* Descriptor for chosen Tx queue */
  2046. txq = &priv->txq[txq_id];
  2047. q = &txq->q;
  2048. spin_lock_irqsave(&priv->lock, flags);
  2049. /* Set up first empty TFD within this queue's circular TFD buffer */
  2050. tfd = &txq->bd[q->write_ptr];
  2051. memset(tfd, 0, sizeof(*tfd));
  2052. control_flags = (u32 *) tfd;
  2053. idx = get_cmd_index(q, q->write_ptr, 0);
  2054. /* Set up driver data for this TFD */
  2055. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2056. txq->txb[q->write_ptr].skb[0] = skb;
  2057. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2058. out_cmd = &txq->cmd[idx];
  2059. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2060. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2061. /*
  2062. * Set up the Tx-command (not MAC!) header.
  2063. * Store the chosen Tx queue and TFD index within the sequence field;
  2064. * after Tx, uCode's Tx response will return this value so driver can
  2065. * locate the frame within the tx queue and do post-tx processing.
  2066. */
  2067. out_cmd->hdr.cmd = REPLY_TX;
  2068. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2069. INDEX_TO_SEQ(q->write_ptr)));
  2070. /* Copy MAC header from skb into command buffer */
  2071. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2072. /*
  2073. * Use the first empty entry in this queue's command buffer array
  2074. * to contain the Tx command and MAC header concatenated together
  2075. * (payload data will be in another buffer).
  2076. * Size of this varies, due to varying MAC header length.
  2077. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2078. * of the MAC header (device reads on dword boundaries).
  2079. * We'll tell device about this padding later.
  2080. */
  2081. len = priv->hw_setting.tx_cmd_len +
  2082. sizeof(struct iwl_cmd_header) + hdr_len;
  2083. len_org = len;
  2084. len = (len + 3) & ~3;
  2085. if (len_org != len)
  2086. len_org = 1;
  2087. else
  2088. len_org = 0;
  2089. /* Physical address of this Tx command's header (not MAC header!),
  2090. * within command buffer array. */
  2091. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2092. offsetof(struct iwl3945_cmd, hdr);
  2093. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2094. * first entry */
  2095. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2096. if (info->control.hw_key)
  2097. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2098. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2099. * if any (802.11 null frames have no payload). */
  2100. len = skb->len - hdr_len;
  2101. if (len) {
  2102. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2103. len, PCI_DMA_TODEVICE);
  2104. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2105. }
  2106. if (!len)
  2107. /* If there is no payload, then we use only one Tx buffer */
  2108. *control_flags = TFD_CTL_COUNT_SET(1);
  2109. else
  2110. /* Else use 2 buffers.
  2111. * Tell 3945 about any padding after MAC header */
  2112. *control_flags = TFD_CTL_COUNT_SET(2) |
  2113. TFD_CTL_PAD_SET(U32_PAD(len));
  2114. /* Total # bytes to be transmitted */
  2115. len = (u16)skb->len;
  2116. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2117. /* TODO need this for burst mode later on */
  2118. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2119. /* set is_hcca to 0; it probably will never be implemented */
  2120. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2121. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2122. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2123. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2124. txq->need_update = 1;
  2125. if (qc)
  2126. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2127. } else {
  2128. wait_write_ptr = 1;
  2129. txq->need_update = 0;
  2130. }
  2131. iwl_print_hex_dump(priv, IWL_DL_TX, out_cmd->cmd.payload,
  2132. sizeof(out_cmd->cmd.tx));
  2133. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2134. ieee80211_hdrlen(fc));
  2135. /* Tell device the write index *just past* this latest filled TFD */
  2136. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2137. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2138. spin_unlock_irqrestore(&priv->lock, flags);
  2139. if (rc)
  2140. return rc;
  2141. if ((iwl_queue_space(q) < q->high_mark)
  2142. && priv->mac80211_registered) {
  2143. if (wait_write_ptr) {
  2144. spin_lock_irqsave(&priv->lock, flags);
  2145. txq->need_update = 1;
  2146. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2147. spin_unlock_irqrestore(&priv->lock, flags);
  2148. }
  2149. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2150. }
  2151. return 0;
  2152. drop_unlock:
  2153. spin_unlock_irqrestore(&priv->lock, flags);
  2154. drop:
  2155. return -1;
  2156. }
  2157. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2158. {
  2159. const struct ieee80211_supported_band *sband = NULL;
  2160. struct ieee80211_rate *rate;
  2161. int i;
  2162. sband = iwl3945_get_band(priv, priv->band);
  2163. if (!sband) {
  2164. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2165. return;
  2166. }
  2167. priv->active_rate = 0;
  2168. priv->active_rate_basic = 0;
  2169. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2170. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2171. for (i = 0; i < sband->n_bitrates; i++) {
  2172. rate = &sband->bitrates[i];
  2173. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2174. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2175. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2176. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2177. priv->active_rate |= (1 << rate->hw_value);
  2178. }
  2179. }
  2180. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2181. priv->active_rate, priv->active_rate_basic);
  2182. /*
  2183. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2184. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2185. * OFDM
  2186. */
  2187. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2188. priv->staging_rxon.cck_basic_rates =
  2189. ((priv->active_rate_basic &
  2190. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2191. else
  2192. priv->staging_rxon.cck_basic_rates =
  2193. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2194. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2195. priv->staging_rxon.ofdm_basic_rates =
  2196. ((priv->active_rate_basic &
  2197. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2198. IWL_FIRST_OFDM_RATE) & 0xFF;
  2199. else
  2200. priv->staging_rxon.ofdm_basic_rates =
  2201. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2202. }
  2203. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2204. {
  2205. unsigned long flags;
  2206. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2207. return;
  2208. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2209. disable_radio ? "OFF" : "ON");
  2210. if (disable_radio) {
  2211. iwl3945_scan_cancel(priv);
  2212. /* FIXME: This is a workaround for AP */
  2213. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2214. spin_lock_irqsave(&priv->lock, flags);
  2215. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2216. CSR_UCODE_SW_BIT_RFKILL);
  2217. spin_unlock_irqrestore(&priv->lock, flags);
  2218. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2219. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2220. }
  2221. return;
  2222. }
  2223. spin_lock_irqsave(&priv->lock, flags);
  2224. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2225. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2226. spin_unlock_irqrestore(&priv->lock, flags);
  2227. /* wake up ucode */
  2228. msleep(10);
  2229. spin_lock_irqsave(&priv->lock, flags);
  2230. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2231. if (!iwl3945_grab_nic_access(priv))
  2232. iwl3945_release_nic_access(priv);
  2233. spin_unlock_irqrestore(&priv->lock, flags);
  2234. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2235. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2236. "disabled by HW switch\n");
  2237. return;
  2238. }
  2239. if (priv->is_open)
  2240. queue_work(priv->workqueue, &priv->restart);
  2241. return;
  2242. }
  2243. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2244. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2245. {
  2246. u16 fc =
  2247. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2248. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2249. return;
  2250. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2251. return;
  2252. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2253. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2254. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2255. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2256. RX_RES_STATUS_BAD_ICV_MIC)
  2257. stats->flag |= RX_FLAG_MMIC_ERROR;
  2258. case RX_RES_STATUS_SEC_TYPE_WEP:
  2259. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2260. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2261. RX_RES_STATUS_DECRYPT_OK) {
  2262. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2263. stats->flag |= RX_FLAG_DECRYPTED;
  2264. }
  2265. break;
  2266. default:
  2267. break;
  2268. }
  2269. }
  2270. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2271. #include "iwl-spectrum.h"
  2272. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2273. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2274. #define TIME_UNIT 1024
  2275. /*
  2276. * extended beacon time format
  2277. * time in usec will be changed into a 32-bit value in 8:24 format
  2278. * the high 1 byte is the beacon counts
  2279. * the lower 3 bytes is the time in usec within one beacon interval
  2280. */
  2281. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2282. {
  2283. u32 quot;
  2284. u32 rem;
  2285. u32 interval = beacon_interval * 1024;
  2286. if (!interval || !usec)
  2287. return 0;
  2288. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2289. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2290. return (quot << 24) + rem;
  2291. }
  2292. /* base is usually what we get from ucode with each received frame,
  2293. * the same as HW timer counter counting down
  2294. */
  2295. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2296. {
  2297. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2298. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2299. u32 interval = beacon_interval * TIME_UNIT;
  2300. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2301. (addon & BEACON_TIME_MASK_HIGH);
  2302. if (base_low > addon_low)
  2303. res += base_low - addon_low;
  2304. else if (base_low < addon_low) {
  2305. res += interval + base_low - addon_low;
  2306. res += (1 << 24);
  2307. } else
  2308. res += (1 << 24);
  2309. return cpu_to_le32(res);
  2310. }
  2311. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2312. struct ieee80211_measurement_params *params,
  2313. u8 type)
  2314. {
  2315. struct iwl_spectrum_cmd spectrum;
  2316. struct iwl_rx_packet *res;
  2317. struct iwl3945_host_cmd cmd = {
  2318. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2319. .data = (void *)&spectrum,
  2320. .meta.flags = CMD_WANT_SKB,
  2321. };
  2322. u32 add_time = le64_to_cpu(params->start_time);
  2323. int rc;
  2324. int spectrum_resp_status;
  2325. int duration = le16_to_cpu(params->duration);
  2326. if (iwl3945_is_associated(priv))
  2327. add_time =
  2328. iwl3945_usecs_to_beacons(
  2329. le64_to_cpu(params->start_time) - priv->last_tsf,
  2330. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2331. memset(&spectrum, 0, sizeof(spectrum));
  2332. spectrum.channel_count = cpu_to_le16(1);
  2333. spectrum.flags =
  2334. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2335. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2336. cmd.len = sizeof(spectrum);
  2337. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2338. if (iwl3945_is_associated(priv))
  2339. spectrum.start_time =
  2340. iwl3945_add_beacon_time(priv->last_beacon_time,
  2341. add_time,
  2342. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2343. else
  2344. spectrum.start_time = 0;
  2345. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2346. spectrum.channels[0].channel = params->channel;
  2347. spectrum.channels[0].type = type;
  2348. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2349. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2350. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2351. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2352. if (rc)
  2353. return rc;
  2354. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2355. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2356. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2357. rc = -EIO;
  2358. }
  2359. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2360. switch (spectrum_resp_status) {
  2361. case 0: /* Command will be handled */
  2362. if (res->u.spectrum.id != 0xff) {
  2363. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2364. res->u.spectrum.id);
  2365. priv->measurement_status &= ~MEASUREMENT_READY;
  2366. }
  2367. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2368. rc = 0;
  2369. break;
  2370. case 1: /* Command will not be handled */
  2371. rc = -EAGAIN;
  2372. break;
  2373. }
  2374. dev_kfree_skb_any(cmd.meta.u.skb);
  2375. return rc;
  2376. }
  2377. #endif
  2378. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2379. struct iwl3945_rx_mem_buffer *rxb)
  2380. {
  2381. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2382. struct iwl_alive_resp *palive;
  2383. struct delayed_work *pwork;
  2384. palive = &pkt->u.alive_frame;
  2385. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2386. "0x%01X 0x%01X\n",
  2387. palive->is_valid, palive->ver_type,
  2388. palive->ver_subtype);
  2389. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2390. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2391. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2392. sizeof(struct iwl_alive_resp));
  2393. pwork = &priv->init_alive_start;
  2394. } else {
  2395. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2396. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2397. sizeof(struct iwl_alive_resp));
  2398. pwork = &priv->alive_start;
  2399. iwl3945_disable_events(priv);
  2400. }
  2401. /* We delay the ALIVE response by 5ms to
  2402. * give the HW RF Kill time to activate... */
  2403. if (palive->is_valid == UCODE_VALID_OK)
  2404. queue_delayed_work(priv->workqueue, pwork,
  2405. msecs_to_jiffies(5));
  2406. else
  2407. IWL_WARNING("uCode did not respond OK.\n");
  2408. }
  2409. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2410. struct iwl3945_rx_mem_buffer *rxb)
  2411. {
  2412. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2413. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2414. return;
  2415. }
  2416. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2417. struct iwl3945_rx_mem_buffer *rxb)
  2418. {
  2419. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2420. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2421. "seq 0x%04X ser 0x%08X\n",
  2422. le32_to_cpu(pkt->u.err_resp.error_type),
  2423. get_cmd_string(pkt->u.err_resp.cmd_id),
  2424. pkt->u.err_resp.cmd_id,
  2425. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2426. le32_to_cpu(pkt->u.err_resp.error_info));
  2427. }
  2428. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2429. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2430. {
  2431. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2432. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2433. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2434. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2435. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2436. rxon->channel = csa->channel;
  2437. priv->staging_rxon.channel = csa->channel;
  2438. }
  2439. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2440. struct iwl3945_rx_mem_buffer *rxb)
  2441. {
  2442. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2443. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2444. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2445. if (!report->state) {
  2446. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2447. "Spectrum Measure Notification: Start\n");
  2448. return;
  2449. }
  2450. memcpy(&priv->measure_report, report, sizeof(*report));
  2451. priv->measurement_status |= MEASUREMENT_READY;
  2452. #endif
  2453. }
  2454. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2455. struct iwl3945_rx_mem_buffer *rxb)
  2456. {
  2457. #ifdef CONFIG_IWL3945_DEBUG
  2458. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2459. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2460. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2461. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2462. #endif
  2463. }
  2464. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2465. struct iwl3945_rx_mem_buffer *rxb)
  2466. {
  2467. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2468. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2469. "notification for %s:\n",
  2470. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2471. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2472. le32_to_cpu(pkt->len));
  2473. }
  2474. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2475. {
  2476. struct iwl3945_priv *priv =
  2477. container_of(work, struct iwl3945_priv, beacon_update);
  2478. struct sk_buff *beacon;
  2479. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2480. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2481. if (!beacon) {
  2482. IWL_ERROR("update beacon failed\n");
  2483. return;
  2484. }
  2485. mutex_lock(&priv->mutex);
  2486. /* new beacon skb is allocated every time; dispose previous.*/
  2487. if (priv->ibss_beacon)
  2488. dev_kfree_skb(priv->ibss_beacon);
  2489. priv->ibss_beacon = beacon;
  2490. mutex_unlock(&priv->mutex);
  2491. iwl3945_send_beacon_cmd(priv);
  2492. }
  2493. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2494. struct iwl3945_rx_mem_buffer *rxb)
  2495. {
  2496. #ifdef CONFIG_IWL3945_DEBUG
  2497. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2498. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2499. u8 rate = beacon->beacon_notify_hdr.rate;
  2500. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2501. "tsf %d %d rate %d\n",
  2502. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2503. beacon->beacon_notify_hdr.failure_frame,
  2504. le32_to_cpu(beacon->ibss_mgr_status),
  2505. le32_to_cpu(beacon->high_tsf),
  2506. le32_to_cpu(beacon->low_tsf), rate);
  2507. #endif
  2508. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2509. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2510. queue_work(priv->workqueue, &priv->beacon_update);
  2511. }
  2512. /* Service response to REPLY_SCAN_CMD (0x80) */
  2513. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2514. struct iwl3945_rx_mem_buffer *rxb)
  2515. {
  2516. #ifdef CONFIG_IWL3945_DEBUG
  2517. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2518. struct iwl_scanreq_notification *notif =
  2519. (struct iwl_scanreq_notification *)pkt->u.raw;
  2520. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2521. #endif
  2522. }
  2523. /* Service SCAN_START_NOTIFICATION (0x82) */
  2524. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2525. struct iwl3945_rx_mem_buffer *rxb)
  2526. {
  2527. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2528. struct iwl_scanstart_notification *notif =
  2529. (struct iwl_scanstart_notification *)pkt->u.raw;
  2530. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2531. IWL_DEBUG_SCAN("Scan start: "
  2532. "%d [802.11%s] "
  2533. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2534. notif->channel,
  2535. notif->band ? "bg" : "a",
  2536. notif->tsf_high,
  2537. notif->tsf_low, notif->status, notif->beacon_timer);
  2538. }
  2539. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2540. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2541. struct iwl3945_rx_mem_buffer *rxb)
  2542. {
  2543. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2544. struct iwl_scanresults_notification *notif =
  2545. (struct iwl_scanresults_notification *)pkt->u.raw;
  2546. IWL_DEBUG_SCAN("Scan ch.res: "
  2547. "%d [802.11%s] "
  2548. "(TSF: 0x%08X:%08X) - %d "
  2549. "elapsed=%lu usec (%dms since last)\n",
  2550. notif->channel,
  2551. notif->band ? "bg" : "a",
  2552. le32_to_cpu(notif->tsf_high),
  2553. le32_to_cpu(notif->tsf_low),
  2554. le32_to_cpu(notif->statistics[0]),
  2555. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2556. jiffies_to_msecs(elapsed_jiffies
  2557. (priv->last_scan_jiffies, jiffies)));
  2558. priv->last_scan_jiffies = jiffies;
  2559. priv->next_scan_jiffies = 0;
  2560. }
  2561. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2562. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2563. struct iwl3945_rx_mem_buffer *rxb)
  2564. {
  2565. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2566. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2567. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2568. scan_notif->scanned_channels,
  2569. scan_notif->tsf_low,
  2570. scan_notif->tsf_high, scan_notif->status);
  2571. /* The HW is no longer scanning */
  2572. clear_bit(STATUS_SCAN_HW, &priv->status);
  2573. /* The scan completion notification came in, so kill that timer... */
  2574. cancel_delayed_work(&priv->scan_check);
  2575. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2576. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2577. "2.4" : "5.2",
  2578. jiffies_to_msecs(elapsed_jiffies
  2579. (priv->scan_pass_start, jiffies)));
  2580. /* Remove this scanned band from the list of pending
  2581. * bands to scan, band G precedes A in order of scanning
  2582. * as seen in iwl3945_bg_request_scan */
  2583. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2584. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2585. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2586. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2587. /* If a request to abort was given, or the scan did not succeed
  2588. * then we reset the scan state machine and terminate,
  2589. * re-queuing another scan if one has been requested */
  2590. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2591. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2592. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2593. } else {
  2594. /* If there are more bands on this scan pass reschedule */
  2595. if (priv->scan_bands > 0)
  2596. goto reschedule;
  2597. }
  2598. priv->last_scan_jiffies = jiffies;
  2599. priv->next_scan_jiffies = 0;
  2600. IWL_DEBUG_INFO("Setting scan to off\n");
  2601. clear_bit(STATUS_SCANNING, &priv->status);
  2602. IWL_DEBUG_INFO("Scan took %dms\n",
  2603. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2604. queue_work(priv->workqueue, &priv->scan_completed);
  2605. return;
  2606. reschedule:
  2607. priv->scan_pass_start = jiffies;
  2608. queue_work(priv->workqueue, &priv->request_scan);
  2609. }
  2610. /* Handle notification from uCode that card's power state is changing
  2611. * due to software, hardware, or critical temperature RFKILL */
  2612. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2613. struct iwl3945_rx_mem_buffer *rxb)
  2614. {
  2615. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2616. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2617. unsigned long status = priv->status;
  2618. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2619. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2620. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2621. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2622. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2623. if (flags & HW_CARD_DISABLED)
  2624. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2625. else
  2626. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2627. if (flags & SW_CARD_DISABLED)
  2628. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2629. else
  2630. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2631. iwl3945_scan_cancel(priv);
  2632. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2633. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2634. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2635. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2636. queue_work(priv->workqueue, &priv->rf_kill);
  2637. else
  2638. wake_up_interruptible(&priv->wait_command_queue);
  2639. }
  2640. /**
  2641. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2642. *
  2643. * Setup the RX handlers for each of the reply types sent from the uCode
  2644. * to the host.
  2645. *
  2646. * This function chains into the hardware specific files for them to setup
  2647. * any hardware specific handlers as well.
  2648. */
  2649. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2650. {
  2651. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2652. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2653. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2654. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2655. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2656. iwl3945_rx_spectrum_measure_notif;
  2657. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2658. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2659. iwl3945_rx_pm_debug_statistics_notif;
  2660. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2661. /*
  2662. * The same handler is used for both the REPLY to a discrete
  2663. * statistics request from the host as well as for the periodic
  2664. * statistics notifications (after received beacons) from the uCode.
  2665. */
  2666. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2667. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2668. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2669. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2670. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2671. iwl3945_rx_scan_results_notif;
  2672. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2673. iwl3945_rx_scan_complete_notif;
  2674. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2675. /* Set up hardware specific Rx handlers */
  2676. iwl3945_hw_rx_handler_setup(priv);
  2677. }
  2678. /**
  2679. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2680. * When FW advances 'R' index, all entries between old and new 'R' index
  2681. * need to be reclaimed.
  2682. */
  2683. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2684. int txq_id, int index)
  2685. {
  2686. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2687. struct iwl_queue *q = &txq->q;
  2688. int nfreed = 0;
  2689. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2690. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2691. "is out of range [0-%d] %d %d.\n", txq_id,
  2692. index, q->n_bd, q->write_ptr, q->read_ptr);
  2693. return;
  2694. }
  2695. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2696. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2697. if (nfreed > 1) {
  2698. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2699. q->write_ptr, q->read_ptr);
  2700. queue_work(priv->workqueue, &priv->restart);
  2701. break;
  2702. }
  2703. nfreed++;
  2704. }
  2705. }
  2706. /**
  2707. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2708. * @rxb: Rx buffer to reclaim
  2709. *
  2710. * If an Rx buffer has an async callback associated with it the callback
  2711. * will be executed. The attached skb (if present) will only be freed
  2712. * if the callback returns 1
  2713. */
  2714. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2715. struct iwl3945_rx_mem_buffer *rxb)
  2716. {
  2717. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2718. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2719. int txq_id = SEQ_TO_QUEUE(sequence);
  2720. int index = SEQ_TO_INDEX(sequence);
  2721. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2722. int cmd_index;
  2723. struct iwl3945_cmd *cmd;
  2724. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2725. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2726. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2727. /* Input error checking is done when commands are added to queue. */
  2728. if (cmd->meta.flags & CMD_WANT_SKB) {
  2729. cmd->meta.source->u.skb = rxb->skb;
  2730. rxb->skb = NULL;
  2731. } else if (cmd->meta.u.callback &&
  2732. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2733. rxb->skb = NULL;
  2734. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2735. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2736. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2737. wake_up_interruptible(&priv->wait_command_queue);
  2738. }
  2739. }
  2740. /************************** RX-FUNCTIONS ****************************/
  2741. /*
  2742. * Rx theory of operation
  2743. *
  2744. * The host allocates 32 DMA target addresses and passes the host address
  2745. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2746. * 0 to 31
  2747. *
  2748. * Rx Queue Indexes
  2749. * The host/firmware share two index registers for managing the Rx buffers.
  2750. *
  2751. * The READ index maps to the first position that the firmware may be writing
  2752. * to -- the driver can read up to (but not including) this position and get
  2753. * good data.
  2754. * The READ index is managed by the firmware once the card is enabled.
  2755. *
  2756. * The WRITE index maps to the last position the driver has read from -- the
  2757. * position preceding WRITE is the last slot the firmware can place a packet.
  2758. *
  2759. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2760. * WRITE = READ.
  2761. *
  2762. * During initialization, the host sets up the READ queue position to the first
  2763. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2764. *
  2765. * When the firmware places a packet in a buffer, it will advance the READ index
  2766. * and fire the RX interrupt. The driver can then query the READ index and
  2767. * process as many packets as possible, moving the WRITE index forward as it
  2768. * resets the Rx queue buffers with new memory.
  2769. *
  2770. * The management in the driver is as follows:
  2771. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2772. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2773. * to replenish the iwl->rxq->rx_free.
  2774. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2775. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2776. * 'processed' and 'read' driver indexes as well)
  2777. * + A received packet is processed and handed to the kernel network stack,
  2778. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2779. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2780. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2781. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2782. * were enough free buffers and RX_STALLED is set it is cleared.
  2783. *
  2784. *
  2785. * Driver sequence:
  2786. *
  2787. * iwl3945_rx_queue_alloc() Allocates rx_free
  2788. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2789. * iwl3945_rx_queue_restock
  2790. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2791. * queue, updates firmware pointers, and updates
  2792. * the WRITE index. If insufficient rx_free buffers
  2793. * are available, schedules iwl3945_rx_replenish
  2794. *
  2795. * -- enable interrupts --
  2796. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2797. * READ INDEX, detaching the SKB from the pool.
  2798. * Moves the packet buffer from queue to rx_used.
  2799. * Calls iwl3945_rx_queue_restock to refill any empty
  2800. * slots.
  2801. * ...
  2802. *
  2803. */
  2804. /**
  2805. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2806. */
  2807. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2808. {
  2809. int s = q->read - q->write;
  2810. if (s <= 0)
  2811. s += RX_QUEUE_SIZE;
  2812. /* keep some buffer to not confuse full and empty queue */
  2813. s -= 2;
  2814. if (s < 0)
  2815. s = 0;
  2816. return s;
  2817. }
  2818. /**
  2819. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2820. */
  2821. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2822. {
  2823. u32 reg = 0;
  2824. int rc = 0;
  2825. unsigned long flags;
  2826. spin_lock_irqsave(&q->lock, flags);
  2827. if (q->need_update == 0)
  2828. goto exit_unlock;
  2829. /* If power-saving is in use, make sure device is awake */
  2830. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2831. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2832. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2833. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2834. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2835. goto exit_unlock;
  2836. }
  2837. rc = iwl3945_grab_nic_access(priv);
  2838. if (rc)
  2839. goto exit_unlock;
  2840. /* Device expects a multiple of 8 */
  2841. iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2842. q->write & ~0x7);
  2843. iwl3945_release_nic_access(priv);
  2844. /* Else device is assumed to be awake */
  2845. } else
  2846. /* Device expects a multiple of 8 */
  2847. iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2848. q->need_update = 0;
  2849. exit_unlock:
  2850. spin_unlock_irqrestore(&q->lock, flags);
  2851. return rc;
  2852. }
  2853. /**
  2854. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2855. */
  2856. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2857. dma_addr_t dma_addr)
  2858. {
  2859. return cpu_to_le32((u32)dma_addr);
  2860. }
  2861. /**
  2862. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2863. *
  2864. * If there are slots in the RX queue that need to be restocked,
  2865. * and we have free pre-allocated buffers, fill the ranks as much
  2866. * as we can, pulling from rx_free.
  2867. *
  2868. * This moves the 'write' index forward to catch up with 'processed', and
  2869. * also updates the memory address in the firmware to reference the new
  2870. * target buffer.
  2871. */
  2872. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2873. {
  2874. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2875. struct list_head *element;
  2876. struct iwl3945_rx_mem_buffer *rxb;
  2877. unsigned long flags;
  2878. int write, rc;
  2879. spin_lock_irqsave(&rxq->lock, flags);
  2880. write = rxq->write & ~0x7;
  2881. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2882. /* Get next free Rx buffer, remove from free list */
  2883. element = rxq->rx_free.next;
  2884. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2885. list_del(element);
  2886. /* Point to Rx buffer via next RBD in circular buffer */
  2887. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  2888. rxq->queue[rxq->write] = rxb;
  2889. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2890. rxq->free_count--;
  2891. }
  2892. spin_unlock_irqrestore(&rxq->lock, flags);
  2893. /* If the pre-allocated buffer pool is dropping low, schedule to
  2894. * refill it */
  2895. if (rxq->free_count <= RX_LOW_WATERMARK)
  2896. queue_work(priv->workqueue, &priv->rx_replenish);
  2897. /* If we've added more space for the firmware to place data, tell it.
  2898. * Increment device's write pointer in multiples of 8. */
  2899. if ((write != (rxq->write & ~0x7))
  2900. || (abs(rxq->write - rxq->read) > 7)) {
  2901. spin_lock_irqsave(&rxq->lock, flags);
  2902. rxq->need_update = 1;
  2903. spin_unlock_irqrestore(&rxq->lock, flags);
  2904. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2905. if (rc)
  2906. return rc;
  2907. }
  2908. return 0;
  2909. }
  2910. /**
  2911. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2912. *
  2913. * When moving to rx_free an SKB is allocated for the slot.
  2914. *
  2915. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2916. * This is called as a scheduled work item (except for during initialization)
  2917. */
  2918. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  2919. {
  2920. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2921. struct list_head *element;
  2922. struct iwl3945_rx_mem_buffer *rxb;
  2923. unsigned long flags;
  2924. spin_lock_irqsave(&rxq->lock, flags);
  2925. while (!list_empty(&rxq->rx_used)) {
  2926. element = rxq->rx_used.next;
  2927. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2928. /* Alloc a new receive buffer */
  2929. rxb->skb =
  2930. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2931. if (!rxb->skb) {
  2932. if (net_ratelimit())
  2933. printk(KERN_CRIT DRV_NAME
  2934. ": Can not allocate SKB buffers\n");
  2935. /* We don't reschedule replenish work here -- we will
  2936. * call the restock method and if it still needs
  2937. * more buffers it will schedule replenish */
  2938. break;
  2939. }
  2940. /* If radiotap head is required, reserve some headroom here.
  2941. * The physical head count is a variable rx_stats->phy_count.
  2942. * We reserve 4 bytes here. Plus these extra bytes, the
  2943. * headroom of the physical head should be enough for the
  2944. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2945. */
  2946. skb_reserve(rxb->skb, 4);
  2947. priv->alloc_rxb_skb++;
  2948. list_del(element);
  2949. /* Get physical address of RB/SKB */
  2950. rxb->dma_addr =
  2951. pci_map_single(priv->pci_dev, rxb->skb->data,
  2952. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2953. list_add_tail(&rxb->list, &rxq->rx_free);
  2954. rxq->free_count++;
  2955. }
  2956. spin_unlock_irqrestore(&rxq->lock, flags);
  2957. }
  2958. /*
  2959. * this should be called while priv->lock is locked
  2960. */
  2961. static void __iwl3945_rx_replenish(void *data)
  2962. {
  2963. struct iwl3945_priv *priv = data;
  2964. iwl3945_rx_allocate(priv);
  2965. iwl3945_rx_queue_restock(priv);
  2966. }
  2967. void iwl3945_rx_replenish(void *data)
  2968. {
  2969. struct iwl3945_priv *priv = data;
  2970. unsigned long flags;
  2971. iwl3945_rx_allocate(priv);
  2972. spin_lock_irqsave(&priv->lock, flags);
  2973. iwl3945_rx_queue_restock(priv);
  2974. spin_unlock_irqrestore(&priv->lock, flags);
  2975. }
  2976. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  2977. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  2978. * This free routine walks the list of POOL entries and if SKB is set to
  2979. * non NULL it is unmapped and freed
  2980. */
  2981. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  2982. {
  2983. int i;
  2984. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  2985. if (rxq->pool[i].skb != NULL) {
  2986. pci_unmap_single(priv->pci_dev,
  2987. rxq->pool[i].dma_addr,
  2988. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2989. dev_kfree_skb(rxq->pool[i].skb);
  2990. }
  2991. }
  2992. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2993. rxq->dma_addr);
  2994. rxq->bd = NULL;
  2995. }
  2996. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  2997. {
  2998. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2999. struct pci_dev *dev = priv->pci_dev;
  3000. int i;
  3001. spin_lock_init(&rxq->lock);
  3002. INIT_LIST_HEAD(&rxq->rx_free);
  3003. INIT_LIST_HEAD(&rxq->rx_used);
  3004. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3005. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3006. if (!rxq->bd)
  3007. return -ENOMEM;
  3008. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3009. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3010. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3011. /* Set us so that we have processed and used all buffers, but have
  3012. * not restocked the Rx queue with fresh buffers */
  3013. rxq->read = rxq->write = 0;
  3014. rxq->free_count = 0;
  3015. rxq->need_update = 0;
  3016. return 0;
  3017. }
  3018. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3019. {
  3020. unsigned long flags;
  3021. int i;
  3022. spin_lock_irqsave(&rxq->lock, flags);
  3023. INIT_LIST_HEAD(&rxq->rx_free);
  3024. INIT_LIST_HEAD(&rxq->rx_used);
  3025. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3026. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3027. /* In the reset function, these buffers may have been allocated
  3028. * to an SKB, so we need to unmap and free potential storage */
  3029. if (rxq->pool[i].skb != NULL) {
  3030. pci_unmap_single(priv->pci_dev,
  3031. rxq->pool[i].dma_addr,
  3032. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3033. priv->alloc_rxb_skb--;
  3034. dev_kfree_skb(rxq->pool[i].skb);
  3035. rxq->pool[i].skb = NULL;
  3036. }
  3037. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3038. }
  3039. /* Set us so that we have processed and used all buffers, but have
  3040. * not restocked the Rx queue with fresh buffers */
  3041. rxq->read = rxq->write = 0;
  3042. rxq->free_count = 0;
  3043. spin_unlock_irqrestore(&rxq->lock, flags);
  3044. }
  3045. /* Convert linear signal-to-noise ratio into dB */
  3046. static u8 ratio2dB[100] = {
  3047. /* 0 1 2 3 4 5 6 7 8 9 */
  3048. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3049. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3050. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3051. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3052. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3053. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3054. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3055. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3056. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3057. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3058. };
  3059. /* Calculates a relative dB value from a ratio of linear
  3060. * (i.e. not dB) signal levels.
  3061. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3062. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3063. {
  3064. /* 1000:1 or higher just report as 60 dB */
  3065. if (sig_ratio >= 1000)
  3066. return 60;
  3067. /* 100:1 or higher, divide by 10 and use table,
  3068. * add 20 dB to make up for divide by 10 */
  3069. if (sig_ratio >= 100)
  3070. return 20 + (int)ratio2dB[sig_ratio/10];
  3071. /* We shouldn't see this */
  3072. if (sig_ratio < 1)
  3073. return 0;
  3074. /* Use table for ratios 1:1 - 99:1 */
  3075. return (int)ratio2dB[sig_ratio];
  3076. }
  3077. #define PERFECT_RSSI (-20) /* dBm */
  3078. #define WORST_RSSI (-95) /* dBm */
  3079. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3080. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3081. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3082. * about formulas used below. */
  3083. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3084. {
  3085. int sig_qual;
  3086. int degradation = PERFECT_RSSI - rssi_dbm;
  3087. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3088. * as indicator; formula is (signal dbm - noise dbm).
  3089. * SNR at or above 40 is a great signal (100%).
  3090. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3091. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3092. if (noise_dbm) {
  3093. if (rssi_dbm - noise_dbm >= 40)
  3094. return 100;
  3095. else if (rssi_dbm < noise_dbm)
  3096. return 0;
  3097. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3098. /* Else use just the signal level.
  3099. * This formula is a least squares fit of data points collected and
  3100. * compared with a reference system that had a percentage (%) display
  3101. * for signal quality. */
  3102. } else
  3103. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3104. (15 * RSSI_RANGE + 62 * degradation)) /
  3105. (RSSI_RANGE * RSSI_RANGE);
  3106. if (sig_qual > 100)
  3107. sig_qual = 100;
  3108. else if (sig_qual < 1)
  3109. sig_qual = 0;
  3110. return sig_qual;
  3111. }
  3112. /**
  3113. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3114. *
  3115. * Uses the priv->rx_handlers callback function array to invoke
  3116. * the appropriate handlers, including command responses,
  3117. * frame-received notifications, and other notifications.
  3118. */
  3119. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3120. {
  3121. struct iwl3945_rx_mem_buffer *rxb;
  3122. struct iwl_rx_packet *pkt;
  3123. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3124. u32 r, i;
  3125. int reclaim;
  3126. unsigned long flags;
  3127. u8 fill_rx = 0;
  3128. u32 count = 8;
  3129. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3130. * buffer that the driver may process (last buffer filled by ucode). */
  3131. r = iwl3945_hw_get_rx_read(priv);
  3132. i = rxq->read;
  3133. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3134. fill_rx = 1;
  3135. /* Rx interrupt, but nothing sent from uCode */
  3136. if (i == r)
  3137. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3138. while (i != r) {
  3139. rxb = rxq->queue[i];
  3140. /* If an RXB doesn't have a Rx queue slot associated with it,
  3141. * then a bug has been introduced in the queue refilling
  3142. * routines -- catch it here */
  3143. BUG_ON(rxb == NULL);
  3144. rxq->queue[i] = NULL;
  3145. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3146. IWL_RX_BUF_SIZE,
  3147. PCI_DMA_FROMDEVICE);
  3148. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  3149. /* Reclaim a command buffer only if this packet is a response
  3150. * to a (driver-originated) command.
  3151. * If the packet (e.g. Rx frame) originated from uCode,
  3152. * there is no command buffer to reclaim.
  3153. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3154. * but apparently a few don't get set; catch them here. */
  3155. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3156. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3157. (pkt->hdr.cmd != REPLY_TX);
  3158. /* Based on type of command response or notification,
  3159. * handle those that need handling via function in
  3160. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3161. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3162. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3163. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3164. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3165. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3166. } else {
  3167. /* No handling needed */
  3168. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3169. "r %d i %d No handler needed for %s, 0x%02x\n",
  3170. r, i, get_cmd_string(pkt->hdr.cmd),
  3171. pkt->hdr.cmd);
  3172. }
  3173. if (reclaim) {
  3174. /* Invoke any callbacks, transfer the skb to caller, and
  3175. * fire off the (possibly) blocking iwl3945_send_cmd()
  3176. * as we reclaim the driver command queue */
  3177. if (rxb && rxb->skb)
  3178. iwl3945_tx_cmd_complete(priv, rxb);
  3179. else
  3180. IWL_WARNING("Claim null rxb?\n");
  3181. }
  3182. /* For now we just don't re-use anything. We can tweak this
  3183. * later to try and re-use notification packets and SKBs that
  3184. * fail to Rx correctly */
  3185. if (rxb->skb != NULL) {
  3186. priv->alloc_rxb_skb--;
  3187. dev_kfree_skb_any(rxb->skb);
  3188. rxb->skb = NULL;
  3189. }
  3190. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3191. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3192. spin_lock_irqsave(&rxq->lock, flags);
  3193. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3194. spin_unlock_irqrestore(&rxq->lock, flags);
  3195. i = (i + 1) & RX_QUEUE_MASK;
  3196. /* If there are a lot of unused frames,
  3197. * restock the Rx queue so ucode won't assert. */
  3198. if (fill_rx) {
  3199. count++;
  3200. if (count >= 8) {
  3201. priv->rxq.read = i;
  3202. __iwl3945_rx_replenish(priv);
  3203. count = 0;
  3204. }
  3205. }
  3206. }
  3207. /* Backtrack one entry */
  3208. priv->rxq.read = i;
  3209. iwl3945_rx_queue_restock(priv);
  3210. }
  3211. /**
  3212. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3213. */
  3214. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3215. struct iwl3945_tx_queue *txq)
  3216. {
  3217. u32 reg = 0;
  3218. int rc = 0;
  3219. int txq_id = txq->q.id;
  3220. if (txq->need_update == 0)
  3221. return rc;
  3222. /* if we're trying to save power */
  3223. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3224. /* wake up nic if it's powered down ...
  3225. * uCode will wake up, and interrupt us again, so next
  3226. * time we'll skip this part. */
  3227. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3228. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3229. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3230. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3231. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3232. return rc;
  3233. }
  3234. /* restore this queue's parameters in nic hardware. */
  3235. rc = iwl3945_grab_nic_access(priv);
  3236. if (rc)
  3237. return rc;
  3238. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3239. txq->q.write_ptr | (txq_id << 8));
  3240. iwl3945_release_nic_access(priv);
  3241. /* else not in power-save mode, uCode will never sleep when we're
  3242. * trying to tx (during RFKILL, we're not trying to tx). */
  3243. } else
  3244. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3245. txq->q.write_ptr | (txq_id << 8));
  3246. txq->need_update = 0;
  3247. return rc;
  3248. }
  3249. #ifdef CONFIG_IWL3945_DEBUG
  3250. static void iwl3945_print_rx_config_cmd(struct iwl3945_priv *priv,
  3251. struct iwl3945_rxon_cmd *rxon)
  3252. {
  3253. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3254. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3255. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3256. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3257. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3258. le32_to_cpu(rxon->filter_flags));
  3259. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3260. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3261. rxon->ofdm_basic_rates);
  3262. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3263. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3264. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3265. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3266. }
  3267. #endif
  3268. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3269. {
  3270. IWL_DEBUG_ISR("Enabling interrupts\n");
  3271. set_bit(STATUS_INT_ENABLED, &priv->status);
  3272. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3273. }
  3274. /* call this function to flush any scheduled tasklet */
  3275. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3276. {
  3277. /* wait to make sure we flush pending tasklet*/
  3278. synchronize_irq(priv->pci_dev->irq);
  3279. tasklet_kill(&priv->irq_tasklet);
  3280. }
  3281. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3282. {
  3283. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3284. /* disable interrupts from uCode/NIC to host */
  3285. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3286. /* acknowledge/clear/reset any interrupts still pending
  3287. * from uCode or flow handler (Rx/Tx DMA) */
  3288. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3289. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3290. IWL_DEBUG_ISR("Disabled interrupts\n");
  3291. }
  3292. static const char *desc_lookup(int i)
  3293. {
  3294. switch (i) {
  3295. case 1:
  3296. return "FAIL";
  3297. case 2:
  3298. return "BAD_PARAM";
  3299. case 3:
  3300. return "BAD_CHECKSUM";
  3301. case 4:
  3302. return "NMI_INTERRUPT";
  3303. case 5:
  3304. return "SYSASSERT";
  3305. case 6:
  3306. return "FATAL_ERROR";
  3307. }
  3308. return "UNKNOWN";
  3309. }
  3310. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3311. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3312. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3313. {
  3314. u32 i;
  3315. u32 desc, time, count, base, data1;
  3316. u32 blink1, blink2, ilink1, ilink2;
  3317. int rc;
  3318. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3319. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3320. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3321. return;
  3322. }
  3323. rc = iwl3945_grab_nic_access(priv);
  3324. if (rc) {
  3325. IWL_WARNING("Can not read from adapter at this time.\n");
  3326. return;
  3327. }
  3328. count = iwl3945_read_targ_mem(priv, base);
  3329. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3330. IWL_ERROR("Start IWL Error Log Dump:\n");
  3331. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3332. }
  3333. IWL_ERROR("Desc Time asrtPC blink2 "
  3334. "ilink1 nmiPC Line\n");
  3335. for (i = ERROR_START_OFFSET;
  3336. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3337. i += ERROR_ELEM_SIZE) {
  3338. desc = iwl3945_read_targ_mem(priv, base + i);
  3339. time =
  3340. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3341. blink1 =
  3342. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3343. blink2 =
  3344. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3345. ilink1 =
  3346. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3347. ilink2 =
  3348. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3349. data1 =
  3350. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3351. IWL_ERROR
  3352. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3353. desc_lookup(desc), desc, time, blink1, blink2,
  3354. ilink1, ilink2, data1);
  3355. }
  3356. iwl3945_release_nic_access(priv);
  3357. }
  3358. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3359. /**
  3360. * iwl3945_print_event_log - Dump error event log to syslog
  3361. *
  3362. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3363. */
  3364. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3365. u32 num_events, u32 mode)
  3366. {
  3367. u32 i;
  3368. u32 base; /* SRAM byte address of event log header */
  3369. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3370. u32 ptr; /* SRAM byte address of log data */
  3371. u32 ev, time, data; /* event log data */
  3372. if (num_events == 0)
  3373. return;
  3374. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3375. if (mode == 0)
  3376. event_size = 2 * sizeof(u32);
  3377. else
  3378. event_size = 3 * sizeof(u32);
  3379. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3380. /* "time" is actually "data" for mode 0 (no timestamp).
  3381. * place event id # at far right for easier visual parsing. */
  3382. for (i = 0; i < num_events; i++) {
  3383. ev = iwl3945_read_targ_mem(priv, ptr);
  3384. ptr += sizeof(u32);
  3385. time = iwl3945_read_targ_mem(priv, ptr);
  3386. ptr += sizeof(u32);
  3387. if (mode == 0)
  3388. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3389. else {
  3390. data = iwl3945_read_targ_mem(priv, ptr);
  3391. ptr += sizeof(u32);
  3392. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3393. }
  3394. }
  3395. }
  3396. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3397. {
  3398. int rc;
  3399. u32 base; /* SRAM byte address of event log header */
  3400. u32 capacity; /* event log capacity in # entries */
  3401. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3402. u32 num_wraps; /* # times uCode wrapped to top of log */
  3403. u32 next_entry; /* index of next entry to be written by uCode */
  3404. u32 size; /* # entries that we'll print */
  3405. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3406. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3407. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3408. return;
  3409. }
  3410. rc = iwl3945_grab_nic_access(priv);
  3411. if (rc) {
  3412. IWL_WARNING("Can not read from adapter at this time.\n");
  3413. return;
  3414. }
  3415. /* event log header */
  3416. capacity = iwl3945_read_targ_mem(priv, base);
  3417. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3418. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3419. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3420. size = num_wraps ? capacity : next_entry;
  3421. /* bail out if nothing in log */
  3422. if (size == 0) {
  3423. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3424. iwl3945_release_nic_access(priv);
  3425. return;
  3426. }
  3427. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3428. size, num_wraps);
  3429. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3430. * i.e the next one that uCode would fill. */
  3431. if (num_wraps)
  3432. iwl3945_print_event_log(priv, next_entry,
  3433. capacity - next_entry, mode);
  3434. /* (then/else) start at top of log */
  3435. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3436. iwl3945_release_nic_access(priv);
  3437. }
  3438. /**
  3439. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3440. */
  3441. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3442. {
  3443. /* Set the FW error flag -- cleared on iwl3945_down */
  3444. set_bit(STATUS_FW_ERROR, &priv->status);
  3445. /* Cancel currently queued command. */
  3446. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3447. #ifdef CONFIG_IWL3945_DEBUG
  3448. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3449. iwl3945_dump_nic_error_log(priv);
  3450. iwl3945_dump_nic_event_log(priv);
  3451. iwl3945_print_rx_config_cmd(priv, &priv->staging_rxon);
  3452. }
  3453. #endif
  3454. wake_up_interruptible(&priv->wait_command_queue);
  3455. /* Keep the restart process from trying to send host
  3456. * commands by clearing the INIT status bit */
  3457. clear_bit(STATUS_READY, &priv->status);
  3458. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3459. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3460. "Restarting adapter due to uCode error.\n");
  3461. if (iwl3945_is_associated(priv)) {
  3462. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3463. sizeof(priv->recovery_rxon));
  3464. priv->error_recovering = 1;
  3465. }
  3466. queue_work(priv->workqueue, &priv->restart);
  3467. }
  3468. }
  3469. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3470. {
  3471. unsigned long flags;
  3472. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3473. sizeof(priv->staging_rxon));
  3474. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3475. iwl3945_commit_rxon(priv);
  3476. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3477. spin_lock_irqsave(&priv->lock, flags);
  3478. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3479. priv->error_recovering = 0;
  3480. spin_unlock_irqrestore(&priv->lock, flags);
  3481. }
  3482. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3483. {
  3484. u32 inta, handled = 0;
  3485. u32 inta_fh;
  3486. unsigned long flags;
  3487. #ifdef CONFIG_IWL3945_DEBUG
  3488. u32 inta_mask;
  3489. #endif
  3490. spin_lock_irqsave(&priv->lock, flags);
  3491. /* Ack/clear/reset pending uCode interrupts.
  3492. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3493. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3494. inta = iwl3945_read32(priv, CSR_INT);
  3495. iwl3945_write32(priv, CSR_INT, inta);
  3496. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3497. * Any new interrupts that happen after this, either while we're
  3498. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3499. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3500. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3501. #ifdef CONFIG_IWL3945_DEBUG
  3502. if (priv->debug_level & IWL_DL_ISR) {
  3503. /* just for debug */
  3504. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3505. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3506. inta, inta_mask, inta_fh);
  3507. }
  3508. #endif
  3509. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3510. * atomic, make sure that inta covers all the interrupts that
  3511. * we've discovered, even if FH interrupt came in just after
  3512. * reading CSR_INT. */
  3513. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3514. inta |= CSR_INT_BIT_FH_RX;
  3515. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3516. inta |= CSR_INT_BIT_FH_TX;
  3517. /* Now service all interrupt bits discovered above. */
  3518. if (inta & CSR_INT_BIT_HW_ERR) {
  3519. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3520. /* Tell the device to stop sending interrupts */
  3521. iwl3945_disable_interrupts(priv);
  3522. iwl3945_irq_handle_error(priv);
  3523. handled |= CSR_INT_BIT_HW_ERR;
  3524. spin_unlock_irqrestore(&priv->lock, flags);
  3525. return;
  3526. }
  3527. #ifdef CONFIG_IWL3945_DEBUG
  3528. if (priv->debug_level & (IWL_DL_ISR)) {
  3529. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3530. if (inta & CSR_INT_BIT_SCD)
  3531. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3532. "the frame/frames.\n");
  3533. /* Alive notification via Rx interrupt will do the real work */
  3534. if (inta & CSR_INT_BIT_ALIVE)
  3535. IWL_DEBUG_ISR("Alive interrupt\n");
  3536. }
  3537. #endif
  3538. /* Safely ignore these bits for debug checks below */
  3539. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3540. /* Error detected by uCode */
  3541. if (inta & CSR_INT_BIT_SW_ERR) {
  3542. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3543. inta);
  3544. iwl3945_irq_handle_error(priv);
  3545. handled |= CSR_INT_BIT_SW_ERR;
  3546. }
  3547. /* uCode wakes up after power-down sleep */
  3548. if (inta & CSR_INT_BIT_WAKEUP) {
  3549. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3550. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3551. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3552. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3553. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3554. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3555. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3556. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3557. handled |= CSR_INT_BIT_WAKEUP;
  3558. }
  3559. /* All uCode command responses, including Tx command responses,
  3560. * Rx "responses" (frame-received notification), and other
  3561. * notifications from uCode come through here*/
  3562. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3563. iwl3945_rx_handle(priv);
  3564. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3565. }
  3566. if (inta & CSR_INT_BIT_FH_TX) {
  3567. IWL_DEBUG_ISR("Tx interrupt\n");
  3568. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3569. if (!iwl3945_grab_nic_access(priv)) {
  3570. iwl3945_write_direct32(priv, FH39_TCSR_CREDIT
  3571. (FH39_SRVC_CHNL), 0x0);
  3572. iwl3945_release_nic_access(priv);
  3573. }
  3574. handled |= CSR_INT_BIT_FH_TX;
  3575. }
  3576. if (inta & ~handled)
  3577. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3578. if (inta & ~CSR_INI_SET_MASK) {
  3579. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3580. inta & ~CSR_INI_SET_MASK);
  3581. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3582. }
  3583. /* Re-enable all interrupts */
  3584. /* only Re-enable if disabled by irq */
  3585. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3586. iwl3945_enable_interrupts(priv);
  3587. #ifdef CONFIG_IWL3945_DEBUG
  3588. if (priv->debug_level & (IWL_DL_ISR)) {
  3589. inta = iwl3945_read32(priv, CSR_INT);
  3590. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3591. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3592. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3593. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3594. }
  3595. #endif
  3596. spin_unlock_irqrestore(&priv->lock, flags);
  3597. }
  3598. static irqreturn_t iwl3945_isr(int irq, void *data)
  3599. {
  3600. struct iwl3945_priv *priv = data;
  3601. u32 inta, inta_mask;
  3602. u32 inta_fh;
  3603. if (!priv)
  3604. return IRQ_NONE;
  3605. spin_lock(&priv->lock);
  3606. /* Disable (but don't clear!) interrupts here to avoid
  3607. * back-to-back ISRs and sporadic interrupts from our NIC.
  3608. * If we have something to service, the tasklet will re-enable ints.
  3609. * If we *don't* have something, we'll re-enable before leaving here. */
  3610. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3611. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3612. /* Discover which interrupts are active/pending */
  3613. inta = iwl3945_read32(priv, CSR_INT);
  3614. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3615. /* Ignore interrupt if there's nothing in NIC to service.
  3616. * This may be due to IRQ shared with another device,
  3617. * or due to sporadic interrupts thrown from our NIC. */
  3618. if (!inta && !inta_fh) {
  3619. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3620. goto none;
  3621. }
  3622. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3623. /* Hardware disappeared */
  3624. IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3625. goto unplugged;
  3626. }
  3627. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3628. inta, inta_mask, inta_fh);
  3629. inta &= ~CSR_INT_BIT_SCD;
  3630. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3631. if (likely(inta || inta_fh))
  3632. tasklet_schedule(&priv->irq_tasklet);
  3633. unplugged:
  3634. spin_unlock(&priv->lock);
  3635. return IRQ_HANDLED;
  3636. none:
  3637. /* re-enable interrupts here since we don't have anything to service. */
  3638. /* only Re-enable if disabled by irq */
  3639. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3640. iwl3945_enable_interrupts(priv);
  3641. spin_unlock(&priv->lock);
  3642. return IRQ_NONE;
  3643. }
  3644. /************************** EEPROM BANDS ****************************
  3645. *
  3646. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3647. * EEPROM contents to the specific channel number supported for each
  3648. * band.
  3649. *
  3650. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3651. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3652. * The specific geography and calibration information for that channel
  3653. * is contained in the eeprom map itself.
  3654. *
  3655. * During init, we copy the eeprom information and channel map
  3656. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3657. *
  3658. * channel_map_24/52 provides the index in the channel_info array for a
  3659. * given channel. We have to have two separate maps as there is channel
  3660. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3661. * band_2
  3662. *
  3663. * A value of 0xff stored in the channel_map indicates that the channel
  3664. * is not supported by the hardware at all.
  3665. *
  3666. * A value of 0xfe in the channel_map indicates that the channel is not
  3667. * valid for Tx with the current hardware. This means that
  3668. * while the system can tune and receive on a given channel, it may not
  3669. * be able to associate or transmit any frames on that
  3670. * channel. There is no corresponding channel information for that
  3671. * entry.
  3672. *
  3673. *********************************************************************/
  3674. /* 2.4 GHz */
  3675. static const u8 iwl3945_eeprom_band_1[14] = {
  3676. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3677. };
  3678. /* 5.2 GHz bands */
  3679. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3680. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3681. };
  3682. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3683. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3684. };
  3685. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3686. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3687. };
  3688. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3689. 145, 149, 153, 157, 161, 165
  3690. };
  3691. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3692. int *eeprom_ch_count,
  3693. const struct iwl_eeprom_channel
  3694. **eeprom_ch_info,
  3695. const u8 **eeprom_ch_index)
  3696. {
  3697. switch (band) {
  3698. case 1: /* 2.4GHz band */
  3699. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3700. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3701. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3702. break;
  3703. case 2: /* 4.9GHz band */
  3704. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3705. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3706. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3707. break;
  3708. case 3: /* 5.2GHz band */
  3709. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3710. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3711. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3712. break;
  3713. case 4: /* 5.5GHz band */
  3714. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3715. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3716. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3717. break;
  3718. case 5: /* 5.7GHz band */
  3719. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3720. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3721. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3722. break;
  3723. default:
  3724. BUG();
  3725. return;
  3726. }
  3727. }
  3728. /**
  3729. * iwl3945_get_channel_info - Find driver's private channel info
  3730. *
  3731. * Based on band and channel number.
  3732. */
  3733. const struct iwl_channel_info *
  3734. iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3735. enum ieee80211_band band, u16 channel)
  3736. {
  3737. int i;
  3738. switch (band) {
  3739. case IEEE80211_BAND_5GHZ:
  3740. for (i = 14; i < priv->channel_count; i++) {
  3741. if (priv->channel_info[i].channel == channel)
  3742. return &priv->channel_info[i];
  3743. }
  3744. break;
  3745. case IEEE80211_BAND_2GHZ:
  3746. if (channel >= 1 && channel <= 14)
  3747. return &priv->channel_info[channel - 1];
  3748. break;
  3749. case IEEE80211_NUM_BANDS:
  3750. WARN_ON(1);
  3751. }
  3752. return NULL;
  3753. }
  3754. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3755. ? # x " " : "")
  3756. /**
  3757. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3758. */
  3759. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3760. {
  3761. int eeprom_ch_count = 0;
  3762. const u8 *eeprom_ch_index = NULL;
  3763. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3764. int band, ch;
  3765. struct iwl_channel_info *ch_info;
  3766. if (priv->channel_count) {
  3767. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3768. return 0;
  3769. }
  3770. if (priv->eeprom.version < 0x2f) {
  3771. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3772. priv->eeprom.version);
  3773. return -EINVAL;
  3774. }
  3775. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3776. priv->channel_count =
  3777. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3778. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3779. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3780. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3781. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3782. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3783. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3784. priv->channel_count, GFP_KERNEL);
  3785. if (!priv->channel_info) {
  3786. IWL_ERROR("Could not allocate channel_info\n");
  3787. priv->channel_count = 0;
  3788. return -ENOMEM;
  3789. }
  3790. ch_info = priv->channel_info;
  3791. /* Loop through the 5 EEPROM bands adding them in order to the
  3792. * channel map we maintain (that contains additional information than
  3793. * what just in the EEPROM) */
  3794. for (band = 1; band <= 5; band++) {
  3795. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3796. &eeprom_ch_info, &eeprom_ch_index);
  3797. /* Loop through each band adding each of the channels */
  3798. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3799. ch_info->channel = eeprom_ch_index[ch];
  3800. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3801. IEEE80211_BAND_5GHZ;
  3802. /* permanently store EEPROM's channel regulatory flags
  3803. * and max power in channel info database. */
  3804. ch_info->eeprom = eeprom_ch_info[ch];
  3805. /* Copy the run-time flags so they are there even on
  3806. * invalid channels */
  3807. ch_info->flags = eeprom_ch_info[ch].flags;
  3808. if (!(is_channel_valid(ch_info))) {
  3809. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3810. "No traffic\n",
  3811. ch_info->channel,
  3812. ch_info->flags,
  3813. is_channel_a_band(ch_info) ?
  3814. "5.2" : "2.4");
  3815. ch_info++;
  3816. continue;
  3817. }
  3818. /* Initialize regulatory-based run-time data */
  3819. ch_info->max_power_avg = ch_info->curr_txpow =
  3820. eeprom_ch_info[ch].max_power_avg;
  3821. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3822. ch_info->min_power = 0;
  3823. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3824. " %ddBm): Ad-Hoc %ssupported\n",
  3825. ch_info->channel,
  3826. is_channel_a_band(ch_info) ?
  3827. "5.2" : "2.4",
  3828. CHECK_AND_PRINT(VALID),
  3829. CHECK_AND_PRINT(IBSS),
  3830. CHECK_AND_PRINT(ACTIVE),
  3831. CHECK_AND_PRINT(RADAR),
  3832. CHECK_AND_PRINT(WIDE),
  3833. CHECK_AND_PRINT(DFS),
  3834. eeprom_ch_info[ch].flags,
  3835. eeprom_ch_info[ch].max_power_avg,
  3836. ((eeprom_ch_info[ch].
  3837. flags & EEPROM_CHANNEL_IBSS)
  3838. && !(eeprom_ch_info[ch].
  3839. flags & EEPROM_CHANNEL_RADAR))
  3840. ? "" : "not ");
  3841. /* Set the user_txpower_limit to the highest power
  3842. * supported by any channel */
  3843. if (eeprom_ch_info[ch].max_power_avg >
  3844. priv->user_txpower_limit)
  3845. priv->user_txpower_limit =
  3846. eeprom_ch_info[ch].max_power_avg;
  3847. ch_info++;
  3848. }
  3849. }
  3850. /* Set up txpower settings in driver for all channels */
  3851. if (iwl3945_txpower_set_from_eeprom(priv))
  3852. return -EIO;
  3853. return 0;
  3854. }
  3855. /*
  3856. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3857. */
  3858. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  3859. {
  3860. kfree(priv->channel_info);
  3861. priv->channel_count = 0;
  3862. }
  3863. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3864. * sending probe req. This should be set long enough to hear probe responses
  3865. * from more than one AP. */
  3866. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3867. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3868. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3869. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3870. /* For faster active scanning, scan will move to the next channel if fewer than
  3871. * PLCP_QUIET_THRESH packets are heard on this channel within
  3872. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3873. * time if it's a quiet channel (nothing responded to our probe, and there's
  3874. * no other traffic).
  3875. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3876. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3877. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3878. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3879. * Must be set longer than active dwell time.
  3880. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3881. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3882. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3883. #define IWL_PASSIVE_DWELL_BASE (100)
  3884. #define IWL_CHANNEL_TUNE_TIME 5
  3885. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3886. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  3887. enum ieee80211_band band,
  3888. u8 n_probes)
  3889. {
  3890. if (band == IEEE80211_BAND_5GHZ)
  3891. return IWL_ACTIVE_DWELL_TIME_52 +
  3892. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3893. else
  3894. return IWL_ACTIVE_DWELL_TIME_24 +
  3895. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3896. }
  3897. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  3898. enum ieee80211_band band)
  3899. {
  3900. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3901. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3902. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3903. if (iwl3945_is_associated(priv)) {
  3904. /* If we're associated, we clamp the maximum passive
  3905. * dwell time to be 98% of the beacon interval (minus
  3906. * 2 * channel tune time) */
  3907. passive = priv->beacon_int;
  3908. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3909. passive = IWL_PASSIVE_DWELL_BASE;
  3910. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3911. }
  3912. return passive;
  3913. }
  3914. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  3915. enum ieee80211_band band,
  3916. u8 is_active, u8 n_probes,
  3917. struct iwl3945_scan_channel *scan_ch)
  3918. {
  3919. const struct ieee80211_channel *channels = NULL;
  3920. const struct ieee80211_supported_band *sband;
  3921. const struct iwl_channel_info *ch_info;
  3922. u16 passive_dwell = 0;
  3923. u16 active_dwell = 0;
  3924. int added, i;
  3925. sband = iwl3945_get_band(priv, band);
  3926. if (!sband)
  3927. return 0;
  3928. channels = sband->channels;
  3929. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3930. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3931. if (passive_dwell <= active_dwell)
  3932. passive_dwell = active_dwell + 1;
  3933. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3934. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3935. continue;
  3936. scan_ch->channel = channels[i].hw_value;
  3937. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3938. if (!is_channel_valid(ch_info)) {
  3939. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3940. scan_ch->channel);
  3941. continue;
  3942. }
  3943. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3944. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3945. /* If passive , set up for auto-switch
  3946. * and use long active_dwell time.
  3947. */
  3948. if (!is_active || is_channel_passive(ch_info) ||
  3949. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3950. scan_ch->type = 0; /* passive */
  3951. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3952. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3953. } else {
  3954. scan_ch->type = 1; /* active */
  3955. }
  3956. /* Set direct probe bits. These may be used both for active
  3957. * scan channels (probes gets sent right away),
  3958. * or for passive channels (probes get se sent only after
  3959. * hearing clear Rx packet).*/
  3960. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3961. if (n_probes)
  3962. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3963. } else {
  3964. /* uCode v1 does not allow setting direct probe bits on
  3965. * passive channel. */
  3966. if ((scan_ch->type & 1) && n_probes)
  3967. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3968. }
  3969. /* Set txpower levels to defaults */
  3970. scan_ch->tpc.dsp_atten = 110;
  3971. /* scan_pwr_info->tpc.dsp_atten; */
  3972. /*scan_pwr_info->tpc.tx_gain; */
  3973. if (band == IEEE80211_BAND_5GHZ)
  3974. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3975. else {
  3976. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3977. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3978. * power level:
  3979. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3980. */
  3981. }
  3982. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3983. scan_ch->channel,
  3984. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3985. (scan_ch->type & 1) ?
  3986. active_dwell : passive_dwell);
  3987. scan_ch++;
  3988. added++;
  3989. }
  3990. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3991. return added;
  3992. }
  3993. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  3994. struct ieee80211_rate *rates)
  3995. {
  3996. int i;
  3997. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3998. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3999. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4000. rates[i].hw_value_short = i;
  4001. rates[i].flags = 0;
  4002. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4003. /*
  4004. * If CCK != 1M then set short preamble rate flag.
  4005. */
  4006. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4007. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4008. }
  4009. }
  4010. }
  4011. /**
  4012. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4013. */
  4014. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4015. {
  4016. struct iwl_channel_info *ch;
  4017. struct ieee80211_supported_band *sband;
  4018. struct ieee80211_channel *channels;
  4019. struct ieee80211_channel *geo_ch;
  4020. struct ieee80211_rate *rates;
  4021. int i = 0;
  4022. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4023. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4024. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4025. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4026. return 0;
  4027. }
  4028. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4029. priv->channel_count, GFP_KERNEL);
  4030. if (!channels)
  4031. return -ENOMEM;
  4032. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4033. GFP_KERNEL);
  4034. if (!rates) {
  4035. kfree(channels);
  4036. return -ENOMEM;
  4037. }
  4038. /* 5.2GHz channels start after the 2.4GHz channels */
  4039. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4040. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4041. /* just OFDM */
  4042. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4043. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4044. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4045. sband->channels = channels;
  4046. /* OFDM & CCK */
  4047. sband->bitrates = rates;
  4048. sband->n_bitrates = IWL_RATE_COUNT;
  4049. priv->ieee_channels = channels;
  4050. priv->ieee_rates = rates;
  4051. iwl3945_init_hw_rates(priv, rates);
  4052. for (i = 0; i < priv->channel_count; i++) {
  4053. ch = &priv->channel_info[i];
  4054. /* FIXME: might be removed if scan is OK*/
  4055. if (!is_channel_valid(ch))
  4056. continue;
  4057. if (is_channel_a_band(ch))
  4058. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4059. else
  4060. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4061. geo_ch = &sband->channels[sband->n_channels++];
  4062. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4063. geo_ch->max_power = ch->max_power_avg;
  4064. geo_ch->max_antenna_gain = 0xff;
  4065. geo_ch->hw_value = ch->channel;
  4066. if (is_channel_valid(ch)) {
  4067. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4068. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4069. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4070. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4071. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4072. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4073. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4074. priv->max_channel_txpower_limit =
  4075. ch->max_power_avg;
  4076. } else {
  4077. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4078. }
  4079. /* Save flags for reg domain usage */
  4080. geo_ch->orig_flags = geo_ch->flags;
  4081. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4082. ch->channel, geo_ch->center_freq,
  4083. is_channel_a_band(ch) ? "5.2" : "2.4",
  4084. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4085. "restricted" : "valid",
  4086. geo_ch->flags);
  4087. }
  4088. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4089. priv->cfg->sku & IWL_SKU_A) {
  4090. printk(KERN_INFO DRV_NAME
  4091. ": Incorrectly detected BG card as ABG. Please send "
  4092. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4093. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4094. priv->cfg->sku &= ~IWL_SKU_A;
  4095. }
  4096. printk(KERN_INFO DRV_NAME
  4097. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4098. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4099. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4100. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4101. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4102. &priv->bands[IEEE80211_BAND_2GHZ];
  4103. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4104. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4105. &priv->bands[IEEE80211_BAND_5GHZ];
  4106. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4107. return 0;
  4108. }
  4109. /*
  4110. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4111. */
  4112. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4113. {
  4114. kfree(priv->ieee_channels);
  4115. kfree(priv->ieee_rates);
  4116. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4117. }
  4118. /******************************************************************************
  4119. *
  4120. * uCode download functions
  4121. *
  4122. ******************************************************************************/
  4123. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4124. {
  4125. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4126. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4127. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4128. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4129. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4130. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4131. }
  4132. /**
  4133. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4134. * looking at all data.
  4135. */
  4136. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4137. {
  4138. u32 val;
  4139. u32 save_len = len;
  4140. int rc = 0;
  4141. u32 errcnt;
  4142. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4143. rc = iwl3945_grab_nic_access(priv);
  4144. if (rc)
  4145. return rc;
  4146. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4147. IWL39_RTC_INST_LOWER_BOUND);
  4148. errcnt = 0;
  4149. for (; len > 0; len -= sizeof(u32), image++) {
  4150. /* read data comes through single port, auto-incr addr */
  4151. /* NOTE: Use the debugless read so we don't flood kernel log
  4152. * if IWL_DL_IO is set */
  4153. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4154. if (val != le32_to_cpu(*image)) {
  4155. IWL_ERROR("uCode INST section is invalid at "
  4156. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4157. save_len - len, val, le32_to_cpu(*image));
  4158. rc = -EIO;
  4159. errcnt++;
  4160. if (errcnt >= 20)
  4161. break;
  4162. }
  4163. }
  4164. iwl3945_release_nic_access(priv);
  4165. if (!errcnt)
  4166. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4167. return rc;
  4168. }
  4169. /**
  4170. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4171. * using sample data 100 bytes apart. If these sample points are good,
  4172. * it's a pretty good bet that everything between them is good, too.
  4173. */
  4174. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4175. {
  4176. u32 val;
  4177. int rc = 0;
  4178. u32 errcnt = 0;
  4179. u32 i;
  4180. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4181. rc = iwl3945_grab_nic_access(priv);
  4182. if (rc)
  4183. return rc;
  4184. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4185. /* read data comes through single port, auto-incr addr */
  4186. /* NOTE: Use the debugless read so we don't flood kernel log
  4187. * if IWL_DL_IO is set */
  4188. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4189. i + IWL39_RTC_INST_LOWER_BOUND);
  4190. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4191. if (val != le32_to_cpu(*image)) {
  4192. #if 0 /* Enable this if you want to see details */
  4193. IWL_ERROR("uCode INST section is invalid at "
  4194. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4195. i, val, *image);
  4196. #endif
  4197. rc = -EIO;
  4198. errcnt++;
  4199. if (errcnt >= 3)
  4200. break;
  4201. }
  4202. }
  4203. iwl3945_release_nic_access(priv);
  4204. return rc;
  4205. }
  4206. /**
  4207. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4208. * and verify its contents
  4209. */
  4210. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4211. {
  4212. __le32 *image;
  4213. u32 len;
  4214. int rc = 0;
  4215. /* Try bootstrap */
  4216. image = (__le32 *)priv->ucode_boot.v_addr;
  4217. len = priv->ucode_boot.len;
  4218. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4219. if (rc == 0) {
  4220. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4221. return 0;
  4222. }
  4223. /* Try initialize */
  4224. image = (__le32 *)priv->ucode_init.v_addr;
  4225. len = priv->ucode_init.len;
  4226. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4227. if (rc == 0) {
  4228. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4229. return 0;
  4230. }
  4231. /* Try runtime/protocol */
  4232. image = (__le32 *)priv->ucode_code.v_addr;
  4233. len = priv->ucode_code.len;
  4234. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4235. if (rc == 0) {
  4236. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4237. return 0;
  4238. }
  4239. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4240. /* Since nothing seems to match, show first several data entries in
  4241. * instruction SRAM, so maybe visual inspection will give a clue.
  4242. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4243. image = (__le32 *)priv->ucode_boot.v_addr;
  4244. len = priv->ucode_boot.len;
  4245. rc = iwl3945_verify_inst_full(priv, image, len);
  4246. return rc;
  4247. }
  4248. /* check contents of special bootstrap uCode SRAM */
  4249. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4250. {
  4251. __le32 *image = priv->ucode_boot.v_addr;
  4252. u32 len = priv->ucode_boot.len;
  4253. u32 reg;
  4254. u32 val;
  4255. IWL_DEBUG_INFO("Begin verify bsm\n");
  4256. /* verify BSM SRAM contents */
  4257. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4258. for (reg = BSM_SRAM_LOWER_BOUND;
  4259. reg < BSM_SRAM_LOWER_BOUND + len;
  4260. reg += sizeof(u32), image++) {
  4261. val = iwl3945_read_prph(priv, reg);
  4262. if (val != le32_to_cpu(*image)) {
  4263. IWL_ERROR("BSM uCode verification failed at "
  4264. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4265. BSM_SRAM_LOWER_BOUND,
  4266. reg - BSM_SRAM_LOWER_BOUND, len,
  4267. val, le32_to_cpu(*image));
  4268. return -EIO;
  4269. }
  4270. }
  4271. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4272. return 0;
  4273. }
  4274. /**
  4275. * iwl3945_load_bsm - Load bootstrap instructions
  4276. *
  4277. * BSM operation:
  4278. *
  4279. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4280. * in special SRAM that does not power down during RFKILL. When powering back
  4281. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4282. * the bootstrap program into the on-board processor, and starts it.
  4283. *
  4284. * The bootstrap program loads (via DMA) instructions and data for a new
  4285. * program from host DRAM locations indicated by the host driver in the
  4286. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4287. * automatically.
  4288. *
  4289. * When initializing the NIC, the host driver points the BSM to the
  4290. * "initialize" uCode image. This uCode sets up some internal data, then
  4291. * notifies host via "initialize alive" that it is complete.
  4292. *
  4293. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4294. * normal runtime uCode instructions and a backup uCode data cache buffer
  4295. * (filled initially with starting data values for the on-board processor),
  4296. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4297. * which begins normal operation.
  4298. *
  4299. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4300. * the backup data cache in DRAM before SRAM is powered down.
  4301. *
  4302. * When powering back up, the BSM loads the bootstrap program. This reloads
  4303. * the runtime uCode instructions and the backup data cache into SRAM,
  4304. * and re-launches the runtime uCode from where it left off.
  4305. */
  4306. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4307. {
  4308. __le32 *image = priv->ucode_boot.v_addr;
  4309. u32 len = priv->ucode_boot.len;
  4310. dma_addr_t pinst;
  4311. dma_addr_t pdata;
  4312. u32 inst_len;
  4313. u32 data_len;
  4314. int rc;
  4315. int i;
  4316. u32 done;
  4317. u32 reg_offset;
  4318. IWL_DEBUG_INFO("Begin load bsm\n");
  4319. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4320. if (len > IWL39_MAX_BSM_SIZE)
  4321. return -EINVAL;
  4322. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4323. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4324. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4325. * after the "initialize" uCode has run, to point to
  4326. * runtime/protocol instructions and backup data cache. */
  4327. pinst = priv->ucode_init.p_addr;
  4328. pdata = priv->ucode_init_data.p_addr;
  4329. inst_len = priv->ucode_init.len;
  4330. data_len = priv->ucode_init_data.len;
  4331. rc = iwl3945_grab_nic_access(priv);
  4332. if (rc)
  4333. return rc;
  4334. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4335. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4336. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4337. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4338. /* Fill BSM memory with bootstrap instructions */
  4339. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4340. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4341. reg_offset += sizeof(u32), image++)
  4342. _iwl3945_write_prph(priv, reg_offset,
  4343. le32_to_cpu(*image));
  4344. rc = iwl3945_verify_bsm(priv);
  4345. if (rc) {
  4346. iwl3945_release_nic_access(priv);
  4347. return rc;
  4348. }
  4349. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4350. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4351. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4352. IWL39_RTC_INST_LOWER_BOUND);
  4353. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4354. /* Load bootstrap code into instruction SRAM now,
  4355. * to prepare to load "initialize" uCode */
  4356. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4357. BSM_WR_CTRL_REG_BIT_START);
  4358. /* Wait for load of bootstrap uCode to finish */
  4359. for (i = 0; i < 100; i++) {
  4360. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4361. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4362. break;
  4363. udelay(10);
  4364. }
  4365. if (i < 100)
  4366. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4367. else {
  4368. IWL_ERROR("BSM write did not complete!\n");
  4369. return -EIO;
  4370. }
  4371. /* Enable future boot loads whenever power management unit triggers it
  4372. * (e.g. when powering back up after power-save shutdown) */
  4373. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4374. BSM_WR_CTRL_REG_BIT_START_EN);
  4375. iwl3945_release_nic_access(priv);
  4376. return 0;
  4377. }
  4378. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4379. {
  4380. /* Remove all resets to allow NIC to operate */
  4381. iwl3945_write32(priv, CSR_RESET, 0);
  4382. }
  4383. /**
  4384. * iwl3945_read_ucode - Read uCode images from disk file.
  4385. *
  4386. * Copy into buffers for card to fetch via bus-mastering
  4387. */
  4388. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4389. {
  4390. struct iwl3945_ucode *ucode;
  4391. int ret = -EINVAL, index;
  4392. const struct firmware *ucode_raw;
  4393. /* firmware file name contains uCode/driver compatibility version */
  4394. const char *name_pre = priv->cfg->fw_name_pre;
  4395. const unsigned int api_max = priv->cfg->ucode_api_max;
  4396. const unsigned int api_min = priv->cfg->ucode_api_min;
  4397. char buf[25];
  4398. u8 *src;
  4399. size_t len;
  4400. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4401. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4402. * request_firmware() is synchronous, file is in memory on return. */
  4403. for (index = api_max; index >= api_min; index--) {
  4404. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4405. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4406. if (ret < 0) {
  4407. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4408. buf, ret);
  4409. if (ret == -ENOENT)
  4410. continue;
  4411. else
  4412. goto error;
  4413. } else {
  4414. if (index < api_max)
  4415. IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
  4416. buf, api_max);
  4417. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4418. buf, ucode_raw->size);
  4419. break;
  4420. }
  4421. }
  4422. if (ret < 0)
  4423. goto error;
  4424. /* Make sure that we got at least our header! */
  4425. if (ucode_raw->size < sizeof(*ucode)) {
  4426. IWL_ERROR("File size way too small!\n");
  4427. ret = -EINVAL;
  4428. goto err_release;
  4429. }
  4430. /* Data from ucode file: header followed by uCode images */
  4431. ucode = (void *)ucode_raw->data;
  4432. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4433. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4434. inst_size = le32_to_cpu(ucode->inst_size);
  4435. data_size = le32_to_cpu(ucode->data_size);
  4436. init_size = le32_to_cpu(ucode->init_size);
  4437. init_data_size = le32_to_cpu(ucode->init_data_size);
  4438. boot_size = le32_to_cpu(ucode->boot_size);
  4439. /* api_ver should match the api version forming part of the
  4440. * firmware filename ... but we don't check for that and only rely
  4441. * on the API version read from firware header from here on forward */
  4442. if (api_ver < api_min || api_ver > api_max) {
  4443. IWL_ERROR("Driver unable to support your firmware API. "
  4444. "Driver supports v%u, firmware is v%u.\n",
  4445. api_max, api_ver);
  4446. priv->ucode_ver = 0;
  4447. ret = -EINVAL;
  4448. goto err_release;
  4449. }
  4450. if (api_ver != api_max)
  4451. IWL_ERROR("Firmware has old API version. Expected %u, "
  4452. "got %u. New firmware can be obtained "
  4453. "from http://www.intellinuxwireless.org.\n",
  4454. api_max, api_ver);
  4455. printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
  4456. IWL_UCODE_MAJOR(priv->ucode_ver),
  4457. IWL_UCODE_MINOR(priv->ucode_ver),
  4458. IWL_UCODE_API(priv->ucode_ver),
  4459. IWL_UCODE_SERIAL(priv->ucode_ver));
  4460. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4461. priv->ucode_ver);
  4462. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4463. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4464. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4465. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4466. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4467. /* Verify size of file vs. image size info in file's header */
  4468. if (ucode_raw->size < sizeof(*ucode) +
  4469. inst_size + data_size + init_size +
  4470. init_data_size + boot_size) {
  4471. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4472. (int)ucode_raw->size);
  4473. ret = -EINVAL;
  4474. goto err_release;
  4475. }
  4476. /* Verify that uCode images will fit in card's SRAM */
  4477. if (inst_size > IWL39_MAX_INST_SIZE) {
  4478. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4479. inst_size);
  4480. ret = -EINVAL;
  4481. goto err_release;
  4482. }
  4483. if (data_size > IWL39_MAX_DATA_SIZE) {
  4484. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4485. data_size);
  4486. ret = -EINVAL;
  4487. goto err_release;
  4488. }
  4489. if (init_size > IWL39_MAX_INST_SIZE) {
  4490. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4491. init_size);
  4492. ret = -EINVAL;
  4493. goto err_release;
  4494. }
  4495. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4496. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4497. init_data_size);
  4498. ret = -EINVAL;
  4499. goto err_release;
  4500. }
  4501. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4502. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4503. boot_size);
  4504. ret = -EINVAL;
  4505. goto err_release;
  4506. }
  4507. /* Allocate ucode buffers for card's bus-master loading ... */
  4508. /* Runtime instructions and 2 copies of data:
  4509. * 1) unmodified from disk
  4510. * 2) backup cache for save/restore during power-downs */
  4511. priv->ucode_code.len = inst_size;
  4512. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4513. priv->ucode_data.len = data_size;
  4514. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4515. priv->ucode_data_backup.len = data_size;
  4516. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4517. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4518. !priv->ucode_data_backup.v_addr)
  4519. goto err_pci_alloc;
  4520. /* Initialization instructions and data */
  4521. if (init_size && init_data_size) {
  4522. priv->ucode_init.len = init_size;
  4523. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4524. priv->ucode_init_data.len = init_data_size;
  4525. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4526. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4527. goto err_pci_alloc;
  4528. }
  4529. /* Bootstrap (instructions only, no data) */
  4530. if (boot_size) {
  4531. priv->ucode_boot.len = boot_size;
  4532. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4533. if (!priv->ucode_boot.v_addr)
  4534. goto err_pci_alloc;
  4535. }
  4536. /* Copy images into buffers for card's bus-master reads ... */
  4537. /* Runtime instructions (first block of data in file) */
  4538. src = &ucode->data[0];
  4539. len = priv->ucode_code.len;
  4540. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4541. memcpy(priv->ucode_code.v_addr, src, len);
  4542. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4543. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4544. /* Runtime data (2nd block)
  4545. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4546. src = &ucode->data[inst_size];
  4547. len = priv->ucode_data.len;
  4548. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4549. memcpy(priv->ucode_data.v_addr, src, len);
  4550. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4551. /* Initialization instructions (3rd block) */
  4552. if (init_size) {
  4553. src = &ucode->data[inst_size + data_size];
  4554. len = priv->ucode_init.len;
  4555. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4556. len);
  4557. memcpy(priv->ucode_init.v_addr, src, len);
  4558. }
  4559. /* Initialization data (4th block) */
  4560. if (init_data_size) {
  4561. src = &ucode->data[inst_size + data_size + init_size];
  4562. len = priv->ucode_init_data.len;
  4563. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4564. (int)len);
  4565. memcpy(priv->ucode_init_data.v_addr, src, len);
  4566. }
  4567. /* Bootstrap instructions (5th block) */
  4568. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4569. len = priv->ucode_boot.len;
  4570. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4571. (int)len);
  4572. memcpy(priv->ucode_boot.v_addr, src, len);
  4573. /* We have our copies now, allow OS release its copies */
  4574. release_firmware(ucode_raw);
  4575. return 0;
  4576. err_pci_alloc:
  4577. IWL_ERROR("failed to allocate pci memory\n");
  4578. ret = -ENOMEM;
  4579. iwl3945_dealloc_ucode_pci(priv);
  4580. err_release:
  4581. release_firmware(ucode_raw);
  4582. error:
  4583. return ret;
  4584. }
  4585. /**
  4586. * iwl3945_set_ucode_ptrs - Set uCode address location
  4587. *
  4588. * Tell initialization uCode where to find runtime uCode.
  4589. *
  4590. * BSM registers initially contain pointers to initialization uCode.
  4591. * We need to replace them to load runtime uCode inst and data,
  4592. * and to save runtime data when powering down.
  4593. */
  4594. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4595. {
  4596. dma_addr_t pinst;
  4597. dma_addr_t pdata;
  4598. int rc = 0;
  4599. unsigned long flags;
  4600. /* bits 31:0 for 3945 */
  4601. pinst = priv->ucode_code.p_addr;
  4602. pdata = priv->ucode_data_backup.p_addr;
  4603. spin_lock_irqsave(&priv->lock, flags);
  4604. rc = iwl3945_grab_nic_access(priv);
  4605. if (rc) {
  4606. spin_unlock_irqrestore(&priv->lock, flags);
  4607. return rc;
  4608. }
  4609. /* Tell bootstrap uCode where to find image to load */
  4610. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4611. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4612. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4613. priv->ucode_data.len);
  4614. /* Inst byte count must be last to set up, bit 31 signals uCode
  4615. * that all new ptr/size info is in place */
  4616. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4617. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4618. iwl3945_release_nic_access(priv);
  4619. spin_unlock_irqrestore(&priv->lock, flags);
  4620. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4621. return rc;
  4622. }
  4623. /**
  4624. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4625. *
  4626. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4627. *
  4628. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4629. */
  4630. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4631. {
  4632. /* Check alive response for "valid" sign from uCode */
  4633. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4634. /* We had an error bringing up the hardware, so take it
  4635. * all the way back down so we can try again */
  4636. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4637. goto restart;
  4638. }
  4639. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4640. * This is a paranoid check, because we would not have gotten the
  4641. * "initialize" alive if code weren't properly loaded. */
  4642. if (iwl3945_verify_ucode(priv)) {
  4643. /* Runtime instruction load was bad;
  4644. * take it all the way back down so we can try again */
  4645. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4646. goto restart;
  4647. }
  4648. /* Send pointers to protocol/runtime uCode image ... init code will
  4649. * load and launch runtime uCode, which will send us another "Alive"
  4650. * notification. */
  4651. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4652. if (iwl3945_set_ucode_ptrs(priv)) {
  4653. /* Runtime instruction load won't happen;
  4654. * take it all the way back down so we can try again */
  4655. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4656. goto restart;
  4657. }
  4658. return;
  4659. restart:
  4660. queue_work(priv->workqueue, &priv->restart);
  4661. }
  4662. /* temporary */
  4663. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4664. struct sk_buff *skb);
  4665. /**
  4666. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4667. * from protocol/runtime uCode (initialization uCode's
  4668. * Alive gets handled by iwl3945_init_alive_start()).
  4669. */
  4670. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4671. {
  4672. int rc = 0;
  4673. int thermal_spin = 0;
  4674. u32 rfkill;
  4675. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4676. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4677. /* We had an error bringing up the hardware, so take it
  4678. * all the way back down so we can try again */
  4679. IWL_DEBUG_INFO("Alive failed.\n");
  4680. goto restart;
  4681. }
  4682. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4683. * This is a paranoid check, because we would not have gotten the
  4684. * "runtime" alive if code weren't properly loaded. */
  4685. if (iwl3945_verify_ucode(priv)) {
  4686. /* Runtime instruction load was bad;
  4687. * take it all the way back down so we can try again */
  4688. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4689. goto restart;
  4690. }
  4691. iwl3945_clear_stations_table(priv);
  4692. rc = iwl3945_grab_nic_access(priv);
  4693. if (rc) {
  4694. IWL_WARNING("Can not read RFKILL status from adapter\n");
  4695. return;
  4696. }
  4697. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4698. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4699. iwl3945_release_nic_access(priv);
  4700. if (rfkill & 0x1) {
  4701. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4702. /* if RFKILL is not on, then wait for thermal
  4703. * sensor in adapter to kick in */
  4704. while (iwl3945_hw_get_temperature(priv) == 0) {
  4705. thermal_spin++;
  4706. udelay(10);
  4707. }
  4708. if (thermal_spin)
  4709. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4710. thermal_spin * 10);
  4711. } else
  4712. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4713. /* After the ALIVE response, we can send commands to 3945 uCode */
  4714. set_bit(STATUS_ALIVE, &priv->status);
  4715. /* Clear out the uCode error bit if it is set */
  4716. clear_bit(STATUS_FW_ERROR, &priv->status);
  4717. if (iwl3945_is_rfkill(priv))
  4718. return;
  4719. ieee80211_wake_queues(priv->hw);
  4720. priv->active_rate = priv->rates_mask;
  4721. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4722. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4723. if (iwl3945_is_associated(priv)) {
  4724. struct iwl3945_rxon_cmd *active_rxon =
  4725. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4726. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4727. sizeof(priv->staging_rxon));
  4728. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4729. } else {
  4730. /* Initialize our rx_config data */
  4731. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4732. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4733. }
  4734. /* Configure Bluetooth device coexistence support */
  4735. iwl3945_send_bt_config(priv);
  4736. /* Configure the adapter for unassociated operation */
  4737. iwl3945_commit_rxon(priv);
  4738. iwl3945_reg_txpower_periodic(priv);
  4739. iwl3945_led_register(priv);
  4740. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4741. set_bit(STATUS_READY, &priv->status);
  4742. wake_up_interruptible(&priv->wait_command_queue);
  4743. if (priv->error_recovering)
  4744. iwl3945_error_recovery(priv);
  4745. /* reassociate for ADHOC mode */
  4746. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4747. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4748. priv->vif);
  4749. if (beacon)
  4750. iwl3945_mac_beacon_update(priv->hw, beacon);
  4751. }
  4752. return;
  4753. restart:
  4754. queue_work(priv->workqueue, &priv->restart);
  4755. }
  4756. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4757. static void __iwl3945_down(struct iwl3945_priv *priv)
  4758. {
  4759. unsigned long flags;
  4760. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4761. struct ieee80211_conf *conf = NULL;
  4762. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4763. conf = ieee80211_get_hw_conf(priv->hw);
  4764. if (!exit_pending)
  4765. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4766. iwl3945_led_unregister(priv);
  4767. iwl3945_clear_stations_table(priv);
  4768. /* Unblock any waiting calls */
  4769. wake_up_interruptible_all(&priv->wait_command_queue);
  4770. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4771. * exiting the module */
  4772. if (!exit_pending)
  4773. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4774. /* stop and reset the on-board processor */
  4775. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4776. /* tell the device to stop sending interrupts */
  4777. spin_lock_irqsave(&priv->lock, flags);
  4778. iwl3945_disable_interrupts(priv);
  4779. spin_unlock_irqrestore(&priv->lock, flags);
  4780. iwl_synchronize_irq(priv);
  4781. if (priv->mac80211_registered)
  4782. ieee80211_stop_queues(priv->hw);
  4783. /* If we have not previously called iwl3945_init() then
  4784. * clear all bits but the RF Kill and SUSPEND bits and return */
  4785. if (!iwl3945_is_init(priv)) {
  4786. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4787. STATUS_RF_KILL_HW |
  4788. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4789. STATUS_RF_KILL_SW |
  4790. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4791. STATUS_GEO_CONFIGURED |
  4792. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4793. STATUS_IN_SUSPEND |
  4794. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4795. STATUS_EXIT_PENDING;
  4796. goto exit;
  4797. }
  4798. /* ...otherwise clear out all the status bits but the RF Kill and
  4799. * SUSPEND bits and continue taking the NIC down. */
  4800. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4801. STATUS_RF_KILL_HW |
  4802. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4803. STATUS_RF_KILL_SW |
  4804. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4805. STATUS_GEO_CONFIGURED |
  4806. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4807. STATUS_IN_SUSPEND |
  4808. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4809. STATUS_FW_ERROR |
  4810. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4811. STATUS_EXIT_PENDING;
  4812. spin_lock_irqsave(&priv->lock, flags);
  4813. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4814. spin_unlock_irqrestore(&priv->lock, flags);
  4815. iwl3945_hw_txq_ctx_stop(priv);
  4816. iwl3945_hw_rxq_stop(priv);
  4817. spin_lock_irqsave(&priv->lock, flags);
  4818. if (!iwl3945_grab_nic_access(priv)) {
  4819. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4820. APMG_CLK_VAL_DMA_CLK_RQT);
  4821. iwl3945_release_nic_access(priv);
  4822. }
  4823. spin_unlock_irqrestore(&priv->lock, flags);
  4824. udelay(5);
  4825. iwl3945_hw_nic_stop_master(priv);
  4826. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4827. iwl3945_hw_nic_reset(priv);
  4828. exit:
  4829. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4830. if (priv->ibss_beacon)
  4831. dev_kfree_skb(priv->ibss_beacon);
  4832. priv->ibss_beacon = NULL;
  4833. /* clear out any free frames */
  4834. iwl3945_clear_free_frames(priv);
  4835. }
  4836. static void iwl3945_down(struct iwl3945_priv *priv)
  4837. {
  4838. mutex_lock(&priv->mutex);
  4839. __iwl3945_down(priv);
  4840. mutex_unlock(&priv->mutex);
  4841. iwl3945_cancel_deferred_work(priv);
  4842. }
  4843. #define MAX_HW_RESTARTS 5
  4844. static int __iwl3945_up(struct iwl3945_priv *priv)
  4845. {
  4846. int rc, i;
  4847. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4848. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4849. return -EIO;
  4850. }
  4851. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4852. IWL_WARNING("Radio disabled by SW RF kill (module "
  4853. "parameter)\n");
  4854. return -ENODEV;
  4855. }
  4856. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4857. IWL_ERROR("ucode not available for device bring up\n");
  4858. return -EIO;
  4859. }
  4860. /* If platform's RF_KILL switch is NOT set to KILL */
  4861. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4862. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4863. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4864. else {
  4865. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4866. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4867. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4868. return -ENODEV;
  4869. }
  4870. }
  4871. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4872. rc = iwl3945_hw_nic_init(priv);
  4873. if (rc) {
  4874. IWL_ERROR("Unable to int nic\n");
  4875. return rc;
  4876. }
  4877. /* make sure rfkill handshake bits are cleared */
  4878. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4879. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4880. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4881. /* clear (again), then enable host interrupts */
  4882. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4883. iwl3945_enable_interrupts(priv);
  4884. /* really make sure rfkill handshake bits are cleared */
  4885. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4886. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4887. /* Copy original ucode data image from disk into backup cache.
  4888. * This will be used to initialize the on-board processor's
  4889. * data SRAM for a clean start when the runtime program first loads. */
  4890. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4891. priv->ucode_data.len);
  4892. /* We return success when we resume from suspend and rf_kill is on. */
  4893. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4894. return 0;
  4895. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4896. iwl3945_clear_stations_table(priv);
  4897. /* load bootstrap state machine,
  4898. * load bootstrap program into processor's memory,
  4899. * prepare to load the "initialize" uCode */
  4900. rc = iwl3945_load_bsm(priv);
  4901. if (rc) {
  4902. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4903. continue;
  4904. }
  4905. /* start card; "initialize" will load runtime ucode */
  4906. iwl3945_nic_start(priv);
  4907. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4908. return 0;
  4909. }
  4910. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4911. __iwl3945_down(priv);
  4912. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4913. /* tried to restart and config the device for as long as our
  4914. * patience could withstand */
  4915. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4916. return -EIO;
  4917. }
  4918. /*****************************************************************************
  4919. *
  4920. * Workqueue callbacks
  4921. *
  4922. *****************************************************************************/
  4923. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4924. {
  4925. struct iwl3945_priv *priv =
  4926. container_of(data, struct iwl3945_priv, init_alive_start.work);
  4927. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4928. return;
  4929. mutex_lock(&priv->mutex);
  4930. iwl3945_init_alive_start(priv);
  4931. mutex_unlock(&priv->mutex);
  4932. }
  4933. static void iwl3945_bg_alive_start(struct work_struct *data)
  4934. {
  4935. struct iwl3945_priv *priv =
  4936. container_of(data, struct iwl3945_priv, alive_start.work);
  4937. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4938. return;
  4939. mutex_lock(&priv->mutex);
  4940. iwl3945_alive_start(priv);
  4941. mutex_unlock(&priv->mutex);
  4942. }
  4943. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4944. {
  4945. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  4946. wake_up_interruptible(&priv->wait_command_queue);
  4947. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4948. return;
  4949. mutex_lock(&priv->mutex);
  4950. if (!iwl3945_is_rfkill(priv)) {
  4951. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4952. "HW and/or SW RF Kill no longer active, restarting "
  4953. "device\n");
  4954. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4955. queue_work(priv->workqueue, &priv->restart);
  4956. } else {
  4957. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4958. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4959. "disabled by SW switch\n");
  4960. else
  4961. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  4962. "Kill switch must be turned off for "
  4963. "wireless networking to work.\n");
  4964. }
  4965. mutex_unlock(&priv->mutex);
  4966. iwl3945_rfkill_set_hw_state(priv);
  4967. }
  4968. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4969. static void iwl3945_bg_scan_check(struct work_struct *data)
  4970. {
  4971. struct iwl3945_priv *priv =
  4972. container_of(data, struct iwl3945_priv, scan_check.work);
  4973. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4974. return;
  4975. mutex_lock(&priv->mutex);
  4976. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4977. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4978. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4979. "Scan completion watchdog resetting adapter (%dms)\n",
  4980. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4981. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4982. iwl3945_send_scan_abort(priv);
  4983. }
  4984. mutex_unlock(&priv->mutex);
  4985. }
  4986. static void iwl3945_bg_request_scan(struct work_struct *data)
  4987. {
  4988. struct iwl3945_priv *priv =
  4989. container_of(data, struct iwl3945_priv, request_scan);
  4990. struct iwl3945_host_cmd cmd = {
  4991. .id = REPLY_SCAN_CMD,
  4992. .len = sizeof(struct iwl3945_scan_cmd),
  4993. .meta.flags = CMD_SIZE_HUGE,
  4994. };
  4995. int rc = 0;
  4996. struct iwl3945_scan_cmd *scan;
  4997. struct ieee80211_conf *conf = NULL;
  4998. u8 n_probes = 2;
  4999. enum ieee80211_band band;
  5000. DECLARE_SSID_BUF(ssid);
  5001. conf = ieee80211_get_hw_conf(priv->hw);
  5002. mutex_lock(&priv->mutex);
  5003. if (!iwl3945_is_ready(priv)) {
  5004. IWL_WARNING("request scan called when driver not ready.\n");
  5005. goto done;
  5006. }
  5007. /* Make sure the scan wasn't canceled before this queued work
  5008. * was given the chance to run... */
  5009. if (!test_bit(STATUS_SCANNING, &priv->status))
  5010. goto done;
  5011. /* This should never be called or scheduled if there is currently
  5012. * a scan active in the hardware. */
  5013. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5014. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5015. "Ignoring second request.\n");
  5016. rc = -EIO;
  5017. goto done;
  5018. }
  5019. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5020. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5021. goto done;
  5022. }
  5023. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5024. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5025. goto done;
  5026. }
  5027. if (iwl3945_is_rfkill(priv)) {
  5028. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5029. goto done;
  5030. }
  5031. if (!test_bit(STATUS_READY, &priv->status)) {
  5032. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5033. goto done;
  5034. }
  5035. if (!priv->scan_bands) {
  5036. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5037. goto done;
  5038. }
  5039. if (!priv->scan) {
  5040. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5041. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5042. if (!priv->scan) {
  5043. rc = -ENOMEM;
  5044. goto done;
  5045. }
  5046. }
  5047. scan = priv->scan;
  5048. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5049. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5050. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5051. if (iwl3945_is_associated(priv)) {
  5052. u16 interval = 0;
  5053. u32 extra;
  5054. u32 suspend_time = 100;
  5055. u32 scan_suspend_time = 100;
  5056. unsigned long flags;
  5057. IWL_DEBUG_INFO("Scanning while associated...\n");
  5058. spin_lock_irqsave(&priv->lock, flags);
  5059. interval = priv->beacon_int;
  5060. spin_unlock_irqrestore(&priv->lock, flags);
  5061. scan->suspend_time = 0;
  5062. scan->max_out_time = cpu_to_le32(200 * 1024);
  5063. if (!interval)
  5064. interval = suspend_time;
  5065. /*
  5066. * suspend time format:
  5067. * 0-19: beacon interval in usec (time before exec.)
  5068. * 20-23: 0
  5069. * 24-31: number of beacons (suspend between channels)
  5070. */
  5071. extra = (suspend_time / interval) << 24;
  5072. scan_suspend_time = 0xFF0FFFFF &
  5073. (extra | ((suspend_time % interval) * 1024));
  5074. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5075. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5076. scan_suspend_time, interval);
  5077. }
  5078. /* We should add the ability for user to lock to PASSIVE ONLY */
  5079. if (priv->one_direct_scan) {
  5080. IWL_DEBUG_SCAN
  5081. ("Kicking off one direct scan for '%s'\n",
  5082. print_ssid(ssid, priv->direct_ssid,
  5083. priv->direct_ssid_len));
  5084. scan->direct_scan[0].id = WLAN_EID_SSID;
  5085. scan->direct_scan[0].len = priv->direct_ssid_len;
  5086. memcpy(scan->direct_scan[0].ssid,
  5087. priv->direct_ssid, priv->direct_ssid_len);
  5088. n_probes++;
  5089. } else
  5090. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5091. /* We don't build a direct scan probe request; the uCode will do
  5092. * that based on the direct_mask added to each channel entry */
  5093. scan->tx_cmd.len = cpu_to_le16(
  5094. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5095. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  5096. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5097. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5098. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5099. /* flags + rate selection */
  5100. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5101. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5102. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5103. scan->good_CRC_th = 0;
  5104. band = IEEE80211_BAND_2GHZ;
  5105. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5106. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5107. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5108. band = IEEE80211_BAND_5GHZ;
  5109. } else {
  5110. IWL_WARNING("Invalid scan band count\n");
  5111. goto done;
  5112. }
  5113. /* select Rx antennas */
  5114. scan->flags |= iwl3945_get_antenna_flags(priv);
  5115. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5116. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5117. scan->channel_count =
  5118. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5119. n_probes,
  5120. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5121. if (scan->channel_count == 0) {
  5122. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5123. goto done;
  5124. }
  5125. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5126. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5127. cmd.data = scan;
  5128. scan->len = cpu_to_le16(cmd.len);
  5129. set_bit(STATUS_SCAN_HW, &priv->status);
  5130. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5131. if (rc)
  5132. goto done;
  5133. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5134. IWL_SCAN_CHECK_WATCHDOG);
  5135. mutex_unlock(&priv->mutex);
  5136. return;
  5137. done:
  5138. /* can not perform scan make sure we clear scanning
  5139. * bits from status so next scan request can be performed.
  5140. * if we dont clear scanning status bit here all next scan
  5141. * will fail
  5142. */
  5143. clear_bit(STATUS_SCAN_HW, &priv->status);
  5144. clear_bit(STATUS_SCANNING, &priv->status);
  5145. /* inform mac80211 scan aborted */
  5146. queue_work(priv->workqueue, &priv->scan_completed);
  5147. mutex_unlock(&priv->mutex);
  5148. }
  5149. static void iwl3945_bg_up(struct work_struct *data)
  5150. {
  5151. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5152. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5153. return;
  5154. mutex_lock(&priv->mutex);
  5155. __iwl3945_up(priv);
  5156. mutex_unlock(&priv->mutex);
  5157. iwl3945_rfkill_set_hw_state(priv);
  5158. }
  5159. static void iwl3945_bg_restart(struct work_struct *data)
  5160. {
  5161. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5162. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5163. return;
  5164. iwl3945_down(priv);
  5165. queue_work(priv->workqueue, &priv->up);
  5166. }
  5167. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5168. {
  5169. struct iwl3945_priv *priv =
  5170. container_of(data, struct iwl3945_priv, rx_replenish);
  5171. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5172. return;
  5173. mutex_lock(&priv->mutex);
  5174. iwl3945_rx_replenish(priv);
  5175. mutex_unlock(&priv->mutex);
  5176. }
  5177. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5178. static void iwl3945_post_associate(struct iwl3945_priv *priv)
  5179. {
  5180. int rc = 0;
  5181. struct ieee80211_conf *conf = NULL;
  5182. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5183. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5184. return;
  5185. }
  5186. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  5187. priv->assoc_id, priv->active_rxon.bssid_addr);
  5188. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5189. return;
  5190. if (!priv->vif || !priv->is_open)
  5191. return;
  5192. iwl3945_scan_cancel_timeout(priv, 200);
  5193. conf = ieee80211_get_hw_conf(priv->hw);
  5194. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5195. iwl3945_commit_rxon(priv);
  5196. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5197. iwl3945_setup_rxon_timing(priv);
  5198. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5199. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5200. if (rc)
  5201. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5202. "Attempting to continue.\n");
  5203. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5204. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5205. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5206. priv->assoc_id, priv->beacon_int);
  5207. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5208. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5209. else
  5210. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5211. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5212. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5213. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5214. else
  5215. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5216. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5217. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5218. }
  5219. iwl3945_commit_rxon(priv);
  5220. switch (priv->iw_mode) {
  5221. case NL80211_IFTYPE_STATION:
  5222. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5223. break;
  5224. case NL80211_IFTYPE_ADHOC:
  5225. priv->assoc_id = 1;
  5226. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5227. iwl3945_sync_sta(priv, IWL_STA_ID,
  5228. (priv->band == IEEE80211_BAND_5GHZ) ?
  5229. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5230. CMD_ASYNC);
  5231. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5232. iwl3945_send_beacon_cmd(priv);
  5233. break;
  5234. default:
  5235. IWL_ERROR("%s Should not be called in %d mode\n",
  5236. __func__, priv->iw_mode);
  5237. break;
  5238. }
  5239. iwl3945_activate_qos(priv, 0);
  5240. /* we have just associated, don't start scan too early */
  5241. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5242. }
  5243. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5244. {
  5245. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5246. if (!iwl3945_is_ready(priv))
  5247. return;
  5248. mutex_lock(&priv->mutex);
  5249. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5250. iwl3945_send_scan_abort(priv);
  5251. mutex_unlock(&priv->mutex);
  5252. }
  5253. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5254. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5255. {
  5256. struct iwl3945_priv *priv =
  5257. container_of(work, struct iwl3945_priv, scan_completed);
  5258. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5259. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5260. return;
  5261. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5262. iwl3945_mac_config(priv->hw, 0);
  5263. ieee80211_scan_completed(priv->hw);
  5264. /* Since setting the TXPOWER may have been deferred while
  5265. * performing the scan, fire one off */
  5266. mutex_lock(&priv->mutex);
  5267. iwl3945_hw_reg_send_txpower(priv);
  5268. mutex_unlock(&priv->mutex);
  5269. }
  5270. /*****************************************************************************
  5271. *
  5272. * mac80211 entry point functions
  5273. *
  5274. *****************************************************************************/
  5275. #define UCODE_READY_TIMEOUT (2 * HZ)
  5276. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5277. {
  5278. struct iwl3945_priv *priv = hw->priv;
  5279. int ret;
  5280. IWL_DEBUG_MAC80211("enter\n");
  5281. if (pci_enable_device(priv->pci_dev)) {
  5282. IWL_ERROR("Fail to pci_enable_device\n");
  5283. return -ENODEV;
  5284. }
  5285. pci_restore_state(priv->pci_dev);
  5286. pci_enable_msi(priv->pci_dev);
  5287. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5288. DRV_NAME, priv);
  5289. if (ret) {
  5290. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5291. goto out_disable_msi;
  5292. }
  5293. /* we should be verifying the device is ready to be opened */
  5294. mutex_lock(&priv->mutex);
  5295. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5296. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5297. * ucode filename and max sizes are card-specific. */
  5298. if (!priv->ucode_code.len) {
  5299. ret = iwl3945_read_ucode(priv);
  5300. if (ret) {
  5301. IWL_ERROR("Could not read microcode: %d\n", ret);
  5302. mutex_unlock(&priv->mutex);
  5303. goto out_release_irq;
  5304. }
  5305. }
  5306. ret = __iwl3945_up(priv);
  5307. mutex_unlock(&priv->mutex);
  5308. iwl3945_rfkill_set_hw_state(priv);
  5309. if (ret)
  5310. goto out_release_irq;
  5311. IWL_DEBUG_INFO("Start UP work.\n");
  5312. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5313. return 0;
  5314. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5315. * mac80211 will not be run successfully. */
  5316. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5317. test_bit(STATUS_READY, &priv->status),
  5318. UCODE_READY_TIMEOUT);
  5319. if (!ret) {
  5320. if (!test_bit(STATUS_READY, &priv->status)) {
  5321. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5322. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5323. ret = -ETIMEDOUT;
  5324. goto out_release_irq;
  5325. }
  5326. }
  5327. priv->is_open = 1;
  5328. IWL_DEBUG_MAC80211("leave\n");
  5329. return 0;
  5330. out_release_irq:
  5331. free_irq(priv->pci_dev->irq, priv);
  5332. out_disable_msi:
  5333. pci_disable_msi(priv->pci_dev);
  5334. pci_disable_device(priv->pci_dev);
  5335. priv->is_open = 0;
  5336. IWL_DEBUG_MAC80211("leave - failed\n");
  5337. return ret;
  5338. }
  5339. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5340. {
  5341. struct iwl3945_priv *priv = hw->priv;
  5342. IWL_DEBUG_MAC80211("enter\n");
  5343. if (!priv->is_open) {
  5344. IWL_DEBUG_MAC80211("leave - skip\n");
  5345. return;
  5346. }
  5347. priv->is_open = 0;
  5348. if (iwl3945_is_ready_rf(priv)) {
  5349. /* stop mac, cancel any scan request and clear
  5350. * RXON_FILTER_ASSOC_MSK BIT
  5351. */
  5352. mutex_lock(&priv->mutex);
  5353. iwl3945_scan_cancel_timeout(priv, 100);
  5354. mutex_unlock(&priv->mutex);
  5355. }
  5356. iwl3945_down(priv);
  5357. flush_workqueue(priv->workqueue);
  5358. free_irq(priv->pci_dev->irq, priv);
  5359. pci_disable_msi(priv->pci_dev);
  5360. pci_save_state(priv->pci_dev);
  5361. pci_disable_device(priv->pci_dev);
  5362. IWL_DEBUG_MAC80211("leave\n");
  5363. }
  5364. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5365. {
  5366. struct iwl3945_priv *priv = hw->priv;
  5367. IWL_DEBUG_MAC80211("enter\n");
  5368. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5369. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5370. if (iwl3945_tx_skb(priv, skb))
  5371. dev_kfree_skb_any(skb);
  5372. IWL_DEBUG_MAC80211("leave\n");
  5373. return NETDEV_TX_OK;
  5374. }
  5375. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5376. struct ieee80211_if_init_conf *conf)
  5377. {
  5378. struct iwl3945_priv *priv = hw->priv;
  5379. unsigned long flags;
  5380. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5381. if (priv->vif) {
  5382. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5383. return -EOPNOTSUPP;
  5384. }
  5385. spin_lock_irqsave(&priv->lock, flags);
  5386. priv->vif = conf->vif;
  5387. priv->iw_mode = conf->type;
  5388. spin_unlock_irqrestore(&priv->lock, flags);
  5389. mutex_lock(&priv->mutex);
  5390. if (conf->mac_addr) {
  5391. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5392. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5393. }
  5394. if (iwl3945_is_ready(priv))
  5395. iwl3945_set_mode(priv, conf->type);
  5396. mutex_unlock(&priv->mutex);
  5397. IWL_DEBUG_MAC80211("leave\n");
  5398. return 0;
  5399. }
  5400. /**
  5401. * iwl3945_mac_config - mac80211 config callback
  5402. *
  5403. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5404. * be set inappropriately and the driver currently sets the hardware up to
  5405. * use it whenever needed.
  5406. */
  5407. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5408. {
  5409. struct iwl3945_priv *priv = hw->priv;
  5410. const struct iwl_channel_info *ch_info;
  5411. struct ieee80211_conf *conf = &hw->conf;
  5412. unsigned long flags;
  5413. int ret = 0;
  5414. mutex_lock(&priv->mutex);
  5415. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5416. if (!iwl3945_is_ready(priv)) {
  5417. IWL_DEBUG_MAC80211("leave - not ready\n");
  5418. ret = -EIO;
  5419. goto out;
  5420. }
  5421. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5422. test_bit(STATUS_SCANNING, &priv->status))) {
  5423. IWL_DEBUG_MAC80211("leave - scanning\n");
  5424. set_bit(STATUS_CONF_PENDING, &priv->status);
  5425. mutex_unlock(&priv->mutex);
  5426. return 0;
  5427. }
  5428. spin_lock_irqsave(&priv->lock, flags);
  5429. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5430. conf->channel->hw_value);
  5431. if (!is_channel_valid(ch_info)) {
  5432. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5433. conf->channel->hw_value, conf->channel->band);
  5434. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5435. spin_unlock_irqrestore(&priv->lock, flags);
  5436. ret = -EINVAL;
  5437. goto out;
  5438. }
  5439. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5440. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5441. /* The list of supported rates and rate mask can be different
  5442. * for each phymode; since the phymode may have changed, reset
  5443. * the rate mask to what mac80211 lists */
  5444. iwl3945_set_rate(priv);
  5445. spin_unlock_irqrestore(&priv->lock, flags);
  5446. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5447. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5448. iwl3945_hw_channel_switch(priv, conf->channel);
  5449. goto out;
  5450. }
  5451. #endif
  5452. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5453. if (!conf->radio_enabled) {
  5454. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5455. goto out;
  5456. }
  5457. if (iwl3945_is_rfkill(priv)) {
  5458. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5459. ret = -EIO;
  5460. goto out;
  5461. }
  5462. iwl3945_set_rate(priv);
  5463. if (memcmp(&priv->active_rxon,
  5464. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5465. iwl3945_commit_rxon(priv);
  5466. else
  5467. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5468. IWL_DEBUG_MAC80211("leave\n");
  5469. out:
  5470. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5471. mutex_unlock(&priv->mutex);
  5472. return ret;
  5473. }
  5474. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5475. {
  5476. int rc = 0;
  5477. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5478. return;
  5479. /* The following should be done only at AP bring up */
  5480. if (!(iwl3945_is_associated(priv))) {
  5481. /* RXON - unassoc (to set timing command) */
  5482. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5483. iwl3945_commit_rxon(priv);
  5484. /* RXON Timing */
  5485. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5486. iwl3945_setup_rxon_timing(priv);
  5487. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5488. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5489. if (rc)
  5490. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5491. "Attempting to continue.\n");
  5492. /* FIXME: what should be the assoc_id for AP? */
  5493. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5494. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5495. priv->staging_rxon.flags |=
  5496. RXON_FLG_SHORT_PREAMBLE_MSK;
  5497. else
  5498. priv->staging_rxon.flags &=
  5499. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5500. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5501. if (priv->assoc_capability &
  5502. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5503. priv->staging_rxon.flags |=
  5504. RXON_FLG_SHORT_SLOT_MSK;
  5505. else
  5506. priv->staging_rxon.flags &=
  5507. ~RXON_FLG_SHORT_SLOT_MSK;
  5508. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5509. priv->staging_rxon.flags &=
  5510. ~RXON_FLG_SHORT_SLOT_MSK;
  5511. }
  5512. /* restore RXON assoc */
  5513. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5514. iwl3945_commit_rxon(priv);
  5515. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5516. }
  5517. iwl3945_send_beacon_cmd(priv);
  5518. /* FIXME - we need to add code here to detect a totally new
  5519. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5520. * clear sta table, add BCAST sta... */
  5521. }
  5522. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5523. struct ieee80211_vif *vif,
  5524. struct ieee80211_if_conf *conf)
  5525. {
  5526. struct iwl3945_priv *priv = hw->priv;
  5527. int rc;
  5528. if (conf == NULL)
  5529. return -EIO;
  5530. if (priv->vif != vif) {
  5531. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5532. return 0;
  5533. }
  5534. /* handle this temporarily here */
  5535. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5536. conf->changed & IEEE80211_IFCC_BEACON) {
  5537. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5538. if (!beacon)
  5539. return -ENOMEM;
  5540. mutex_lock(&priv->mutex);
  5541. rc = iwl3945_mac_beacon_update(hw, beacon);
  5542. mutex_unlock(&priv->mutex);
  5543. if (rc)
  5544. return rc;
  5545. }
  5546. if (!iwl3945_is_alive(priv))
  5547. return -EAGAIN;
  5548. mutex_lock(&priv->mutex);
  5549. if (conf->bssid)
  5550. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5551. /*
  5552. * very dubious code was here; the probe filtering flag is never set:
  5553. *
  5554. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5555. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5556. */
  5557. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5558. if (!conf->bssid) {
  5559. conf->bssid = priv->mac_addr;
  5560. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5561. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5562. conf->bssid);
  5563. }
  5564. if (priv->ibss_beacon)
  5565. dev_kfree_skb(priv->ibss_beacon);
  5566. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5567. }
  5568. if (iwl3945_is_rfkill(priv))
  5569. goto done;
  5570. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5571. !is_multicast_ether_addr(conf->bssid)) {
  5572. /* If there is currently a HW scan going on in the background
  5573. * then we need to cancel it else the RXON below will fail. */
  5574. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5575. IWL_WARNING("Aborted scan still in progress "
  5576. "after 100ms\n");
  5577. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5578. mutex_unlock(&priv->mutex);
  5579. return -EAGAIN;
  5580. }
  5581. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5582. /* TODO: Audit driver for usage of these members and see
  5583. * if mac80211 deprecates them (priv->bssid looks like it
  5584. * shouldn't be there, but I haven't scanned the IBSS code
  5585. * to verify) - jpk */
  5586. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5587. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5588. iwl3945_config_ap(priv);
  5589. else {
  5590. rc = iwl3945_commit_rxon(priv);
  5591. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5592. iwl3945_add_station(priv,
  5593. priv->active_rxon.bssid_addr, 1, 0);
  5594. }
  5595. } else {
  5596. iwl3945_scan_cancel_timeout(priv, 100);
  5597. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5598. iwl3945_commit_rxon(priv);
  5599. }
  5600. done:
  5601. IWL_DEBUG_MAC80211("leave\n");
  5602. mutex_unlock(&priv->mutex);
  5603. return 0;
  5604. }
  5605. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5606. unsigned int changed_flags,
  5607. unsigned int *total_flags,
  5608. int mc_count, struct dev_addr_list *mc_list)
  5609. {
  5610. struct iwl3945_priv *priv = hw->priv;
  5611. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  5612. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5613. changed_flags, *total_flags);
  5614. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5615. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5616. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5617. else
  5618. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5619. }
  5620. if (changed_flags & FIF_ALLMULTI) {
  5621. if (*total_flags & FIF_ALLMULTI)
  5622. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5623. else
  5624. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5625. }
  5626. if (changed_flags & FIF_CONTROL) {
  5627. if (*total_flags & FIF_CONTROL)
  5628. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5629. else
  5630. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5631. }
  5632. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5633. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5634. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5635. else
  5636. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5637. }
  5638. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5639. * since mac80211 will call ieee80211_hw_config immediately.
  5640. * (mc_list is not supported at this time). Otherwise, we need to
  5641. * queue a background iwl_commit_rxon work.
  5642. */
  5643. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5644. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5645. }
  5646. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5647. struct ieee80211_if_init_conf *conf)
  5648. {
  5649. struct iwl3945_priv *priv = hw->priv;
  5650. IWL_DEBUG_MAC80211("enter\n");
  5651. mutex_lock(&priv->mutex);
  5652. if (iwl3945_is_ready_rf(priv)) {
  5653. iwl3945_scan_cancel_timeout(priv, 100);
  5654. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5655. iwl3945_commit_rxon(priv);
  5656. }
  5657. if (priv->vif == conf->vif) {
  5658. priv->vif = NULL;
  5659. memset(priv->bssid, 0, ETH_ALEN);
  5660. }
  5661. mutex_unlock(&priv->mutex);
  5662. IWL_DEBUG_MAC80211("leave\n");
  5663. }
  5664. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5665. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5666. struct ieee80211_vif *vif,
  5667. struct ieee80211_bss_conf *bss_conf,
  5668. u32 changes)
  5669. {
  5670. struct iwl3945_priv *priv = hw->priv;
  5671. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5672. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5673. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5674. bss_conf->use_short_preamble);
  5675. if (bss_conf->use_short_preamble)
  5676. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5677. else
  5678. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5679. }
  5680. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5681. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5682. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5683. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5684. else
  5685. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5686. }
  5687. if (changes & BSS_CHANGED_ASSOC) {
  5688. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5689. /* This should never happen as this function should
  5690. * never be called from interrupt context. */
  5691. if (WARN_ON_ONCE(in_interrupt()))
  5692. return;
  5693. if (bss_conf->assoc) {
  5694. priv->assoc_id = bss_conf->aid;
  5695. priv->beacon_int = bss_conf->beacon_int;
  5696. priv->timestamp = bss_conf->timestamp;
  5697. priv->assoc_capability = bss_conf->assoc_capability;
  5698. priv->next_scan_jiffies = jiffies +
  5699. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5700. mutex_lock(&priv->mutex);
  5701. iwl3945_post_associate(priv);
  5702. mutex_unlock(&priv->mutex);
  5703. } else {
  5704. priv->assoc_id = 0;
  5705. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5706. }
  5707. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5708. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5709. iwl3945_send_rxon_assoc(priv);
  5710. }
  5711. }
  5712. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5713. {
  5714. int rc = 0;
  5715. unsigned long flags;
  5716. struct iwl3945_priv *priv = hw->priv;
  5717. DECLARE_SSID_BUF(ssid_buf);
  5718. IWL_DEBUG_MAC80211("enter\n");
  5719. mutex_lock(&priv->mutex);
  5720. spin_lock_irqsave(&priv->lock, flags);
  5721. if (!iwl3945_is_ready_rf(priv)) {
  5722. rc = -EIO;
  5723. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5724. goto out_unlock;
  5725. }
  5726. /* we don't schedule scan within next_scan_jiffies period */
  5727. if (priv->next_scan_jiffies &&
  5728. time_after(priv->next_scan_jiffies, jiffies)) {
  5729. rc = -EAGAIN;
  5730. goto out_unlock;
  5731. }
  5732. /* if we just finished scan ask for delay for a broadcast scan */
  5733. if ((len == 0) && priv->last_scan_jiffies &&
  5734. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5735. jiffies)) {
  5736. rc = -EAGAIN;
  5737. goto out_unlock;
  5738. }
  5739. if (len) {
  5740. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5741. print_ssid(ssid_buf, ssid, len), (int)len);
  5742. priv->one_direct_scan = 1;
  5743. priv->direct_ssid_len = (u8)
  5744. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5745. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5746. } else
  5747. priv->one_direct_scan = 0;
  5748. rc = iwl3945_scan_initiate(priv);
  5749. IWL_DEBUG_MAC80211("leave\n");
  5750. out_unlock:
  5751. spin_unlock_irqrestore(&priv->lock, flags);
  5752. mutex_unlock(&priv->mutex);
  5753. return rc;
  5754. }
  5755. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5756. const u8 *local_addr, const u8 *addr,
  5757. struct ieee80211_key_conf *key)
  5758. {
  5759. struct iwl3945_priv *priv = hw->priv;
  5760. int rc = 0;
  5761. u8 sta_id;
  5762. IWL_DEBUG_MAC80211("enter\n");
  5763. if (!iwl3945_param_hwcrypto) {
  5764. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5765. return -EOPNOTSUPP;
  5766. }
  5767. if (is_zero_ether_addr(addr))
  5768. /* only support pairwise keys */
  5769. return -EOPNOTSUPP;
  5770. sta_id = iwl3945_hw_find_station(priv, addr);
  5771. if (sta_id == IWL_INVALID_STATION) {
  5772. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5773. addr);
  5774. return -EINVAL;
  5775. }
  5776. mutex_lock(&priv->mutex);
  5777. iwl3945_scan_cancel_timeout(priv, 100);
  5778. switch (cmd) {
  5779. case SET_KEY:
  5780. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5781. if (!rc) {
  5782. iwl3945_set_rxon_hwcrypto(priv, 1);
  5783. iwl3945_commit_rxon(priv);
  5784. key->hw_key_idx = sta_id;
  5785. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5786. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5787. }
  5788. break;
  5789. case DISABLE_KEY:
  5790. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5791. if (!rc) {
  5792. iwl3945_set_rxon_hwcrypto(priv, 0);
  5793. iwl3945_commit_rxon(priv);
  5794. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5795. }
  5796. break;
  5797. default:
  5798. rc = -EINVAL;
  5799. }
  5800. IWL_DEBUG_MAC80211("leave\n");
  5801. mutex_unlock(&priv->mutex);
  5802. return rc;
  5803. }
  5804. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5805. const struct ieee80211_tx_queue_params *params)
  5806. {
  5807. struct iwl3945_priv *priv = hw->priv;
  5808. unsigned long flags;
  5809. int q;
  5810. IWL_DEBUG_MAC80211("enter\n");
  5811. if (!iwl3945_is_ready_rf(priv)) {
  5812. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5813. return -EIO;
  5814. }
  5815. if (queue >= AC_NUM) {
  5816. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5817. return 0;
  5818. }
  5819. q = AC_NUM - 1 - queue;
  5820. spin_lock_irqsave(&priv->lock, flags);
  5821. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5822. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5823. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5824. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5825. cpu_to_le16((params->txop * 32));
  5826. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5827. priv->qos_data.qos_active = 1;
  5828. spin_unlock_irqrestore(&priv->lock, flags);
  5829. mutex_lock(&priv->mutex);
  5830. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5831. iwl3945_activate_qos(priv, 1);
  5832. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5833. iwl3945_activate_qos(priv, 0);
  5834. mutex_unlock(&priv->mutex);
  5835. IWL_DEBUG_MAC80211("leave\n");
  5836. return 0;
  5837. }
  5838. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5839. struct ieee80211_tx_queue_stats *stats)
  5840. {
  5841. struct iwl3945_priv *priv = hw->priv;
  5842. int i, avail;
  5843. struct iwl3945_tx_queue *txq;
  5844. struct iwl_queue *q;
  5845. unsigned long flags;
  5846. IWL_DEBUG_MAC80211("enter\n");
  5847. if (!iwl3945_is_ready_rf(priv)) {
  5848. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5849. return -EIO;
  5850. }
  5851. spin_lock_irqsave(&priv->lock, flags);
  5852. for (i = 0; i < AC_NUM; i++) {
  5853. txq = &priv->txq[i];
  5854. q = &txq->q;
  5855. avail = iwl_queue_space(q);
  5856. stats[i].len = q->n_window - avail;
  5857. stats[i].limit = q->n_window - q->high_mark;
  5858. stats[i].count = q->n_window;
  5859. }
  5860. spin_unlock_irqrestore(&priv->lock, flags);
  5861. IWL_DEBUG_MAC80211("leave\n");
  5862. return 0;
  5863. }
  5864. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5865. {
  5866. struct iwl3945_priv *priv = hw->priv;
  5867. unsigned long flags;
  5868. mutex_lock(&priv->mutex);
  5869. IWL_DEBUG_MAC80211("enter\n");
  5870. iwl3945_reset_qos(priv);
  5871. spin_lock_irqsave(&priv->lock, flags);
  5872. priv->assoc_id = 0;
  5873. priv->assoc_capability = 0;
  5874. priv->call_post_assoc_from_beacon = 0;
  5875. /* new association get rid of ibss beacon skb */
  5876. if (priv->ibss_beacon)
  5877. dev_kfree_skb(priv->ibss_beacon);
  5878. priv->ibss_beacon = NULL;
  5879. priv->beacon_int = priv->hw->conf.beacon_int;
  5880. priv->timestamp = 0;
  5881. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5882. priv->beacon_int = 0;
  5883. spin_unlock_irqrestore(&priv->lock, flags);
  5884. if (!iwl3945_is_ready_rf(priv)) {
  5885. IWL_DEBUG_MAC80211("leave - not ready\n");
  5886. mutex_unlock(&priv->mutex);
  5887. return;
  5888. }
  5889. /* we are restarting association process
  5890. * clear RXON_FILTER_ASSOC_MSK bit
  5891. */
  5892. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5893. iwl3945_scan_cancel_timeout(priv, 100);
  5894. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5895. iwl3945_commit_rxon(priv);
  5896. }
  5897. /* Per mac80211.h: This is only used in IBSS mode... */
  5898. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5899. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5900. mutex_unlock(&priv->mutex);
  5901. return;
  5902. }
  5903. iwl3945_set_rate(priv);
  5904. mutex_unlock(&priv->mutex);
  5905. IWL_DEBUG_MAC80211("leave\n");
  5906. }
  5907. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5908. {
  5909. struct iwl3945_priv *priv = hw->priv;
  5910. unsigned long flags;
  5911. IWL_DEBUG_MAC80211("enter\n");
  5912. if (!iwl3945_is_ready_rf(priv)) {
  5913. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5914. return -EIO;
  5915. }
  5916. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5917. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5918. return -EIO;
  5919. }
  5920. spin_lock_irqsave(&priv->lock, flags);
  5921. if (priv->ibss_beacon)
  5922. dev_kfree_skb(priv->ibss_beacon);
  5923. priv->ibss_beacon = skb;
  5924. priv->assoc_id = 0;
  5925. IWL_DEBUG_MAC80211("leave\n");
  5926. spin_unlock_irqrestore(&priv->lock, flags);
  5927. iwl3945_reset_qos(priv);
  5928. iwl3945_post_associate(priv);
  5929. return 0;
  5930. }
  5931. /*****************************************************************************
  5932. *
  5933. * sysfs attributes
  5934. *
  5935. *****************************************************************************/
  5936. #ifdef CONFIG_IWL3945_DEBUG
  5937. /*
  5938. * The following adds a new attribute to the sysfs representation
  5939. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5940. * used for controlling the debug level.
  5941. *
  5942. * See the level definitions in iwl for details.
  5943. */
  5944. static ssize_t show_debug_level(struct device *d,
  5945. struct device_attribute *attr, char *buf)
  5946. {
  5947. struct iwl3945_priv *priv = d->driver_data;
  5948. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5949. }
  5950. static ssize_t store_debug_level(struct device *d,
  5951. struct device_attribute *attr,
  5952. const char *buf, size_t count)
  5953. {
  5954. struct iwl3945_priv *priv = d->driver_data;
  5955. unsigned long val;
  5956. int ret;
  5957. ret = strict_strtoul(buf, 0, &val);
  5958. if (ret)
  5959. printk(KERN_INFO DRV_NAME
  5960. ": %s is not in hex or decimal form.\n", buf);
  5961. else
  5962. priv->debug_level = val;
  5963. return strnlen(buf, count);
  5964. }
  5965. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5966. show_debug_level, store_debug_level);
  5967. #endif /* CONFIG_IWL3945_DEBUG */
  5968. static ssize_t show_temperature(struct device *d,
  5969. struct device_attribute *attr, char *buf)
  5970. {
  5971. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  5972. if (!iwl3945_is_alive(priv))
  5973. return -EAGAIN;
  5974. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5975. }
  5976. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5977. static ssize_t show_tx_power(struct device *d,
  5978. struct device_attribute *attr, char *buf)
  5979. {
  5980. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  5981. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5982. }
  5983. static ssize_t store_tx_power(struct device *d,
  5984. struct device_attribute *attr,
  5985. const char *buf, size_t count)
  5986. {
  5987. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  5988. char *p = (char *)buf;
  5989. u32 val;
  5990. val = simple_strtoul(p, &p, 10);
  5991. if (p == buf)
  5992. printk(KERN_INFO DRV_NAME
  5993. ": %s is not in decimal form.\n", buf);
  5994. else
  5995. iwl3945_hw_reg_set_txpower(priv, val);
  5996. return count;
  5997. }
  5998. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5999. static ssize_t show_flags(struct device *d,
  6000. struct device_attribute *attr, char *buf)
  6001. {
  6002. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6003. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6004. }
  6005. static ssize_t store_flags(struct device *d,
  6006. struct device_attribute *attr,
  6007. const char *buf, size_t count)
  6008. {
  6009. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6010. u32 flags = simple_strtoul(buf, NULL, 0);
  6011. mutex_lock(&priv->mutex);
  6012. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6013. /* Cancel any currently running scans... */
  6014. if (iwl3945_scan_cancel_timeout(priv, 100))
  6015. IWL_WARNING("Could not cancel scan.\n");
  6016. else {
  6017. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6018. flags);
  6019. priv->staging_rxon.flags = cpu_to_le32(flags);
  6020. iwl3945_commit_rxon(priv);
  6021. }
  6022. }
  6023. mutex_unlock(&priv->mutex);
  6024. return count;
  6025. }
  6026. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6027. static ssize_t show_filter_flags(struct device *d,
  6028. struct device_attribute *attr, char *buf)
  6029. {
  6030. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6031. return sprintf(buf, "0x%04X\n",
  6032. le32_to_cpu(priv->active_rxon.filter_flags));
  6033. }
  6034. static ssize_t store_filter_flags(struct device *d,
  6035. struct device_attribute *attr,
  6036. const char *buf, size_t count)
  6037. {
  6038. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6039. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6040. mutex_lock(&priv->mutex);
  6041. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6042. /* Cancel any currently running scans... */
  6043. if (iwl3945_scan_cancel_timeout(priv, 100))
  6044. IWL_WARNING("Could not cancel scan.\n");
  6045. else {
  6046. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6047. "0x%04X\n", filter_flags);
  6048. priv->staging_rxon.filter_flags =
  6049. cpu_to_le32(filter_flags);
  6050. iwl3945_commit_rxon(priv);
  6051. }
  6052. }
  6053. mutex_unlock(&priv->mutex);
  6054. return count;
  6055. }
  6056. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6057. store_filter_flags);
  6058. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6059. static ssize_t show_measurement(struct device *d,
  6060. struct device_attribute *attr, char *buf)
  6061. {
  6062. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6063. struct iwl_spectrum_notification measure_report;
  6064. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6065. u8 *data = (u8 *)&measure_report;
  6066. unsigned long flags;
  6067. spin_lock_irqsave(&priv->lock, flags);
  6068. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6069. spin_unlock_irqrestore(&priv->lock, flags);
  6070. return 0;
  6071. }
  6072. memcpy(&measure_report, &priv->measure_report, size);
  6073. priv->measurement_status = 0;
  6074. spin_unlock_irqrestore(&priv->lock, flags);
  6075. while (size && (PAGE_SIZE - len)) {
  6076. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6077. PAGE_SIZE - len, 1);
  6078. len = strlen(buf);
  6079. if (PAGE_SIZE - len)
  6080. buf[len++] = '\n';
  6081. ofs += 16;
  6082. size -= min(size, 16U);
  6083. }
  6084. return len;
  6085. }
  6086. static ssize_t store_measurement(struct device *d,
  6087. struct device_attribute *attr,
  6088. const char *buf, size_t count)
  6089. {
  6090. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6091. struct ieee80211_measurement_params params = {
  6092. .channel = le16_to_cpu(priv->active_rxon.channel),
  6093. .start_time = cpu_to_le64(priv->last_tsf),
  6094. .duration = cpu_to_le16(1),
  6095. };
  6096. u8 type = IWL_MEASURE_BASIC;
  6097. u8 buffer[32];
  6098. u8 channel;
  6099. if (count) {
  6100. char *p = buffer;
  6101. strncpy(buffer, buf, min(sizeof(buffer), count));
  6102. channel = simple_strtoul(p, NULL, 0);
  6103. if (channel)
  6104. params.channel = channel;
  6105. p = buffer;
  6106. while (*p && *p != ' ')
  6107. p++;
  6108. if (*p)
  6109. type = simple_strtoul(p + 1, NULL, 0);
  6110. }
  6111. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6112. "channel %d (for '%s')\n", type, params.channel, buf);
  6113. iwl3945_get_measurement(priv, &params, type);
  6114. return count;
  6115. }
  6116. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6117. show_measurement, store_measurement);
  6118. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6119. static ssize_t store_retry_rate(struct device *d,
  6120. struct device_attribute *attr,
  6121. const char *buf, size_t count)
  6122. {
  6123. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6124. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6125. if (priv->retry_rate <= 0)
  6126. priv->retry_rate = 1;
  6127. return count;
  6128. }
  6129. static ssize_t show_retry_rate(struct device *d,
  6130. struct device_attribute *attr, char *buf)
  6131. {
  6132. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6133. return sprintf(buf, "%d", priv->retry_rate);
  6134. }
  6135. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6136. store_retry_rate);
  6137. static ssize_t store_power_level(struct device *d,
  6138. struct device_attribute *attr,
  6139. const char *buf, size_t count)
  6140. {
  6141. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6142. int rc;
  6143. int mode;
  6144. mode = simple_strtoul(buf, NULL, 0);
  6145. mutex_lock(&priv->mutex);
  6146. if (!iwl3945_is_ready(priv)) {
  6147. rc = -EAGAIN;
  6148. goto out;
  6149. }
  6150. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  6151. (mode == IWL39_POWER_AC))
  6152. mode = IWL39_POWER_AC;
  6153. else
  6154. mode |= IWL_POWER_ENABLED;
  6155. if (mode != priv->power_mode) {
  6156. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6157. if (rc) {
  6158. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6159. goto out;
  6160. }
  6161. priv->power_mode = mode;
  6162. }
  6163. rc = count;
  6164. out:
  6165. mutex_unlock(&priv->mutex);
  6166. return rc;
  6167. }
  6168. #define MAX_WX_STRING 80
  6169. /* Values are in microsecond */
  6170. static const s32 timeout_duration[] = {
  6171. 350000,
  6172. 250000,
  6173. 75000,
  6174. 37000,
  6175. 25000,
  6176. };
  6177. static const s32 period_duration[] = {
  6178. 400000,
  6179. 700000,
  6180. 1000000,
  6181. 1000000,
  6182. 1000000
  6183. };
  6184. static ssize_t show_power_level(struct device *d,
  6185. struct device_attribute *attr, char *buf)
  6186. {
  6187. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6188. int level = IWL_POWER_LEVEL(priv->power_mode);
  6189. char *p = buf;
  6190. p += sprintf(p, "%d ", level);
  6191. switch (level) {
  6192. case IWL_POWER_MODE_CAM:
  6193. case IWL39_POWER_AC:
  6194. p += sprintf(p, "(AC)");
  6195. break;
  6196. case IWL39_POWER_BATTERY:
  6197. p += sprintf(p, "(BATTERY)");
  6198. break;
  6199. default:
  6200. p += sprintf(p,
  6201. "(Timeout %dms, Period %dms)",
  6202. timeout_duration[level - 1] / 1000,
  6203. period_duration[level - 1] / 1000);
  6204. }
  6205. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6206. p += sprintf(p, " OFF\n");
  6207. else
  6208. p += sprintf(p, " \n");
  6209. return p - buf + 1;
  6210. }
  6211. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6212. store_power_level);
  6213. static ssize_t show_channels(struct device *d,
  6214. struct device_attribute *attr, char *buf)
  6215. {
  6216. /* all this shit doesn't belong into sysfs anyway */
  6217. return 0;
  6218. }
  6219. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6220. static ssize_t show_statistics(struct device *d,
  6221. struct device_attribute *attr, char *buf)
  6222. {
  6223. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6224. u32 size = sizeof(struct iwl3945_notif_statistics);
  6225. u32 len = 0, ofs = 0;
  6226. u8 *data = (u8 *)&priv->statistics;
  6227. int rc = 0;
  6228. if (!iwl3945_is_alive(priv))
  6229. return -EAGAIN;
  6230. mutex_lock(&priv->mutex);
  6231. rc = iwl3945_send_statistics_request(priv);
  6232. mutex_unlock(&priv->mutex);
  6233. if (rc) {
  6234. len = sprintf(buf,
  6235. "Error sending statistics request: 0x%08X\n", rc);
  6236. return len;
  6237. }
  6238. while (size && (PAGE_SIZE - len)) {
  6239. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6240. PAGE_SIZE - len, 1);
  6241. len = strlen(buf);
  6242. if (PAGE_SIZE - len)
  6243. buf[len++] = '\n';
  6244. ofs += 16;
  6245. size -= min(size, 16U);
  6246. }
  6247. return len;
  6248. }
  6249. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6250. static ssize_t show_antenna(struct device *d,
  6251. struct device_attribute *attr, char *buf)
  6252. {
  6253. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6254. if (!iwl3945_is_alive(priv))
  6255. return -EAGAIN;
  6256. return sprintf(buf, "%d\n", priv->antenna);
  6257. }
  6258. static ssize_t store_antenna(struct device *d,
  6259. struct device_attribute *attr,
  6260. const char *buf, size_t count)
  6261. {
  6262. int ant;
  6263. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6264. if (count == 0)
  6265. return 0;
  6266. if (sscanf(buf, "%1i", &ant) != 1) {
  6267. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6268. return count;
  6269. }
  6270. if ((ant >= 0) && (ant <= 2)) {
  6271. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6272. priv->antenna = (enum iwl3945_antenna)ant;
  6273. } else
  6274. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6275. return count;
  6276. }
  6277. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6278. static ssize_t show_status(struct device *d,
  6279. struct device_attribute *attr, char *buf)
  6280. {
  6281. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6282. if (!iwl3945_is_alive(priv))
  6283. return -EAGAIN;
  6284. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6285. }
  6286. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6287. static ssize_t dump_error_log(struct device *d,
  6288. struct device_attribute *attr,
  6289. const char *buf, size_t count)
  6290. {
  6291. char *p = (char *)buf;
  6292. if (p[0] == '1')
  6293. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6294. return strnlen(buf, count);
  6295. }
  6296. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6297. static ssize_t dump_event_log(struct device *d,
  6298. struct device_attribute *attr,
  6299. const char *buf, size_t count)
  6300. {
  6301. char *p = (char *)buf;
  6302. if (p[0] == '1')
  6303. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6304. return strnlen(buf, count);
  6305. }
  6306. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6307. /*****************************************************************************
  6308. *
  6309. * driver setup and tear down
  6310. *
  6311. *****************************************************************************/
  6312. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6313. {
  6314. priv->workqueue = create_workqueue(DRV_NAME);
  6315. init_waitqueue_head(&priv->wait_command_queue);
  6316. INIT_WORK(&priv->up, iwl3945_bg_up);
  6317. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6318. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6319. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6320. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6321. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6322. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6323. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6324. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6325. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6326. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6327. iwl3945_hw_setup_deferred_work(priv);
  6328. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6329. iwl3945_irq_tasklet, (unsigned long)priv);
  6330. }
  6331. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6332. {
  6333. iwl3945_hw_cancel_deferred_work(priv);
  6334. cancel_delayed_work_sync(&priv->init_alive_start);
  6335. cancel_delayed_work(&priv->scan_check);
  6336. cancel_delayed_work(&priv->alive_start);
  6337. cancel_work_sync(&priv->beacon_update);
  6338. }
  6339. static struct attribute *iwl3945_sysfs_entries[] = {
  6340. &dev_attr_antenna.attr,
  6341. &dev_attr_channels.attr,
  6342. &dev_attr_dump_errors.attr,
  6343. &dev_attr_dump_events.attr,
  6344. &dev_attr_flags.attr,
  6345. &dev_attr_filter_flags.attr,
  6346. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6347. &dev_attr_measurement.attr,
  6348. #endif
  6349. &dev_attr_power_level.attr,
  6350. &dev_attr_retry_rate.attr,
  6351. &dev_attr_statistics.attr,
  6352. &dev_attr_status.attr,
  6353. &dev_attr_temperature.attr,
  6354. &dev_attr_tx_power.attr,
  6355. #ifdef CONFIG_IWL3945_DEBUG
  6356. &dev_attr_debug_level.attr,
  6357. #endif
  6358. NULL
  6359. };
  6360. static struct attribute_group iwl3945_attribute_group = {
  6361. .name = NULL, /* put in device directory */
  6362. .attrs = iwl3945_sysfs_entries,
  6363. };
  6364. static struct ieee80211_ops iwl3945_hw_ops = {
  6365. .tx = iwl3945_mac_tx,
  6366. .start = iwl3945_mac_start,
  6367. .stop = iwl3945_mac_stop,
  6368. .add_interface = iwl3945_mac_add_interface,
  6369. .remove_interface = iwl3945_mac_remove_interface,
  6370. .config = iwl3945_mac_config,
  6371. .config_interface = iwl3945_mac_config_interface,
  6372. .configure_filter = iwl3945_configure_filter,
  6373. .set_key = iwl3945_mac_set_key,
  6374. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6375. .conf_tx = iwl3945_mac_conf_tx,
  6376. .reset_tsf = iwl3945_mac_reset_tsf,
  6377. .bss_info_changed = iwl3945_bss_info_changed,
  6378. .hw_scan = iwl3945_mac_hw_scan
  6379. };
  6380. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6381. {
  6382. int err = 0;
  6383. struct iwl3945_priv *priv;
  6384. struct ieee80211_hw *hw;
  6385. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6386. unsigned long flags;
  6387. /***********************
  6388. * 1. Allocating HW data
  6389. * ********************/
  6390. /* mac80211 allocates memory for this device instance, including
  6391. * space for this driver's private structure */
  6392. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6393. if (hw == NULL) {
  6394. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6395. err = -ENOMEM;
  6396. goto out;
  6397. }
  6398. SET_IEEE80211_DEV(hw, &pdev->dev);
  6399. priv = hw->priv;
  6400. priv->hw = hw;
  6401. priv->pci_dev = pdev;
  6402. priv->cfg = cfg;
  6403. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6404. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6405. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6406. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6407. err = -EINVAL;
  6408. goto out;
  6409. }
  6410. /* Disabling hardware scan means that mac80211 will perform scans
  6411. * "the hard way", rather than using device's scan. */
  6412. if (iwl3945_param_disable_hw_scan) {
  6413. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6414. iwl3945_hw_ops.hw_scan = NULL;
  6415. }
  6416. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6417. hw->rate_control_algorithm = "iwl-3945-rs";
  6418. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6419. /* Select antenna (may be helpful if only one antenna is connected) */
  6420. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6421. #ifdef CONFIG_IWL3945_DEBUG
  6422. priv->debug_level = iwl3945_param_debug;
  6423. atomic_set(&priv->restrict_refcnt, 0);
  6424. #endif
  6425. /* Tell mac80211 our characteristics */
  6426. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6427. IEEE80211_HW_NOISE_DBM;
  6428. hw->wiphy->interface_modes =
  6429. BIT(NL80211_IFTYPE_STATION) |
  6430. BIT(NL80211_IFTYPE_ADHOC);
  6431. hw->wiphy->fw_handles_regulatory = true;
  6432. /* 4 EDCA QOS priorities */
  6433. hw->queues = 4;
  6434. /***************************
  6435. * 2. Initializing PCI bus
  6436. * *************************/
  6437. if (pci_enable_device(pdev)) {
  6438. err = -ENODEV;
  6439. goto out_ieee80211_free_hw;
  6440. }
  6441. pci_set_master(pdev);
  6442. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6443. if (!err)
  6444. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6445. if (err) {
  6446. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6447. goto out_pci_disable_device;
  6448. }
  6449. pci_set_drvdata(pdev, priv);
  6450. err = pci_request_regions(pdev, DRV_NAME);
  6451. if (err)
  6452. goto out_pci_disable_device;
  6453. /***********************
  6454. * 3. Read REV Register
  6455. * ********************/
  6456. priv->hw_base = pci_iomap(pdev, 0, 0);
  6457. if (!priv->hw_base) {
  6458. err = -ENODEV;
  6459. goto out_pci_release_regions;
  6460. }
  6461. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6462. (unsigned long long) pci_resource_len(pdev, 0));
  6463. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6464. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6465. * PCI Tx retries from interfering with C3 CPU state */
  6466. pci_write_config_byte(pdev, 0x41, 0x00);
  6467. /* nic init */
  6468. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6469. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6470. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6471. err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
  6472. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6473. if (err < 0) {
  6474. IWL_DEBUG_INFO("Failed to init the card\n");
  6475. goto out_remove_sysfs;
  6476. }
  6477. /***********************
  6478. * 4. Read EEPROM
  6479. * ********************/
  6480. /* Read the EEPROM */
  6481. err = iwl3945_eeprom_init(priv);
  6482. if (err) {
  6483. IWL_ERROR("Unable to init EEPROM\n");
  6484. goto out_remove_sysfs;
  6485. }
  6486. /* MAC Address location in EEPROM same for 3945/4965 */
  6487. get_eeprom_mac(priv, priv->mac_addr);
  6488. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6489. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6490. /***********************
  6491. * 5. Setup HW Constants
  6492. * ********************/
  6493. /* Device-specific setup */
  6494. if (iwl3945_hw_set_hw_setting(priv)) {
  6495. IWL_ERROR("failed to set hw settings\n");
  6496. goto out_iounmap;
  6497. }
  6498. /***********************
  6499. * 6. Setup priv
  6500. * ********************/
  6501. priv->retry_rate = 1;
  6502. priv->ibss_beacon = NULL;
  6503. spin_lock_init(&priv->lock);
  6504. spin_lock_init(&priv->power_data.lock);
  6505. spin_lock_init(&priv->sta_lock);
  6506. spin_lock_init(&priv->hcmd_lock);
  6507. INIT_LIST_HEAD(&priv->free_frames);
  6508. mutex_init(&priv->mutex);
  6509. /* Clear the driver's (not device's) station table */
  6510. iwl3945_clear_stations_table(priv);
  6511. priv->data_retry_limit = -1;
  6512. priv->ieee_channels = NULL;
  6513. priv->ieee_rates = NULL;
  6514. priv->band = IEEE80211_BAND_2GHZ;
  6515. priv->iw_mode = NL80211_IFTYPE_STATION;
  6516. iwl3945_reset_qos(priv);
  6517. priv->qos_data.qos_active = 0;
  6518. priv->qos_data.qos_cap.val = 0;
  6519. priv->rates_mask = IWL_RATES_MASK;
  6520. /* If power management is turned on, default to AC mode */
  6521. priv->power_mode = IWL39_POWER_AC;
  6522. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6523. err = iwl3945_init_channel_map(priv);
  6524. if (err) {
  6525. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6526. goto out_release_irq;
  6527. }
  6528. err = iwl3945_init_geos(priv);
  6529. if (err) {
  6530. IWL_ERROR("initializing geos failed: %d\n", err);
  6531. goto out_free_channel_map;
  6532. }
  6533. printk(KERN_INFO DRV_NAME
  6534. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6535. /***********************************
  6536. * 7. Initialize Module Parameters
  6537. * **********************************/
  6538. /* Initialize module parameter values here */
  6539. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6540. if (iwl3945_param_disable) {
  6541. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6542. IWL_DEBUG_INFO("Radio disabled.\n");
  6543. }
  6544. /***********************
  6545. * 8. Setup Services
  6546. * ********************/
  6547. spin_lock_irqsave(&priv->lock, flags);
  6548. iwl3945_disable_interrupts(priv);
  6549. spin_unlock_irqrestore(&priv->lock, flags);
  6550. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6551. if (err) {
  6552. IWL_ERROR("failed to create sysfs device attributes\n");
  6553. goto out_free_geos;
  6554. }
  6555. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6556. iwl3945_setup_deferred_work(priv);
  6557. iwl3945_setup_rx_handlers(priv);
  6558. /***********************
  6559. * 9. Conclude
  6560. * ********************/
  6561. pci_save_state(pdev);
  6562. pci_disable_device(pdev);
  6563. /*********************************
  6564. * 10. Setup and Register mac80211
  6565. * *******************************/
  6566. err = ieee80211_register_hw(priv->hw);
  6567. if (err) {
  6568. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6569. goto out_remove_sysfs;
  6570. }
  6571. priv->hw->conf.beacon_int = 100;
  6572. priv->mac80211_registered = 1;
  6573. err = iwl3945_rfkill_init(priv);
  6574. if (err)
  6575. IWL_ERROR("Unable to initialize RFKILL system. "
  6576. "Ignoring error: %d\n", err);
  6577. return 0;
  6578. out_remove_sysfs:
  6579. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6580. out_free_geos:
  6581. iwl3945_free_geos(priv);
  6582. out_free_channel_map:
  6583. iwl3945_free_channel_map(priv);
  6584. out_release_irq:
  6585. destroy_workqueue(priv->workqueue);
  6586. priv->workqueue = NULL;
  6587. iwl3945_unset_hw_setting(priv);
  6588. out_iounmap:
  6589. pci_iounmap(pdev, priv->hw_base);
  6590. out_pci_release_regions:
  6591. pci_release_regions(pdev);
  6592. out_pci_disable_device:
  6593. pci_disable_device(pdev);
  6594. pci_set_drvdata(pdev, NULL);
  6595. out_ieee80211_free_hw:
  6596. ieee80211_free_hw(priv->hw);
  6597. out:
  6598. return err;
  6599. }
  6600. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6601. {
  6602. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6603. unsigned long flags;
  6604. if (!priv)
  6605. return;
  6606. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6607. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6608. iwl3945_down(priv);
  6609. /* make sure we flush any pending irq or
  6610. * tasklet for the driver
  6611. */
  6612. spin_lock_irqsave(&priv->lock, flags);
  6613. iwl3945_disable_interrupts(priv);
  6614. spin_unlock_irqrestore(&priv->lock, flags);
  6615. iwl_synchronize_irq(priv);
  6616. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6617. iwl3945_rfkill_unregister(priv);
  6618. iwl3945_dealloc_ucode_pci(priv);
  6619. if (priv->rxq.bd)
  6620. iwl3945_rx_queue_free(priv, &priv->rxq);
  6621. iwl3945_hw_txq_ctx_free(priv);
  6622. iwl3945_unset_hw_setting(priv);
  6623. iwl3945_clear_stations_table(priv);
  6624. if (priv->mac80211_registered)
  6625. ieee80211_unregister_hw(priv->hw);
  6626. /*netif_stop_queue(dev); */
  6627. flush_workqueue(priv->workqueue);
  6628. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6629. * priv->workqueue... so we can't take down the workqueue
  6630. * until now... */
  6631. destroy_workqueue(priv->workqueue);
  6632. priv->workqueue = NULL;
  6633. pci_iounmap(pdev, priv->hw_base);
  6634. pci_release_regions(pdev);
  6635. pci_disable_device(pdev);
  6636. pci_set_drvdata(pdev, NULL);
  6637. iwl3945_free_channel_map(priv);
  6638. iwl3945_free_geos(priv);
  6639. kfree(priv->scan);
  6640. if (priv->ibss_beacon)
  6641. dev_kfree_skb(priv->ibss_beacon);
  6642. ieee80211_free_hw(priv->hw);
  6643. }
  6644. #ifdef CONFIG_PM
  6645. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6646. {
  6647. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6648. if (priv->is_open) {
  6649. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6650. iwl3945_mac_stop(priv->hw);
  6651. priv->is_open = 1;
  6652. }
  6653. pci_set_power_state(pdev, PCI_D3hot);
  6654. return 0;
  6655. }
  6656. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6657. {
  6658. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6659. pci_set_power_state(pdev, PCI_D0);
  6660. if (priv->is_open)
  6661. iwl3945_mac_start(priv->hw);
  6662. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6663. return 0;
  6664. }
  6665. #endif /* CONFIG_PM */
  6666. /*************** RFKILL FUNCTIONS **********/
  6667. #ifdef CONFIG_IWL3945_RFKILL
  6668. /* software rf-kill from user */
  6669. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6670. {
  6671. struct iwl3945_priv *priv = data;
  6672. int err = 0;
  6673. if (!priv->rfkill)
  6674. return 0;
  6675. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6676. return 0;
  6677. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6678. mutex_lock(&priv->mutex);
  6679. switch (state) {
  6680. case RFKILL_STATE_UNBLOCKED:
  6681. if (iwl3945_is_rfkill_hw(priv)) {
  6682. err = -EBUSY;
  6683. goto out_unlock;
  6684. }
  6685. iwl3945_radio_kill_sw(priv, 0);
  6686. break;
  6687. case RFKILL_STATE_SOFT_BLOCKED:
  6688. iwl3945_radio_kill_sw(priv, 1);
  6689. break;
  6690. default:
  6691. IWL_WARNING("we received unexpected RFKILL state %d\n", state);
  6692. break;
  6693. }
  6694. out_unlock:
  6695. mutex_unlock(&priv->mutex);
  6696. return err;
  6697. }
  6698. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6699. {
  6700. struct device *device = wiphy_dev(priv->hw->wiphy);
  6701. int ret = 0;
  6702. BUG_ON(device == NULL);
  6703. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6704. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6705. if (!priv->rfkill) {
  6706. IWL_ERROR("Unable to allocate rfkill device.\n");
  6707. ret = -ENOMEM;
  6708. goto error;
  6709. }
  6710. priv->rfkill->name = priv->cfg->name;
  6711. priv->rfkill->data = priv;
  6712. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6713. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6714. priv->rfkill->user_claim_unsupported = 1;
  6715. priv->rfkill->dev.class->suspend = NULL;
  6716. priv->rfkill->dev.class->resume = NULL;
  6717. ret = rfkill_register(priv->rfkill);
  6718. if (ret) {
  6719. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6720. goto freed_rfkill;
  6721. }
  6722. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6723. return ret;
  6724. freed_rfkill:
  6725. if (priv->rfkill != NULL)
  6726. rfkill_free(priv->rfkill);
  6727. priv->rfkill = NULL;
  6728. error:
  6729. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6730. return ret;
  6731. }
  6732. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6733. {
  6734. if (priv->rfkill)
  6735. rfkill_unregister(priv->rfkill);
  6736. priv->rfkill = NULL;
  6737. }
  6738. /* set rf-kill to the right state. */
  6739. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6740. {
  6741. if (!priv->rfkill)
  6742. return;
  6743. if (iwl3945_is_rfkill_hw(priv)) {
  6744. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6745. return;
  6746. }
  6747. if (!iwl3945_is_rfkill_sw(priv))
  6748. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6749. else
  6750. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6751. }
  6752. #endif
  6753. /*****************************************************************************
  6754. *
  6755. * driver and module entry point
  6756. *
  6757. *****************************************************************************/
  6758. static struct pci_driver iwl3945_driver = {
  6759. .name = DRV_NAME,
  6760. .id_table = iwl3945_hw_card_ids,
  6761. .probe = iwl3945_pci_probe,
  6762. .remove = __devexit_p(iwl3945_pci_remove),
  6763. #ifdef CONFIG_PM
  6764. .suspend = iwl3945_pci_suspend,
  6765. .resume = iwl3945_pci_resume,
  6766. #endif
  6767. };
  6768. static int __init iwl3945_init(void)
  6769. {
  6770. int ret;
  6771. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6772. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6773. ret = iwl3945_rate_control_register();
  6774. if (ret) {
  6775. printk(KERN_ERR DRV_NAME
  6776. "Unable to register rate control algorithm: %d\n", ret);
  6777. return ret;
  6778. }
  6779. ret = pci_register_driver(&iwl3945_driver);
  6780. if (ret) {
  6781. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6782. goto error_register;
  6783. }
  6784. return ret;
  6785. error_register:
  6786. iwl3945_rate_control_unregister();
  6787. return ret;
  6788. }
  6789. static void __exit iwl3945_exit(void)
  6790. {
  6791. pci_unregister_driver(&iwl3945_driver);
  6792. iwl3945_rate_control_unregister();
  6793. }
  6794. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6795. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6796. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6797. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6798. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6799. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6800. MODULE_PARM_DESC(hwcrypto,
  6801. "using hardware crypto engine (default 0 [software])\n");
  6802. module_param_named(debug, iwl3945_param_debug, uint, 0444);
  6803. MODULE_PARM_DESC(debug, "debug output mask");
  6804. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6805. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6806. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6807. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6808. module_exit(iwl3945_exit);
  6809. module_init(iwl3945_init);