hpsa.c 124 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12. * NON INFRINGEMENT. See the GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. *
  18. * Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/types.h>
  24. #include <linux/pci.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/delay.h>
  28. #include <linux/fs.h>
  29. #include <linux/timer.h>
  30. #include <linux/seq_file.h>
  31. #include <linux/init.h>
  32. #include <linux/spinlock.h>
  33. #include <linux/compat.h>
  34. #include <linux/blktrace_api.h>
  35. #include <linux/uaccess.h>
  36. #include <linux/io.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/completion.h>
  39. #include <linux/moduleparam.h>
  40. #include <scsi/scsi.h>
  41. #include <scsi/scsi_cmnd.h>
  42. #include <scsi/scsi_device.h>
  43. #include <scsi/scsi_host.h>
  44. #include <scsi/scsi_tcq.h>
  45. #include <linux/cciss_ioctl.h>
  46. #include <linux/string.h>
  47. #include <linux/bitmap.h>
  48. #include <linux/atomic.h>
  49. #include <linux/kthread.h>
  50. #include "hpsa_cmd.h"
  51. #include "hpsa.h"
  52. /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
  53. #define HPSA_DRIVER_VERSION "2.0.2-1"
  54. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  55. /* How long to wait (in milliseconds) for board to go into simple mode */
  56. #define MAX_CONFIG_WAIT 30000
  57. #define MAX_IOCTL_CONFIG_WAIT 1000
  58. /*define how many times we will try a command because of bus resets */
  59. #define MAX_CMD_RETRIES 3
  60. /* Embedded module documentation macros - see modules.h */
  61. MODULE_AUTHOR("Hewlett-Packard Company");
  62. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  63. HPSA_DRIVER_VERSION);
  64. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  65. MODULE_VERSION(HPSA_DRIVER_VERSION);
  66. MODULE_LICENSE("GPL");
  67. static int hpsa_allow_any;
  68. module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
  69. MODULE_PARM_DESC(hpsa_allow_any,
  70. "Allow hpsa driver to access unknown HP Smart Array hardware");
  71. static int hpsa_simple_mode;
  72. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  73. MODULE_PARM_DESC(hpsa_simple_mode,
  74. "Use 'simple mode' rather than 'performant mode'");
  75. /* define the PCI info for the cards we can control */
  76. static const struct pci_device_id hpsa_pci_device_id[] = {
  77. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  78. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  79. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  80. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  81. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  82. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324a},
  83. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324b},
  84. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  85. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  86. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  92. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  93. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  94. {0,}
  95. };
  96. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  97. /* board_id = Subsystem Device ID & Vendor ID
  98. * product = Marketing Name for the board
  99. * access = Address of the struct of function pointers
  100. */
  101. static struct board_type products[] = {
  102. {0x3241103C, "Smart Array P212", &SA5_access},
  103. {0x3243103C, "Smart Array P410", &SA5_access},
  104. {0x3245103C, "Smart Array P410i", &SA5_access},
  105. {0x3247103C, "Smart Array P411", &SA5_access},
  106. {0x3249103C, "Smart Array P812", &SA5_access},
  107. {0x324a103C, "Smart Array P712m", &SA5_access},
  108. {0x324b103C, "Smart Array P711m", &SA5_access},
  109. {0x3350103C, "Smart Array", &SA5_access},
  110. {0x3351103C, "Smart Array", &SA5_access},
  111. {0x3352103C, "Smart Array", &SA5_access},
  112. {0x3353103C, "Smart Array", &SA5_access},
  113. {0x3354103C, "Smart Array", &SA5_access},
  114. {0x3355103C, "Smart Array", &SA5_access},
  115. {0x3356103C, "Smart Array", &SA5_access},
  116. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  117. };
  118. static int number_of_controllers;
  119. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  120. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  121. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
  122. static void start_io(struct ctlr_info *h);
  123. #ifdef CONFIG_COMPAT
  124. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
  125. #endif
  126. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  127. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
  128. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  129. static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
  130. static void fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  131. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  132. int cmd_type);
  133. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  134. static void hpsa_scan_start(struct Scsi_Host *);
  135. static int hpsa_scan_finished(struct Scsi_Host *sh,
  136. unsigned long elapsed_time);
  137. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  138. int qdepth, int reason);
  139. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  140. static int hpsa_slave_alloc(struct scsi_device *sdev);
  141. static void hpsa_slave_destroy(struct scsi_device *sdev);
  142. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
  143. static int check_for_unit_attention(struct ctlr_info *h,
  144. struct CommandList *c);
  145. static void check_ioctl_unit_attention(struct ctlr_info *h,
  146. struct CommandList *c);
  147. /* performant mode helper functions */
  148. static void calc_bucket_map(int *bucket, int num_buckets,
  149. int nsgs, int *bucket_map);
  150. static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  151. static inline u32 next_command(struct ctlr_info *h);
  152. static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
  153. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  154. u64 *cfg_offset);
  155. static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  156. unsigned long *memory_bar);
  157. static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
  158. static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
  159. void __iomem *vaddr, int wait_for_ready);
  160. #define BOARD_NOT_READY 0
  161. #define BOARD_READY 1
  162. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  163. {
  164. unsigned long *priv = shost_priv(sdev->host);
  165. return (struct ctlr_info *) *priv;
  166. }
  167. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  168. {
  169. unsigned long *priv = shost_priv(sh);
  170. return (struct ctlr_info *) *priv;
  171. }
  172. static int check_for_unit_attention(struct ctlr_info *h,
  173. struct CommandList *c)
  174. {
  175. if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
  176. return 0;
  177. switch (c->err_info->SenseInfo[12]) {
  178. case STATE_CHANGED:
  179. dev_warn(&h->pdev->dev, "hpsa%d: a state change "
  180. "detected, command retried\n", h->ctlr);
  181. break;
  182. case LUN_FAILED:
  183. dev_warn(&h->pdev->dev, "hpsa%d: LUN failure "
  184. "detected, action required\n", h->ctlr);
  185. break;
  186. case REPORT_LUNS_CHANGED:
  187. dev_warn(&h->pdev->dev, "hpsa%d: report LUN data "
  188. "changed, action required\n", h->ctlr);
  189. /*
  190. * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
  191. */
  192. break;
  193. case POWER_OR_RESET:
  194. dev_warn(&h->pdev->dev, "hpsa%d: a power on "
  195. "or device reset detected\n", h->ctlr);
  196. break;
  197. case UNIT_ATTENTION_CLEARED:
  198. dev_warn(&h->pdev->dev, "hpsa%d: unit attention "
  199. "cleared by another initiator\n", h->ctlr);
  200. break;
  201. default:
  202. dev_warn(&h->pdev->dev, "hpsa%d: unknown "
  203. "unit attention detected\n", h->ctlr);
  204. break;
  205. }
  206. return 1;
  207. }
  208. static ssize_t host_store_rescan(struct device *dev,
  209. struct device_attribute *attr,
  210. const char *buf, size_t count)
  211. {
  212. struct ctlr_info *h;
  213. struct Scsi_Host *shost = class_to_shost(dev);
  214. h = shost_to_hba(shost);
  215. hpsa_scan_start(h->scsi_host);
  216. return count;
  217. }
  218. static ssize_t host_show_firmware_revision(struct device *dev,
  219. struct device_attribute *attr, char *buf)
  220. {
  221. struct ctlr_info *h;
  222. struct Scsi_Host *shost = class_to_shost(dev);
  223. unsigned char *fwrev;
  224. h = shost_to_hba(shost);
  225. if (!h->hba_inquiry_data)
  226. return 0;
  227. fwrev = &h->hba_inquiry_data[32];
  228. return snprintf(buf, 20, "%c%c%c%c\n",
  229. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  230. }
  231. static ssize_t host_show_commands_outstanding(struct device *dev,
  232. struct device_attribute *attr, char *buf)
  233. {
  234. struct Scsi_Host *shost = class_to_shost(dev);
  235. struct ctlr_info *h = shost_to_hba(shost);
  236. return snprintf(buf, 20, "%d\n", h->commands_outstanding);
  237. }
  238. static ssize_t host_show_transport_mode(struct device *dev,
  239. struct device_attribute *attr, char *buf)
  240. {
  241. struct ctlr_info *h;
  242. struct Scsi_Host *shost = class_to_shost(dev);
  243. h = shost_to_hba(shost);
  244. return snprintf(buf, 20, "%s\n",
  245. h->transMethod & CFGTBL_Trans_Performant ?
  246. "performant" : "simple");
  247. }
  248. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  249. static u32 unresettable_controller[] = {
  250. 0x324a103C, /* Smart Array P712m */
  251. 0x324b103C, /* SmartArray P711m */
  252. 0x3223103C, /* Smart Array P800 */
  253. 0x3234103C, /* Smart Array P400 */
  254. 0x3235103C, /* Smart Array P400i */
  255. 0x3211103C, /* Smart Array E200i */
  256. 0x3212103C, /* Smart Array E200 */
  257. 0x3213103C, /* Smart Array E200i */
  258. 0x3214103C, /* Smart Array E200i */
  259. 0x3215103C, /* Smart Array E200i */
  260. 0x3237103C, /* Smart Array E500 */
  261. 0x323D103C, /* Smart Array P700m */
  262. 0x409C0E11, /* Smart Array 6400 */
  263. 0x409D0E11, /* Smart Array 6400 EM */
  264. };
  265. /* List of controllers which cannot even be soft reset */
  266. static u32 soft_unresettable_controller[] = {
  267. /* Exclude 640x boards. These are two pci devices in one slot
  268. * which share a battery backed cache module. One controls the
  269. * cache, the other accesses the cache through the one that controls
  270. * it. If we reset the one controlling the cache, the other will
  271. * likely not be happy. Just forbid resetting this conjoined mess.
  272. * The 640x isn't really supported by hpsa anyway.
  273. */
  274. 0x409C0E11, /* Smart Array 6400 */
  275. 0x409D0E11, /* Smart Array 6400 EM */
  276. };
  277. static int ctlr_is_hard_resettable(u32 board_id)
  278. {
  279. int i;
  280. for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
  281. if (unresettable_controller[i] == board_id)
  282. return 0;
  283. return 1;
  284. }
  285. static int ctlr_is_soft_resettable(u32 board_id)
  286. {
  287. int i;
  288. for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
  289. if (soft_unresettable_controller[i] == board_id)
  290. return 0;
  291. return 1;
  292. }
  293. static int ctlr_is_resettable(u32 board_id)
  294. {
  295. return ctlr_is_hard_resettable(board_id) ||
  296. ctlr_is_soft_resettable(board_id);
  297. }
  298. static ssize_t host_show_resettable(struct device *dev,
  299. struct device_attribute *attr, char *buf)
  300. {
  301. struct ctlr_info *h;
  302. struct Scsi_Host *shost = class_to_shost(dev);
  303. h = shost_to_hba(shost);
  304. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  305. }
  306. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  307. {
  308. return (scsi3addr[3] & 0xC0) == 0x40;
  309. }
  310. static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
  311. "UNKNOWN"
  312. };
  313. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
  314. static ssize_t raid_level_show(struct device *dev,
  315. struct device_attribute *attr, char *buf)
  316. {
  317. ssize_t l = 0;
  318. unsigned char rlevel;
  319. struct ctlr_info *h;
  320. struct scsi_device *sdev;
  321. struct hpsa_scsi_dev_t *hdev;
  322. unsigned long flags;
  323. sdev = to_scsi_device(dev);
  324. h = sdev_to_hba(sdev);
  325. spin_lock_irqsave(&h->lock, flags);
  326. hdev = sdev->hostdata;
  327. if (!hdev) {
  328. spin_unlock_irqrestore(&h->lock, flags);
  329. return -ENODEV;
  330. }
  331. /* Is this even a logical drive? */
  332. if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
  333. spin_unlock_irqrestore(&h->lock, flags);
  334. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  335. return l;
  336. }
  337. rlevel = hdev->raid_level;
  338. spin_unlock_irqrestore(&h->lock, flags);
  339. if (rlevel > RAID_UNKNOWN)
  340. rlevel = RAID_UNKNOWN;
  341. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  342. return l;
  343. }
  344. static ssize_t lunid_show(struct device *dev,
  345. struct device_attribute *attr, char *buf)
  346. {
  347. struct ctlr_info *h;
  348. struct scsi_device *sdev;
  349. struct hpsa_scsi_dev_t *hdev;
  350. unsigned long flags;
  351. unsigned char lunid[8];
  352. sdev = to_scsi_device(dev);
  353. h = sdev_to_hba(sdev);
  354. spin_lock_irqsave(&h->lock, flags);
  355. hdev = sdev->hostdata;
  356. if (!hdev) {
  357. spin_unlock_irqrestore(&h->lock, flags);
  358. return -ENODEV;
  359. }
  360. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  361. spin_unlock_irqrestore(&h->lock, flags);
  362. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  363. lunid[0], lunid[1], lunid[2], lunid[3],
  364. lunid[4], lunid[5], lunid[6], lunid[7]);
  365. }
  366. static ssize_t unique_id_show(struct device *dev,
  367. struct device_attribute *attr, char *buf)
  368. {
  369. struct ctlr_info *h;
  370. struct scsi_device *sdev;
  371. struct hpsa_scsi_dev_t *hdev;
  372. unsigned long flags;
  373. unsigned char sn[16];
  374. sdev = to_scsi_device(dev);
  375. h = sdev_to_hba(sdev);
  376. spin_lock_irqsave(&h->lock, flags);
  377. hdev = sdev->hostdata;
  378. if (!hdev) {
  379. spin_unlock_irqrestore(&h->lock, flags);
  380. return -ENODEV;
  381. }
  382. memcpy(sn, hdev->device_id, sizeof(sn));
  383. spin_unlock_irqrestore(&h->lock, flags);
  384. return snprintf(buf, 16 * 2 + 2,
  385. "%02X%02X%02X%02X%02X%02X%02X%02X"
  386. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  387. sn[0], sn[1], sn[2], sn[3],
  388. sn[4], sn[5], sn[6], sn[7],
  389. sn[8], sn[9], sn[10], sn[11],
  390. sn[12], sn[13], sn[14], sn[15]);
  391. }
  392. static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
  393. static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
  394. static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
  395. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  396. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  397. host_show_firmware_revision, NULL);
  398. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  399. host_show_commands_outstanding, NULL);
  400. static DEVICE_ATTR(transport_mode, S_IRUGO,
  401. host_show_transport_mode, NULL);
  402. static DEVICE_ATTR(resettable, S_IRUGO,
  403. host_show_resettable, NULL);
  404. static struct device_attribute *hpsa_sdev_attrs[] = {
  405. &dev_attr_raid_level,
  406. &dev_attr_lunid,
  407. &dev_attr_unique_id,
  408. NULL,
  409. };
  410. static struct device_attribute *hpsa_shost_attrs[] = {
  411. &dev_attr_rescan,
  412. &dev_attr_firmware_revision,
  413. &dev_attr_commands_outstanding,
  414. &dev_attr_transport_mode,
  415. &dev_attr_resettable,
  416. NULL,
  417. };
  418. static struct scsi_host_template hpsa_driver_template = {
  419. .module = THIS_MODULE,
  420. .name = "hpsa",
  421. .proc_name = "hpsa",
  422. .queuecommand = hpsa_scsi_queue_command,
  423. .scan_start = hpsa_scan_start,
  424. .scan_finished = hpsa_scan_finished,
  425. .change_queue_depth = hpsa_change_queue_depth,
  426. .this_id = -1,
  427. .use_clustering = ENABLE_CLUSTERING,
  428. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  429. .ioctl = hpsa_ioctl,
  430. .slave_alloc = hpsa_slave_alloc,
  431. .slave_destroy = hpsa_slave_destroy,
  432. #ifdef CONFIG_COMPAT
  433. .compat_ioctl = hpsa_compat_ioctl,
  434. #endif
  435. .sdev_attrs = hpsa_sdev_attrs,
  436. .shost_attrs = hpsa_shost_attrs,
  437. .max_sectors = 8192,
  438. };
  439. /* Enqueuing and dequeuing functions for cmdlists. */
  440. static inline void addQ(struct list_head *list, struct CommandList *c)
  441. {
  442. list_add_tail(&c->list, list);
  443. }
  444. static inline u32 next_command(struct ctlr_info *h)
  445. {
  446. u32 a;
  447. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  448. return h->access.command_completed(h);
  449. if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
  450. a = *(h->reply_pool_head); /* Next cmd in ring buffer */
  451. (h->reply_pool_head)++;
  452. h->commands_outstanding--;
  453. } else {
  454. a = FIFO_EMPTY;
  455. }
  456. /* Check for wraparound */
  457. if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
  458. h->reply_pool_head = h->reply_pool;
  459. h->reply_pool_wraparound ^= 1;
  460. }
  461. return a;
  462. }
  463. /* set_performant_mode: Modify the tag for cciss performant
  464. * set bit 0 for pull model, bits 3-1 for block fetch
  465. * register number
  466. */
  467. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
  468. {
  469. if (likely(h->transMethod & CFGTBL_Trans_Performant))
  470. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  471. }
  472. static void enqueue_cmd_and_start_io(struct ctlr_info *h,
  473. struct CommandList *c)
  474. {
  475. unsigned long flags;
  476. set_performant_mode(h, c);
  477. spin_lock_irqsave(&h->lock, flags);
  478. addQ(&h->reqQ, c);
  479. h->Qdepth++;
  480. start_io(h);
  481. spin_unlock_irqrestore(&h->lock, flags);
  482. }
  483. static inline void removeQ(struct CommandList *c)
  484. {
  485. if (WARN_ON(list_empty(&c->list)))
  486. return;
  487. list_del_init(&c->list);
  488. }
  489. static inline int is_hba_lunid(unsigned char scsi3addr[])
  490. {
  491. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  492. }
  493. static inline int is_scsi_rev_5(struct ctlr_info *h)
  494. {
  495. if (!h->hba_inquiry_data)
  496. return 0;
  497. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  498. return 1;
  499. return 0;
  500. }
  501. static int hpsa_find_target_lun(struct ctlr_info *h,
  502. unsigned char scsi3addr[], int bus, int *target, int *lun)
  503. {
  504. /* finds an unused bus, target, lun for a new physical device
  505. * assumes h->devlock is held
  506. */
  507. int i, found = 0;
  508. DECLARE_BITMAP(lun_taken, HPSA_MAX_SCSI_DEVS_PER_HBA);
  509. memset(&lun_taken[0], 0, HPSA_MAX_SCSI_DEVS_PER_HBA >> 3);
  510. for (i = 0; i < h->ndevices; i++) {
  511. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  512. set_bit(h->dev[i]->target, lun_taken);
  513. }
  514. for (i = 0; i < HPSA_MAX_SCSI_DEVS_PER_HBA; i++) {
  515. if (!test_bit(i, lun_taken)) {
  516. /* *bus = 1; */
  517. *target = i;
  518. *lun = 0;
  519. found = 1;
  520. break;
  521. }
  522. }
  523. return !found;
  524. }
  525. /* Add an entry into h->dev[] array. */
  526. static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
  527. struct hpsa_scsi_dev_t *device,
  528. struct hpsa_scsi_dev_t *added[], int *nadded)
  529. {
  530. /* assumes h->devlock is held */
  531. int n = h->ndevices;
  532. int i;
  533. unsigned char addr1[8], addr2[8];
  534. struct hpsa_scsi_dev_t *sd;
  535. if (n >= HPSA_MAX_SCSI_DEVS_PER_HBA) {
  536. dev_err(&h->pdev->dev, "too many devices, some will be "
  537. "inaccessible.\n");
  538. return -1;
  539. }
  540. /* physical devices do not have lun or target assigned until now. */
  541. if (device->lun != -1)
  542. /* Logical device, lun is already assigned. */
  543. goto lun_assigned;
  544. /* If this device a non-zero lun of a multi-lun device
  545. * byte 4 of the 8-byte LUN addr will contain the logical
  546. * unit no, zero otherise.
  547. */
  548. if (device->scsi3addr[4] == 0) {
  549. /* This is not a non-zero lun of a multi-lun device */
  550. if (hpsa_find_target_lun(h, device->scsi3addr,
  551. device->bus, &device->target, &device->lun) != 0)
  552. return -1;
  553. goto lun_assigned;
  554. }
  555. /* This is a non-zero lun of a multi-lun device.
  556. * Search through our list and find the device which
  557. * has the same 8 byte LUN address, excepting byte 4.
  558. * Assign the same bus and target for this new LUN.
  559. * Use the logical unit number from the firmware.
  560. */
  561. memcpy(addr1, device->scsi3addr, 8);
  562. addr1[4] = 0;
  563. for (i = 0; i < n; i++) {
  564. sd = h->dev[i];
  565. memcpy(addr2, sd->scsi3addr, 8);
  566. addr2[4] = 0;
  567. /* differ only in byte 4? */
  568. if (memcmp(addr1, addr2, 8) == 0) {
  569. device->bus = sd->bus;
  570. device->target = sd->target;
  571. device->lun = device->scsi3addr[4];
  572. break;
  573. }
  574. }
  575. if (device->lun == -1) {
  576. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  577. " suspect firmware bug or unsupported hardware "
  578. "configuration.\n");
  579. return -1;
  580. }
  581. lun_assigned:
  582. h->dev[n] = device;
  583. h->ndevices++;
  584. added[*nadded] = device;
  585. (*nadded)++;
  586. /* initially, (before registering with scsi layer) we don't
  587. * know our hostno and we don't want to print anything first
  588. * time anyway (the scsi layer's inquiries will show that info)
  589. */
  590. /* if (hostno != -1) */
  591. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
  592. scsi_device_type(device->devtype), hostno,
  593. device->bus, device->target, device->lun);
  594. return 0;
  595. }
  596. /* Replace an entry from h->dev[] array. */
  597. static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
  598. int entry, struct hpsa_scsi_dev_t *new_entry,
  599. struct hpsa_scsi_dev_t *added[], int *nadded,
  600. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  601. {
  602. /* assumes h->devlock is held */
  603. BUG_ON(entry < 0 || entry >= HPSA_MAX_SCSI_DEVS_PER_HBA);
  604. removed[*nremoved] = h->dev[entry];
  605. (*nremoved)++;
  606. /*
  607. * New physical devices won't have target/lun assigned yet
  608. * so we need to preserve the values in the slot we are replacing.
  609. */
  610. if (new_entry->target == -1) {
  611. new_entry->target = h->dev[entry]->target;
  612. new_entry->lun = h->dev[entry]->lun;
  613. }
  614. h->dev[entry] = new_entry;
  615. added[*nadded] = new_entry;
  616. (*nadded)++;
  617. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
  618. scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
  619. new_entry->target, new_entry->lun);
  620. }
  621. /* Remove an entry from h->dev[] array. */
  622. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
  623. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  624. {
  625. /* assumes h->devlock is held */
  626. int i;
  627. struct hpsa_scsi_dev_t *sd;
  628. BUG_ON(entry < 0 || entry >= HPSA_MAX_SCSI_DEVS_PER_HBA);
  629. sd = h->dev[entry];
  630. removed[*nremoved] = h->dev[entry];
  631. (*nremoved)++;
  632. for (i = entry; i < h->ndevices-1; i++)
  633. h->dev[i] = h->dev[i+1];
  634. h->ndevices--;
  635. dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
  636. scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
  637. sd->lun);
  638. }
  639. #define SCSI3ADDR_EQ(a, b) ( \
  640. (a)[7] == (b)[7] && \
  641. (a)[6] == (b)[6] && \
  642. (a)[5] == (b)[5] && \
  643. (a)[4] == (b)[4] && \
  644. (a)[3] == (b)[3] && \
  645. (a)[2] == (b)[2] && \
  646. (a)[1] == (b)[1] && \
  647. (a)[0] == (b)[0])
  648. static void fixup_botched_add(struct ctlr_info *h,
  649. struct hpsa_scsi_dev_t *added)
  650. {
  651. /* called when scsi_add_device fails in order to re-adjust
  652. * h->dev[] to match the mid layer's view.
  653. */
  654. unsigned long flags;
  655. int i, j;
  656. spin_lock_irqsave(&h->lock, flags);
  657. for (i = 0; i < h->ndevices; i++) {
  658. if (h->dev[i] == added) {
  659. for (j = i; j < h->ndevices-1; j++)
  660. h->dev[j] = h->dev[j+1];
  661. h->ndevices--;
  662. break;
  663. }
  664. }
  665. spin_unlock_irqrestore(&h->lock, flags);
  666. kfree(added);
  667. }
  668. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  669. struct hpsa_scsi_dev_t *dev2)
  670. {
  671. /* we compare everything except lun and target as these
  672. * are not yet assigned. Compare parts likely
  673. * to differ first
  674. */
  675. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  676. sizeof(dev1->scsi3addr)) != 0)
  677. return 0;
  678. if (memcmp(dev1->device_id, dev2->device_id,
  679. sizeof(dev1->device_id)) != 0)
  680. return 0;
  681. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  682. return 0;
  683. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  684. return 0;
  685. if (dev1->devtype != dev2->devtype)
  686. return 0;
  687. if (dev1->bus != dev2->bus)
  688. return 0;
  689. return 1;
  690. }
  691. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  692. * and return needle location in *index. If scsi3addr matches, but not
  693. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  694. * location in *index. If needle not found, return DEVICE_NOT_FOUND.
  695. */
  696. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  697. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  698. int *index)
  699. {
  700. int i;
  701. #define DEVICE_NOT_FOUND 0
  702. #define DEVICE_CHANGED 1
  703. #define DEVICE_SAME 2
  704. for (i = 0; i < haystack_size; i++) {
  705. if (haystack[i] == NULL) /* previously removed. */
  706. continue;
  707. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  708. *index = i;
  709. if (device_is_the_same(needle, haystack[i]))
  710. return DEVICE_SAME;
  711. else
  712. return DEVICE_CHANGED;
  713. }
  714. }
  715. *index = -1;
  716. return DEVICE_NOT_FOUND;
  717. }
  718. static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
  719. struct hpsa_scsi_dev_t *sd[], int nsds)
  720. {
  721. /* sd contains scsi3 addresses and devtypes, and inquiry
  722. * data. This function takes what's in sd to be the current
  723. * reality and updates h->dev[] to reflect that reality.
  724. */
  725. int i, entry, device_change, changes = 0;
  726. struct hpsa_scsi_dev_t *csd;
  727. unsigned long flags;
  728. struct hpsa_scsi_dev_t **added, **removed;
  729. int nadded, nremoved;
  730. struct Scsi_Host *sh = NULL;
  731. added = kzalloc(sizeof(*added) * HPSA_MAX_SCSI_DEVS_PER_HBA,
  732. GFP_KERNEL);
  733. removed = kzalloc(sizeof(*removed) * HPSA_MAX_SCSI_DEVS_PER_HBA,
  734. GFP_KERNEL);
  735. if (!added || !removed) {
  736. dev_warn(&h->pdev->dev, "out of memory in "
  737. "adjust_hpsa_scsi_table\n");
  738. goto free_and_out;
  739. }
  740. spin_lock_irqsave(&h->devlock, flags);
  741. /* find any devices in h->dev[] that are not in
  742. * sd[] and remove them from h->dev[], and for any
  743. * devices which have changed, remove the old device
  744. * info and add the new device info.
  745. */
  746. i = 0;
  747. nremoved = 0;
  748. nadded = 0;
  749. while (i < h->ndevices) {
  750. csd = h->dev[i];
  751. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  752. if (device_change == DEVICE_NOT_FOUND) {
  753. changes++;
  754. hpsa_scsi_remove_entry(h, hostno, i,
  755. removed, &nremoved);
  756. continue; /* remove ^^^, hence i not incremented */
  757. } else if (device_change == DEVICE_CHANGED) {
  758. changes++;
  759. hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
  760. added, &nadded, removed, &nremoved);
  761. /* Set it to NULL to prevent it from being freed
  762. * at the bottom of hpsa_update_scsi_devices()
  763. */
  764. sd[entry] = NULL;
  765. }
  766. i++;
  767. }
  768. /* Now, make sure every device listed in sd[] is also
  769. * listed in h->dev[], adding them if they aren't found
  770. */
  771. for (i = 0; i < nsds; i++) {
  772. if (!sd[i]) /* if already added above. */
  773. continue;
  774. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  775. h->ndevices, &entry);
  776. if (device_change == DEVICE_NOT_FOUND) {
  777. changes++;
  778. if (hpsa_scsi_add_entry(h, hostno, sd[i],
  779. added, &nadded) != 0)
  780. break;
  781. sd[i] = NULL; /* prevent from being freed later. */
  782. } else if (device_change == DEVICE_CHANGED) {
  783. /* should never happen... */
  784. changes++;
  785. dev_warn(&h->pdev->dev,
  786. "device unexpectedly changed.\n");
  787. /* but if it does happen, we just ignore that device */
  788. }
  789. }
  790. spin_unlock_irqrestore(&h->devlock, flags);
  791. /* Don't notify scsi mid layer of any changes the first time through
  792. * (or if there are no changes) scsi_scan_host will do it later the
  793. * first time through.
  794. */
  795. if (hostno == -1 || !changes)
  796. goto free_and_out;
  797. sh = h->scsi_host;
  798. /* Notify scsi mid layer of any removed devices */
  799. for (i = 0; i < nremoved; i++) {
  800. struct scsi_device *sdev =
  801. scsi_device_lookup(sh, removed[i]->bus,
  802. removed[i]->target, removed[i]->lun);
  803. if (sdev != NULL) {
  804. scsi_remove_device(sdev);
  805. scsi_device_put(sdev);
  806. } else {
  807. /* We don't expect to get here.
  808. * future cmds to this device will get selection
  809. * timeout as if the device was gone.
  810. */
  811. dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
  812. " for removal.", hostno, removed[i]->bus,
  813. removed[i]->target, removed[i]->lun);
  814. }
  815. kfree(removed[i]);
  816. removed[i] = NULL;
  817. }
  818. /* Notify scsi mid layer of any added devices */
  819. for (i = 0; i < nadded; i++) {
  820. if (scsi_add_device(sh, added[i]->bus,
  821. added[i]->target, added[i]->lun) == 0)
  822. continue;
  823. dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
  824. "device not added.\n", hostno, added[i]->bus,
  825. added[i]->target, added[i]->lun);
  826. /* now we have to remove it from h->dev,
  827. * since it didn't get added to scsi mid layer
  828. */
  829. fixup_botched_add(h, added[i]);
  830. }
  831. free_and_out:
  832. kfree(added);
  833. kfree(removed);
  834. }
  835. /*
  836. * Lookup bus/target/lun and retrun corresponding struct hpsa_scsi_dev_t *
  837. * Assume's h->devlock is held.
  838. */
  839. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  840. int bus, int target, int lun)
  841. {
  842. int i;
  843. struct hpsa_scsi_dev_t *sd;
  844. for (i = 0; i < h->ndevices; i++) {
  845. sd = h->dev[i];
  846. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  847. return sd;
  848. }
  849. return NULL;
  850. }
  851. /* link sdev->hostdata to our per-device structure. */
  852. static int hpsa_slave_alloc(struct scsi_device *sdev)
  853. {
  854. struct hpsa_scsi_dev_t *sd;
  855. unsigned long flags;
  856. struct ctlr_info *h;
  857. h = sdev_to_hba(sdev);
  858. spin_lock_irqsave(&h->devlock, flags);
  859. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  860. sdev_id(sdev), sdev->lun);
  861. if (sd != NULL)
  862. sdev->hostdata = sd;
  863. spin_unlock_irqrestore(&h->devlock, flags);
  864. return 0;
  865. }
  866. static void hpsa_slave_destroy(struct scsi_device *sdev)
  867. {
  868. /* nothing to do. */
  869. }
  870. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  871. {
  872. int i;
  873. if (!h->cmd_sg_list)
  874. return;
  875. for (i = 0; i < h->nr_cmds; i++) {
  876. kfree(h->cmd_sg_list[i]);
  877. h->cmd_sg_list[i] = NULL;
  878. }
  879. kfree(h->cmd_sg_list);
  880. h->cmd_sg_list = NULL;
  881. }
  882. static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
  883. {
  884. int i;
  885. if (h->chainsize <= 0)
  886. return 0;
  887. h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
  888. GFP_KERNEL);
  889. if (!h->cmd_sg_list)
  890. return -ENOMEM;
  891. for (i = 0; i < h->nr_cmds; i++) {
  892. h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
  893. h->chainsize, GFP_KERNEL);
  894. if (!h->cmd_sg_list[i])
  895. goto clean;
  896. }
  897. return 0;
  898. clean:
  899. hpsa_free_sg_chain_blocks(h);
  900. return -ENOMEM;
  901. }
  902. static void hpsa_map_sg_chain_block(struct ctlr_info *h,
  903. struct CommandList *c)
  904. {
  905. struct SGDescriptor *chain_sg, *chain_block;
  906. u64 temp64;
  907. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  908. chain_block = h->cmd_sg_list[c->cmdindex];
  909. chain_sg->Ext = HPSA_SG_CHAIN;
  910. chain_sg->Len = sizeof(*chain_sg) *
  911. (c->Header.SGTotal - h->max_cmd_sg_entries);
  912. temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
  913. PCI_DMA_TODEVICE);
  914. chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
  915. chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
  916. }
  917. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  918. struct CommandList *c)
  919. {
  920. struct SGDescriptor *chain_sg;
  921. union u64bit temp64;
  922. if (c->Header.SGTotal <= h->max_cmd_sg_entries)
  923. return;
  924. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  925. temp64.val32.lower = chain_sg->Addr.lower;
  926. temp64.val32.upper = chain_sg->Addr.upper;
  927. pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
  928. }
  929. static void complete_scsi_command(struct CommandList *cp)
  930. {
  931. struct scsi_cmnd *cmd;
  932. struct ctlr_info *h;
  933. struct ErrorInfo *ei;
  934. unsigned char sense_key;
  935. unsigned char asc; /* additional sense code */
  936. unsigned char ascq; /* additional sense code qualifier */
  937. unsigned long sense_data_size;
  938. ei = cp->err_info;
  939. cmd = (struct scsi_cmnd *) cp->scsi_cmd;
  940. h = cp->h;
  941. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  942. if (cp->Header.SGTotal > h->max_cmd_sg_entries)
  943. hpsa_unmap_sg_chain_block(h, cp);
  944. cmd->result = (DID_OK << 16); /* host byte */
  945. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  946. cmd->result |= ei->ScsiStatus;
  947. /* copy the sense data whether we need to or not. */
  948. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  949. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  950. else
  951. sense_data_size = sizeof(ei->SenseInfo);
  952. if (ei->SenseLen < sense_data_size)
  953. sense_data_size = ei->SenseLen;
  954. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  955. scsi_set_resid(cmd, ei->ResidualCnt);
  956. if (ei->CommandStatus == 0) {
  957. cmd->scsi_done(cmd);
  958. cmd_free(h, cp);
  959. return;
  960. }
  961. /* an error has occurred */
  962. switch (ei->CommandStatus) {
  963. case CMD_TARGET_STATUS:
  964. if (ei->ScsiStatus) {
  965. /* Get sense key */
  966. sense_key = 0xf & ei->SenseInfo[2];
  967. /* Get additional sense code */
  968. asc = ei->SenseInfo[12];
  969. /* Get addition sense code qualifier */
  970. ascq = ei->SenseInfo[13];
  971. }
  972. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  973. if (check_for_unit_attention(h, cp)) {
  974. cmd->result = DID_SOFT_ERROR << 16;
  975. break;
  976. }
  977. if (sense_key == ILLEGAL_REQUEST) {
  978. /*
  979. * SCSI REPORT_LUNS is commonly unsupported on
  980. * Smart Array. Suppress noisy complaint.
  981. */
  982. if (cp->Request.CDB[0] == REPORT_LUNS)
  983. break;
  984. /* If ASC/ASCQ indicate Logical Unit
  985. * Not Supported condition,
  986. */
  987. if ((asc == 0x25) && (ascq == 0x0)) {
  988. dev_warn(&h->pdev->dev, "cp %p "
  989. "has check condition\n", cp);
  990. break;
  991. }
  992. }
  993. if (sense_key == NOT_READY) {
  994. /* If Sense is Not Ready, Logical Unit
  995. * Not ready, Manual Intervention
  996. * required
  997. */
  998. if ((asc == 0x04) && (ascq == 0x03)) {
  999. dev_warn(&h->pdev->dev, "cp %p "
  1000. "has check condition: unit "
  1001. "not ready, manual "
  1002. "intervention required\n", cp);
  1003. break;
  1004. }
  1005. }
  1006. if (sense_key == ABORTED_COMMAND) {
  1007. /* Aborted command is retryable */
  1008. dev_warn(&h->pdev->dev, "cp %p "
  1009. "has check condition: aborted command: "
  1010. "ASC: 0x%x, ASCQ: 0x%x\n",
  1011. cp, asc, ascq);
  1012. cmd->result = DID_SOFT_ERROR << 16;
  1013. break;
  1014. }
  1015. /* Must be some other type of check condition */
  1016. dev_warn(&h->pdev->dev, "cp %p has check condition: "
  1017. "unknown type: "
  1018. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1019. "Returning result: 0x%x, "
  1020. "cmd=[%02x %02x %02x %02x %02x "
  1021. "%02x %02x %02x %02x %02x %02x "
  1022. "%02x %02x %02x %02x %02x]\n",
  1023. cp, sense_key, asc, ascq,
  1024. cmd->result,
  1025. cmd->cmnd[0], cmd->cmnd[1],
  1026. cmd->cmnd[2], cmd->cmnd[3],
  1027. cmd->cmnd[4], cmd->cmnd[5],
  1028. cmd->cmnd[6], cmd->cmnd[7],
  1029. cmd->cmnd[8], cmd->cmnd[9],
  1030. cmd->cmnd[10], cmd->cmnd[11],
  1031. cmd->cmnd[12], cmd->cmnd[13],
  1032. cmd->cmnd[14], cmd->cmnd[15]);
  1033. break;
  1034. }
  1035. /* Problem was not a check condition
  1036. * Pass it up to the upper layers...
  1037. */
  1038. if (ei->ScsiStatus) {
  1039. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  1040. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  1041. "Returning result: 0x%x\n",
  1042. cp, ei->ScsiStatus,
  1043. sense_key, asc, ascq,
  1044. cmd->result);
  1045. } else { /* scsi status is zero??? How??? */
  1046. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  1047. "Returning no connection.\n", cp),
  1048. /* Ordinarily, this case should never happen,
  1049. * but there is a bug in some released firmware
  1050. * revisions that allows it to happen if, for
  1051. * example, a 4100 backplane loses power and
  1052. * the tape drive is in it. We assume that
  1053. * it's a fatal error of some kind because we
  1054. * can't show that it wasn't. We will make it
  1055. * look like selection timeout since that is
  1056. * the most common reason for this to occur,
  1057. * and it's severe enough.
  1058. */
  1059. cmd->result = DID_NO_CONNECT << 16;
  1060. }
  1061. break;
  1062. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1063. break;
  1064. case CMD_DATA_OVERRUN:
  1065. dev_warn(&h->pdev->dev, "cp %p has"
  1066. " completed with data overrun "
  1067. "reported\n", cp);
  1068. break;
  1069. case CMD_INVALID: {
  1070. /* print_bytes(cp, sizeof(*cp), 1, 0);
  1071. print_cmd(cp); */
  1072. /* We get CMD_INVALID if you address a non-existent device
  1073. * instead of a selection timeout (no response). You will
  1074. * see this if you yank out a drive, then try to access it.
  1075. * This is kind of a shame because it means that any other
  1076. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  1077. * missing target. */
  1078. cmd->result = DID_NO_CONNECT << 16;
  1079. }
  1080. break;
  1081. case CMD_PROTOCOL_ERR:
  1082. dev_warn(&h->pdev->dev, "cp %p has "
  1083. "protocol error \n", cp);
  1084. break;
  1085. case CMD_HARDWARE_ERR:
  1086. cmd->result = DID_ERROR << 16;
  1087. dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
  1088. break;
  1089. case CMD_CONNECTION_LOST:
  1090. cmd->result = DID_ERROR << 16;
  1091. dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
  1092. break;
  1093. case CMD_ABORTED:
  1094. cmd->result = DID_ABORT << 16;
  1095. dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
  1096. cp, ei->ScsiStatus);
  1097. break;
  1098. case CMD_ABORT_FAILED:
  1099. cmd->result = DID_ERROR << 16;
  1100. dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
  1101. break;
  1102. case CMD_UNSOLICITED_ABORT:
  1103. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  1104. dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
  1105. "abort\n", cp);
  1106. break;
  1107. case CMD_TIMEOUT:
  1108. cmd->result = DID_TIME_OUT << 16;
  1109. dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
  1110. break;
  1111. case CMD_UNABORTABLE:
  1112. cmd->result = DID_ERROR << 16;
  1113. dev_warn(&h->pdev->dev, "Command unabortable\n");
  1114. break;
  1115. default:
  1116. cmd->result = DID_ERROR << 16;
  1117. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  1118. cp, ei->CommandStatus);
  1119. }
  1120. cmd->scsi_done(cmd);
  1121. cmd_free(h, cp);
  1122. }
  1123. static int hpsa_scsi_detect(struct ctlr_info *h)
  1124. {
  1125. struct Scsi_Host *sh;
  1126. int error;
  1127. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
  1128. if (sh == NULL)
  1129. goto fail;
  1130. sh->io_port = 0;
  1131. sh->n_io_port = 0;
  1132. sh->this_id = -1;
  1133. sh->max_channel = 3;
  1134. sh->max_cmd_len = MAX_COMMAND_SIZE;
  1135. sh->max_lun = HPSA_MAX_LUN;
  1136. sh->max_id = HPSA_MAX_LUN;
  1137. sh->can_queue = h->nr_cmds;
  1138. sh->cmd_per_lun = h->nr_cmds;
  1139. sh->sg_tablesize = h->maxsgentries;
  1140. h->scsi_host = sh;
  1141. sh->hostdata[0] = (unsigned long) h;
  1142. sh->irq = h->intr[h->intr_mode];
  1143. sh->unique_id = sh->irq;
  1144. error = scsi_add_host(sh, &h->pdev->dev);
  1145. if (error)
  1146. goto fail_host_put;
  1147. scsi_scan_host(sh);
  1148. return 0;
  1149. fail_host_put:
  1150. dev_err(&h->pdev->dev, "hpsa_scsi_detect: scsi_add_host"
  1151. " failed for controller %d\n", h->ctlr);
  1152. scsi_host_put(sh);
  1153. return error;
  1154. fail:
  1155. dev_err(&h->pdev->dev, "hpsa_scsi_detect: scsi_host_alloc"
  1156. " failed for controller %d\n", h->ctlr);
  1157. return -ENOMEM;
  1158. }
  1159. static void hpsa_pci_unmap(struct pci_dev *pdev,
  1160. struct CommandList *c, int sg_used, int data_direction)
  1161. {
  1162. int i;
  1163. union u64bit addr64;
  1164. for (i = 0; i < sg_used; i++) {
  1165. addr64.val32.lower = c->SG[i].Addr.lower;
  1166. addr64.val32.upper = c->SG[i].Addr.upper;
  1167. pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
  1168. data_direction);
  1169. }
  1170. }
  1171. static void hpsa_map_one(struct pci_dev *pdev,
  1172. struct CommandList *cp,
  1173. unsigned char *buf,
  1174. size_t buflen,
  1175. int data_direction)
  1176. {
  1177. u64 addr64;
  1178. if (buflen == 0 || data_direction == PCI_DMA_NONE) {
  1179. cp->Header.SGList = 0;
  1180. cp->Header.SGTotal = 0;
  1181. return;
  1182. }
  1183. addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
  1184. cp->SG[0].Addr.lower =
  1185. (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
  1186. cp->SG[0].Addr.upper =
  1187. (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
  1188. cp->SG[0].Len = buflen;
  1189. cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
  1190. cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
  1191. }
  1192. static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  1193. struct CommandList *c)
  1194. {
  1195. DECLARE_COMPLETION_ONSTACK(wait);
  1196. c->waiting = &wait;
  1197. enqueue_cmd_and_start_io(h, c);
  1198. wait_for_completion(&wait);
  1199. }
  1200. static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  1201. struct CommandList *c, int data_direction)
  1202. {
  1203. int retry_count = 0;
  1204. do {
  1205. memset(c->err_info, 0, sizeof(*c->err_info));
  1206. hpsa_scsi_do_simple_cmd_core(h, c);
  1207. retry_count++;
  1208. } while (check_for_unit_attention(h, c) && retry_count <= 3);
  1209. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  1210. }
  1211. static void hpsa_scsi_interpret_error(struct CommandList *cp)
  1212. {
  1213. struct ErrorInfo *ei;
  1214. struct device *d = &cp->h->pdev->dev;
  1215. ei = cp->err_info;
  1216. switch (ei->CommandStatus) {
  1217. case CMD_TARGET_STATUS:
  1218. dev_warn(d, "cmd %p has completed with errors\n", cp);
  1219. dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
  1220. ei->ScsiStatus);
  1221. if (ei->ScsiStatus == 0)
  1222. dev_warn(d, "SCSI status is abnormally zero. "
  1223. "(probably indicates selection timeout "
  1224. "reported incorrectly due to a known "
  1225. "firmware bug, circa July, 2001.)\n");
  1226. break;
  1227. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  1228. dev_info(d, "UNDERRUN\n");
  1229. break;
  1230. case CMD_DATA_OVERRUN:
  1231. dev_warn(d, "cp %p has completed with data overrun\n", cp);
  1232. break;
  1233. case CMD_INVALID: {
  1234. /* controller unfortunately reports SCSI passthru's
  1235. * to non-existent targets as invalid commands.
  1236. */
  1237. dev_warn(d, "cp %p is reported invalid (probably means "
  1238. "target device no longer present)\n", cp);
  1239. /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
  1240. print_cmd(cp); */
  1241. }
  1242. break;
  1243. case CMD_PROTOCOL_ERR:
  1244. dev_warn(d, "cp %p has protocol error \n", cp);
  1245. break;
  1246. case CMD_HARDWARE_ERR:
  1247. /* cmd->result = DID_ERROR << 16; */
  1248. dev_warn(d, "cp %p had hardware error\n", cp);
  1249. break;
  1250. case CMD_CONNECTION_LOST:
  1251. dev_warn(d, "cp %p had connection lost\n", cp);
  1252. break;
  1253. case CMD_ABORTED:
  1254. dev_warn(d, "cp %p was aborted\n", cp);
  1255. break;
  1256. case CMD_ABORT_FAILED:
  1257. dev_warn(d, "cp %p reports abort failed\n", cp);
  1258. break;
  1259. case CMD_UNSOLICITED_ABORT:
  1260. dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
  1261. break;
  1262. case CMD_TIMEOUT:
  1263. dev_warn(d, "cp %p timed out\n", cp);
  1264. break;
  1265. case CMD_UNABORTABLE:
  1266. dev_warn(d, "Command unabortable\n");
  1267. break;
  1268. default:
  1269. dev_warn(d, "cp %p returned unknown status %x\n", cp,
  1270. ei->CommandStatus);
  1271. }
  1272. }
  1273. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  1274. unsigned char page, unsigned char *buf,
  1275. unsigned char bufsize)
  1276. {
  1277. int rc = IO_OK;
  1278. struct CommandList *c;
  1279. struct ErrorInfo *ei;
  1280. c = cmd_special_alloc(h);
  1281. if (c == NULL) { /* trouble... */
  1282. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1283. return -ENOMEM;
  1284. }
  1285. fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, page, scsi3addr, TYPE_CMD);
  1286. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1287. ei = c->err_info;
  1288. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1289. hpsa_scsi_interpret_error(c);
  1290. rc = -1;
  1291. }
  1292. cmd_special_free(h, c);
  1293. return rc;
  1294. }
  1295. static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
  1296. {
  1297. int rc = IO_OK;
  1298. struct CommandList *c;
  1299. struct ErrorInfo *ei;
  1300. c = cmd_special_alloc(h);
  1301. if (c == NULL) { /* trouble... */
  1302. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1303. return -ENOMEM;
  1304. }
  1305. fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, scsi3addr, TYPE_MSG);
  1306. hpsa_scsi_do_simple_cmd_core(h, c);
  1307. /* no unmap needed here because no data xfer. */
  1308. ei = c->err_info;
  1309. if (ei->CommandStatus != 0) {
  1310. hpsa_scsi_interpret_error(c);
  1311. rc = -1;
  1312. }
  1313. cmd_special_free(h, c);
  1314. return rc;
  1315. }
  1316. static void hpsa_get_raid_level(struct ctlr_info *h,
  1317. unsigned char *scsi3addr, unsigned char *raid_level)
  1318. {
  1319. int rc;
  1320. unsigned char *buf;
  1321. *raid_level = RAID_UNKNOWN;
  1322. buf = kzalloc(64, GFP_KERNEL);
  1323. if (!buf)
  1324. return;
  1325. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
  1326. if (rc == 0)
  1327. *raid_level = buf[8];
  1328. if (*raid_level > RAID_UNKNOWN)
  1329. *raid_level = RAID_UNKNOWN;
  1330. kfree(buf);
  1331. return;
  1332. }
  1333. /* Get the device id from inquiry page 0x83 */
  1334. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  1335. unsigned char *device_id, int buflen)
  1336. {
  1337. int rc;
  1338. unsigned char *buf;
  1339. if (buflen > 16)
  1340. buflen = 16;
  1341. buf = kzalloc(64, GFP_KERNEL);
  1342. if (!buf)
  1343. return -1;
  1344. rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
  1345. if (rc == 0)
  1346. memcpy(device_id, &buf[8], buflen);
  1347. kfree(buf);
  1348. return rc != 0;
  1349. }
  1350. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  1351. struct ReportLUNdata *buf, int bufsize,
  1352. int extended_response)
  1353. {
  1354. int rc = IO_OK;
  1355. struct CommandList *c;
  1356. unsigned char scsi3addr[8];
  1357. struct ErrorInfo *ei;
  1358. c = cmd_special_alloc(h);
  1359. if (c == NULL) { /* trouble... */
  1360. dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  1361. return -1;
  1362. }
  1363. /* address the controller */
  1364. memset(scsi3addr, 0, sizeof(scsi3addr));
  1365. fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  1366. buf, bufsize, 0, scsi3addr, TYPE_CMD);
  1367. if (extended_response)
  1368. c->Request.CDB[1] = extended_response;
  1369. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
  1370. ei = c->err_info;
  1371. if (ei->CommandStatus != 0 &&
  1372. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  1373. hpsa_scsi_interpret_error(c);
  1374. rc = -1;
  1375. }
  1376. cmd_special_free(h, c);
  1377. return rc;
  1378. }
  1379. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  1380. struct ReportLUNdata *buf,
  1381. int bufsize, int extended_response)
  1382. {
  1383. return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
  1384. }
  1385. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  1386. struct ReportLUNdata *buf, int bufsize)
  1387. {
  1388. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  1389. }
  1390. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  1391. int bus, int target, int lun)
  1392. {
  1393. device->bus = bus;
  1394. device->target = target;
  1395. device->lun = lun;
  1396. }
  1397. static int hpsa_update_device_info(struct ctlr_info *h,
  1398. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  1399. unsigned char *is_OBDR_device)
  1400. {
  1401. #define OBDR_SIG_OFFSET 43
  1402. #define OBDR_TAPE_SIG "$DR-10"
  1403. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  1404. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  1405. unsigned char *inq_buff;
  1406. unsigned char *obdr_sig;
  1407. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  1408. if (!inq_buff)
  1409. goto bail_out;
  1410. /* Do an inquiry to the device to see what it is. */
  1411. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  1412. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  1413. /* Inquiry failed (msg printed already) */
  1414. dev_err(&h->pdev->dev,
  1415. "hpsa_update_device_info: inquiry failed\n");
  1416. goto bail_out;
  1417. }
  1418. this_device->devtype = (inq_buff[0] & 0x1f);
  1419. memcpy(this_device->scsi3addr, scsi3addr, 8);
  1420. memcpy(this_device->vendor, &inq_buff[8],
  1421. sizeof(this_device->vendor));
  1422. memcpy(this_device->model, &inq_buff[16],
  1423. sizeof(this_device->model));
  1424. memset(this_device->device_id, 0,
  1425. sizeof(this_device->device_id));
  1426. hpsa_get_device_id(h, scsi3addr, this_device->device_id,
  1427. sizeof(this_device->device_id));
  1428. if (this_device->devtype == TYPE_DISK &&
  1429. is_logical_dev_addr_mode(scsi3addr))
  1430. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  1431. else
  1432. this_device->raid_level = RAID_UNKNOWN;
  1433. if (is_OBDR_device) {
  1434. /* See if this is a One-Button-Disaster-Recovery device
  1435. * by looking for "$DR-10" at offset 43 in inquiry data.
  1436. */
  1437. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  1438. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  1439. strncmp(obdr_sig, OBDR_TAPE_SIG,
  1440. OBDR_SIG_LEN) == 0);
  1441. }
  1442. kfree(inq_buff);
  1443. return 0;
  1444. bail_out:
  1445. kfree(inq_buff);
  1446. return 1;
  1447. }
  1448. static unsigned char *msa2xxx_model[] = {
  1449. "MSA2012",
  1450. "MSA2024",
  1451. "MSA2312",
  1452. "MSA2324",
  1453. "P2000 G3 SAS",
  1454. NULL,
  1455. };
  1456. static int is_msa2xxx(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1457. {
  1458. int i;
  1459. for (i = 0; msa2xxx_model[i]; i++)
  1460. if (strncmp(device->model, msa2xxx_model[i],
  1461. strlen(msa2xxx_model[i])) == 0)
  1462. return 1;
  1463. return 0;
  1464. }
  1465. /* Helper function to assign bus, target, lun mapping of devices.
  1466. * Puts non-msa2xxx logical volumes on bus 0, msa2xxx logical
  1467. * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
  1468. * Logical drive target and lun are assigned at this time, but
  1469. * physical device lun and target assignment are deferred (assigned
  1470. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  1471. */
  1472. static void figure_bus_target_lun(struct ctlr_info *h,
  1473. u8 *lunaddrbytes, int *bus, int *target, int *lun,
  1474. struct hpsa_scsi_dev_t *device)
  1475. {
  1476. u32 lunid;
  1477. if (is_logical_dev_addr_mode(lunaddrbytes)) {
  1478. /* logical device */
  1479. if (unlikely(is_scsi_rev_5(h))) {
  1480. /* p1210m, logical drives lun assignments
  1481. * match SCSI REPORT LUNS data.
  1482. */
  1483. lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1484. *bus = 0;
  1485. *target = 0;
  1486. *lun = (lunid & 0x3fff) + 1;
  1487. } else {
  1488. /* not p1210m... */
  1489. lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
  1490. if (is_msa2xxx(h, device)) {
  1491. /* msa2xxx way, put logicals on bus 1
  1492. * and match target/lun numbers box
  1493. * reports.
  1494. */
  1495. *bus = 1;
  1496. *target = (lunid >> 16) & 0x3fff;
  1497. *lun = lunid & 0x00ff;
  1498. } else {
  1499. /* Traditional smart array way. */
  1500. *bus = 0;
  1501. *lun = 0;
  1502. *target = lunid & 0x3fff;
  1503. }
  1504. }
  1505. } else {
  1506. /* physical device */
  1507. if (is_hba_lunid(lunaddrbytes))
  1508. if (unlikely(is_scsi_rev_5(h))) {
  1509. *bus = 0; /* put p1210m ctlr at 0,0,0 */
  1510. *target = 0;
  1511. *lun = 0;
  1512. return;
  1513. } else
  1514. *bus = 3; /* traditional smartarray */
  1515. else
  1516. *bus = 2; /* physical disk */
  1517. *target = -1;
  1518. *lun = -1; /* we will fill these in later. */
  1519. }
  1520. }
  1521. /*
  1522. * If there is no lun 0 on a target, linux won't find any devices.
  1523. * For the MSA2xxx boxes, we have to manually detect the enclosure
  1524. * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
  1525. * it for some reason. *tmpdevice is the target we're adding,
  1526. * this_device is a pointer into the current element of currentsd[]
  1527. * that we're building up in update_scsi_devices(), below.
  1528. * lunzerobits is a bitmap that tracks which targets already have a
  1529. * lun 0 assigned.
  1530. * Returns 1 if an enclosure was added, 0 if not.
  1531. */
  1532. static int add_msa2xxx_enclosure_device(struct ctlr_info *h,
  1533. struct hpsa_scsi_dev_t *tmpdevice,
  1534. struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
  1535. int bus, int target, int lun, unsigned long lunzerobits[],
  1536. int *nmsa2xxx_enclosures)
  1537. {
  1538. unsigned char scsi3addr[8];
  1539. if (test_bit(target, lunzerobits))
  1540. return 0; /* There is already a lun 0 on this target. */
  1541. if (!is_logical_dev_addr_mode(lunaddrbytes))
  1542. return 0; /* It's the logical targets that may lack lun 0. */
  1543. if (!is_msa2xxx(h, tmpdevice))
  1544. return 0; /* It's only the MSA2xxx that have this problem. */
  1545. if (lun == 0) /* if lun is 0, then obviously we have a lun 0. */
  1546. return 0;
  1547. memset(scsi3addr, 0, 8);
  1548. scsi3addr[3] = target;
  1549. if (is_hba_lunid(scsi3addr))
  1550. return 0; /* Don't add the RAID controller here. */
  1551. if (is_scsi_rev_5(h))
  1552. return 0; /* p1210m doesn't need to do this. */
  1553. #define MAX_MSA2XXX_ENCLOSURES 32
  1554. if (*nmsa2xxx_enclosures >= MAX_MSA2XXX_ENCLOSURES) {
  1555. dev_warn(&h->pdev->dev, "Maximum number of MSA2XXX "
  1556. "enclosures exceeded. Check your hardware "
  1557. "configuration.");
  1558. return 0;
  1559. }
  1560. if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
  1561. return 0;
  1562. (*nmsa2xxx_enclosures)++;
  1563. hpsa_set_bus_target_lun(this_device, bus, target, 0);
  1564. set_bit(target, lunzerobits);
  1565. return 1;
  1566. }
  1567. /*
  1568. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  1569. * logdev. The number of luns in physdev and logdev are returned in
  1570. * *nphysicals and *nlogicals, respectively.
  1571. * Returns 0 on success, -1 otherwise.
  1572. */
  1573. static int hpsa_gather_lun_info(struct ctlr_info *h,
  1574. int reportlunsize,
  1575. struct ReportLUNdata *physdev, u32 *nphysicals,
  1576. struct ReportLUNdata *logdev, u32 *nlogicals)
  1577. {
  1578. if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize, 0)) {
  1579. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  1580. return -1;
  1581. }
  1582. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 8;
  1583. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  1584. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
  1585. " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1586. *nphysicals - HPSA_MAX_PHYS_LUN);
  1587. *nphysicals = HPSA_MAX_PHYS_LUN;
  1588. }
  1589. if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
  1590. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  1591. return -1;
  1592. }
  1593. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  1594. /* Reject Logicals in excess of our max capability. */
  1595. if (*nlogicals > HPSA_MAX_LUN) {
  1596. dev_warn(&h->pdev->dev,
  1597. "maximum logical LUNs (%d) exceeded. "
  1598. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  1599. *nlogicals - HPSA_MAX_LUN);
  1600. *nlogicals = HPSA_MAX_LUN;
  1601. }
  1602. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  1603. dev_warn(&h->pdev->dev,
  1604. "maximum logical + physical LUNs (%d) exceeded. "
  1605. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  1606. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  1607. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  1608. }
  1609. return 0;
  1610. }
  1611. u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
  1612. int nphysicals, int nlogicals, struct ReportLUNdata *physdev_list,
  1613. struct ReportLUNdata *logdev_list)
  1614. {
  1615. /* Helper function, figure out where the LUN ID info is coming from
  1616. * given index i, lists of physical and logical devices, where in
  1617. * the list the raid controller is supposed to appear (first or last)
  1618. */
  1619. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  1620. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  1621. if (i == raid_ctlr_position)
  1622. return RAID_CTLR_LUNID;
  1623. if (i < logicals_start)
  1624. return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
  1625. if (i < last_device)
  1626. return &logdev_list->LUN[i - nphysicals -
  1627. (raid_ctlr_position == 0)][0];
  1628. BUG();
  1629. return NULL;
  1630. }
  1631. static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
  1632. {
  1633. /* the idea here is we could get notified
  1634. * that some devices have changed, so we do a report
  1635. * physical luns and report logical luns cmd, and adjust
  1636. * our list of devices accordingly.
  1637. *
  1638. * The scsi3addr's of devices won't change so long as the
  1639. * adapter is not reset. That means we can rescan and
  1640. * tell which devices we already know about, vs. new
  1641. * devices, vs. disappearing devices.
  1642. */
  1643. struct ReportLUNdata *physdev_list = NULL;
  1644. struct ReportLUNdata *logdev_list = NULL;
  1645. u32 nphysicals = 0;
  1646. u32 nlogicals = 0;
  1647. u32 ndev_allocated = 0;
  1648. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  1649. int ncurrent = 0;
  1650. int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 8;
  1651. int i, nmsa2xxx_enclosures, ndevs_to_allocate;
  1652. int bus, target, lun;
  1653. int raid_ctlr_position;
  1654. DECLARE_BITMAP(lunzerobits, HPSA_MAX_TARGETS_PER_CTLR);
  1655. currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_SCSI_DEVS_PER_HBA,
  1656. GFP_KERNEL);
  1657. physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1658. logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
  1659. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  1660. if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
  1661. dev_err(&h->pdev->dev, "out of memory\n");
  1662. goto out;
  1663. }
  1664. memset(lunzerobits, 0, sizeof(lunzerobits));
  1665. if (hpsa_gather_lun_info(h, reportlunsize, physdev_list, &nphysicals,
  1666. logdev_list, &nlogicals))
  1667. goto out;
  1668. /* We might see up to 32 MSA2xxx enclosures, actually 8 of them
  1669. * but each of them 4 times through different paths. The plus 1
  1670. * is for the RAID controller.
  1671. */
  1672. ndevs_to_allocate = nphysicals + nlogicals + MAX_MSA2XXX_ENCLOSURES + 1;
  1673. /* Allocate the per device structures */
  1674. for (i = 0; i < ndevs_to_allocate; i++) {
  1675. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  1676. if (!currentsd[i]) {
  1677. dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
  1678. __FILE__, __LINE__);
  1679. goto out;
  1680. }
  1681. ndev_allocated++;
  1682. }
  1683. if (unlikely(is_scsi_rev_5(h)))
  1684. raid_ctlr_position = 0;
  1685. else
  1686. raid_ctlr_position = nphysicals + nlogicals;
  1687. /* adjust our table of devices */
  1688. nmsa2xxx_enclosures = 0;
  1689. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  1690. u8 *lunaddrbytes, is_OBDR = 0;
  1691. /* Figure out where the LUN ID info is coming from */
  1692. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  1693. i, nphysicals, nlogicals, physdev_list, logdev_list);
  1694. /* skip masked physical devices. */
  1695. if (lunaddrbytes[3] & 0xC0 &&
  1696. i < nphysicals + (raid_ctlr_position == 0))
  1697. continue;
  1698. /* Get device type, vendor, model, device id */
  1699. if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  1700. &is_OBDR))
  1701. continue; /* skip it if we can't talk to it. */
  1702. figure_bus_target_lun(h, lunaddrbytes, &bus, &target, &lun,
  1703. tmpdevice);
  1704. this_device = currentsd[ncurrent];
  1705. /*
  1706. * For the msa2xxx boxes, we have to insert a LUN 0 which
  1707. * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
  1708. * is nonetheless an enclosure device there. We have to
  1709. * present that otherwise linux won't find anything if
  1710. * there is no lun 0.
  1711. */
  1712. if (add_msa2xxx_enclosure_device(h, tmpdevice, this_device,
  1713. lunaddrbytes, bus, target, lun, lunzerobits,
  1714. &nmsa2xxx_enclosures)) {
  1715. ncurrent++;
  1716. this_device = currentsd[ncurrent];
  1717. }
  1718. *this_device = *tmpdevice;
  1719. hpsa_set_bus_target_lun(this_device, bus, target, lun);
  1720. switch (this_device->devtype) {
  1721. case TYPE_ROM:
  1722. /* We don't *really* support actual CD-ROM devices,
  1723. * just "One Button Disaster Recovery" tape drive
  1724. * which temporarily pretends to be a CD-ROM drive.
  1725. * So we check that the device is really an OBDR tape
  1726. * device by checking for "$DR-10" in bytes 43-48 of
  1727. * the inquiry data.
  1728. */
  1729. if (is_OBDR)
  1730. ncurrent++;
  1731. break;
  1732. case TYPE_DISK:
  1733. if (i < nphysicals)
  1734. break;
  1735. ncurrent++;
  1736. break;
  1737. case TYPE_TAPE:
  1738. case TYPE_MEDIUM_CHANGER:
  1739. ncurrent++;
  1740. break;
  1741. case TYPE_RAID:
  1742. /* Only present the Smartarray HBA as a RAID controller.
  1743. * If it's a RAID controller other than the HBA itself
  1744. * (an external RAID controller, MSA500 or similar)
  1745. * don't present it.
  1746. */
  1747. if (!is_hba_lunid(lunaddrbytes))
  1748. break;
  1749. ncurrent++;
  1750. break;
  1751. default:
  1752. break;
  1753. }
  1754. if (ncurrent >= HPSA_MAX_SCSI_DEVS_PER_HBA)
  1755. break;
  1756. }
  1757. adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
  1758. out:
  1759. kfree(tmpdevice);
  1760. for (i = 0; i < ndev_allocated; i++)
  1761. kfree(currentsd[i]);
  1762. kfree(currentsd);
  1763. kfree(physdev_list);
  1764. kfree(logdev_list);
  1765. }
  1766. /* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  1767. * dma mapping and fills in the scatter gather entries of the
  1768. * hpsa command, cp.
  1769. */
  1770. static int hpsa_scatter_gather(struct ctlr_info *h,
  1771. struct CommandList *cp,
  1772. struct scsi_cmnd *cmd)
  1773. {
  1774. unsigned int len;
  1775. struct scatterlist *sg;
  1776. u64 addr64;
  1777. int use_sg, i, sg_index, chained;
  1778. struct SGDescriptor *curr_sg;
  1779. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  1780. use_sg = scsi_dma_map(cmd);
  1781. if (use_sg < 0)
  1782. return use_sg;
  1783. if (!use_sg)
  1784. goto sglist_finished;
  1785. curr_sg = cp->SG;
  1786. chained = 0;
  1787. sg_index = 0;
  1788. scsi_for_each_sg(cmd, sg, use_sg, i) {
  1789. if (i == h->max_cmd_sg_entries - 1 &&
  1790. use_sg > h->max_cmd_sg_entries) {
  1791. chained = 1;
  1792. curr_sg = h->cmd_sg_list[cp->cmdindex];
  1793. sg_index = 0;
  1794. }
  1795. addr64 = (u64) sg_dma_address(sg);
  1796. len = sg_dma_len(sg);
  1797. curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
  1798. curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
  1799. curr_sg->Len = len;
  1800. curr_sg->Ext = 0; /* we are not chaining */
  1801. curr_sg++;
  1802. }
  1803. if (use_sg + chained > h->maxSG)
  1804. h->maxSG = use_sg + chained;
  1805. if (chained) {
  1806. cp->Header.SGList = h->max_cmd_sg_entries;
  1807. cp->Header.SGTotal = (u16) (use_sg + 1);
  1808. hpsa_map_sg_chain_block(h, cp);
  1809. return 0;
  1810. }
  1811. sglist_finished:
  1812. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  1813. cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
  1814. return 0;
  1815. }
  1816. static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
  1817. void (*done)(struct scsi_cmnd *))
  1818. {
  1819. struct ctlr_info *h;
  1820. struct hpsa_scsi_dev_t *dev;
  1821. unsigned char scsi3addr[8];
  1822. struct CommandList *c;
  1823. unsigned long flags;
  1824. /* Get the ptr to our adapter structure out of cmd->host. */
  1825. h = sdev_to_hba(cmd->device);
  1826. dev = cmd->device->hostdata;
  1827. if (!dev) {
  1828. cmd->result = DID_NO_CONNECT << 16;
  1829. done(cmd);
  1830. return 0;
  1831. }
  1832. memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
  1833. /* Need a lock as this is being allocated from the pool */
  1834. spin_lock_irqsave(&h->lock, flags);
  1835. c = cmd_alloc(h);
  1836. spin_unlock_irqrestore(&h->lock, flags);
  1837. if (c == NULL) { /* trouble... */
  1838. dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
  1839. return SCSI_MLQUEUE_HOST_BUSY;
  1840. }
  1841. /* Fill in the command list header */
  1842. cmd->scsi_done = done; /* save this for use by completion code */
  1843. /* save c in case we have to abort it */
  1844. cmd->host_scribble = (unsigned char *) c;
  1845. c->cmd_type = CMD_SCSI;
  1846. c->scsi_cmd = cmd;
  1847. c->Header.ReplyQueue = 0; /* unused in simple mode */
  1848. memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
  1849. c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
  1850. c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
  1851. /* Fill in the request block... */
  1852. c->Request.Timeout = 0;
  1853. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  1854. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  1855. c->Request.CDBLen = cmd->cmd_len;
  1856. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  1857. c->Request.Type.Type = TYPE_CMD;
  1858. c->Request.Type.Attribute = ATTR_SIMPLE;
  1859. switch (cmd->sc_data_direction) {
  1860. case DMA_TO_DEVICE:
  1861. c->Request.Type.Direction = XFER_WRITE;
  1862. break;
  1863. case DMA_FROM_DEVICE:
  1864. c->Request.Type.Direction = XFER_READ;
  1865. break;
  1866. case DMA_NONE:
  1867. c->Request.Type.Direction = XFER_NONE;
  1868. break;
  1869. case DMA_BIDIRECTIONAL:
  1870. /* This can happen if a buggy application does a scsi passthru
  1871. * and sets both inlen and outlen to non-zero. ( see
  1872. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  1873. */
  1874. c->Request.Type.Direction = XFER_RSVD;
  1875. /* This is technically wrong, and hpsa controllers should
  1876. * reject it with CMD_INVALID, which is the most correct
  1877. * response, but non-fibre backends appear to let it
  1878. * slide by, and give the same results as if this field
  1879. * were set correctly. Either way is acceptable for
  1880. * our purposes here.
  1881. */
  1882. break;
  1883. default:
  1884. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  1885. cmd->sc_data_direction);
  1886. BUG();
  1887. break;
  1888. }
  1889. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  1890. cmd_free(h, c);
  1891. return SCSI_MLQUEUE_HOST_BUSY;
  1892. }
  1893. enqueue_cmd_and_start_io(h, c);
  1894. /* the cmd'll come back via intr handler in complete_scsi_command() */
  1895. return 0;
  1896. }
  1897. static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
  1898. static void hpsa_scan_start(struct Scsi_Host *sh)
  1899. {
  1900. struct ctlr_info *h = shost_to_hba(sh);
  1901. unsigned long flags;
  1902. /* wait until any scan already in progress is finished. */
  1903. while (1) {
  1904. spin_lock_irqsave(&h->scan_lock, flags);
  1905. if (h->scan_finished)
  1906. break;
  1907. spin_unlock_irqrestore(&h->scan_lock, flags);
  1908. wait_event(h->scan_wait_queue, h->scan_finished);
  1909. /* Note: We don't need to worry about a race between this
  1910. * thread and driver unload because the midlayer will
  1911. * have incremented the reference count, so unload won't
  1912. * happen if we're in here.
  1913. */
  1914. }
  1915. h->scan_finished = 0; /* mark scan as in progress */
  1916. spin_unlock_irqrestore(&h->scan_lock, flags);
  1917. hpsa_update_scsi_devices(h, h->scsi_host->host_no);
  1918. spin_lock_irqsave(&h->scan_lock, flags);
  1919. h->scan_finished = 1; /* mark scan as finished. */
  1920. wake_up_all(&h->scan_wait_queue);
  1921. spin_unlock_irqrestore(&h->scan_lock, flags);
  1922. }
  1923. static int hpsa_scan_finished(struct Scsi_Host *sh,
  1924. unsigned long elapsed_time)
  1925. {
  1926. struct ctlr_info *h = shost_to_hba(sh);
  1927. unsigned long flags;
  1928. int finished;
  1929. spin_lock_irqsave(&h->scan_lock, flags);
  1930. finished = h->scan_finished;
  1931. spin_unlock_irqrestore(&h->scan_lock, flags);
  1932. return finished;
  1933. }
  1934. static int hpsa_change_queue_depth(struct scsi_device *sdev,
  1935. int qdepth, int reason)
  1936. {
  1937. struct ctlr_info *h = sdev_to_hba(sdev);
  1938. if (reason != SCSI_QDEPTH_DEFAULT)
  1939. return -ENOTSUPP;
  1940. if (qdepth < 1)
  1941. qdepth = 1;
  1942. else
  1943. if (qdepth > h->nr_cmds)
  1944. qdepth = h->nr_cmds;
  1945. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1946. return sdev->queue_depth;
  1947. }
  1948. static void hpsa_unregister_scsi(struct ctlr_info *h)
  1949. {
  1950. /* we are being forcibly unloaded, and may not refuse. */
  1951. scsi_remove_host(h->scsi_host);
  1952. scsi_host_put(h->scsi_host);
  1953. h->scsi_host = NULL;
  1954. }
  1955. static int hpsa_register_scsi(struct ctlr_info *h)
  1956. {
  1957. int rc;
  1958. rc = hpsa_scsi_detect(h);
  1959. if (rc != 0)
  1960. dev_err(&h->pdev->dev, "hpsa_register_scsi: failed"
  1961. " hpsa_scsi_detect(), rc is %d\n", rc);
  1962. return rc;
  1963. }
  1964. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  1965. unsigned char lunaddr[])
  1966. {
  1967. int rc = 0;
  1968. int count = 0;
  1969. int waittime = 1; /* seconds */
  1970. struct CommandList *c;
  1971. c = cmd_special_alloc(h);
  1972. if (!c) {
  1973. dev_warn(&h->pdev->dev, "out of memory in "
  1974. "wait_for_device_to_become_ready.\n");
  1975. return IO_ERROR;
  1976. }
  1977. /* Send test unit ready until device ready, or give up. */
  1978. while (count < HPSA_TUR_RETRY_LIMIT) {
  1979. /* Wait for a bit. do this first, because if we send
  1980. * the TUR right away, the reset will just abort it.
  1981. */
  1982. msleep(1000 * waittime);
  1983. count++;
  1984. /* Increase wait time with each try, up to a point. */
  1985. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  1986. waittime = waittime * 2;
  1987. /* Send the Test Unit Ready */
  1988. fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, lunaddr, TYPE_CMD);
  1989. hpsa_scsi_do_simple_cmd_core(h, c);
  1990. /* no unmap needed here because no data xfer. */
  1991. if (c->err_info->CommandStatus == CMD_SUCCESS)
  1992. break;
  1993. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  1994. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  1995. (c->err_info->SenseInfo[2] == NO_SENSE ||
  1996. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  1997. break;
  1998. dev_warn(&h->pdev->dev, "waiting %d secs "
  1999. "for device to become ready.\n", waittime);
  2000. rc = 1; /* device not ready. */
  2001. }
  2002. if (rc)
  2003. dev_warn(&h->pdev->dev, "giving up on device.\n");
  2004. else
  2005. dev_warn(&h->pdev->dev, "device is ready.\n");
  2006. cmd_special_free(h, c);
  2007. return rc;
  2008. }
  2009. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  2010. * complaining. Doing a host- or bus-reset can't do anything good here.
  2011. */
  2012. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  2013. {
  2014. int rc;
  2015. struct ctlr_info *h;
  2016. struct hpsa_scsi_dev_t *dev;
  2017. /* find the controller to which the command to be aborted was sent */
  2018. h = sdev_to_hba(scsicmd->device);
  2019. if (h == NULL) /* paranoia */
  2020. return FAILED;
  2021. dev = scsicmd->device->hostdata;
  2022. if (!dev) {
  2023. dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
  2024. "device lookup failed.\n");
  2025. return FAILED;
  2026. }
  2027. dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
  2028. h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
  2029. /* send a reset to the SCSI LUN which the command was sent to */
  2030. rc = hpsa_send_reset(h, dev->scsi3addr);
  2031. if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
  2032. return SUCCESS;
  2033. dev_warn(&h->pdev->dev, "resetting device failed.\n");
  2034. return FAILED;
  2035. }
  2036. /*
  2037. * For operations that cannot sleep, a command block is allocated at init,
  2038. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  2039. * which ones are free or in use. Lock must be held when calling this.
  2040. * cmd_free() is the complement.
  2041. */
  2042. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  2043. {
  2044. struct CommandList *c;
  2045. int i;
  2046. union u64bit temp64;
  2047. dma_addr_t cmd_dma_handle, err_dma_handle;
  2048. do {
  2049. i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
  2050. if (i == h->nr_cmds)
  2051. return NULL;
  2052. } while (test_and_set_bit
  2053. (i & (BITS_PER_LONG - 1),
  2054. h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
  2055. c = h->cmd_pool + i;
  2056. memset(c, 0, sizeof(*c));
  2057. cmd_dma_handle = h->cmd_pool_dhandle
  2058. + i * sizeof(*c);
  2059. c->err_info = h->errinfo_pool + i;
  2060. memset(c->err_info, 0, sizeof(*c->err_info));
  2061. err_dma_handle = h->errinfo_pool_dhandle
  2062. + i * sizeof(*c->err_info);
  2063. h->nr_allocs++;
  2064. c->cmdindex = i;
  2065. INIT_LIST_HEAD(&c->list);
  2066. c->busaddr = (u32) cmd_dma_handle;
  2067. temp64.val = (u64) err_dma_handle;
  2068. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2069. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2070. c->ErrDesc.Len = sizeof(*c->err_info);
  2071. c->h = h;
  2072. return c;
  2073. }
  2074. /* For operations that can wait for kmalloc to possibly sleep,
  2075. * this routine can be called. Lock need not be held to call
  2076. * cmd_special_alloc. cmd_special_free() is the complement.
  2077. */
  2078. static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
  2079. {
  2080. struct CommandList *c;
  2081. union u64bit temp64;
  2082. dma_addr_t cmd_dma_handle, err_dma_handle;
  2083. c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
  2084. if (c == NULL)
  2085. return NULL;
  2086. memset(c, 0, sizeof(*c));
  2087. c->cmdindex = -1;
  2088. c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
  2089. &err_dma_handle);
  2090. if (c->err_info == NULL) {
  2091. pci_free_consistent(h->pdev,
  2092. sizeof(*c), c, cmd_dma_handle);
  2093. return NULL;
  2094. }
  2095. memset(c->err_info, 0, sizeof(*c->err_info));
  2096. INIT_LIST_HEAD(&c->list);
  2097. c->busaddr = (u32) cmd_dma_handle;
  2098. temp64.val = (u64) err_dma_handle;
  2099. c->ErrDesc.Addr.lower = temp64.val32.lower;
  2100. c->ErrDesc.Addr.upper = temp64.val32.upper;
  2101. c->ErrDesc.Len = sizeof(*c->err_info);
  2102. c->h = h;
  2103. return c;
  2104. }
  2105. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  2106. {
  2107. int i;
  2108. i = c - h->cmd_pool;
  2109. clear_bit(i & (BITS_PER_LONG - 1),
  2110. h->cmd_pool_bits + (i / BITS_PER_LONG));
  2111. h->nr_frees++;
  2112. }
  2113. static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
  2114. {
  2115. union u64bit temp64;
  2116. temp64.val32.lower = c->ErrDesc.Addr.lower;
  2117. temp64.val32.upper = c->ErrDesc.Addr.upper;
  2118. pci_free_consistent(h->pdev, sizeof(*c->err_info),
  2119. c->err_info, (dma_addr_t) temp64.val);
  2120. pci_free_consistent(h->pdev, sizeof(*c),
  2121. c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
  2122. }
  2123. #ifdef CONFIG_COMPAT
  2124. static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
  2125. {
  2126. IOCTL32_Command_struct __user *arg32 =
  2127. (IOCTL32_Command_struct __user *) arg;
  2128. IOCTL_Command_struct arg64;
  2129. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  2130. int err;
  2131. u32 cp;
  2132. memset(&arg64, 0, sizeof(arg64));
  2133. err = 0;
  2134. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2135. sizeof(arg64.LUN_info));
  2136. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2137. sizeof(arg64.Request));
  2138. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2139. sizeof(arg64.error_info));
  2140. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2141. err |= get_user(cp, &arg32->buf);
  2142. arg64.buf = compat_ptr(cp);
  2143. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2144. if (err)
  2145. return -EFAULT;
  2146. err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
  2147. if (err)
  2148. return err;
  2149. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2150. sizeof(arg32->error_info));
  2151. if (err)
  2152. return -EFAULT;
  2153. return err;
  2154. }
  2155. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  2156. int cmd, void *arg)
  2157. {
  2158. BIG_IOCTL32_Command_struct __user *arg32 =
  2159. (BIG_IOCTL32_Command_struct __user *) arg;
  2160. BIG_IOCTL_Command_struct arg64;
  2161. BIG_IOCTL_Command_struct __user *p =
  2162. compat_alloc_user_space(sizeof(arg64));
  2163. int err;
  2164. u32 cp;
  2165. memset(&arg64, 0, sizeof(arg64));
  2166. err = 0;
  2167. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  2168. sizeof(arg64.LUN_info));
  2169. err |= copy_from_user(&arg64.Request, &arg32->Request,
  2170. sizeof(arg64.Request));
  2171. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  2172. sizeof(arg64.error_info));
  2173. err |= get_user(arg64.buf_size, &arg32->buf_size);
  2174. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  2175. err |= get_user(cp, &arg32->buf);
  2176. arg64.buf = compat_ptr(cp);
  2177. err |= copy_to_user(p, &arg64, sizeof(arg64));
  2178. if (err)
  2179. return -EFAULT;
  2180. err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
  2181. if (err)
  2182. return err;
  2183. err |= copy_in_user(&arg32->error_info, &p->error_info,
  2184. sizeof(arg32->error_info));
  2185. if (err)
  2186. return -EFAULT;
  2187. return err;
  2188. }
  2189. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2190. {
  2191. switch (cmd) {
  2192. case CCISS_GETPCIINFO:
  2193. case CCISS_GETINTINFO:
  2194. case CCISS_SETINTINFO:
  2195. case CCISS_GETNODENAME:
  2196. case CCISS_SETNODENAME:
  2197. case CCISS_GETHEARTBEAT:
  2198. case CCISS_GETBUSTYPES:
  2199. case CCISS_GETFIRMVER:
  2200. case CCISS_GETDRIVVER:
  2201. case CCISS_REVALIDVOLS:
  2202. case CCISS_DEREGDISK:
  2203. case CCISS_REGNEWDISK:
  2204. case CCISS_REGNEWD:
  2205. case CCISS_RESCANDISK:
  2206. case CCISS_GETLUNINFO:
  2207. return hpsa_ioctl(dev, cmd, arg);
  2208. case CCISS_PASSTHRU32:
  2209. return hpsa_ioctl32_passthru(dev, cmd, arg);
  2210. case CCISS_BIG_PASSTHRU32:
  2211. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  2212. default:
  2213. return -ENOIOCTLCMD;
  2214. }
  2215. }
  2216. #endif
  2217. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  2218. {
  2219. struct hpsa_pci_info pciinfo;
  2220. if (!argp)
  2221. return -EINVAL;
  2222. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  2223. pciinfo.bus = h->pdev->bus->number;
  2224. pciinfo.dev_fn = h->pdev->devfn;
  2225. pciinfo.board_id = h->board_id;
  2226. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  2227. return -EFAULT;
  2228. return 0;
  2229. }
  2230. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  2231. {
  2232. DriverVer_type DriverVer;
  2233. unsigned char vmaj, vmin, vsubmin;
  2234. int rc;
  2235. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  2236. &vmaj, &vmin, &vsubmin);
  2237. if (rc != 3) {
  2238. dev_info(&h->pdev->dev, "driver version string '%s' "
  2239. "unrecognized.", HPSA_DRIVER_VERSION);
  2240. vmaj = 0;
  2241. vmin = 0;
  2242. vsubmin = 0;
  2243. }
  2244. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  2245. if (!argp)
  2246. return -EINVAL;
  2247. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  2248. return -EFAULT;
  2249. return 0;
  2250. }
  2251. static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2252. {
  2253. IOCTL_Command_struct iocommand;
  2254. struct CommandList *c;
  2255. char *buff = NULL;
  2256. union u64bit temp64;
  2257. if (!argp)
  2258. return -EINVAL;
  2259. if (!capable(CAP_SYS_RAWIO))
  2260. return -EPERM;
  2261. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  2262. return -EFAULT;
  2263. if ((iocommand.buf_size < 1) &&
  2264. (iocommand.Request.Type.Direction != XFER_NONE)) {
  2265. return -EINVAL;
  2266. }
  2267. if (iocommand.buf_size > 0) {
  2268. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  2269. if (buff == NULL)
  2270. return -EFAULT;
  2271. if (iocommand.Request.Type.Direction == XFER_WRITE) {
  2272. /* Copy the data into the buffer we created */
  2273. if (copy_from_user(buff, iocommand.buf,
  2274. iocommand.buf_size)) {
  2275. kfree(buff);
  2276. return -EFAULT;
  2277. }
  2278. } else {
  2279. memset(buff, 0, iocommand.buf_size);
  2280. }
  2281. }
  2282. c = cmd_special_alloc(h);
  2283. if (c == NULL) {
  2284. kfree(buff);
  2285. return -ENOMEM;
  2286. }
  2287. /* Fill in the command type */
  2288. c->cmd_type = CMD_IOCTL_PEND;
  2289. /* Fill in Command Header */
  2290. c->Header.ReplyQueue = 0; /* unused in simple mode */
  2291. if (iocommand.buf_size > 0) { /* buffer to fill */
  2292. c->Header.SGList = 1;
  2293. c->Header.SGTotal = 1;
  2294. } else { /* no buffers to fill */
  2295. c->Header.SGList = 0;
  2296. c->Header.SGTotal = 0;
  2297. }
  2298. memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
  2299. /* use the kernel address the cmd block for tag */
  2300. c->Header.Tag.lower = c->busaddr;
  2301. /* Fill in Request block */
  2302. memcpy(&c->Request, &iocommand.Request,
  2303. sizeof(c->Request));
  2304. /* Fill in the scatter gather information */
  2305. if (iocommand.buf_size > 0) {
  2306. temp64.val = pci_map_single(h->pdev, buff,
  2307. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  2308. c->SG[0].Addr.lower = temp64.val32.lower;
  2309. c->SG[0].Addr.upper = temp64.val32.upper;
  2310. c->SG[0].Len = iocommand.buf_size;
  2311. c->SG[0].Ext = 0; /* we are not chaining*/
  2312. }
  2313. hpsa_scsi_do_simple_cmd_core(h, c);
  2314. if (iocommand.buf_size > 0)
  2315. hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
  2316. check_ioctl_unit_attention(h, c);
  2317. /* Copy the error information out */
  2318. memcpy(&iocommand.error_info, c->err_info,
  2319. sizeof(iocommand.error_info));
  2320. if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
  2321. kfree(buff);
  2322. cmd_special_free(h, c);
  2323. return -EFAULT;
  2324. }
  2325. if (iocommand.Request.Type.Direction == XFER_READ &&
  2326. iocommand.buf_size > 0) {
  2327. /* Copy the data out of the buffer we created */
  2328. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  2329. kfree(buff);
  2330. cmd_special_free(h, c);
  2331. return -EFAULT;
  2332. }
  2333. }
  2334. kfree(buff);
  2335. cmd_special_free(h, c);
  2336. return 0;
  2337. }
  2338. static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  2339. {
  2340. BIG_IOCTL_Command_struct *ioc;
  2341. struct CommandList *c;
  2342. unsigned char **buff = NULL;
  2343. int *buff_size = NULL;
  2344. union u64bit temp64;
  2345. BYTE sg_used = 0;
  2346. int status = 0;
  2347. int i;
  2348. u32 left;
  2349. u32 sz;
  2350. BYTE __user *data_ptr;
  2351. if (!argp)
  2352. return -EINVAL;
  2353. if (!capable(CAP_SYS_RAWIO))
  2354. return -EPERM;
  2355. ioc = (BIG_IOCTL_Command_struct *)
  2356. kmalloc(sizeof(*ioc), GFP_KERNEL);
  2357. if (!ioc) {
  2358. status = -ENOMEM;
  2359. goto cleanup1;
  2360. }
  2361. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  2362. status = -EFAULT;
  2363. goto cleanup1;
  2364. }
  2365. if ((ioc->buf_size < 1) &&
  2366. (ioc->Request.Type.Direction != XFER_NONE)) {
  2367. status = -EINVAL;
  2368. goto cleanup1;
  2369. }
  2370. /* Check kmalloc limits using all SGs */
  2371. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  2372. status = -EINVAL;
  2373. goto cleanup1;
  2374. }
  2375. if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
  2376. status = -EINVAL;
  2377. goto cleanup1;
  2378. }
  2379. buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
  2380. if (!buff) {
  2381. status = -ENOMEM;
  2382. goto cleanup1;
  2383. }
  2384. buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
  2385. if (!buff_size) {
  2386. status = -ENOMEM;
  2387. goto cleanup1;
  2388. }
  2389. left = ioc->buf_size;
  2390. data_ptr = ioc->buf;
  2391. while (left) {
  2392. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  2393. buff_size[sg_used] = sz;
  2394. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  2395. if (buff[sg_used] == NULL) {
  2396. status = -ENOMEM;
  2397. goto cleanup1;
  2398. }
  2399. if (ioc->Request.Type.Direction == XFER_WRITE) {
  2400. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  2401. status = -ENOMEM;
  2402. goto cleanup1;
  2403. }
  2404. } else
  2405. memset(buff[sg_used], 0, sz);
  2406. left -= sz;
  2407. data_ptr += sz;
  2408. sg_used++;
  2409. }
  2410. c = cmd_special_alloc(h);
  2411. if (c == NULL) {
  2412. status = -ENOMEM;
  2413. goto cleanup1;
  2414. }
  2415. c->cmd_type = CMD_IOCTL_PEND;
  2416. c->Header.ReplyQueue = 0;
  2417. c->Header.SGList = c->Header.SGTotal = sg_used;
  2418. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  2419. c->Header.Tag.lower = c->busaddr;
  2420. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  2421. if (ioc->buf_size > 0) {
  2422. int i;
  2423. for (i = 0; i < sg_used; i++) {
  2424. temp64.val = pci_map_single(h->pdev, buff[i],
  2425. buff_size[i], PCI_DMA_BIDIRECTIONAL);
  2426. c->SG[i].Addr.lower = temp64.val32.lower;
  2427. c->SG[i].Addr.upper = temp64.val32.upper;
  2428. c->SG[i].Len = buff_size[i];
  2429. /* we are not chaining */
  2430. c->SG[i].Ext = 0;
  2431. }
  2432. }
  2433. hpsa_scsi_do_simple_cmd_core(h, c);
  2434. if (sg_used)
  2435. hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
  2436. check_ioctl_unit_attention(h, c);
  2437. /* Copy the error information out */
  2438. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  2439. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  2440. cmd_special_free(h, c);
  2441. status = -EFAULT;
  2442. goto cleanup1;
  2443. }
  2444. if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
  2445. /* Copy the data out of the buffer we created */
  2446. BYTE __user *ptr = ioc->buf;
  2447. for (i = 0; i < sg_used; i++) {
  2448. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  2449. cmd_special_free(h, c);
  2450. status = -EFAULT;
  2451. goto cleanup1;
  2452. }
  2453. ptr += buff_size[i];
  2454. }
  2455. }
  2456. cmd_special_free(h, c);
  2457. status = 0;
  2458. cleanup1:
  2459. if (buff) {
  2460. for (i = 0; i < sg_used; i++)
  2461. kfree(buff[i]);
  2462. kfree(buff);
  2463. }
  2464. kfree(buff_size);
  2465. kfree(ioc);
  2466. return status;
  2467. }
  2468. static void check_ioctl_unit_attention(struct ctlr_info *h,
  2469. struct CommandList *c)
  2470. {
  2471. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  2472. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  2473. (void) check_for_unit_attention(h, c);
  2474. }
  2475. /*
  2476. * ioctl
  2477. */
  2478. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
  2479. {
  2480. struct ctlr_info *h;
  2481. void __user *argp = (void __user *)arg;
  2482. h = sdev_to_hba(dev);
  2483. switch (cmd) {
  2484. case CCISS_DEREGDISK:
  2485. case CCISS_REGNEWDISK:
  2486. case CCISS_REGNEWD:
  2487. hpsa_scan_start(h->scsi_host);
  2488. return 0;
  2489. case CCISS_GETPCIINFO:
  2490. return hpsa_getpciinfo_ioctl(h, argp);
  2491. case CCISS_GETDRIVVER:
  2492. return hpsa_getdrivver_ioctl(h, argp);
  2493. case CCISS_PASSTHRU:
  2494. return hpsa_passthru_ioctl(h, argp);
  2495. case CCISS_BIG_PASSTHRU:
  2496. return hpsa_big_passthru_ioctl(h, argp);
  2497. default:
  2498. return -ENOTTY;
  2499. }
  2500. }
  2501. static int __devinit hpsa_send_host_reset(struct ctlr_info *h,
  2502. unsigned char *scsi3addr, u8 reset_type)
  2503. {
  2504. struct CommandList *c;
  2505. c = cmd_alloc(h);
  2506. if (!c)
  2507. return -ENOMEM;
  2508. fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  2509. RAID_CTLR_LUNID, TYPE_MSG);
  2510. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  2511. c->waiting = NULL;
  2512. enqueue_cmd_and_start_io(h, c);
  2513. /* Don't wait for completion, the reset won't complete. Don't free
  2514. * the command either. This is the last command we will send before
  2515. * re-initializing everything, so it doesn't matter and won't leak.
  2516. */
  2517. return 0;
  2518. }
  2519. static void fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  2520. void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
  2521. int cmd_type)
  2522. {
  2523. int pci_dir = XFER_NONE;
  2524. c->cmd_type = CMD_IOCTL_PEND;
  2525. c->Header.ReplyQueue = 0;
  2526. if (buff != NULL && size > 0) {
  2527. c->Header.SGList = 1;
  2528. c->Header.SGTotal = 1;
  2529. } else {
  2530. c->Header.SGList = 0;
  2531. c->Header.SGTotal = 0;
  2532. }
  2533. c->Header.Tag.lower = c->busaddr;
  2534. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  2535. c->Request.Type.Type = cmd_type;
  2536. if (cmd_type == TYPE_CMD) {
  2537. switch (cmd) {
  2538. case HPSA_INQUIRY:
  2539. /* are we trying to read a vital product page */
  2540. if (page_code != 0) {
  2541. c->Request.CDB[1] = 0x01;
  2542. c->Request.CDB[2] = page_code;
  2543. }
  2544. c->Request.CDBLen = 6;
  2545. c->Request.Type.Attribute = ATTR_SIMPLE;
  2546. c->Request.Type.Direction = XFER_READ;
  2547. c->Request.Timeout = 0;
  2548. c->Request.CDB[0] = HPSA_INQUIRY;
  2549. c->Request.CDB[4] = size & 0xFF;
  2550. break;
  2551. case HPSA_REPORT_LOG:
  2552. case HPSA_REPORT_PHYS:
  2553. /* Talking to controller so It's a physical command
  2554. mode = 00 target = 0. Nothing to write.
  2555. */
  2556. c->Request.CDBLen = 12;
  2557. c->Request.Type.Attribute = ATTR_SIMPLE;
  2558. c->Request.Type.Direction = XFER_READ;
  2559. c->Request.Timeout = 0;
  2560. c->Request.CDB[0] = cmd;
  2561. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  2562. c->Request.CDB[7] = (size >> 16) & 0xFF;
  2563. c->Request.CDB[8] = (size >> 8) & 0xFF;
  2564. c->Request.CDB[9] = size & 0xFF;
  2565. break;
  2566. case HPSA_CACHE_FLUSH:
  2567. c->Request.CDBLen = 12;
  2568. c->Request.Type.Attribute = ATTR_SIMPLE;
  2569. c->Request.Type.Direction = XFER_WRITE;
  2570. c->Request.Timeout = 0;
  2571. c->Request.CDB[0] = BMIC_WRITE;
  2572. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  2573. break;
  2574. case TEST_UNIT_READY:
  2575. c->Request.CDBLen = 6;
  2576. c->Request.Type.Attribute = ATTR_SIMPLE;
  2577. c->Request.Type.Direction = XFER_NONE;
  2578. c->Request.Timeout = 0;
  2579. break;
  2580. default:
  2581. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  2582. BUG();
  2583. return;
  2584. }
  2585. } else if (cmd_type == TYPE_MSG) {
  2586. switch (cmd) {
  2587. case HPSA_DEVICE_RESET_MSG:
  2588. c->Request.CDBLen = 16;
  2589. c->Request.Type.Type = 1; /* It is a MSG not a CMD */
  2590. c->Request.Type.Attribute = ATTR_SIMPLE;
  2591. c->Request.Type.Direction = XFER_NONE;
  2592. c->Request.Timeout = 0; /* Don't time out */
  2593. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  2594. c->Request.CDB[0] = cmd;
  2595. c->Request.CDB[1] = 0x03; /* Reset target above */
  2596. /* If bytes 4-7 are zero, it means reset the */
  2597. /* LunID device */
  2598. c->Request.CDB[4] = 0x00;
  2599. c->Request.CDB[5] = 0x00;
  2600. c->Request.CDB[6] = 0x00;
  2601. c->Request.CDB[7] = 0x00;
  2602. break;
  2603. default:
  2604. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  2605. cmd);
  2606. BUG();
  2607. }
  2608. } else {
  2609. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  2610. BUG();
  2611. }
  2612. switch (c->Request.Type.Direction) {
  2613. case XFER_READ:
  2614. pci_dir = PCI_DMA_FROMDEVICE;
  2615. break;
  2616. case XFER_WRITE:
  2617. pci_dir = PCI_DMA_TODEVICE;
  2618. break;
  2619. case XFER_NONE:
  2620. pci_dir = PCI_DMA_NONE;
  2621. break;
  2622. default:
  2623. pci_dir = PCI_DMA_BIDIRECTIONAL;
  2624. }
  2625. hpsa_map_one(h->pdev, c, buff, size, pci_dir);
  2626. return;
  2627. }
  2628. /*
  2629. * Map (physical) PCI mem into (virtual) kernel space
  2630. */
  2631. static void __iomem *remap_pci_mem(ulong base, ulong size)
  2632. {
  2633. ulong page_base = ((ulong) base) & PAGE_MASK;
  2634. ulong page_offs = ((ulong) base) - page_base;
  2635. void __iomem *page_remapped = ioremap(page_base, page_offs + size);
  2636. return page_remapped ? (page_remapped + page_offs) : NULL;
  2637. }
  2638. /* Takes cmds off the submission queue and sends them to the hardware,
  2639. * then puts them on the queue of cmds waiting for completion.
  2640. */
  2641. static void start_io(struct ctlr_info *h)
  2642. {
  2643. struct CommandList *c;
  2644. while (!list_empty(&h->reqQ)) {
  2645. c = list_entry(h->reqQ.next, struct CommandList, list);
  2646. /* can't do anything if fifo is full */
  2647. if ((h->access.fifo_full(h))) {
  2648. dev_warn(&h->pdev->dev, "fifo full\n");
  2649. break;
  2650. }
  2651. /* Get the first entry from the Request Q */
  2652. removeQ(c);
  2653. h->Qdepth--;
  2654. /* Tell the controller execute command */
  2655. h->access.submit_command(h, c);
  2656. /* Put job onto the completed Q */
  2657. addQ(&h->cmpQ, c);
  2658. }
  2659. }
  2660. static inline unsigned long get_next_completion(struct ctlr_info *h)
  2661. {
  2662. return h->access.command_completed(h);
  2663. }
  2664. static inline bool interrupt_pending(struct ctlr_info *h)
  2665. {
  2666. return h->access.intr_pending(h);
  2667. }
  2668. static inline long interrupt_not_for_us(struct ctlr_info *h)
  2669. {
  2670. return (h->access.intr_pending(h) == 0) ||
  2671. (h->interrupts_enabled == 0);
  2672. }
  2673. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  2674. u32 raw_tag)
  2675. {
  2676. if (unlikely(tag_index >= h->nr_cmds)) {
  2677. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  2678. return 1;
  2679. }
  2680. return 0;
  2681. }
  2682. static inline void finish_cmd(struct CommandList *c, u32 raw_tag)
  2683. {
  2684. removeQ(c);
  2685. if (likely(c->cmd_type == CMD_SCSI))
  2686. complete_scsi_command(c);
  2687. else if (c->cmd_type == CMD_IOCTL_PEND)
  2688. complete(c->waiting);
  2689. }
  2690. static inline u32 hpsa_tag_contains_index(u32 tag)
  2691. {
  2692. return tag & DIRECT_LOOKUP_BIT;
  2693. }
  2694. static inline u32 hpsa_tag_to_index(u32 tag)
  2695. {
  2696. return tag >> DIRECT_LOOKUP_SHIFT;
  2697. }
  2698. static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
  2699. {
  2700. #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
  2701. #define HPSA_SIMPLE_ERROR_BITS 0x03
  2702. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  2703. return tag & ~HPSA_SIMPLE_ERROR_BITS;
  2704. return tag & ~HPSA_PERF_ERROR_BITS;
  2705. }
  2706. /* process completion of an indexed ("direct lookup") command */
  2707. static inline u32 process_indexed_cmd(struct ctlr_info *h,
  2708. u32 raw_tag)
  2709. {
  2710. u32 tag_index;
  2711. struct CommandList *c;
  2712. tag_index = hpsa_tag_to_index(raw_tag);
  2713. if (bad_tag(h, tag_index, raw_tag))
  2714. return next_command(h);
  2715. c = h->cmd_pool + tag_index;
  2716. finish_cmd(c, raw_tag);
  2717. return next_command(h);
  2718. }
  2719. /* process completion of a non-indexed command */
  2720. static inline u32 process_nonindexed_cmd(struct ctlr_info *h,
  2721. u32 raw_tag)
  2722. {
  2723. u32 tag;
  2724. struct CommandList *c = NULL;
  2725. tag = hpsa_tag_discard_error_bits(h, raw_tag);
  2726. list_for_each_entry(c, &h->cmpQ, list) {
  2727. if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
  2728. finish_cmd(c, raw_tag);
  2729. return next_command(h);
  2730. }
  2731. }
  2732. bad_tag(h, h->nr_cmds + 1, raw_tag);
  2733. return next_command(h);
  2734. }
  2735. /* Some controllers, like p400, will give us one interrupt
  2736. * after a soft reset, even if we turned interrupts off.
  2737. * Only need to check for this in the hpsa_xxx_discard_completions
  2738. * functions.
  2739. */
  2740. static int ignore_bogus_interrupt(struct ctlr_info *h)
  2741. {
  2742. if (likely(!reset_devices))
  2743. return 0;
  2744. if (likely(h->interrupts_enabled))
  2745. return 0;
  2746. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  2747. "(known firmware bug.) Ignoring.\n");
  2748. return 1;
  2749. }
  2750. static irqreturn_t hpsa_intx_discard_completions(int irq, void *dev_id)
  2751. {
  2752. struct ctlr_info *h = dev_id;
  2753. unsigned long flags;
  2754. u32 raw_tag;
  2755. if (ignore_bogus_interrupt(h))
  2756. return IRQ_NONE;
  2757. if (interrupt_not_for_us(h))
  2758. return IRQ_NONE;
  2759. spin_lock_irqsave(&h->lock, flags);
  2760. while (interrupt_pending(h)) {
  2761. raw_tag = get_next_completion(h);
  2762. while (raw_tag != FIFO_EMPTY)
  2763. raw_tag = next_command(h);
  2764. }
  2765. spin_unlock_irqrestore(&h->lock, flags);
  2766. return IRQ_HANDLED;
  2767. }
  2768. static irqreturn_t hpsa_msix_discard_completions(int irq, void *dev_id)
  2769. {
  2770. struct ctlr_info *h = dev_id;
  2771. unsigned long flags;
  2772. u32 raw_tag;
  2773. if (ignore_bogus_interrupt(h))
  2774. return IRQ_NONE;
  2775. spin_lock_irqsave(&h->lock, flags);
  2776. raw_tag = get_next_completion(h);
  2777. while (raw_tag != FIFO_EMPTY)
  2778. raw_tag = next_command(h);
  2779. spin_unlock_irqrestore(&h->lock, flags);
  2780. return IRQ_HANDLED;
  2781. }
  2782. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id)
  2783. {
  2784. struct ctlr_info *h = dev_id;
  2785. unsigned long flags;
  2786. u32 raw_tag;
  2787. if (interrupt_not_for_us(h))
  2788. return IRQ_NONE;
  2789. spin_lock_irqsave(&h->lock, flags);
  2790. while (interrupt_pending(h)) {
  2791. raw_tag = get_next_completion(h);
  2792. while (raw_tag != FIFO_EMPTY) {
  2793. if (hpsa_tag_contains_index(raw_tag))
  2794. raw_tag = process_indexed_cmd(h, raw_tag);
  2795. else
  2796. raw_tag = process_nonindexed_cmd(h, raw_tag);
  2797. }
  2798. }
  2799. spin_unlock_irqrestore(&h->lock, flags);
  2800. return IRQ_HANDLED;
  2801. }
  2802. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id)
  2803. {
  2804. struct ctlr_info *h = dev_id;
  2805. unsigned long flags;
  2806. u32 raw_tag;
  2807. spin_lock_irqsave(&h->lock, flags);
  2808. raw_tag = get_next_completion(h);
  2809. while (raw_tag != FIFO_EMPTY) {
  2810. if (hpsa_tag_contains_index(raw_tag))
  2811. raw_tag = process_indexed_cmd(h, raw_tag);
  2812. else
  2813. raw_tag = process_nonindexed_cmd(h, raw_tag);
  2814. }
  2815. spin_unlock_irqrestore(&h->lock, flags);
  2816. return IRQ_HANDLED;
  2817. }
  2818. /* Send a message CDB to the firmware. Careful, this only works
  2819. * in simple mode, not performant mode due to the tag lookup.
  2820. * We only ever use this immediately after a controller reset.
  2821. */
  2822. static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  2823. unsigned char type)
  2824. {
  2825. struct Command {
  2826. struct CommandListHeader CommandHeader;
  2827. struct RequestBlock Request;
  2828. struct ErrDescriptor ErrorDescriptor;
  2829. };
  2830. struct Command *cmd;
  2831. static const size_t cmd_sz = sizeof(*cmd) +
  2832. sizeof(cmd->ErrorDescriptor);
  2833. dma_addr_t paddr64;
  2834. uint32_t paddr32, tag;
  2835. void __iomem *vaddr;
  2836. int i, err;
  2837. vaddr = pci_ioremap_bar(pdev, 0);
  2838. if (vaddr == NULL)
  2839. return -ENOMEM;
  2840. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  2841. * CCISS commands, so they must be allocated from the lower 4GiB of
  2842. * memory.
  2843. */
  2844. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2845. if (err) {
  2846. iounmap(vaddr);
  2847. return -ENOMEM;
  2848. }
  2849. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  2850. if (cmd == NULL) {
  2851. iounmap(vaddr);
  2852. return -ENOMEM;
  2853. }
  2854. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  2855. * although there's no guarantee, we assume that the address is at
  2856. * least 4-byte aligned (most likely, it's page-aligned).
  2857. */
  2858. paddr32 = paddr64;
  2859. cmd->CommandHeader.ReplyQueue = 0;
  2860. cmd->CommandHeader.SGList = 0;
  2861. cmd->CommandHeader.SGTotal = 0;
  2862. cmd->CommandHeader.Tag.lower = paddr32;
  2863. cmd->CommandHeader.Tag.upper = 0;
  2864. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  2865. cmd->Request.CDBLen = 16;
  2866. cmd->Request.Type.Type = TYPE_MSG;
  2867. cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
  2868. cmd->Request.Type.Direction = XFER_NONE;
  2869. cmd->Request.Timeout = 0; /* Don't time out */
  2870. cmd->Request.CDB[0] = opcode;
  2871. cmd->Request.CDB[1] = type;
  2872. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  2873. cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
  2874. cmd->ErrorDescriptor.Addr.upper = 0;
  2875. cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
  2876. writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
  2877. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  2878. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  2879. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
  2880. break;
  2881. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  2882. }
  2883. iounmap(vaddr);
  2884. /* we leak the DMA buffer here ... no choice since the controller could
  2885. * still complete the command.
  2886. */
  2887. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  2888. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  2889. opcode, type);
  2890. return -ETIMEDOUT;
  2891. }
  2892. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  2893. if (tag & HPSA_ERROR_BIT) {
  2894. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  2895. opcode, type);
  2896. return -EIO;
  2897. }
  2898. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  2899. opcode, type);
  2900. return 0;
  2901. }
  2902. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  2903. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  2904. void * __iomem vaddr, u32 use_doorbell)
  2905. {
  2906. u16 pmcsr;
  2907. int pos;
  2908. if (use_doorbell) {
  2909. /* For everything after the P600, the PCI power state method
  2910. * of resetting the controller doesn't work, so we have this
  2911. * other way using the doorbell register.
  2912. */
  2913. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  2914. writel(use_doorbell, vaddr + SA5_DOORBELL);
  2915. } else { /* Try to do it the PCI power state way */
  2916. /* Quoting from the Open CISS Specification: "The Power
  2917. * Management Control/Status Register (CSR) controls the power
  2918. * state of the device. The normal operating state is D0,
  2919. * CSR=00h. The software off state is D3, CSR=03h. To reset
  2920. * the controller, place the interface device in D3 then to D0,
  2921. * this causes a secondary PCI reset which will reset the
  2922. * controller." */
  2923. pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
  2924. if (pos == 0) {
  2925. dev_err(&pdev->dev,
  2926. "hpsa_reset_controller: "
  2927. "PCI PM not supported\n");
  2928. return -ENODEV;
  2929. }
  2930. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  2931. /* enter the D3hot power management state */
  2932. pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
  2933. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2934. pmcsr |= PCI_D3hot;
  2935. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  2936. msleep(500);
  2937. /* enter the D0 power management state */
  2938. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2939. pmcsr |= PCI_D0;
  2940. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  2941. }
  2942. return 0;
  2943. }
  2944. static __devinit void init_driver_version(char *driver_version, int len)
  2945. {
  2946. memset(driver_version, 0, len);
  2947. strncpy(driver_version, "hpsa " HPSA_DRIVER_VERSION, len - 1);
  2948. }
  2949. static __devinit int write_driver_ver_to_cfgtable(
  2950. struct CfgTable __iomem *cfgtable)
  2951. {
  2952. char *driver_version;
  2953. int i, size = sizeof(cfgtable->driver_version);
  2954. driver_version = kmalloc(size, GFP_KERNEL);
  2955. if (!driver_version)
  2956. return -ENOMEM;
  2957. init_driver_version(driver_version, size);
  2958. for (i = 0; i < size; i++)
  2959. writeb(driver_version[i], &cfgtable->driver_version[i]);
  2960. kfree(driver_version);
  2961. return 0;
  2962. }
  2963. static __devinit void read_driver_ver_from_cfgtable(
  2964. struct CfgTable __iomem *cfgtable, unsigned char *driver_ver)
  2965. {
  2966. int i;
  2967. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  2968. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  2969. }
  2970. static __devinit int controller_reset_failed(
  2971. struct CfgTable __iomem *cfgtable)
  2972. {
  2973. char *driver_ver, *old_driver_ver;
  2974. int rc, size = sizeof(cfgtable->driver_version);
  2975. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  2976. if (!old_driver_ver)
  2977. return -ENOMEM;
  2978. driver_ver = old_driver_ver + size;
  2979. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  2980. * should have been changed, otherwise we know the reset failed.
  2981. */
  2982. init_driver_version(old_driver_ver, size);
  2983. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  2984. rc = !memcmp(driver_ver, old_driver_ver, size);
  2985. kfree(old_driver_ver);
  2986. return rc;
  2987. }
  2988. /* This does a hard reset of the controller using PCI power management
  2989. * states or the using the doorbell register.
  2990. */
  2991. static __devinit int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
  2992. {
  2993. u64 cfg_offset;
  2994. u32 cfg_base_addr;
  2995. u64 cfg_base_addr_index;
  2996. void __iomem *vaddr;
  2997. unsigned long paddr;
  2998. u32 misc_fw_support;
  2999. int rc;
  3000. struct CfgTable __iomem *cfgtable;
  3001. u32 use_doorbell;
  3002. u32 board_id;
  3003. u16 command_register;
  3004. /* For controllers as old as the P600, this is very nearly
  3005. * the same thing as
  3006. *
  3007. * pci_save_state(pci_dev);
  3008. * pci_set_power_state(pci_dev, PCI_D3hot);
  3009. * pci_set_power_state(pci_dev, PCI_D0);
  3010. * pci_restore_state(pci_dev);
  3011. *
  3012. * For controllers newer than the P600, the pci power state
  3013. * method of resetting doesn't work so we have another way
  3014. * using the doorbell register.
  3015. */
  3016. rc = hpsa_lookup_board_id(pdev, &board_id);
  3017. if (rc < 0 || !ctlr_is_resettable(board_id)) {
  3018. dev_warn(&pdev->dev, "Not resetting device.\n");
  3019. return -ENODEV;
  3020. }
  3021. /* if controller is soft- but not hard resettable... */
  3022. if (!ctlr_is_hard_resettable(board_id))
  3023. return -ENOTSUPP; /* try soft reset later. */
  3024. /* Save the PCI command register */
  3025. pci_read_config_word(pdev, 4, &command_register);
  3026. /* Turn the board off. This is so that later pci_restore_state()
  3027. * won't turn the board on before the rest of config space is ready.
  3028. */
  3029. pci_disable_device(pdev);
  3030. pci_save_state(pdev);
  3031. /* find the first memory BAR, so we can find the cfg table */
  3032. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  3033. if (rc)
  3034. return rc;
  3035. vaddr = remap_pci_mem(paddr, 0x250);
  3036. if (!vaddr)
  3037. return -ENOMEM;
  3038. /* find cfgtable in order to check if reset via doorbell is supported */
  3039. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  3040. &cfg_base_addr_index, &cfg_offset);
  3041. if (rc)
  3042. goto unmap_vaddr;
  3043. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  3044. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  3045. if (!cfgtable) {
  3046. rc = -ENOMEM;
  3047. goto unmap_vaddr;
  3048. }
  3049. rc = write_driver_ver_to_cfgtable(cfgtable);
  3050. if (rc)
  3051. goto unmap_vaddr;
  3052. /* If reset via doorbell register is supported, use that.
  3053. * There are two such methods. Favor the newest method.
  3054. */
  3055. misc_fw_support = readl(&cfgtable->misc_fw_support);
  3056. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  3057. if (use_doorbell) {
  3058. use_doorbell = DOORBELL_CTLR_RESET2;
  3059. } else {
  3060. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  3061. if (use_doorbell) {
  3062. dev_warn(&pdev->dev, "Soft reset not supported. "
  3063. "Firmware update is required.\n");
  3064. rc = -ENOTSUPP; /* try soft reset */
  3065. goto unmap_cfgtable;
  3066. }
  3067. }
  3068. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  3069. if (rc)
  3070. goto unmap_cfgtable;
  3071. pci_restore_state(pdev);
  3072. rc = pci_enable_device(pdev);
  3073. if (rc) {
  3074. dev_warn(&pdev->dev, "failed to enable device.\n");
  3075. goto unmap_cfgtable;
  3076. }
  3077. pci_write_config_word(pdev, 4, command_register);
  3078. /* Some devices (notably the HP Smart Array 5i Controller)
  3079. need a little pause here */
  3080. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  3081. /* Wait for board to become not ready, then ready. */
  3082. dev_info(&pdev->dev, "Waiting for board to reset.\n");
  3083. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
  3084. if (rc) {
  3085. dev_warn(&pdev->dev,
  3086. "failed waiting for board to reset."
  3087. " Will try soft reset.\n");
  3088. rc = -ENOTSUPP; /* Not expected, but try soft reset later */
  3089. goto unmap_cfgtable;
  3090. }
  3091. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  3092. if (rc) {
  3093. dev_warn(&pdev->dev,
  3094. "failed waiting for board to become ready "
  3095. "after hard reset\n");
  3096. goto unmap_cfgtable;
  3097. }
  3098. rc = controller_reset_failed(vaddr);
  3099. if (rc < 0)
  3100. goto unmap_cfgtable;
  3101. if (rc) {
  3102. dev_warn(&pdev->dev, "Unable to successfully reset "
  3103. "controller. Will try soft reset.\n");
  3104. rc = -ENOTSUPP;
  3105. } else {
  3106. dev_info(&pdev->dev, "board ready after hard reset.\n");
  3107. }
  3108. unmap_cfgtable:
  3109. iounmap(cfgtable);
  3110. unmap_vaddr:
  3111. iounmap(vaddr);
  3112. return rc;
  3113. }
  3114. /*
  3115. * We cannot read the structure directly, for portability we must use
  3116. * the io functions.
  3117. * This is for debug only.
  3118. */
  3119. static void print_cfg_table(struct device *dev, struct CfgTable *tb)
  3120. {
  3121. #ifdef HPSA_DEBUG
  3122. int i;
  3123. char temp_name[17];
  3124. dev_info(dev, "Controller Configuration information\n");
  3125. dev_info(dev, "------------------------------------\n");
  3126. for (i = 0; i < 4; i++)
  3127. temp_name[i] = readb(&(tb->Signature[i]));
  3128. temp_name[4] = '\0';
  3129. dev_info(dev, " Signature = %s\n", temp_name);
  3130. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  3131. dev_info(dev, " Transport methods supported = 0x%x\n",
  3132. readl(&(tb->TransportSupport)));
  3133. dev_info(dev, " Transport methods active = 0x%x\n",
  3134. readl(&(tb->TransportActive)));
  3135. dev_info(dev, " Requested transport Method = 0x%x\n",
  3136. readl(&(tb->HostWrite.TransportRequest)));
  3137. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  3138. readl(&(tb->HostWrite.CoalIntDelay)));
  3139. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  3140. readl(&(tb->HostWrite.CoalIntCount)));
  3141. dev_info(dev, " Max outstanding commands = 0x%d\n",
  3142. readl(&(tb->CmdsOutMax)));
  3143. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  3144. for (i = 0; i < 16; i++)
  3145. temp_name[i] = readb(&(tb->ServerName[i]));
  3146. temp_name[16] = '\0';
  3147. dev_info(dev, " Server Name = %s\n", temp_name);
  3148. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  3149. readl(&(tb->HeartBeat)));
  3150. #endif /* HPSA_DEBUG */
  3151. }
  3152. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  3153. {
  3154. int i, offset, mem_type, bar_type;
  3155. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  3156. return 0;
  3157. offset = 0;
  3158. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  3159. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  3160. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  3161. offset += 4;
  3162. else {
  3163. mem_type = pci_resource_flags(pdev, i) &
  3164. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  3165. switch (mem_type) {
  3166. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  3167. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  3168. offset += 4; /* 32 bit */
  3169. break;
  3170. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  3171. offset += 8;
  3172. break;
  3173. default: /* reserved in PCI 2.2 */
  3174. dev_warn(&pdev->dev,
  3175. "base address is invalid\n");
  3176. return -1;
  3177. break;
  3178. }
  3179. }
  3180. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  3181. return i + 1;
  3182. }
  3183. return -1;
  3184. }
  3185. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  3186. * controllers that are capable. If not, we use IO-APIC mode.
  3187. */
  3188. static void __devinit hpsa_interrupt_mode(struct ctlr_info *h)
  3189. {
  3190. #ifdef CONFIG_PCI_MSI
  3191. int err;
  3192. struct msix_entry hpsa_msix_entries[4] = { {0, 0}, {0, 1},
  3193. {0, 2}, {0, 3}
  3194. };
  3195. /* Some boards advertise MSI but don't really support it */
  3196. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  3197. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  3198. goto default_int_mode;
  3199. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  3200. dev_info(&h->pdev->dev, "MSIX\n");
  3201. err = pci_enable_msix(h->pdev, hpsa_msix_entries, 4);
  3202. if (!err) {
  3203. h->intr[0] = hpsa_msix_entries[0].vector;
  3204. h->intr[1] = hpsa_msix_entries[1].vector;
  3205. h->intr[2] = hpsa_msix_entries[2].vector;
  3206. h->intr[3] = hpsa_msix_entries[3].vector;
  3207. h->msix_vector = 1;
  3208. return;
  3209. }
  3210. if (err > 0) {
  3211. dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
  3212. "available\n", err);
  3213. goto default_int_mode;
  3214. } else {
  3215. dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
  3216. err);
  3217. goto default_int_mode;
  3218. }
  3219. }
  3220. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  3221. dev_info(&h->pdev->dev, "MSI\n");
  3222. if (!pci_enable_msi(h->pdev))
  3223. h->msi_vector = 1;
  3224. else
  3225. dev_warn(&h->pdev->dev, "MSI init failed\n");
  3226. }
  3227. default_int_mode:
  3228. #endif /* CONFIG_PCI_MSI */
  3229. /* if we get here we're going to use the default interrupt mode */
  3230. h->intr[h->intr_mode] = h->pdev->irq;
  3231. }
  3232. static int __devinit hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  3233. {
  3234. int i;
  3235. u32 subsystem_vendor_id, subsystem_device_id;
  3236. subsystem_vendor_id = pdev->subsystem_vendor;
  3237. subsystem_device_id = pdev->subsystem_device;
  3238. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  3239. subsystem_vendor_id;
  3240. for (i = 0; i < ARRAY_SIZE(products); i++)
  3241. if (*board_id == products[i].board_id)
  3242. return i;
  3243. if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
  3244. subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
  3245. !hpsa_allow_any) {
  3246. dev_warn(&pdev->dev, "unrecognized board ID: "
  3247. "0x%08x, ignoring.\n", *board_id);
  3248. return -ENODEV;
  3249. }
  3250. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  3251. }
  3252. static inline bool hpsa_board_disabled(struct pci_dev *pdev)
  3253. {
  3254. u16 command;
  3255. (void) pci_read_config_word(pdev, PCI_COMMAND, &command);
  3256. return ((command & PCI_COMMAND_MEMORY) == 0);
  3257. }
  3258. static int __devinit hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  3259. unsigned long *memory_bar)
  3260. {
  3261. int i;
  3262. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  3263. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  3264. /* addressing mode bits already removed */
  3265. *memory_bar = pci_resource_start(pdev, i);
  3266. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  3267. *memory_bar);
  3268. return 0;
  3269. }
  3270. dev_warn(&pdev->dev, "no memory BAR found\n");
  3271. return -ENODEV;
  3272. }
  3273. static int __devinit hpsa_wait_for_board_state(struct pci_dev *pdev,
  3274. void __iomem *vaddr, int wait_for_ready)
  3275. {
  3276. int i, iterations;
  3277. u32 scratchpad;
  3278. if (wait_for_ready)
  3279. iterations = HPSA_BOARD_READY_ITERATIONS;
  3280. else
  3281. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  3282. for (i = 0; i < iterations; i++) {
  3283. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  3284. if (wait_for_ready) {
  3285. if (scratchpad == HPSA_FIRMWARE_READY)
  3286. return 0;
  3287. } else {
  3288. if (scratchpad != HPSA_FIRMWARE_READY)
  3289. return 0;
  3290. }
  3291. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  3292. }
  3293. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  3294. return -ENODEV;
  3295. }
  3296. static int __devinit hpsa_find_cfg_addrs(struct pci_dev *pdev,
  3297. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  3298. u64 *cfg_offset)
  3299. {
  3300. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  3301. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  3302. *cfg_base_addr &= (u32) 0x0000ffff;
  3303. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  3304. if (*cfg_base_addr_index == -1) {
  3305. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  3306. return -ENODEV;
  3307. }
  3308. return 0;
  3309. }
  3310. static int __devinit hpsa_find_cfgtables(struct ctlr_info *h)
  3311. {
  3312. u64 cfg_offset;
  3313. u32 cfg_base_addr;
  3314. u64 cfg_base_addr_index;
  3315. u32 trans_offset;
  3316. int rc;
  3317. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  3318. &cfg_base_addr_index, &cfg_offset);
  3319. if (rc)
  3320. return rc;
  3321. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  3322. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  3323. if (!h->cfgtable)
  3324. return -ENOMEM;
  3325. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  3326. if (rc)
  3327. return rc;
  3328. /* Find performant mode table. */
  3329. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  3330. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  3331. cfg_base_addr_index)+cfg_offset+trans_offset,
  3332. sizeof(*h->transtable));
  3333. if (!h->transtable)
  3334. return -ENOMEM;
  3335. return 0;
  3336. }
  3337. static void __devinit hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  3338. {
  3339. h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
  3340. /* Limit commands in memory limited kdump scenario. */
  3341. if (reset_devices && h->max_commands > 32)
  3342. h->max_commands = 32;
  3343. if (h->max_commands < 16) {
  3344. dev_warn(&h->pdev->dev, "Controller reports "
  3345. "max supported commands of %d, an obvious lie. "
  3346. "Using 16. Ensure that firmware is up to date.\n",
  3347. h->max_commands);
  3348. h->max_commands = 16;
  3349. }
  3350. }
  3351. /* Interrogate the hardware for some limits:
  3352. * max commands, max SG elements without chaining, and with chaining,
  3353. * SG chain block size, etc.
  3354. */
  3355. static void __devinit hpsa_find_board_params(struct ctlr_info *h)
  3356. {
  3357. hpsa_get_max_perf_mode_cmds(h);
  3358. h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
  3359. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  3360. /*
  3361. * Limit in-command s/g elements to 32 save dma'able memory.
  3362. * Howvever spec says if 0, use 31
  3363. */
  3364. h->max_cmd_sg_entries = 31;
  3365. if (h->maxsgentries > 512) {
  3366. h->max_cmd_sg_entries = 32;
  3367. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
  3368. h->maxsgentries--; /* save one for chain pointer */
  3369. } else {
  3370. h->maxsgentries = 31; /* default to traditional values */
  3371. h->chainsize = 0;
  3372. }
  3373. }
  3374. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  3375. {
  3376. if ((readb(&h->cfgtable->Signature[0]) != 'C') ||
  3377. (readb(&h->cfgtable->Signature[1]) != 'I') ||
  3378. (readb(&h->cfgtable->Signature[2]) != 'S') ||
  3379. (readb(&h->cfgtable->Signature[3]) != 'S')) {
  3380. dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
  3381. return false;
  3382. }
  3383. return true;
  3384. }
  3385. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  3386. static inline void hpsa_enable_scsi_prefetch(struct ctlr_info *h)
  3387. {
  3388. #ifdef CONFIG_X86
  3389. u32 prefetch;
  3390. prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
  3391. prefetch |= 0x100;
  3392. writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
  3393. #endif
  3394. }
  3395. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  3396. * in a prefetch beyond physical memory.
  3397. */
  3398. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  3399. {
  3400. u32 dma_prefetch;
  3401. if (h->board_id != 0x3225103C)
  3402. return;
  3403. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  3404. dma_prefetch |= 0x8000;
  3405. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  3406. }
  3407. static void __devinit hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  3408. {
  3409. int i;
  3410. u32 doorbell_value;
  3411. unsigned long flags;
  3412. /* under certain very rare conditions, this can take awhile.
  3413. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  3414. * as we enter this code.)
  3415. */
  3416. for (i = 0; i < MAX_CONFIG_WAIT; i++) {
  3417. spin_lock_irqsave(&h->lock, flags);
  3418. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  3419. spin_unlock_irqrestore(&h->lock, flags);
  3420. if (!(doorbell_value & CFGTBL_ChangeReq))
  3421. break;
  3422. /* delay and try again */
  3423. usleep_range(10000, 20000);
  3424. }
  3425. }
  3426. static int __devinit hpsa_enter_simple_mode(struct ctlr_info *h)
  3427. {
  3428. u32 trans_support;
  3429. trans_support = readl(&(h->cfgtable->TransportSupport));
  3430. if (!(trans_support & SIMPLE_MODE))
  3431. return -ENOTSUPP;
  3432. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  3433. /* Update the field, and then ring the doorbell */
  3434. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  3435. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  3436. hpsa_wait_for_mode_change_ack(h);
  3437. print_cfg_table(&h->pdev->dev, h->cfgtable);
  3438. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
  3439. dev_warn(&h->pdev->dev,
  3440. "unable to get board into simple mode\n");
  3441. return -ENODEV;
  3442. }
  3443. h->transMethod = CFGTBL_Trans_Simple;
  3444. return 0;
  3445. }
  3446. static int __devinit hpsa_pci_init(struct ctlr_info *h)
  3447. {
  3448. int prod_index, err;
  3449. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
  3450. if (prod_index < 0)
  3451. return -ENODEV;
  3452. h->product_name = products[prod_index].product_name;
  3453. h->access = *(products[prod_index].access);
  3454. if (hpsa_board_disabled(h->pdev)) {
  3455. dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
  3456. return -ENODEV;
  3457. }
  3458. err = pci_enable_device(h->pdev);
  3459. if (err) {
  3460. dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
  3461. return err;
  3462. }
  3463. err = pci_request_regions(h->pdev, "hpsa");
  3464. if (err) {
  3465. dev_err(&h->pdev->dev,
  3466. "cannot obtain PCI resources, aborting\n");
  3467. return err;
  3468. }
  3469. hpsa_interrupt_mode(h);
  3470. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  3471. if (err)
  3472. goto err_out_free_res;
  3473. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  3474. if (!h->vaddr) {
  3475. err = -ENOMEM;
  3476. goto err_out_free_res;
  3477. }
  3478. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  3479. if (err)
  3480. goto err_out_free_res;
  3481. err = hpsa_find_cfgtables(h);
  3482. if (err)
  3483. goto err_out_free_res;
  3484. hpsa_find_board_params(h);
  3485. if (!hpsa_CISS_signature_present(h)) {
  3486. err = -ENODEV;
  3487. goto err_out_free_res;
  3488. }
  3489. hpsa_enable_scsi_prefetch(h);
  3490. hpsa_p600_dma_prefetch_quirk(h);
  3491. err = hpsa_enter_simple_mode(h);
  3492. if (err)
  3493. goto err_out_free_res;
  3494. return 0;
  3495. err_out_free_res:
  3496. if (h->transtable)
  3497. iounmap(h->transtable);
  3498. if (h->cfgtable)
  3499. iounmap(h->cfgtable);
  3500. if (h->vaddr)
  3501. iounmap(h->vaddr);
  3502. /*
  3503. * Deliberately omit pci_disable_device(): it does something nasty to
  3504. * Smart Array controllers that pci_enable_device does not undo
  3505. */
  3506. pci_release_regions(h->pdev);
  3507. return err;
  3508. }
  3509. static void __devinit hpsa_hba_inquiry(struct ctlr_info *h)
  3510. {
  3511. int rc;
  3512. #define HBA_INQUIRY_BYTE_COUNT 64
  3513. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  3514. if (!h->hba_inquiry_data)
  3515. return;
  3516. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  3517. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  3518. if (rc != 0) {
  3519. kfree(h->hba_inquiry_data);
  3520. h->hba_inquiry_data = NULL;
  3521. }
  3522. }
  3523. static __devinit int hpsa_init_reset_devices(struct pci_dev *pdev)
  3524. {
  3525. int rc, i;
  3526. if (!reset_devices)
  3527. return 0;
  3528. /* Reset the controller with a PCI power-cycle or via doorbell */
  3529. rc = hpsa_kdump_hard_reset_controller(pdev);
  3530. /* -ENOTSUPP here means we cannot reset the controller
  3531. * but it's already (and still) up and running in
  3532. * "performant mode". Or, it might be 640x, which can't reset
  3533. * due to concerns about shared bbwc between 6402/6404 pair.
  3534. */
  3535. if (rc == -ENOTSUPP)
  3536. return rc; /* just try to do the kdump anyhow. */
  3537. if (rc)
  3538. return -ENODEV;
  3539. /* Now try to get the controller to respond to a no-op */
  3540. dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
  3541. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  3542. if (hpsa_noop(pdev) == 0)
  3543. break;
  3544. else
  3545. dev_warn(&pdev->dev, "no-op failed%s\n",
  3546. (i < 11 ? "; re-trying" : ""));
  3547. }
  3548. return 0;
  3549. }
  3550. static __devinit int hpsa_allocate_cmd_pool(struct ctlr_info *h)
  3551. {
  3552. h->cmd_pool_bits = kzalloc(
  3553. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  3554. sizeof(unsigned long), GFP_KERNEL);
  3555. h->cmd_pool = pci_alloc_consistent(h->pdev,
  3556. h->nr_cmds * sizeof(*h->cmd_pool),
  3557. &(h->cmd_pool_dhandle));
  3558. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  3559. h->nr_cmds * sizeof(*h->errinfo_pool),
  3560. &(h->errinfo_pool_dhandle));
  3561. if ((h->cmd_pool_bits == NULL)
  3562. || (h->cmd_pool == NULL)
  3563. || (h->errinfo_pool == NULL)) {
  3564. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  3565. return -ENOMEM;
  3566. }
  3567. return 0;
  3568. }
  3569. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  3570. {
  3571. kfree(h->cmd_pool_bits);
  3572. if (h->cmd_pool)
  3573. pci_free_consistent(h->pdev,
  3574. h->nr_cmds * sizeof(struct CommandList),
  3575. h->cmd_pool, h->cmd_pool_dhandle);
  3576. if (h->errinfo_pool)
  3577. pci_free_consistent(h->pdev,
  3578. h->nr_cmds * sizeof(struct ErrorInfo),
  3579. h->errinfo_pool,
  3580. h->errinfo_pool_dhandle);
  3581. }
  3582. static int hpsa_request_irq(struct ctlr_info *h,
  3583. irqreturn_t (*msixhandler)(int, void *),
  3584. irqreturn_t (*intxhandler)(int, void *))
  3585. {
  3586. int rc;
  3587. if (h->msix_vector || h->msi_vector)
  3588. rc = request_irq(h->intr[h->intr_mode], msixhandler,
  3589. IRQF_DISABLED, h->devname, h);
  3590. else
  3591. rc = request_irq(h->intr[h->intr_mode], intxhandler,
  3592. IRQF_DISABLED, h->devname, h);
  3593. if (rc) {
  3594. dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
  3595. h->intr[h->intr_mode], h->devname);
  3596. return -ENODEV;
  3597. }
  3598. return 0;
  3599. }
  3600. static int __devinit hpsa_kdump_soft_reset(struct ctlr_info *h)
  3601. {
  3602. if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
  3603. HPSA_RESET_TYPE_CONTROLLER)) {
  3604. dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
  3605. return -EIO;
  3606. }
  3607. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  3608. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
  3609. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  3610. return -1;
  3611. }
  3612. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  3613. if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
  3614. dev_warn(&h->pdev->dev, "Board failed to become ready "
  3615. "after soft reset.\n");
  3616. return -1;
  3617. }
  3618. return 0;
  3619. }
  3620. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  3621. {
  3622. free_irq(h->intr[h->intr_mode], h);
  3623. #ifdef CONFIG_PCI_MSI
  3624. if (h->msix_vector)
  3625. pci_disable_msix(h->pdev);
  3626. else if (h->msi_vector)
  3627. pci_disable_msi(h->pdev);
  3628. #endif /* CONFIG_PCI_MSI */
  3629. hpsa_free_sg_chain_blocks(h);
  3630. hpsa_free_cmd_pool(h);
  3631. kfree(h->blockFetchTable);
  3632. pci_free_consistent(h->pdev, h->reply_pool_size,
  3633. h->reply_pool, h->reply_pool_dhandle);
  3634. if (h->vaddr)
  3635. iounmap(h->vaddr);
  3636. if (h->transtable)
  3637. iounmap(h->transtable);
  3638. if (h->cfgtable)
  3639. iounmap(h->cfgtable);
  3640. pci_release_regions(h->pdev);
  3641. kfree(h);
  3642. }
  3643. static int __devinit hpsa_init_one(struct pci_dev *pdev,
  3644. const struct pci_device_id *ent)
  3645. {
  3646. int dac, rc;
  3647. struct ctlr_info *h;
  3648. int try_soft_reset = 0;
  3649. unsigned long flags;
  3650. if (number_of_controllers == 0)
  3651. printk(KERN_INFO DRIVER_NAME "\n");
  3652. rc = hpsa_init_reset_devices(pdev);
  3653. if (rc) {
  3654. if (rc != -ENOTSUPP)
  3655. return rc;
  3656. /* If the reset fails in a particular way (it has no way to do
  3657. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  3658. * a soft reset once we get the controller configured up to the
  3659. * point that it can accept a command.
  3660. */
  3661. try_soft_reset = 1;
  3662. rc = 0;
  3663. }
  3664. reinit_after_soft_reset:
  3665. /* Command structures must be aligned on a 32-byte boundary because
  3666. * the 5 lower bits of the address are used by the hardware. and by
  3667. * the driver. See comments in hpsa.h for more info.
  3668. */
  3669. #define COMMANDLIST_ALIGNMENT 32
  3670. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  3671. h = kzalloc(sizeof(*h), GFP_KERNEL);
  3672. if (!h)
  3673. return -ENOMEM;
  3674. h->pdev = pdev;
  3675. h->busy_initializing = 1;
  3676. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  3677. INIT_LIST_HEAD(&h->cmpQ);
  3678. INIT_LIST_HEAD(&h->reqQ);
  3679. spin_lock_init(&h->lock);
  3680. spin_lock_init(&h->scan_lock);
  3681. rc = hpsa_pci_init(h);
  3682. if (rc != 0)
  3683. goto clean1;
  3684. sprintf(h->devname, "hpsa%d", number_of_controllers);
  3685. h->ctlr = number_of_controllers;
  3686. number_of_controllers++;
  3687. /* configure PCI DMA stuff */
  3688. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  3689. if (rc == 0) {
  3690. dac = 1;
  3691. } else {
  3692. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3693. if (rc == 0) {
  3694. dac = 0;
  3695. } else {
  3696. dev_err(&pdev->dev, "no suitable DMA available\n");
  3697. goto clean1;
  3698. }
  3699. }
  3700. /* make sure the board interrupts are off */
  3701. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3702. if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
  3703. goto clean2;
  3704. dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
  3705. h->devname, pdev->device,
  3706. h->intr[h->intr_mode], dac ? "" : " not");
  3707. if (hpsa_allocate_cmd_pool(h))
  3708. goto clean4;
  3709. if (hpsa_allocate_sg_chain_blocks(h))
  3710. goto clean4;
  3711. init_waitqueue_head(&h->scan_wait_queue);
  3712. h->scan_finished = 1; /* no scan currently in progress */
  3713. pci_set_drvdata(pdev, h);
  3714. h->ndevices = 0;
  3715. h->scsi_host = NULL;
  3716. spin_lock_init(&h->devlock);
  3717. hpsa_put_ctlr_into_performant_mode(h);
  3718. /* At this point, the controller is ready to take commands.
  3719. * Now, if reset_devices and the hard reset didn't work, try
  3720. * the soft reset and see if that works.
  3721. */
  3722. if (try_soft_reset) {
  3723. /* This is kind of gross. We may or may not get a completion
  3724. * from the soft reset command, and if we do, then the value
  3725. * from the fifo may or may not be valid. So, we wait 10 secs
  3726. * after the reset throwing away any completions we get during
  3727. * that time. Unregister the interrupt handler and register
  3728. * fake ones to scoop up any residual completions.
  3729. */
  3730. spin_lock_irqsave(&h->lock, flags);
  3731. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3732. spin_unlock_irqrestore(&h->lock, flags);
  3733. free_irq(h->intr[h->intr_mode], h);
  3734. rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
  3735. hpsa_intx_discard_completions);
  3736. if (rc) {
  3737. dev_warn(&h->pdev->dev, "Failed to request_irq after "
  3738. "soft reset.\n");
  3739. goto clean4;
  3740. }
  3741. rc = hpsa_kdump_soft_reset(h);
  3742. if (rc)
  3743. /* Neither hard nor soft reset worked, we're hosed. */
  3744. goto clean4;
  3745. dev_info(&h->pdev->dev, "Board READY.\n");
  3746. dev_info(&h->pdev->dev,
  3747. "Waiting for stale completions to drain.\n");
  3748. h->access.set_intr_mask(h, HPSA_INTR_ON);
  3749. msleep(10000);
  3750. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3751. rc = controller_reset_failed(h->cfgtable);
  3752. if (rc)
  3753. dev_info(&h->pdev->dev,
  3754. "Soft reset appears to have failed.\n");
  3755. /* since the controller's reset, we have to go back and re-init
  3756. * everything. Easiest to just forget what we've done and do it
  3757. * all over again.
  3758. */
  3759. hpsa_undo_allocations_after_kdump_soft_reset(h);
  3760. try_soft_reset = 0;
  3761. if (rc)
  3762. /* don't go to clean4, we already unallocated */
  3763. return -ENODEV;
  3764. goto reinit_after_soft_reset;
  3765. }
  3766. /* Turn the interrupts on so we can service requests */
  3767. h->access.set_intr_mask(h, HPSA_INTR_ON);
  3768. hpsa_hba_inquiry(h);
  3769. hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
  3770. h->busy_initializing = 0;
  3771. return 1;
  3772. clean4:
  3773. hpsa_free_sg_chain_blocks(h);
  3774. hpsa_free_cmd_pool(h);
  3775. free_irq(h->intr[h->intr_mode], h);
  3776. clean2:
  3777. clean1:
  3778. h->busy_initializing = 0;
  3779. kfree(h);
  3780. return rc;
  3781. }
  3782. static void hpsa_flush_cache(struct ctlr_info *h)
  3783. {
  3784. char *flush_buf;
  3785. struct CommandList *c;
  3786. flush_buf = kzalloc(4, GFP_KERNEL);
  3787. if (!flush_buf)
  3788. return;
  3789. c = cmd_special_alloc(h);
  3790. if (!c) {
  3791. dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
  3792. goto out_of_memory;
  3793. }
  3794. fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  3795. RAID_CTLR_LUNID, TYPE_CMD);
  3796. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
  3797. if (c->err_info->CommandStatus != 0)
  3798. dev_warn(&h->pdev->dev,
  3799. "error flushing cache on controller\n");
  3800. cmd_special_free(h, c);
  3801. out_of_memory:
  3802. kfree(flush_buf);
  3803. }
  3804. static void hpsa_shutdown(struct pci_dev *pdev)
  3805. {
  3806. struct ctlr_info *h;
  3807. h = pci_get_drvdata(pdev);
  3808. /* Turn board interrupts off and send the flush cache command
  3809. * sendcmd will turn off interrupt, and send the flush...
  3810. * To write all data in the battery backed cache to disks
  3811. */
  3812. hpsa_flush_cache(h);
  3813. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  3814. free_irq(h->intr[h->intr_mode], h);
  3815. #ifdef CONFIG_PCI_MSI
  3816. if (h->msix_vector)
  3817. pci_disable_msix(h->pdev);
  3818. else if (h->msi_vector)
  3819. pci_disable_msi(h->pdev);
  3820. #endif /* CONFIG_PCI_MSI */
  3821. }
  3822. static void __devexit hpsa_remove_one(struct pci_dev *pdev)
  3823. {
  3824. struct ctlr_info *h;
  3825. if (pci_get_drvdata(pdev) == NULL) {
  3826. dev_err(&pdev->dev, "unable to remove device \n");
  3827. return;
  3828. }
  3829. h = pci_get_drvdata(pdev);
  3830. hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
  3831. hpsa_shutdown(pdev);
  3832. iounmap(h->vaddr);
  3833. iounmap(h->transtable);
  3834. iounmap(h->cfgtable);
  3835. hpsa_free_sg_chain_blocks(h);
  3836. pci_free_consistent(h->pdev,
  3837. h->nr_cmds * sizeof(struct CommandList),
  3838. h->cmd_pool, h->cmd_pool_dhandle);
  3839. pci_free_consistent(h->pdev,
  3840. h->nr_cmds * sizeof(struct ErrorInfo),
  3841. h->errinfo_pool, h->errinfo_pool_dhandle);
  3842. pci_free_consistent(h->pdev, h->reply_pool_size,
  3843. h->reply_pool, h->reply_pool_dhandle);
  3844. kfree(h->cmd_pool_bits);
  3845. kfree(h->blockFetchTable);
  3846. kfree(h->hba_inquiry_data);
  3847. /*
  3848. * Deliberately omit pci_disable_device(): it does something nasty to
  3849. * Smart Array controllers that pci_enable_device does not undo
  3850. */
  3851. pci_release_regions(pdev);
  3852. pci_set_drvdata(pdev, NULL);
  3853. kfree(h);
  3854. }
  3855. static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
  3856. __attribute__((unused)) pm_message_t state)
  3857. {
  3858. return -ENOSYS;
  3859. }
  3860. static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
  3861. {
  3862. return -ENOSYS;
  3863. }
  3864. static struct pci_driver hpsa_pci_driver = {
  3865. .name = "hpsa",
  3866. .probe = hpsa_init_one,
  3867. .remove = __devexit_p(hpsa_remove_one),
  3868. .id_table = hpsa_pci_device_id, /* id_table */
  3869. .shutdown = hpsa_shutdown,
  3870. .suspend = hpsa_suspend,
  3871. .resume = hpsa_resume,
  3872. };
  3873. /* Fill in bucket_map[], given nsgs (the max number of
  3874. * scatter gather elements supported) and bucket[],
  3875. * which is an array of 8 integers. The bucket[] array
  3876. * contains 8 different DMA transfer sizes (in 16
  3877. * byte increments) which the controller uses to fetch
  3878. * commands. This function fills in bucket_map[], which
  3879. * maps a given number of scatter gather elements to one of
  3880. * the 8 DMA transfer sizes. The point of it is to allow the
  3881. * controller to only do as much DMA as needed to fetch the
  3882. * command, with the DMA transfer size encoded in the lower
  3883. * bits of the command address.
  3884. */
  3885. static void calc_bucket_map(int bucket[], int num_buckets,
  3886. int nsgs, int *bucket_map)
  3887. {
  3888. int i, j, b, size;
  3889. /* even a command with 0 SGs requires 4 blocks */
  3890. #define MINIMUM_TRANSFER_BLOCKS 4
  3891. #define NUM_BUCKETS 8
  3892. /* Note, bucket_map must have nsgs+1 entries. */
  3893. for (i = 0; i <= nsgs; i++) {
  3894. /* Compute size of a command with i SG entries */
  3895. size = i + MINIMUM_TRANSFER_BLOCKS;
  3896. b = num_buckets; /* Assume the biggest bucket */
  3897. /* Find the bucket that is just big enough */
  3898. for (j = 0; j < 8; j++) {
  3899. if (bucket[j] >= size) {
  3900. b = j;
  3901. break;
  3902. }
  3903. }
  3904. /* for a command with i SG entries, use bucket b. */
  3905. bucket_map[i] = b;
  3906. }
  3907. }
  3908. static __devinit void hpsa_enter_performant_mode(struct ctlr_info *h,
  3909. u32 use_short_tags)
  3910. {
  3911. int i;
  3912. unsigned long register_value;
  3913. /* This is a bit complicated. There are 8 registers on
  3914. * the controller which we write to to tell it 8 different
  3915. * sizes of commands which there may be. It's a way of
  3916. * reducing the DMA done to fetch each command. Encoded into
  3917. * each command's tag are 3 bits which communicate to the controller
  3918. * which of the eight sizes that command fits within. The size of
  3919. * each command depends on how many scatter gather entries there are.
  3920. * Each SG entry requires 16 bytes. The eight registers are programmed
  3921. * with the number of 16-byte blocks a command of that size requires.
  3922. * The smallest command possible requires 5 such 16 byte blocks.
  3923. * the largest command possible requires MAXSGENTRIES + 4 16-byte
  3924. * blocks. Note, this only extends to the SG entries contained
  3925. * within the command block, and does not extend to chained blocks
  3926. * of SG elements. bft[] contains the eight values we write to
  3927. * the registers. They are not evenly distributed, but have more
  3928. * sizes for small commands, and fewer sizes for larger commands.
  3929. */
  3930. int bft[8] = {5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
  3931. BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
  3932. /* 5 = 1 s/g entry or 4k
  3933. * 6 = 2 s/g entry or 8k
  3934. * 8 = 4 s/g entry or 16k
  3935. * 10 = 6 s/g entry or 24k
  3936. */
  3937. h->reply_pool_wraparound = 1; /* spec: init to 1 */
  3938. /* Controller spec: zero out this buffer. */
  3939. memset(h->reply_pool, 0, h->reply_pool_size);
  3940. h->reply_pool_head = h->reply_pool;
  3941. bft[7] = h->max_sg_entries + 4;
  3942. calc_bucket_map(bft, ARRAY_SIZE(bft), 32, h->blockFetchTable);
  3943. for (i = 0; i < 8; i++)
  3944. writel(bft[i], &h->transtable->BlockFetch[i]);
  3945. /* size of controller ring buffer */
  3946. writel(h->max_commands, &h->transtable->RepQSize);
  3947. writel(1, &h->transtable->RepQCount);
  3948. writel(0, &h->transtable->RepQCtrAddrLow32);
  3949. writel(0, &h->transtable->RepQCtrAddrHigh32);
  3950. writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
  3951. writel(0, &h->transtable->RepQAddr0High32);
  3952. writel(CFGTBL_Trans_Performant | use_short_tags,
  3953. &(h->cfgtable->HostWrite.TransportRequest));
  3954. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  3955. hpsa_wait_for_mode_change_ack(h);
  3956. register_value = readl(&(h->cfgtable->TransportActive));
  3957. if (!(register_value & CFGTBL_Trans_Performant)) {
  3958. dev_warn(&h->pdev->dev, "unable to get board into"
  3959. " performant mode\n");
  3960. return;
  3961. }
  3962. /* Change the access methods to the performant access methods */
  3963. h->access = SA5_performant_access;
  3964. h->transMethod = CFGTBL_Trans_Performant;
  3965. }
  3966. static __devinit void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  3967. {
  3968. u32 trans_support;
  3969. if (hpsa_simple_mode)
  3970. return;
  3971. trans_support = readl(&(h->cfgtable->TransportSupport));
  3972. if (!(trans_support & PERFORMANT_MODE))
  3973. return;
  3974. hpsa_get_max_perf_mode_cmds(h);
  3975. h->max_sg_entries = 32;
  3976. /* Performant mode ring buffer and supporting data structures */
  3977. h->reply_pool_size = h->max_commands * sizeof(u64);
  3978. h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
  3979. &(h->reply_pool_dhandle));
  3980. /* Need a block fetch table for performant mode */
  3981. h->blockFetchTable = kmalloc(((h->max_sg_entries+1) *
  3982. sizeof(u32)), GFP_KERNEL);
  3983. if ((h->reply_pool == NULL)
  3984. || (h->blockFetchTable == NULL))
  3985. goto clean_up;
  3986. hpsa_enter_performant_mode(h,
  3987. trans_support & CFGTBL_Trans_use_short_tags);
  3988. return;
  3989. clean_up:
  3990. if (h->reply_pool)
  3991. pci_free_consistent(h->pdev, h->reply_pool_size,
  3992. h->reply_pool, h->reply_pool_dhandle);
  3993. kfree(h->blockFetchTable);
  3994. }
  3995. /*
  3996. * This is it. Register the PCI driver information for the cards we control
  3997. * the OS will call our registered routines when it finds one of our cards.
  3998. */
  3999. static int __init hpsa_init(void)
  4000. {
  4001. return pci_register_driver(&hpsa_pci_driver);
  4002. }
  4003. static void __exit hpsa_cleanup(void)
  4004. {
  4005. pci_unregister_driver(&hpsa_pci_driver);
  4006. }
  4007. module_init(hpsa_init);
  4008. module_exit(hpsa_cleanup);