pwm-tiecap.c 6.0 KB

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  1. /*
  2. * ECAP PWM driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/io.h>
  23. #include <linux/err.h>
  24. #include <linux/clk.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/pwm.h>
  27. /* ECAP registers and bits definitions */
  28. #define CAP1 0x08
  29. #define CAP2 0x0C
  30. #define CAP3 0x10
  31. #define CAP4 0x14
  32. #define ECCTL2 0x2A
  33. #define ECCTL2_APWM_MODE BIT(9)
  34. #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
  35. #define ECCTL2_TSCTR_FREERUN BIT(4)
  36. struct ecap_pwm_chip {
  37. struct pwm_chip chip;
  38. unsigned int clk_rate;
  39. void __iomem *mmio_base;
  40. };
  41. static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
  42. {
  43. return container_of(chip, struct ecap_pwm_chip, chip);
  44. }
  45. /*
  46. * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
  47. * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
  48. */
  49. static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  50. int duty_ns, int period_ns)
  51. {
  52. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  53. unsigned long long c;
  54. unsigned long period_cycles, duty_cycles;
  55. unsigned int reg_val;
  56. if (period_ns < 0 || duty_ns < 0 || period_ns > NSEC_PER_SEC)
  57. return -ERANGE;
  58. c = pc->clk_rate;
  59. c = c * period_ns;
  60. do_div(c, NSEC_PER_SEC);
  61. period_cycles = (unsigned long)c;
  62. if (period_cycles < 1) {
  63. period_cycles = 1;
  64. duty_cycles = 1;
  65. } else {
  66. c = pc->clk_rate;
  67. c = c * duty_ns;
  68. do_div(c, NSEC_PER_SEC);
  69. duty_cycles = (unsigned long)c;
  70. }
  71. pm_runtime_get_sync(pc->chip.dev);
  72. reg_val = readw(pc->mmio_base + ECCTL2);
  73. /* Configure APWM mode & disable sync option */
  74. reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
  75. writew(reg_val, pc->mmio_base + ECCTL2);
  76. if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
  77. /* Update active registers if not running */
  78. writel(duty_cycles, pc->mmio_base + CAP2);
  79. writel(period_cycles, pc->mmio_base + CAP1);
  80. } else {
  81. /*
  82. * Update shadow registers to configure period and
  83. * compare values. This helps current PWM period to
  84. * complete on reconfiguring
  85. */
  86. writel(duty_cycles, pc->mmio_base + CAP4);
  87. writel(period_cycles, pc->mmio_base + CAP3);
  88. }
  89. if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
  90. reg_val = readw(pc->mmio_base + ECCTL2);
  91. /* Disable APWM mode to put APWM output Low */
  92. reg_val &= ~ECCTL2_APWM_MODE;
  93. writew(reg_val, pc->mmio_base + ECCTL2);
  94. }
  95. pm_runtime_put_sync(pc->chip.dev);
  96. return 0;
  97. }
  98. static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  99. {
  100. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  101. unsigned int reg_val;
  102. /* Leave clock enabled on enabling PWM */
  103. pm_runtime_get_sync(pc->chip.dev);
  104. /*
  105. * Enable 'Free run Time stamp counter mode' to start counter
  106. * and 'APWM mode' to enable APWM output
  107. */
  108. reg_val = readw(pc->mmio_base + ECCTL2);
  109. reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
  110. writew(reg_val, pc->mmio_base + ECCTL2);
  111. return 0;
  112. }
  113. static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  114. {
  115. struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
  116. unsigned int reg_val;
  117. /*
  118. * Disable 'Free run Time stamp counter mode' to stop counter
  119. * and 'APWM mode' to put APWM output to low
  120. */
  121. reg_val = readw(pc->mmio_base + ECCTL2);
  122. reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
  123. writew(reg_val, pc->mmio_base + ECCTL2);
  124. /* Disable clock on PWM disable */
  125. pm_runtime_put_sync(pc->chip.dev);
  126. }
  127. static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  128. {
  129. if (test_bit(PWMF_ENABLED, &pwm->flags)) {
  130. dev_warn(chip->dev, "Removing PWM device without disabling\n");
  131. pm_runtime_put_sync(chip->dev);
  132. }
  133. }
  134. static const struct pwm_ops ecap_pwm_ops = {
  135. .free = ecap_pwm_free,
  136. .config = ecap_pwm_config,
  137. .enable = ecap_pwm_enable,
  138. .disable = ecap_pwm_disable,
  139. .owner = THIS_MODULE,
  140. };
  141. static int __devinit ecap_pwm_probe(struct platform_device *pdev)
  142. {
  143. int ret;
  144. struct resource *r;
  145. struct clk *clk;
  146. struct ecap_pwm_chip *pc;
  147. pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
  148. if (!pc) {
  149. dev_err(&pdev->dev, "failed to allocate memory\n");
  150. return -ENOMEM;
  151. }
  152. clk = devm_clk_get(&pdev->dev, "fck");
  153. if (IS_ERR(clk)) {
  154. dev_err(&pdev->dev, "failed to get clock\n");
  155. return PTR_ERR(clk);
  156. }
  157. pc->clk_rate = clk_get_rate(clk);
  158. if (!pc->clk_rate) {
  159. dev_err(&pdev->dev, "failed to get clock rate\n");
  160. return -EINVAL;
  161. }
  162. pc->chip.dev = &pdev->dev;
  163. pc->chip.ops = &ecap_pwm_ops;
  164. pc->chip.base = -1;
  165. pc->chip.npwm = 1;
  166. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  167. if (!r) {
  168. dev_err(&pdev->dev, "no memory resource defined\n");
  169. return -ENODEV;
  170. }
  171. pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
  172. if (!pc->mmio_base)
  173. return -EADDRNOTAVAIL;
  174. ret = pwmchip_add(&pc->chip);
  175. if (ret < 0) {
  176. dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
  177. return ret;
  178. }
  179. pm_runtime_enable(&pdev->dev);
  180. platform_set_drvdata(pdev, pc);
  181. return 0;
  182. }
  183. static int __devexit ecap_pwm_remove(struct platform_device *pdev)
  184. {
  185. struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
  186. pm_runtime_put_sync(&pdev->dev);
  187. pm_runtime_disable(&pdev->dev);
  188. return pwmchip_remove(&pc->chip);
  189. }
  190. static struct platform_driver ecap_pwm_driver = {
  191. .driver = {
  192. .name = "ecap",
  193. },
  194. .probe = ecap_pwm_probe,
  195. .remove = __devexit_p(ecap_pwm_remove),
  196. };
  197. module_platform_driver(ecap_pwm_driver);
  198. MODULE_DESCRIPTION("ECAP PWM driver");
  199. MODULE_AUTHOR("Texas Instruments");
  200. MODULE_LICENSE("GPL");