p5040si-post.dtsi 8.1 KB

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  1. /*
  2. * P5040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * This software is provided by Freescale Semiconductor "as is" and any
  24. * express or implied warranties, including, but not limited to, the implied
  25. * warranties of merchantability and fitness for a particular purpose are
  26. * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27. * direct, indirect, incidental, special, exemplary, or consequential damages
  28. * (including, but not limited to, procurement of substitute goods or services;
  29. * loss of use, data, or profits; or business interruption) however caused and
  30. * on any theory of liability, whether in contract, strict liability, or tort
  31. * (including negligence or otherwise) arising in any way out of the use of this
  32. * software, even if advised of the possibility of such damage.
  33. */
  34. &lbc {
  35. compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <16 2 1 15>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0 0 1 &mpic 40 1 0 0
  60. 0000 0 0 2 &mpic 1 1 0 0
  61. 0000 0 0 3 &mpic 2 1 0 0
  62. 0000 0 0 4 &mpic 3 1 0 0
  63. >;
  64. };
  65. };
  66. /* controller at 0x201000 */
  67. &pci1 {
  68. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  69. device_type = "pci";
  70. #size-cells = <2>;
  71. #address-cells = <3>;
  72. bus-range = <0 0xff>;
  73. clock-frequency = <33333333>;
  74. interrupts = <16 2 1 14>;
  75. pcie@0 {
  76. reg = <0 0 0 0 0>;
  77. #interrupt-cells = <1>;
  78. #size-cells = <2>;
  79. #address-cells = <3>;
  80. device_type = "pci";
  81. interrupts = <16 2 1 14>;
  82. interrupt-map-mask = <0xf800 0 0 7>;
  83. interrupt-map = <
  84. /* IDSEL 0x0 */
  85. 0000 0 0 1 &mpic 41 1 0 0
  86. 0000 0 0 2 &mpic 5 1 0 0
  87. 0000 0 0 3 &mpic 6 1 0 0
  88. 0000 0 0 4 &mpic 7 1 0 0
  89. >;
  90. };
  91. };
  92. /* controller at 0x202000 */
  93. &pci2 {
  94. compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
  95. device_type = "pci";
  96. #size-cells = <2>;
  97. #address-cells = <3>;
  98. bus-range = <0x0 0xff>;
  99. clock-frequency = <33333333>;
  100. interrupts = <16 2 1 13>;
  101. pcie@0 {
  102. reg = <0 0 0 0 0>;
  103. #interrupt-cells = <1>;
  104. #size-cells = <2>;
  105. #address-cells = <3>;
  106. device_type = "pci";
  107. interrupts = <16 2 1 13>;
  108. interrupt-map-mask = <0xf800 0 0 7>;
  109. interrupt-map = <
  110. /* IDSEL 0x0 */
  111. 0000 0 0 1 &mpic 42 1 0 0
  112. 0000 0 0 2 &mpic 9 1 0 0
  113. 0000 0 0 3 &mpic 10 1 0 0
  114. 0000 0 0 4 &mpic 11 1 0 0
  115. >;
  116. };
  117. };
  118. &dcsr {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. compatible = "fsl,dcsr", "simple-bus";
  122. dcsr-epu@0 {
  123. compatible = "fsl,dcsr-epu";
  124. interrupts = <52 2 0 0
  125. 84 2 0 0
  126. 85 2 0 0>;
  127. reg = <0x0 0x1000>;
  128. };
  129. dcsr-npc {
  130. compatible = "fsl,dcsr-npc";
  131. reg = <0x1000 0x1000 0x1000000 0x8000>;
  132. };
  133. dcsr-nxc@2000 {
  134. compatible = "fsl,dcsr-nxc";
  135. reg = <0x2000 0x1000>;
  136. };
  137. dcsr-corenet {
  138. compatible = "fsl,dcsr-corenet";
  139. reg = <0x8000 0x1000 0xB0000 0x1000>;
  140. };
  141. dcsr-dpaa@9000 {
  142. compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
  143. reg = <0x9000 0x1000>;
  144. };
  145. dcsr-ocn@11000 {
  146. compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
  147. reg = <0x11000 0x1000>;
  148. };
  149. dcsr-ddr@12000 {
  150. compatible = "fsl,dcsr-ddr";
  151. dev-handle = <&ddr1>;
  152. reg = <0x12000 0x1000>;
  153. };
  154. dcsr-ddr@13000 {
  155. compatible = "fsl,dcsr-ddr";
  156. dev-handle = <&ddr2>;
  157. reg = <0x13000 0x1000>;
  158. };
  159. dcsr-nal@18000 {
  160. compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
  161. reg = <0x18000 0x1000>;
  162. };
  163. dcsr-rcpm@22000 {
  164. compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
  165. reg = <0x22000 0x1000>;
  166. };
  167. dcsr-cpu-sb-proxy@40000 {
  168. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  169. cpu-handle = <&cpu0>;
  170. reg = <0x40000 0x1000>;
  171. };
  172. dcsr-cpu-sb-proxy@41000 {
  173. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  174. cpu-handle = <&cpu1>;
  175. reg = <0x41000 0x1000>;
  176. };
  177. dcsr-cpu-sb-proxy@42000 {
  178. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  179. cpu-handle = <&cpu2>;
  180. reg = <0x42000 0x1000>;
  181. };
  182. dcsr-cpu-sb-proxy@43000 {
  183. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  184. cpu-handle = <&cpu3>;
  185. reg = <0x43000 0x1000>;
  186. };
  187. };
  188. &soc {
  189. #address-cells = <1>;
  190. #size-cells = <1>;
  191. device_type = "soc";
  192. compatible = "simple-bus";
  193. soc-sram-error {
  194. compatible = "fsl,soc-sram-error";
  195. interrupts = <16 2 1 29>;
  196. };
  197. corenet-law@0 {
  198. compatible = "fsl,corenet-law";
  199. reg = <0x0 0x1000>;
  200. fsl,num-laws = <32>;
  201. };
  202. ddr1: memory-controller@8000 {
  203. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  204. reg = <0x8000 0x1000>;
  205. interrupts = <16 2 1 23>;
  206. };
  207. ddr2: memory-controller@9000 {
  208. compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
  209. reg = <0x9000 0x1000>;
  210. interrupts = <16 2 1 22>;
  211. };
  212. cpc: l3-cache-controller@10000 {
  213. compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  214. reg = <0x10000 0x1000
  215. 0x11000 0x1000>;
  216. interrupts = <16 2 1 27
  217. 16 2 1 26>;
  218. };
  219. corenet-cf@18000 {
  220. compatible = "fsl,corenet-cf";
  221. reg = <0x18000 0x1000>;
  222. interrupts = <16 2 1 31>;
  223. fsl,ccf-num-csdids = <32>;
  224. fsl,ccf-num-snoopids = <32>;
  225. };
  226. iommu@20000 {
  227. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  228. reg = <0x20000 0x5000>;
  229. interrupts = <
  230. 24 2 0 0
  231. 16 2 1 30>;
  232. };
  233. /include/ "qoriq-mpic.dtsi"
  234. guts: global-utilities@e0000 {
  235. compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
  236. reg = <0xe0000 0xe00>;
  237. fsl,has-rstcr;
  238. #sleep-cells = <1>;
  239. fsl,liodn-bits = <12>;
  240. };
  241. pins: global-utilities@e0e00 {
  242. compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
  243. reg = <0xe0e00 0x200>;
  244. #sleep-cells = <2>;
  245. };
  246. clockgen: global-utilities@e1000 {
  247. compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
  248. reg = <0xe1000 0x1000>;
  249. clock-frequency = <0>;
  250. };
  251. rcpm: global-utilities@e2000 {
  252. compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
  253. reg = <0xe2000 0x1000>;
  254. #sleep-cells = <1>;
  255. };
  256. sfp: sfp@e8000 {
  257. compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
  258. reg = <0xe8000 0x1000>;
  259. };
  260. serdes: serdes@ea000 {
  261. compatible = "fsl,p5040-serdes";
  262. reg = <0xea000 0x1000>;
  263. };
  264. /include/ "qoriq-dma-0.dtsi"
  265. /include/ "qoriq-dma-1.dtsi"
  266. /include/ "qoriq-espi-0.dtsi"
  267. spi@110000 {
  268. fsl,espi-num-chipselects = <4>;
  269. };
  270. /include/ "qoriq-esdhc-0.dtsi"
  271. sdhc@114000 {
  272. sdhci,auto-cmd12;
  273. };
  274. /include/ "qoriq-i2c-0.dtsi"
  275. /include/ "qoriq-i2c-1.dtsi"
  276. /include/ "qoriq-duart-0.dtsi"
  277. /include/ "qoriq-duart-1.dtsi"
  278. /include/ "qoriq-gpio-0.dtsi"
  279. /include/ "qoriq-usb2-mph-0.dtsi"
  280. usb0: usb@210000 {
  281. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  282. phy_type = "utmi";
  283. port0;
  284. };
  285. /include/ "qoriq-usb2-dr-0.dtsi"
  286. usb1: usb@211000 {
  287. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  288. dr_mode = "host";
  289. phy_type = "utmi";
  290. };
  291. /include/ "qoriq-sata2-0.dtsi"
  292. /include/ "qoriq-sata2-1.dtsi"
  293. /include/ "qoriq-sec5.2-0.dtsi"
  294. };