imx53.dtsi 7.7 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. gpio0 = &gpio1;
  21. gpio1 = &gpio2;
  22. gpio2 = &gpio3;
  23. gpio3 = &gpio4;
  24. gpio4 = &gpio5;
  25. gpio5 = &gpio6;
  26. gpio6 = &gpio7;
  27. };
  28. tzic: tz-interrupt-controller@0fffc000 {
  29. compatible = "fsl,imx53-tzic", "fsl,tzic";
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. reg = <0x0fffc000 0x4000>;
  33. };
  34. clocks {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. ckil {
  38. compatible = "fsl,imx-ckil", "fixed-clock";
  39. clock-frequency = <32768>;
  40. };
  41. ckih1 {
  42. compatible = "fsl,imx-ckih1", "fixed-clock";
  43. clock-frequency = <22579200>;
  44. };
  45. ckih2 {
  46. compatible = "fsl,imx-ckih2", "fixed-clock";
  47. clock-frequency = <0>;
  48. };
  49. osc {
  50. compatible = "fsl,imx-osc", "fixed-clock";
  51. clock-frequency = <24000000>;
  52. };
  53. };
  54. soc {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "simple-bus";
  58. interrupt-parent = <&tzic>;
  59. ranges;
  60. aips@50000000 { /* AIPS1 */
  61. compatible = "fsl,aips-bus", "simple-bus";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. reg = <0x50000000 0x10000000>;
  65. ranges;
  66. spba@50000000 {
  67. compatible = "fsl,spba-bus", "simple-bus";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. reg = <0x50000000 0x40000>;
  71. ranges;
  72. esdhc@50004000 { /* ESDHC1 */
  73. compatible = "fsl,imx53-esdhc";
  74. reg = <0x50004000 0x4000>;
  75. interrupts = <1>;
  76. status = "disabled";
  77. };
  78. esdhc@50008000 { /* ESDHC2 */
  79. compatible = "fsl,imx53-esdhc";
  80. reg = <0x50008000 0x4000>;
  81. interrupts = <2>;
  82. status = "disabled";
  83. };
  84. uart3: serial@5000c000 {
  85. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  86. reg = <0x5000c000 0x4000>;
  87. interrupts = <33>;
  88. status = "disabled";
  89. };
  90. ecspi@50010000 { /* ECSPI1 */
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  94. reg = <0x50010000 0x4000>;
  95. interrupts = <36>;
  96. status = "disabled";
  97. };
  98. ssi2: ssi@50014000 {
  99. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  100. reg = <0x50014000 0x4000>;
  101. interrupts = <30>;
  102. fsl,fifo-depth = <15>;
  103. fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
  104. status = "disabled";
  105. };
  106. esdhc@50020000 { /* ESDHC3 */
  107. compatible = "fsl,imx53-esdhc";
  108. reg = <0x50020000 0x4000>;
  109. interrupts = <3>;
  110. status = "disabled";
  111. };
  112. esdhc@50024000 { /* ESDHC4 */
  113. compatible = "fsl,imx53-esdhc";
  114. reg = <0x50024000 0x4000>;
  115. interrupts = <4>;
  116. status = "disabled";
  117. };
  118. };
  119. gpio1: gpio@53f84000 {
  120. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  121. reg = <0x53f84000 0x4000>;
  122. interrupts = <50 51>;
  123. gpio-controller;
  124. #gpio-cells = <2>;
  125. interrupt-controller;
  126. #interrupt-cells = <2>;
  127. };
  128. gpio2: gpio@53f88000 {
  129. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  130. reg = <0x53f88000 0x4000>;
  131. interrupts = <52 53>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. interrupt-controller;
  135. #interrupt-cells = <2>;
  136. };
  137. gpio3: gpio@53f8c000 {
  138. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  139. reg = <0x53f8c000 0x4000>;
  140. interrupts = <54 55>;
  141. gpio-controller;
  142. #gpio-cells = <2>;
  143. interrupt-controller;
  144. #interrupt-cells = <2>;
  145. };
  146. gpio4: gpio@53f90000 {
  147. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  148. reg = <0x53f90000 0x4000>;
  149. interrupts = <56 57>;
  150. gpio-controller;
  151. #gpio-cells = <2>;
  152. interrupt-controller;
  153. #interrupt-cells = <2>;
  154. };
  155. wdog@53f98000 { /* WDOG1 */
  156. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  157. reg = <0x53f98000 0x4000>;
  158. interrupts = <58>;
  159. status = "disabled";
  160. };
  161. wdog@53f9c000 { /* WDOG2 */
  162. compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
  163. reg = <0x53f9c000 0x4000>;
  164. interrupts = <59>;
  165. status = "disabled";
  166. };
  167. uart1: serial@53fbc000 {
  168. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  169. reg = <0x53fbc000 0x4000>;
  170. interrupts = <31>;
  171. status = "disabled";
  172. };
  173. uart2: serial@53fc0000 {
  174. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  175. reg = <0x53fc0000 0x4000>;
  176. interrupts = <32>;
  177. status = "disabled";
  178. };
  179. gpio5: gpio@53fdc000 {
  180. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  181. reg = <0x53fdc000 0x4000>;
  182. interrupts = <103 104>;
  183. gpio-controller;
  184. #gpio-cells = <2>;
  185. interrupt-controller;
  186. #interrupt-cells = <2>;
  187. };
  188. gpio6: gpio@53fe0000 {
  189. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  190. reg = <0x53fe0000 0x4000>;
  191. interrupts = <105 106>;
  192. gpio-controller;
  193. #gpio-cells = <2>;
  194. interrupt-controller;
  195. #interrupt-cells = <2>;
  196. };
  197. gpio7: gpio@53fe4000 {
  198. compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  199. reg = <0x53fe4000 0x4000>;
  200. interrupts = <107 108>;
  201. gpio-controller;
  202. #gpio-cells = <2>;
  203. interrupt-controller;
  204. #interrupt-cells = <2>;
  205. };
  206. i2c@53fec000 { /* I2C3 */
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  210. reg = <0x53fec000 0x4000>;
  211. interrupts = <64>;
  212. status = "disabled";
  213. };
  214. uart4: serial@53ff0000 {
  215. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  216. reg = <0x53ff0000 0x4000>;
  217. interrupts = <13>;
  218. status = "disabled";
  219. };
  220. };
  221. aips@60000000 { /* AIPS2 */
  222. compatible = "fsl,aips-bus", "simple-bus";
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. reg = <0x60000000 0x10000000>;
  226. ranges;
  227. uart5: serial@63f90000 {
  228. compatible = "fsl,imx53-uart", "fsl,imx21-uart";
  229. reg = <0x63f90000 0x4000>;
  230. interrupts = <86>;
  231. status = "disabled";
  232. };
  233. ecspi@63fac000 { /* ECSPI2 */
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
  237. reg = <0x63fac000 0x4000>;
  238. interrupts = <37>;
  239. status = "disabled";
  240. };
  241. sdma@63fb0000 {
  242. compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
  243. reg = <0x63fb0000 0x4000>;
  244. interrupts = <6>;
  245. };
  246. cspi@63fc0000 {
  247. #address-cells = <1>;
  248. #size-cells = <0>;
  249. compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
  250. reg = <0x63fc0000 0x4000>;
  251. interrupts = <38>;
  252. status = "disabled";
  253. };
  254. i2c@63fc4000 { /* I2C2 */
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  258. reg = <0x63fc4000 0x4000>;
  259. interrupts = <63>;
  260. status = "disabled";
  261. };
  262. i2c@63fc8000 { /* I2C1 */
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
  266. reg = <0x63fc8000 0x4000>;
  267. interrupts = <62>;
  268. status = "disabled";
  269. };
  270. ssi1: ssi@63fcc000 {
  271. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  272. reg = <0x63fcc000 0x4000>;
  273. interrupts = <29>;
  274. fsl,fifo-depth = <15>;
  275. fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
  276. status = "disabled";
  277. };
  278. audmux@63fd0000 {
  279. compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
  280. reg = <0x63fd0000 0x4000>;
  281. status = "disabled";
  282. };
  283. ssi3: ssi@63fe8000 {
  284. compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
  285. reg = <0x63fe8000 0x4000>;
  286. interrupts = <96>;
  287. fsl,fifo-depth = <15>;
  288. fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
  289. status = "disabled";
  290. };
  291. ethernet@63fec000 {
  292. compatible = "fsl,imx53-fec", "fsl,imx25-fec";
  293. reg = <0x63fec000 0x4000>;
  294. interrupts = <87>;
  295. status = "disabled";
  296. };
  297. };
  298. };
  299. };