arm-gic.h 2.1 KB

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  1. /*
  2. * include/linux/irqchip/arm-gic.h
  3. *
  4. * Copyright (C) 2002 ARM Limited, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef __LINUX_IRQCHIP_ARM_GIC_H
  11. #define __LINUX_IRQCHIP_ARM_GIC_H
  12. #define GIC_CPU_CTRL 0x00
  13. #define GIC_CPU_PRIMASK 0x04
  14. #define GIC_CPU_BINPOINT 0x08
  15. #define GIC_CPU_INTACK 0x0c
  16. #define GIC_CPU_EOI 0x10
  17. #define GIC_CPU_RUNNINGPRI 0x14
  18. #define GIC_CPU_HIGHPRI 0x18
  19. #define GIC_DIST_CTRL 0x000
  20. #define GIC_DIST_CTR 0x004
  21. #define GIC_DIST_IGROUP 0x080
  22. #define GIC_DIST_ENABLE_SET 0x100
  23. #define GIC_DIST_ENABLE_CLEAR 0x180
  24. #define GIC_DIST_PENDING_SET 0x200
  25. #define GIC_DIST_PENDING_CLEAR 0x280
  26. #define GIC_DIST_ACTIVE_SET 0x300
  27. #define GIC_DIST_ACTIVE_CLEAR 0x380
  28. #define GIC_DIST_PRI 0x400
  29. #define GIC_DIST_TARGET 0x800
  30. #define GIC_DIST_CONFIG 0xc00
  31. #define GIC_DIST_SOFTINT 0xf00
  32. #define GICH_HCR 0x0
  33. #define GICH_VTR 0x4
  34. #define GICH_VMCR 0x8
  35. #define GICH_MISR 0x10
  36. #define GICH_EISR0 0x20
  37. #define GICH_EISR1 0x24
  38. #define GICH_ELRSR0 0x30
  39. #define GICH_ELRSR1 0x34
  40. #define GICH_APR 0xf0
  41. #define GICH_LR0 0x100
  42. #define GICH_HCR_EN (1 << 0)
  43. #define GICH_HCR_UIE (1 << 1)
  44. #define GICH_LR_VIRTUALID (0x3ff << 0)
  45. #define GICH_LR_PHYSID_CPUID_SHIFT (10)
  46. #define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT)
  47. #define GICH_LR_STATE (3 << 28)
  48. #define GICH_LR_PENDING_BIT (1 << 28)
  49. #define GICH_LR_ACTIVE_BIT (1 << 29)
  50. #define GICH_LR_EOI (1 << 19)
  51. #define GICH_MISR_EOI (1 << 0)
  52. #define GICH_MISR_U (1 << 1)
  53. #ifndef __ASSEMBLY__
  54. struct device_node;
  55. extern struct irq_chip gic_arch_extn;
  56. void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
  57. u32 offset, struct device_node *);
  58. void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
  59. static inline void gic_init(unsigned int nr, int start,
  60. void __iomem *dist , void __iomem *cpu)
  61. {
  62. gic_init_bases(nr, start, dist, cpu, 0, NULL);
  63. }
  64. #endif /* __ASSEMBLY */
  65. #endif