nouveau_drv.h 16 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #ifndef __NOUVEAU_DRV_H__
  25. #define __NOUVEAU_DRV_H__
  26. #define DRIVER_AUTHOR "Stephane Marchesin"
  27. #define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
  28. #define DRIVER_NAME "nouveau"
  29. #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
  30. #define DRIVER_DATE "20120316"
  31. #define DRIVER_MAJOR 1
  32. #define DRIVER_MINOR 0
  33. #define DRIVER_PATCHLEVEL 0
  34. #define NOUVEAU_FAMILY 0x0000FFFF
  35. #define NOUVEAU_FLAGS 0xFFFF0000
  36. #include "ttm/ttm_bo_api.h"
  37. #include "ttm/ttm_bo_driver.h"
  38. #include "ttm/ttm_placement.h"
  39. #include "ttm/ttm_memory.h"
  40. #include "ttm/ttm_module.h"
  41. #define XXX_THIS_IS_A_HACK
  42. #include <subdev/vm.h>
  43. #include <subdev/fb.h>
  44. #include <core/gpuobj.h>
  45. enum blah {
  46. NV_MEM_TYPE_UNKNOWN = 0,
  47. NV_MEM_TYPE_STOLEN,
  48. NV_MEM_TYPE_SGRAM,
  49. NV_MEM_TYPE_SDRAM,
  50. NV_MEM_TYPE_DDR1,
  51. NV_MEM_TYPE_DDR2,
  52. NV_MEM_TYPE_DDR3,
  53. NV_MEM_TYPE_GDDR2,
  54. NV_MEM_TYPE_GDDR3,
  55. NV_MEM_TYPE_GDDR4,
  56. NV_MEM_TYPE_GDDR5
  57. };
  58. #include <nouveau_drm.h>
  59. #include "nouveau_reg.h"
  60. #include <nouveau_bios.h>
  61. #include <subdev/bios/pll.h>
  62. #include "nouveau_compat.h"
  63. #define nouveau_gpuobj_new(d,c,s,a,f,o) \
  64. _nouveau_gpuobj_new((d), NULL, (s), (a), (f), (o))
  65. #define nouveau_vm_new(d,o,l,m,v) \
  66. _nouveau_vm_new((d), (o), (l), (m), (v))
  67. #define nv50_vm_flush_engine(d,e) \
  68. _nv50_vm_flush_engine((d), (e))
  69. #include "nouveau_bo.h"
  70. #include "nouveau_gem.h"
  71. struct nouveau_page_flip_state {
  72. struct list_head head;
  73. struct drm_pending_vblank_event *event;
  74. int crtc, bpp, pitch, x, y;
  75. uint64_t offset;
  76. };
  77. struct nouveau_display_engine {
  78. void *priv;
  79. int (*early_init)(struct drm_device *);
  80. void (*late_takedown)(struct drm_device *);
  81. int (*create)(struct drm_device *);
  82. void (*destroy)(struct drm_device *);
  83. int (*init)(struct drm_device *);
  84. void (*fini)(struct drm_device *);
  85. struct drm_property *dithering_mode;
  86. struct drm_property *dithering_depth;
  87. struct drm_property *underscan_property;
  88. struct drm_property *underscan_hborder_property;
  89. struct drm_property *underscan_vborder_property;
  90. /* not really hue and saturation: */
  91. struct drm_property *vibrant_hue_property;
  92. struct drm_property *color_vibrance_property;
  93. };
  94. struct nouveau_pm_voltage_level {
  95. u32 voltage; /* microvolts */
  96. u8 vid;
  97. };
  98. struct nouveau_pm_voltage {
  99. bool supported;
  100. u8 version;
  101. u8 vid_mask;
  102. struct nouveau_pm_voltage_level *level;
  103. int nr_level;
  104. };
  105. /* Exclusive upper limits */
  106. #define NV_MEM_CL_DDR2_MAX 8
  107. #define NV_MEM_WR_DDR2_MAX 9
  108. #define NV_MEM_CL_DDR3_MAX 17
  109. #define NV_MEM_WR_DDR3_MAX 17
  110. #define NV_MEM_CL_GDDR3_MAX 16
  111. #define NV_MEM_WR_GDDR3_MAX 18
  112. #define NV_MEM_CL_GDDR5_MAX 21
  113. #define NV_MEM_WR_GDDR5_MAX 20
  114. struct nouveau_pm_memtiming {
  115. int id;
  116. u32 reg[9];
  117. u32 mr[4];
  118. u8 tCWL;
  119. u8 odt;
  120. u8 drive_strength;
  121. };
  122. struct nouveau_pm_tbl_header {
  123. u8 version;
  124. u8 header_len;
  125. u8 entry_cnt;
  126. u8 entry_len;
  127. };
  128. struct nouveau_pm_tbl_entry {
  129. u8 tWR;
  130. u8 tWTR;
  131. u8 tCL;
  132. u8 tRC;
  133. u8 empty_4;
  134. u8 tRFC; /* Byte 5 */
  135. u8 empty_6;
  136. u8 tRAS; /* Byte 7 */
  137. u8 empty_8;
  138. u8 tRP; /* Byte 9 */
  139. u8 tRCDRD;
  140. u8 tRCDWR;
  141. u8 tRRD;
  142. u8 tUNK_13;
  143. u8 RAM_FT1; /* 14, a bitmask of random RAM features */
  144. u8 empty_15;
  145. u8 tUNK_16;
  146. u8 empty_17;
  147. u8 tUNK_18;
  148. u8 tCWL;
  149. u8 tUNK_20, tUNK_21;
  150. };
  151. struct nouveau_pm_profile;
  152. struct nouveau_pm_profile_func {
  153. void (*destroy)(struct nouveau_pm_profile *);
  154. void (*init)(struct nouveau_pm_profile *);
  155. void (*fini)(struct nouveau_pm_profile *);
  156. struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
  157. };
  158. struct nouveau_pm_profile {
  159. const struct nouveau_pm_profile_func *func;
  160. struct list_head head;
  161. char name[8];
  162. };
  163. #define NOUVEAU_PM_MAX_LEVEL 8
  164. struct nouveau_pm_level {
  165. struct nouveau_pm_profile profile;
  166. struct device_attribute dev_attr;
  167. char name[32];
  168. int id;
  169. struct nouveau_pm_memtiming timing;
  170. u32 memory;
  171. u16 memscript;
  172. u32 core;
  173. u32 shader;
  174. u32 rop;
  175. u32 copy;
  176. u32 daemon;
  177. u32 vdec;
  178. u32 dom6;
  179. u32 unka0; /* nva3:nvc0 */
  180. u32 hub01; /* nvc0- */
  181. u32 hub06; /* nvc0- */
  182. u32 hub07; /* nvc0- */
  183. u32 volt_min; /* microvolts */
  184. u32 volt_max;
  185. u8 fanspeed;
  186. };
  187. struct nouveau_pm_temp_sensor_constants {
  188. u16 offset_constant;
  189. s16 offset_mult;
  190. s16 offset_div;
  191. s16 slope_mult;
  192. s16 slope_div;
  193. };
  194. struct nouveau_pm_threshold_temp {
  195. s16 critical;
  196. s16 down_clock;
  197. s16 fan_boost;
  198. };
  199. struct nouveau_pm_fan {
  200. u32 percent;
  201. u32 min_duty;
  202. u32 max_duty;
  203. u32 pwm_freq;
  204. u32 pwm_divisor;
  205. };
  206. struct nouveau_pm_engine {
  207. struct nouveau_pm_voltage voltage;
  208. struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
  209. int nr_perflvl;
  210. struct nouveau_pm_temp_sensor_constants sensor_constants;
  211. struct nouveau_pm_threshold_temp threshold_temp;
  212. struct nouveau_pm_fan fan;
  213. struct nouveau_pm_profile *profile_ac;
  214. struct nouveau_pm_profile *profile_dc;
  215. struct nouveau_pm_profile *profile;
  216. struct list_head profiles;
  217. struct nouveau_pm_level boot;
  218. struct nouveau_pm_level *cur;
  219. struct device *hwmon;
  220. struct notifier_block acpi_nb;
  221. int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
  222. void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
  223. int (*clocks_set)(struct drm_device *, void *);
  224. int (*voltage_get)(struct drm_device *);
  225. int (*voltage_set)(struct drm_device *, int voltage);
  226. int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
  227. int (*pwm_set)(struct drm_device *, int line, u32, u32);
  228. int (*temp_get)(struct drm_device *);
  229. };
  230. struct nouveau_engine {
  231. struct nouveau_display_engine display;
  232. struct nouveau_pm_engine pm;
  233. };
  234. enum nouveau_card_type {
  235. NV_04 = 0x04,
  236. NV_10 = 0x10,
  237. NV_20 = 0x20,
  238. NV_30 = 0x30,
  239. NV_40 = 0x40,
  240. NV_50 = 0x50,
  241. NV_C0 = 0xc0,
  242. NV_D0 = 0xd0,
  243. NV_E0 = 0xe0,
  244. };
  245. struct drm_nouveau_private {
  246. struct drm_device *dev;
  247. void *newpriv;
  248. /* the card type, takes NV_* as values */
  249. enum nouveau_card_type card_type;
  250. /* exact chipset, derived from NV_PMC_BOOT_0 */
  251. int chipset;
  252. u32 crystal;
  253. /* interrupt handling */
  254. void (*irq_handler[32])(struct drm_device *);
  255. bool msi_enabled;
  256. struct nouveau_engine engine;
  257. /* For PFIFO and PGRAPH. */
  258. spinlock_t context_switch_lock;
  259. struct nvbios vbios;
  260. u8 *mxms;
  261. struct backlight_device *backlight;
  262. };
  263. static inline struct drm_nouveau_private *
  264. nouveau_private(struct drm_device *dev)
  265. {
  266. return dev->dev_private;
  267. }
  268. /* nouveau_drv.c */
  269. extern int nouveau_modeset;
  270. extern int nouveau_duallink;
  271. extern int nouveau_uscript_lvds;
  272. extern int nouveau_uscript_tmds;
  273. extern int nouveau_vram_pushbuf;
  274. extern int nouveau_vram_notify;
  275. extern char *nouveau_vram_type;
  276. extern int nouveau_fbpercrtc;
  277. extern int nouveau_tv_disable;
  278. extern char *nouveau_tv_norm;
  279. extern int nouveau_ignorelid;
  280. extern int nouveau_force_post;
  281. extern int nouveau_override_conntype;
  282. extern char *nouveau_perflvl;
  283. extern int nouveau_perflvl_wr;
  284. extern int nouveau_msi;
  285. extern int nouveau_ctxfw;
  286. extern int nouveau_mxmdcb;
  287. extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
  288. extern int nouveau_pci_resume(struct pci_dev *pdev);
  289. /* nouveau_state.c */
  290. extern int nouveau_load(struct drm_device *, unsigned long flags);
  291. extern int nouveau_firstopen(struct drm_device *);
  292. extern void nouveau_lastclose(struct drm_device *);
  293. extern int nouveau_unload(struct drm_device *);
  294. extern int nouveau_card_init(struct drm_device *);
  295. /* nouveau_mem.c */
  296. extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
  297. struct nouveau_pm_memtiming *);
  298. extern void nouveau_mem_timing_read(struct drm_device *,
  299. struct nouveau_pm_memtiming *);
  300. /* nouveau_irq.c */
  301. extern int nouveau_irq_init(struct drm_device *);
  302. extern void nouveau_irq_fini(struct drm_device *);
  303. extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
  304. extern void nouveau_irq_register(struct drm_device *, int status_bit,
  305. void (*)(struct drm_device *));
  306. extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
  307. extern void nouveau_irq_preinstall(struct drm_device *);
  308. extern int nouveau_irq_postinstall(struct drm_device *);
  309. extern void nouveau_irq_uninstall(struct drm_device *);
  310. /* nouveau_backlight.c */
  311. #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
  312. extern int nouveau_backlight_init(struct drm_device *);
  313. extern void nouveau_backlight_exit(struct drm_device *);
  314. #else
  315. static inline int nouveau_backlight_init(struct drm_device *dev)
  316. {
  317. return 0;
  318. }
  319. static inline void nouveau_backlight_exit(struct drm_device *dev) { }
  320. #endif
  321. /* nouveau_bios.c */
  322. extern int nouveau_bios_init(struct drm_device *);
  323. extern void nouveau_bios_takedown(struct drm_device *dev);
  324. extern int nouveau_run_vbios_init(struct drm_device *);
  325. extern struct dcb_connector_table_entry *
  326. nouveau_bios_connector_entry(struct drm_device *, int index);
  327. extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
  328. struct dcb_output *, int crtc);
  329. extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
  330. extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
  331. extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
  332. bool *dl, bool *if_is_24bit);
  333. extern int run_tmds_table(struct drm_device *, struct dcb_output *,
  334. int head, int pxclk);
  335. extern int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
  336. enum LVDS_script, int pxclk);
  337. bool bios_encoder_match(struct dcb_output *, u32 hash);
  338. /* nouveau_ttm.c */
  339. int nouveau_ttm_global_init(struct drm_nouveau_private *);
  340. void nouveau_ttm_global_release(struct drm_nouveau_private *);
  341. int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
  342. /* nouveau_hdmi.c */
  343. void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
  344. extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
  345. unsigned long arg);
  346. /* nvd0_display.c */
  347. extern int nvd0_display_create(struct drm_device *);
  348. extern void nvd0_display_destroy(struct drm_device *);
  349. extern int nvd0_display_init(struct drm_device *);
  350. extern void nvd0_display_fini(struct drm_device *);
  351. struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
  352. void nvd0_display_flip_stop(struct drm_crtc *);
  353. int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
  354. struct nouveau_channel *, u32 swap_interval);
  355. /* nouveau_display.c */
  356. int nouveau_display_create(struct drm_device *dev);
  357. void nouveau_display_destroy(struct drm_device *dev);
  358. int nouveau_display_init(struct drm_device *dev);
  359. void nouveau_display_fini(struct drm_device *dev);
  360. int nouveau_vblank_enable(struct drm_device *dev, int crtc);
  361. void nouveau_vblank_disable(struct drm_device *dev, int crtc);
  362. int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  363. struct drm_pending_vblank_event *event);
  364. int nouveau_finish_page_flip(struct nouveau_channel *,
  365. struct nouveau_page_flip_state *);
  366. int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
  367. struct drm_mode_create_dumb *args);
  368. int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
  369. uint32_t handle, uint64_t *offset);
  370. int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
  371. uint32_t handle);
  372. #ifndef ioread32_native
  373. #ifdef __BIG_ENDIAN
  374. #define ioread16_native ioread16be
  375. #define iowrite16_native iowrite16be
  376. #define ioread32_native ioread32be
  377. #define iowrite32_native iowrite32be
  378. #else /* def __BIG_ENDIAN */
  379. #define ioread16_native ioread16
  380. #define iowrite16_native iowrite16
  381. #define ioread32_native ioread32
  382. #define iowrite32_native iowrite32
  383. #endif /* def __BIG_ENDIAN else */
  384. #endif /* !ioread32_native */
  385. /* register access */
  386. #define nv_rd08 _nv_rd08
  387. #define nv_wr08 _nv_wr08
  388. #define nv_rd32 _nv_rd32
  389. #define nv_wr32 _nv_wr32
  390. #define nv_mask _nv_mask
  391. #define nv_wait(dev, reg, mask, val) \
  392. nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
  393. #define nv_wait_ne(dev, reg, mask, val) \
  394. nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
  395. #define nv_wait_cb(dev, func, data) \
  396. nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
  397. /*
  398. * Logging
  399. * Argument d is (struct drm_device *).
  400. */
  401. #define NV_PRINTK(level, d, fmt, arg...) \
  402. printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
  403. pci_name(d->pdev), ##arg)
  404. #ifndef NV_DEBUG_NOTRACE
  405. #define NV_DEBUG(d, fmt, arg...) do { \
  406. if (drm_debug & DRM_UT_DRIVER) { \
  407. NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
  408. __LINE__, ##arg); \
  409. } \
  410. } while (0)
  411. #define NV_DEBUG_KMS(d, fmt, arg...) do { \
  412. if (drm_debug & DRM_UT_KMS) { \
  413. NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
  414. __LINE__, ##arg); \
  415. } \
  416. } while (0)
  417. #else
  418. #define NV_DEBUG(d, fmt, arg...) do { \
  419. if (drm_debug & DRM_UT_DRIVER) \
  420. NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
  421. } while (0)
  422. #define NV_DEBUG_KMS(d, fmt, arg...) do { \
  423. if (drm_debug & DRM_UT_KMS) \
  424. NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
  425. } while (0)
  426. #endif
  427. #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
  428. #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
  429. #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
  430. #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
  431. #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
  432. #define NV_WARNONCE(d, fmt, arg...) do { \
  433. static int _warned = 0; \
  434. if (!_warned) { \
  435. NV_WARN(d, fmt, ##arg); \
  436. _warned = 1; \
  437. } \
  438. } while(0)
  439. static inline bool
  440. nv_two_heads(struct drm_device *dev)
  441. {
  442. struct drm_nouveau_private *dev_priv = dev->dev_private;
  443. const int impl = dev->pci_device & 0x0ff0;
  444. if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
  445. impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
  446. return true;
  447. return false;
  448. }
  449. static inline bool
  450. nv_gf4_disp_arch(struct drm_device *dev)
  451. {
  452. return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
  453. }
  454. static inline bool
  455. nv_two_reg_pll(struct drm_device *dev)
  456. {
  457. struct drm_nouveau_private *dev_priv = dev->dev_private;
  458. const int impl = dev->pci_device & 0x0ff0;
  459. if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
  460. return true;
  461. return false;
  462. }
  463. static inline bool
  464. nv_match_device(struct drm_device *dev, unsigned device,
  465. unsigned sub_vendor, unsigned sub_device)
  466. {
  467. return dev->pdev->device == device &&
  468. dev->pdev->subsystem_vendor == sub_vendor &&
  469. dev->pdev->subsystem_device == sub_device;
  470. }
  471. #endif /* __NOUVEAU_DRV_H__ */