wm8776.c 18 KB

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  1. /*
  2. * ALSA driver for ICEnsemble VT17xx
  3. *
  4. * Lowlevel functions for WM8776 codec
  5. *
  6. * Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/delay.h>
  24. #include <sound/core.h>
  25. #include <sound/control.h>
  26. #include <sound/tlv.h>
  27. #include "wm8776.h"
  28. /* low-level access */
  29. static void snd_wm8776_write(struct snd_wm8776 *wm, u16 addr, u16 data)
  30. {
  31. u8 bus_addr = addr << 1 | data >> 8; /* addr + 9th data bit */
  32. u8 bus_data = data & 0xff; /* remaining 8 data bits */
  33. if (addr < WM8776_REG_RESET)
  34. wm->regs[addr] = data;
  35. wm->ops.write(wm, bus_addr, bus_data);
  36. }
  37. /* register-level functions */
  38. static void snd_wm8776_activate_ctl(struct snd_wm8776 *wm, char *ctl_name,
  39. bool active)
  40. {
  41. struct snd_card *card = wm->card;
  42. struct snd_kcontrol *kctl;
  43. struct snd_kcontrol_volatile *vd;
  44. struct snd_ctl_elem_id elem_id;
  45. unsigned int index_offset;
  46. memset(&elem_id, 0, sizeof(elem_id));
  47. strncpy(elem_id.name, ctl_name, sizeof(elem_id.name));
  48. elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  49. kctl = snd_ctl_find_id(card, &elem_id);
  50. if (!kctl)
  51. return;
  52. index_offset = snd_ctl_get_ioff(kctl, &kctl->id);
  53. vd = &kctl->vd[index_offset];
  54. if (active)
  55. vd->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  56. else
  57. vd->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  58. snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  59. }
  60. static void snd_wm8776_update_agc_ctl(struct snd_wm8776 *wm)
  61. {
  62. int i, flags_on = 0, flags_off = 0;
  63. switch (wm->agc_mode) {
  64. case WM8776_AGC_OFF:
  65. flags_off = WM8776_FLAG_LIM | WM8776_FLAG_ALC;
  66. break;
  67. case WM8776_AGC_LIM:
  68. flags_off = WM8776_FLAG_ALC;
  69. flags_on = WM8776_FLAG_LIM;
  70. break;
  71. case WM8776_AGC_ALC_R:
  72. case WM8776_AGC_ALC_L:
  73. case WM8776_AGC_ALC_STEREO:
  74. flags_off = WM8776_FLAG_LIM;
  75. flags_on = WM8776_FLAG_ALC;
  76. break;
  77. }
  78. for (i = 0; i < WM8776_CTL_COUNT; i++)
  79. if (wm->ctl[i].flags & flags_off)
  80. snd_wm8776_activate_ctl(wm, wm->ctl[i].name, false);
  81. else if (wm->ctl[i].flags & flags_on)
  82. snd_wm8776_activate_ctl(wm, wm->ctl[i].name, true);
  83. }
  84. static void snd_wm8776_set_agc(struct snd_wm8776 *wm, u16 agc, u16 nothing)
  85. {
  86. u16 alc1 = wm->regs[WM8776_REG_ALCCTRL1] & ~WM8776_ALC1_LCT_MASK;
  87. u16 alc2 = wm->regs[WM8776_REG_ALCCTRL2] & ~WM8776_ALC2_LCEN;
  88. switch (agc) {
  89. case 0: /* Off */
  90. wm->agc_mode = WM8776_AGC_OFF;
  91. break;
  92. case 1: /* Limiter */
  93. alc2 |= WM8776_ALC2_LCEN;
  94. wm->agc_mode = WM8776_AGC_LIM;
  95. break;
  96. case 2: /* ALC Right */
  97. alc1 |= WM8776_ALC1_LCSEL_ALCR;
  98. alc2 |= WM8776_ALC2_LCEN;
  99. wm->agc_mode = WM8776_AGC_ALC_R;
  100. break;
  101. case 3: /* ALC Left */
  102. alc1 |= WM8776_ALC1_LCSEL_ALCL;
  103. alc2 |= WM8776_ALC2_LCEN;
  104. wm->agc_mode = WM8776_AGC_ALC_L;
  105. break;
  106. case 4: /* ALC Stereo */
  107. alc1 |= WM8776_ALC1_LCSEL_ALCSTEREO;
  108. alc2 |= WM8776_ALC2_LCEN;
  109. wm->agc_mode = WM8776_AGC_ALC_STEREO;
  110. break;
  111. }
  112. snd_wm8776_write(wm, WM8776_REG_ALCCTRL1, alc1);
  113. snd_wm8776_write(wm, WM8776_REG_ALCCTRL2, alc2);
  114. snd_wm8776_update_agc_ctl(wm);
  115. }
  116. static void snd_wm8776_get_agc(struct snd_wm8776 *wm, u16 *mode, u16 *nothing)
  117. {
  118. *mode = wm->agc_mode;
  119. }
  120. /* mixer controls */
  121. static const DECLARE_TLV_DB_SCALE(wm8776_hp_tlv, -7400, 100, 1);
  122. static const DECLARE_TLV_DB_SCALE(wm8776_dac_tlv, -12750, 50, 1);
  123. static const DECLARE_TLV_DB_SCALE(wm8776_adc_tlv, -10350, 50, 1);
  124. static const DECLARE_TLV_DB_SCALE(wm8776_lct_tlv, -1600, 100, 0);
  125. static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_tlv, 0, 400, 0);
  126. static const DECLARE_TLV_DB_SCALE(wm8776_ngth_tlv, -7800, 600, 0);
  127. static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_tlv, -1200, 100, 0);
  128. static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_tlv, -2100, 400, 0);
  129. static struct snd_wm8776_ctl snd_wm8776_default_ctl[WM8776_CTL_COUNT] = {
  130. [WM8776_CTL_DAC_VOL] = {
  131. .name = "Master Playback Volume",
  132. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  133. .tlv = wm8776_dac_tlv,
  134. .reg1 = WM8776_REG_DACLVOL,
  135. .reg2 = WM8776_REG_DACRVOL,
  136. .mask1 = WM8776_DACVOL_MASK,
  137. .mask2 = WM8776_DACVOL_MASK,
  138. .max = 0xff,
  139. .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
  140. },
  141. [WM8776_CTL_DAC_SW] = {
  142. .name = "Master Playback Switch",
  143. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  144. .reg1 = WM8776_REG_DACCTRL1,
  145. .reg2 = WM8776_REG_DACCTRL1,
  146. .mask1 = WM8776_DAC_PL_LL,
  147. .mask2 = WM8776_DAC_PL_RR,
  148. .flags = WM8776_FLAG_STEREO,
  149. },
  150. [WM8776_CTL_DAC_ZC_SW] = {
  151. .name = "Master Zero Cross Detect Playback Switch",
  152. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  153. .reg1 = WM8776_REG_DACCTRL1,
  154. .mask1 = WM8776_DAC_DZCEN,
  155. },
  156. [WM8776_CTL_HP_VOL] = {
  157. .name = "Headphone Playback Volume",
  158. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  159. .tlv = wm8776_hp_tlv,
  160. .reg1 = WM8776_REG_HPLVOL,
  161. .reg2 = WM8776_REG_HPRVOL,
  162. .mask1 = WM8776_HPVOL_MASK,
  163. .mask2 = WM8776_HPVOL_MASK,
  164. .min = 0x2f,
  165. .max = 0x7f,
  166. .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
  167. },
  168. [WM8776_CTL_HP_SW] = {
  169. .name = "Headphone Playback Switch",
  170. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  171. .reg1 = WM8776_REG_PWRDOWN,
  172. .mask1 = WM8776_PWR_HPPD,
  173. .flags = WM8776_FLAG_INVERT,
  174. },
  175. [WM8776_CTL_HP_ZC_SW] = {
  176. .name = "Headphone Zero Cross Detect Playback Switch",
  177. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  178. .reg1 = WM8776_REG_HPLVOL,
  179. .reg2 = WM8776_REG_HPRVOL,
  180. .mask1 = WM8776_VOL_HPZCEN,
  181. .mask2 = WM8776_VOL_HPZCEN,
  182. .flags = WM8776_FLAG_STEREO,
  183. },
  184. [WM8776_CTL_AUX_SW] = {
  185. .name = "AUX Playback Switch",
  186. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  187. .reg1 = WM8776_REG_OUTMUX,
  188. .mask1 = WM8776_OUTMUX_AUX,
  189. },
  190. [WM8776_CTL_BYPASS_SW] = {
  191. .name = "Bypass Playback Switch",
  192. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  193. .reg1 = WM8776_REG_OUTMUX,
  194. .mask1 = WM8776_OUTMUX_BYPASS,
  195. },
  196. [WM8776_CTL_DAC_IZD_SW] = {
  197. .name = "Infinite Zero Detect Playback Switch",
  198. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  199. .reg1 = WM8776_REG_DACCTRL1,
  200. .mask1 = WM8776_DAC_IZD,
  201. },
  202. [WM8776_CTL_PHASE_SW] = {
  203. .name = "Phase Invert Playback Switch",
  204. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  205. .reg1 = WM8776_REG_PHASESWAP,
  206. .reg2 = WM8776_REG_PHASESWAP,
  207. .mask1 = WM8776_PHASE_INVERTL,
  208. .mask2 = WM8776_PHASE_INVERTR,
  209. .flags = WM8776_FLAG_STEREO,
  210. },
  211. [WM8776_CTL_DEEMPH_SW] = {
  212. .name = "Deemphasis Playback Switch",
  213. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  214. .reg1 = WM8776_REG_DACCTRL2,
  215. .mask1 = WM8776_DAC2_DEEMPH,
  216. },
  217. [WM8776_CTL_ADC_VOL] = {
  218. .name = "Input Capture Volume",
  219. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  220. .tlv = wm8776_adc_tlv,
  221. .reg1 = WM8776_REG_ADCLVOL,
  222. .reg2 = WM8776_REG_ADCRVOL,
  223. .mask1 = WM8776_ADC_GAIN_MASK,
  224. .mask2 = WM8776_ADC_GAIN_MASK,
  225. .max = 0xff,
  226. .flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
  227. },
  228. [WM8776_CTL_ADC_SW] = {
  229. .name = "Input Capture Switch",
  230. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  231. .reg1 = WM8776_REG_ADCMUX,
  232. .reg2 = WM8776_REG_ADCMUX,
  233. .mask1 = WM8776_ADC_MUTEL,
  234. .mask2 = WM8776_ADC_MUTER,
  235. .flags = WM8776_FLAG_STEREO | WM8776_FLAG_INVERT,
  236. },
  237. [WM8776_CTL_INPUT1_SW] = {
  238. .name = "AIN1 Capture Switch",
  239. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  240. .reg1 = WM8776_REG_ADCMUX,
  241. .mask1 = WM8776_ADC_MUX_AIN1,
  242. },
  243. [WM8776_CTL_INPUT2_SW] = {
  244. .name = "AIN2 Capture Switch",
  245. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  246. .reg1 = WM8776_REG_ADCMUX,
  247. .mask1 = WM8776_ADC_MUX_AIN2,
  248. },
  249. [WM8776_CTL_INPUT3_SW] = {
  250. .name = "AIN3 Capture Switch",
  251. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  252. .reg1 = WM8776_REG_ADCMUX,
  253. .mask1 = WM8776_ADC_MUX_AIN3,
  254. },
  255. [WM8776_CTL_INPUT4_SW] = {
  256. .name = "AIN4 Capture Switch",
  257. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  258. .reg1 = WM8776_REG_ADCMUX,
  259. .mask1 = WM8776_ADC_MUX_AIN4,
  260. },
  261. [WM8776_CTL_INPUT5_SW] = {
  262. .name = "AIN5 Capture Switch",
  263. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  264. .reg1 = WM8776_REG_ADCMUX,
  265. .mask1 = WM8776_ADC_MUX_AIN5,
  266. },
  267. [WM8776_CTL_AGC_SEL] = {
  268. .name = "AGC Select Capture Enum",
  269. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  270. .enum_names = { "Off", "Limiter", "ALC Right", "ALC Left",
  271. "ALC Stereo" },
  272. .max = 5, /* .enum_names item count */
  273. .set = snd_wm8776_set_agc,
  274. .get = snd_wm8776_get_agc,
  275. },
  276. [WM8776_CTL_LIM_THR] = {
  277. .name = "Limiter Threshold Capture Volume",
  278. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  279. .tlv = wm8776_lct_tlv,
  280. .reg1 = WM8776_REG_ALCCTRL1,
  281. .mask1 = WM8776_ALC1_LCT_MASK,
  282. .max = 15,
  283. .flags = WM8776_FLAG_LIM,
  284. },
  285. [WM8776_CTL_LIM_ATK] = {
  286. .name = "Limiter Attack Time Capture Enum",
  287. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  288. .enum_names = { "0.25 ms", "0.5 ms", "1 ms", "2 ms", "4 ms",
  289. "8 ms", "16 ms", "32 ms", "64 ms", "128 ms", "256 ms" },
  290. .max = 11, /* .enum_names item count */
  291. .reg1 = WM8776_REG_ALCCTRL3,
  292. .mask1 = WM8776_ALC3_ATK_MASK,
  293. .flags = WM8776_FLAG_LIM,
  294. },
  295. [WM8776_CTL_LIM_DCY] = {
  296. .name = "Limiter Decay Time Capture Enum",
  297. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  298. .enum_names = { "1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms",
  299. "19.2 ms", "38.4 ms", "76.8 ms", "154 ms", "307 ms",
  300. "614 ms", "1.23 s" },
  301. .max = 11, /* .enum_names item count */
  302. .reg1 = WM8776_REG_ALCCTRL3,
  303. .mask1 = WM8776_ALC3_DCY_MASK,
  304. .flags = WM8776_FLAG_LIM,
  305. },
  306. [WM8776_CTL_LIM_TRANWIN] = {
  307. .name = "Limiter Transient Window Capture Enum",
  308. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  309. .enum_names = { "0 us", "62.5 us", "125 us", "250 us", "500 us",
  310. "1 ms", "2 ms", "4 ms" },
  311. .max = 8, /* .enum_names item count */
  312. .reg1 = WM8776_REG_LIMITER,
  313. .mask1 = WM8776_LIM_TRANWIN_MASK,
  314. .flags = WM8776_FLAG_LIM,
  315. },
  316. [WM8776_CTL_LIM_MAXATTN] = {
  317. .name = "Limiter Maximum Attenuation Capture Volume",
  318. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  319. .tlv = wm8776_maxatten_lim_tlv,
  320. .reg1 = WM8776_REG_LIMITER,
  321. .mask1 = WM8776_LIM_MAXATTEN_MASK,
  322. .min = 3,
  323. .max = 12,
  324. .flags = WM8776_FLAG_LIM | WM8776_FLAG_INVERT,
  325. },
  326. [WM8776_CTL_ALC_TGT] = {
  327. .name = "ALC Target Level Capture Volume",
  328. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  329. .tlv = wm8776_lct_tlv,
  330. .reg1 = WM8776_REG_ALCCTRL1,
  331. .mask1 = WM8776_ALC1_LCT_MASK,
  332. .max = 15,
  333. .flags = WM8776_FLAG_ALC,
  334. },
  335. [WM8776_CTL_ALC_ATK] = {
  336. .name = "ALC Attack Time Capture Enum",
  337. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  338. .enum_names = { "8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms",
  339. "134 ms", "269 ms", "538 ms", "1.08 s", "2.15 s",
  340. "4.3 s", "8.6 s" },
  341. .max = 11, /* .enum_names item count */
  342. .reg1 = WM8776_REG_ALCCTRL3,
  343. .mask1 = WM8776_ALC3_ATK_MASK,
  344. .flags = WM8776_FLAG_ALC,
  345. },
  346. [WM8776_CTL_ALC_DCY] = {
  347. .name = "ALC Decay Time Capture Enum",
  348. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  349. .enum_names = { "33.5 ms", "67.0 ms", "134 ms", "268 ms",
  350. "536 ms", "1.07 s", "2.14 s", "4.29 s", "8.58 s",
  351. "17.2 s", "34.3 s" },
  352. .max = 11, /* .enum_names item count */
  353. .reg1 = WM8776_REG_ALCCTRL3,
  354. .mask1 = WM8776_ALC3_DCY_MASK,
  355. .flags = WM8776_FLAG_ALC,
  356. },
  357. [WM8776_CTL_ALC_MAXGAIN] = {
  358. .name = "ALC Maximum Gain Capture Volume",
  359. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  360. .tlv = wm8776_maxgain_tlv,
  361. .reg1 = WM8776_REG_ALCCTRL1,
  362. .mask1 = WM8776_ALC1_MAXGAIN_MASK,
  363. .min = 1,
  364. .max = 7,
  365. .flags = WM8776_FLAG_ALC,
  366. },
  367. [WM8776_CTL_ALC_MAXATTN] = {
  368. .name = "ALC Maximum Attenuation Capture Volume",
  369. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  370. .tlv = wm8776_maxatten_alc_tlv,
  371. .reg1 = WM8776_REG_LIMITER,
  372. .mask1 = WM8776_LIM_MAXATTEN_MASK,
  373. .min = 10,
  374. .max = 15,
  375. .flags = WM8776_FLAG_ALC | WM8776_FLAG_INVERT,
  376. },
  377. [WM8776_CTL_ALC_HLD] = {
  378. .name = "ALC Hold Time Capture Enum",
  379. .type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
  380. .enum_names = { "0 ms", "2.67 ms", "5.33 ms", "10.6 ms",
  381. "21.3 ms", "42.7 ms", "85.3 ms", "171 ms", "341 ms",
  382. "683 ms", "1.37 s", "2.73 s", "5.46 s", "10.9 s",
  383. "21.8 s", "43.7 s" },
  384. .max = 16, /* .enum_names item count */
  385. .reg1 = WM8776_REG_ALCCTRL2,
  386. .mask1 = WM8776_ALC2_HOLD_MASK,
  387. .flags = WM8776_FLAG_ALC,
  388. },
  389. [WM8776_CTL_NGT_SW] = {
  390. .name = "Noise Gate Capture Switch",
  391. .type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
  392. .reg1 = WM8776_REG_NOISEGATE,
  393. .mask1 = WM8776_NGAT_ENABLE,
  394. .flags = WM8776_FLAG_ALC,
  395. },
  396. [WM8776_CTL_NGT_THR] = {
  397. .name = "Noise Gate Threshold Capture Volume",
  398. .type = SNDRV_CTL_ELEM_TYPE_INTEGER,
  399. .tlv = wm8776_ngth_tlv,
  400. .reg1 = WM8776_REG_NOISEGATE,
  401. .mask1 = WM8776_NGAT_THR_MASK,
  402. .max = 7,
  403. .flags = WM8776_FLAG_ALC,
  404. },
  405. };
  406. /* exported functions */
  407. void snd_wm8776_init(struct snd_wm8776 *wm)
  408. {
  409. int i;
  410. static const u16 default_values[] = {
  411. 0x000, 0x100, 0x000,
  412. 0x000, 0x100, 0x000,
  413. 0x000, 0x090, 0x000, 0x000,
  414. 0x022, 0x022, 0x022,
  415. 0x008, 0x0cf, 0x0cf, 0x07b, 0x000,
  416. 0x032, 0x000, 0x0a6, 0x001, 0x001
  417. };
  418. memcpy(wm->ctl, snd_wm8776_default_ctl, sizeof(wm->ctl));
  419. snd_wm8776_write(wm, WM8776_REG_RESET, 0x00); /* reset */
  420. udelay(10);
  421. /* load defaults */
  422. for (i = 0; i < ARRAY_SIZE(default_values); i++)
  423. snd_wm8776_write(wm, i, default_values[i]);
  424. }
  425. void snd_wm8776_resume(struct snd_wm8776 *wm)
  426. {
  427. int i;
  428. for (i = 0; i < WM8776_REG_COUNT; i++)
  429. snd_wm8776_write(wm, i, wm->regs[i]);
  430. }
  431. void snd_wm8776_set_dac_if(struct snd_wm8776 *wm, u16 dac)
  432. {
  433. snd_wm8776_write(wm, WM8776_REG_DACIFCTRL, dac);
  434. }
  435. void snd_wm8776_set_adc_if(struct snd_wm8776 *wm, u16 adc)
  436. {
  437. snd_wm8776_write(wm, WM8776_REG_ADCIFCTRL, adc);
  438. }
  439. void snd_wm8776_set_master_mode(struct snd_wm8776 *wm, u16 mode)
  440. {
  441. snd_wm8776_write(wm, WM8776_REG_MSTRCTRL, mode);
  442. }
  443. void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power)
  444. {
  445. snd_wm8776_write(wm, WM8776_REG_PWRDOWN, power);
  446. }
  447. void snd_wm8776_volume_restore(struct snd_wm8776 *wm)
  448. {
  449. u16 val = wm->regs[WM8776_REG_DACRVOL];
  450. /* restore volume after MCLK stopped */
  451. snd_wm8776_write(wm, WM8776_REG_DACRVOL, val | WM8776_VOL_UPDATE);
  452. }
  453. /* mixer callbacks */
  454. static int snd_wm8776_volume_info(struct snd_kcontrol *kcontrol,
  455. struct snd_ctl_elem_info *uinfo)
  456. {
  457. struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
  458. int n = kcontrol->private_value;
  459. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  460. uinfo->count = (wm->ctl[n].flags & WM8776_FLAG_STEREO) ? 2 : 1;
  461. uinfo->value.integer.min = wm->ctl[n].min;
  462. uinfo->value.integer.max = wm->ctl[n].max;
  463. return 0;
  464. }
  465. static int snd_wm8776_enum_info(struct snd_kcontrol *kcontrol,
  466. struct snd_ctl_elem_info *uinfo)
  467. {
  468. struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
  469. int n = kcontrol->private_value;
  470. return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max,
  471. wm->ctl[n].enum_names);
  472. }
  473. static int snd_wm8776_ctl_get(struct snd_kcontrol *kcontrol,
  474. struct snd_ctl_elem_value *ucontrol)
  475. {
  476. struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
  477. int n = kcontrol->private_value;
  478. u16 val1, val2;
  479. if (wm->ctl[n].get)
  480. wm->ctl[n].get(wm, &val1, &val2);
  481. else {
  482. val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1;
  483. val1 >>= __ffs(wm->ctl[n].mask1);
  484. if (wm->ctl[n].flags & WM8776_FLAG_STEREO) {
  485. val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
  486. val2 >>= __ffs(wm->ctl[n].mask2);
  487. if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
  488. val2 &= ~WM8776_VOL_UPDATE;
  489. }
  490. }
  491. if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
  492. val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min);
  493. val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min);
  494. }
  495. ucontrol->value.integer.value[0] = val1;
  496. if (wm->ctl[n].flags & WM8776_FLAG_STEREO)
  497. ucontrol->value.integer.value[1] = val2;
  498. return 0;
  499. }
  500. static int snd_wm8776_ctl_put(struct snd_kcontrol *kcontrol,
  501. struct snd_ctl_elem_value *ucontrol)
  502. {
  503. struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
  504. int n = kcontrol->private_value;
  505. u16 val, regval1, regval2;
  506. /* this also works for enum because value is an union */
  507. regval1 = ucontrol->value.integer.value[0];
  508. regval2 = ucontrol->value.integer.value[1];
  509. if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
  510. regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min);
  511. regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min);
  512. }
  513. if (wm->ctl[n].set)
  514. wm->ctl[n].set(wm, regval1, regval2);
  515. else {
  516. val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1;
  517. val |= regval1 << __ffs(wm->ctl[n].mask1);
  518. /* both stereo controls in one register */
  519. if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
  520. wm->ctl[n].reg1 == wm->ctl[n].reg2) {
  521. val &= ~wm->ctl[n].mask2;
  522. val |= regval2 << __ffs(wm->ctl[n].mask2);
  523. }
  524. snd_wm8776_write(wm, wm->ctl[n].reg1, val);
  525. /* stereo controls in different registers */
  526. if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
  527. wm->ctl[n].reg1 != wm->ctl[n].reg2) {
  528. val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
  529. val |= regval2 << __ffs(wm->ctl[n].mask2);
  530. if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
  531. val |= WM8776_VOL_UPDATE;
  532. snd_wm8776_write(wm, wm->ctl[n].reg2, val);
  533. }
  534. }
  535. return 0;
  536. }
  537. static int snd_wm8776_add_control(struct snd_wm8776 *wm, int num)
  538. {
  539. struct snd_kcontrol_new cont;
  540. struct snd_kcontrol *ctl;
  541. memset(&cont, 0, sizeof(cont));
  542. cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  543. cont.private_value = num;
  544. cont.name = wm->ctl[num].name;
  545. cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
  546. if (wm->ctl[num].flags & WM8776_FLAG_LIM ||
  547. wm->ctl[num].flags & WM8776_FLAG_ALC)
  548. cont.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  549. cont.tlv.p = NULL;
  550. cont.get = snd_wm8776_ctl_get;
  551. cont.put = snd_wm8776_ctl_put;
  552. switch (wm->ctl[num].type) {
  553. case SNDRV_CTL_ELEM_TYPE_INTEGER:
  554. cont.info = snd_wm8776_volume_info;
  555. cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  556. cont.tlv.p = wm->ctl[num].tlv;
  557. break;
  558. case SNDRV_CTL_ELEM_TYPE_BOOLEAN:
  559. wm->ctl[num].max = 1;
  560. if (wm->ctl[num].flags & WM8776_FLAG_STEREO)
  561. cont.info = snd_ctl_boolean_stereo_info;
  562. else
  563. cont.info = snd_ctl_boolean_mono_info;
  564. break;
  565. case SNDRV_CTL_ELEM_TYPE_ENUMERATED:
  566. cont.info = snd_wm8776_enum_info;
  567. break;
  568. default:
  569. return -EINVAL;
  570. }
  571. ctl = snd_ctl_new1(&cont, wm);
  572. if (!ctl)
  573. return -ENOMEM;
  574. return snd_ctl_add(wm->card, ctl);
  575. }
  576. int snd_wm8776_build_controls(struct snd_wm8776 *wm)
  577. {
  578. int err, i;
  579. for (i = 0; i < WM8776_CTL_COUNT; i++)
  580. if (wm->ctl[i].name) {
  581. err = snd_wm8776_add_control(wm, i);
  582. if (err < 0)
  583. return err;
  584. }
  585. return 0;
  586. }