nouveau_mem.c 24 KB

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  1. /*
  2. * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
  3. * Copyright 2005 Stephane Marchesin
  4. *
  5. * The Weather Channel (TM) funded Tungsten Graphics to develop the
  6. * initial release of the Radeon 8500 driver under the XFree86 license.
  7. * This notice must be preserved.
  8. *
  9. * Permission is hereby granted, free of charge, to any person obtaining a
  10. * copy of this software and associated documentation files (the "Software"),
  11. * to deal in the Software without restriction, including without limitation
  12. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13. * and/or sell copies of the Software, and to permit persons to whom the
  14. * Software is furnished to do so, subject to the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the next
  17. * paragraph) shall be included in all copies or substantial portions of the
  18. * Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23. * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26. * DEALINGS IN THE SOFTWARE.
  27. *
  28. * Authors:
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. */
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_sarea.h"
  34. #include "nouveau_drv.h"
  35. #include "nouveau_pm.h"
  36. #include "nouveau_mm.h"
  37. #include "nouveau_vm.h"
  38. /*
  39. * NV10-NV40 tiling helpers
  40. */
  41. static void
  42. nv10_mem_update_tile_region(struct drm_device *dev,
  43. struct nouveau_tile_reg *tile, uint32_t addr,
  44. uint32_t size, uint32_t pitch, uint32_t flags)
  45. {
  46. struct drm_nouveau_private *dev_priv = dev->dev_private;
  47. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  48. struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  49. int i = tile - dev_priv->tile.reg, j;
  50. unsigned long save;
  51. nouveau_fence_unref(&tile->fence);
  52. if (tile->pitch)
  53. pfb->free_tile_region(dev, i);
  54. if (pitch)
  55. pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  56. spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  57. pfifo->reassign(dev, false);
  58. pfifo->cache_pull(dev, false);
  59. nouveau_wait_for_idle(dev);
  60. pfb->set_tile_region(dev, i);
  61. for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
  62. if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
  63. dev_priv->eng[j]->set_tile_region(dev, i);
  64. }
  65. pfifo->cache_pull(dev, true);
  66. pfifo->reassign(dev, true);
  67. spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  68. }
  69. static struct nouveau_tile_reg *
  70. nv10_mem_get_tile_region(struct drm_device *dev, int i)
  71. {
  72. struct drm_nouveau_private *dev_priv = dev->dev_private;
  73. struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  74. spin_lock(&dev_priv->tile.lock);
  75. if (!tile->used &&
  76. (!tile->fence || nouveau_fence_signalled(tile->fence)))
  77. tile->used = true;
  78. else
  79. tile = NULL;
  80. spin_unlock(&dev_priv->tile.lock);
  81. return tile;
  82. }
  83. void
  84. nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
  85. struct nouveau_fence *fence)
  86. {
  87. struct drm_nouveau_private *dev_priv = dev->dev_private;
  88. if (tile) {
  89. spin_lock(&dev_priv->tile.lock);
  90. if (fence) {
  91. /* Mark it as pending. */
  92. tile->fence = fence;
  93. nouveau_fence_ref(fence);
  94. }
  95. tile->used = false;
  96. spin_unlock(&dev_priv->tile.lock);
  97. }
  98. }
  99. struct nouveau_tile_reg *
  100. nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
  101. uint32_t pitch, uint32_t flags)
  102. {
  103. struct drm_nouveau_private *dev_priv = dev->dev_private;
  104. struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  105. struct nouveau_tile_reg *tile, *found = NULL;
  106. int i;
  107. for (i = 0; i < pfb->num_tiles; i++) {
  108. tile = nv10_mem_get_tile_region(dev, i);
  109. if (pitch && !found) {
  110. found = tile;
  111. continue;
  112. } else if (tile && tile->pitch) {
  113. /* Kill an unused tile region. */
  114. nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
  115. }
  116. nv10_mem_put_tile_region(dev, tile, NULL);
  117. }
  118. if (found)
  119. nv10_mem_update_tile_region(dev, found, addr, size,
  120. pitch, flags);
  121. return found;
  122. }
  123. /*
  124. * Cleanup everything
  125. */
  126. void
  127. nouveau_mem_vram_fini(struct drm_device *dev)
  128. {
  129. struct drm_nouveau_private *dev_priv = dev->dev_private;
  130. ttm_bo_device_release(&dev_priv->ttm.bdev);
  131. nouveau_ttm_global_release(dev_priv);
  132. if (dev_priv->fb_mtrr >= 0) {
  133. drm_mtrr_del(dev_priv->fb_mtrr,
  134. pci_resource_start(dev->pdev, 1),
  135. pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
  136. dev_priv->fb_mtrr = -1;
  137. }
  138. }
  139. void
  140. nouveau_mem_gart_fini(struct drm_device *dev)
  141. {
  142. nouveau_sgdma_takedown(dev);
  143. if (drm_core_has_AGP(dev) && dev->agp) {
  144. struct drm_agp_mem *entry, *tempe;
  145. /* Remove AGP resources, but leave dev->agp
  146. intact until drv_cleanup is called. */
  147. list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
  148. if (entry->bound)
  149. drm_unbind_agp(entry->memory);
  150. drm_free_agp(entry->memory, entry->pages);
  151. kfree(entry);
  152. }
  153. INIT_LIST_HEAD(&dev->agp->memory);
  154. if (dev->agp->acquired)
  155. drm_agp_release(dev);
  156. dev->agp->acquired = 0;
  157. dev->agp->enabled = 0;
  158. }
  159. }
  160. bool
  161. nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
  162. {
  163. if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
  164. return true;
  165. return false;
  166. }
  167. #if __OS_HAS_AGP
  168. static unsigned long
  169. get_agp_mode(struct drm_device *dev, unsigned long mode)
  170. {
  171. struct drm_nouveau_private *dev_priv = dev->dev_private;
  172. /*
  173. * FW seems to be broken on nv18, it makes the card lock up
  174. * randomly.
  175. */
  176. if (dev_priv->chipset == 0x18)
  177. mode &= ~PCI_AGP_COMMAND_FW;
  178. /*
  179. * AGP mode set in the command line.
  180. */
  181. if (nouveau_agpmode > 0) {
  182. bool agpv3 = mode & 0x8;
  183. int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
  184. mode = (mode & ~0x7) | (rate & 0x7);
  185. }
  186. return mode;
  187. }
  188. #endif
  189. int
  190. nouveau_mem_reset_agp(struct drm_device *dev)
  191. {
  192. #if __OS_HAS_AGP
  193. uint32_t saved_pci_nv_1, pmc_enable;
  194. int ret;
  195. /* First of all, disable fast writes, otherwise if it's
  196. * already enabled in the AGP bridge and we disable the card's
  197. * AGP controller we might be locking ourselves out of it. */
  198. if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
  199. dev->agp->mode) & PCI_AGP_COMMAND_FW) {
  200. struct drm_agp_info info;
  201. struct drm_agp_mode mode;
  202. ret = drm_agp_info(dev, &info);
  203. if (ret)
  204. return ret;
  205. mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
  206. ret = drm_agp_enable(dev, mode);
  207. if (ret)
  208. return ret;
  209. }
  210. saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
  211. /* clear busmaster bit */
  212. nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
  213. /* disable AGP */
  214. nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
  215. /* power cycle pgraph, if enabled */
  216. pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
  217. if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
  218. nv_wr32(dev, NV03_PMC_ENABLE,
  219. pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
  220. nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
  221. NV_PMC_ENABLE_PGRAPH);
  222. }
  223. /* and restore (gives effect of resetting AGP) */
  224. nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
  225. #endif
  226. return 0;
  227. }
  228. int
  229. nouveau_mem_init_agp(struct drm_device *dev)
  230. {
  231. #if __OS_HAS_AGP
  232. struct drm_nouveau_private *dev_priv = dev->dev_private;
  233. struct drm_agp_info info;
  234. struct drm_agp_mode mode;
  235. int ret;
  236. if (!dev->agp->acquired) {
  237. ret = drm_agp_acquire(dev);
  238. if (ret) {
  239. NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
  240. return ret;
  241. }
  242. }
  243. nouveau_mem_reset_agp(dev);
  244. ret = drm_agp_info(dev, &info);
  245. if (ret) {
  246. NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
  247. return ret;
  248. }
  249. /* see agp.h for the AGPSTAT_* modes available */
  250. mode.mode = get_agp_mode(dev, info.mode);
  251. ret = drm_agp_enable(dev, mode);
  252. if (ret) {
  253. NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
  254. return ret;
  255. }
  256. dev_priv->gart_info.type = NOUVEAU_GART_AGP;
  257. dev_priv->gart_info.aper_base = info.aperture_base;
  258. dev_priv->gart_info.aper_size = info.aperture_size;
  259. #endif
  260. return 0;
  261. }
  262. static const struct vram_types {
  263. int value;
  264. const char *name;
  265. } vram_type_map[] = {
  266. { NV_MEM_TYPE_STOLEN , "stolen system memory" },
  267. { NV_MEM_TYPE_SGRAM , "SGRAM" },
  268. { NV_MEM_TYPE_SDRAM , "SDRAM" },
  269. { NV_MEM_TYPE_DDR1 , "DDR1" },
  270. { NV_MEM_TYPE_DDR2 , "DDR2" },
  271. { NV_MEM_TYPE_DDR3 , "DDR3" },
  272. { NV_MEM_TYPE_GDDR2 , "GDDR2" },
  273. { NV_MEM_TYPE_GDDR3 , "GDDR3" },
  274. { NV_MEM_TYPE_GDDR4 , "GDDR4" },
  275. { NV_MEM_TYPE_GDDR5 , "GDDR5" },
  276. { NV_MEM_TYPE_UNKNOWN, "unknown type" }
  277. };
  278. int
  279. nouveau_mem_vram_init(struct drm_device *dev)
  280. {
  281. struct drm_nouveau_private *dev_priv = dev->dev_private;
  282. struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
  283. const struct vram_types *vram_type;
  284. int ret, dma_bits;
  285. dma_bits = 32;
  286. if (dev_priv->card_type >= NV_50) {
  287. if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
  288. dma_bits = 40;
  289. } else
  290. if (0 && pci_is_pcie(dev->pdev) &&
  291. dev_priv->chipset > 0x40 &&
  292. dev_priv->chipset != 0x45) {
  293. if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
  294. dma_bits = 39;
  295. }
  296. ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
  297. if (ret)
  298. return ret;
  299. ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
  300. if (ret) {
  301. /* Reset to default value. */
  302. pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
  303. }
  304. ret = nouveau_ttm_global_init(dev_priv);
  305. if (ret)
  306. return ret;
  307. ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
  308. dev_priv->ttm.bo_global_ref.ref.object,
  309. &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
  310. dma_bits <= 32 ? true : false);
  311. if (ret) {
  312. NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
  313. return ret;
  314. }
  315. vram_type = vram_type_map;
  316. while (vram_type->value != NV_MEM_TYPE_UNKNOWN) {
  317. if (nouveau_vram_type) {
  318. if (!strcasecmp(nouveau_vram_type, vram_type->name))
  319. break;
  320. dev_priv->vram_type = vram_type->value;
  321. } else {
  322. if (vram_type->value == dev_priv->vram_type)
  323. break;
  324. }
  325. vram_type++;
  326. }
  327. NV_INFO(dev, "Detected %dMiB VRAM (%s)\n",
  328. (int)(dev_priv->vram_size >> 20), vram_type->name);
  329. if (dev_priv->vram_sys_base) {
  330. NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
  331. dev_priv->vram_sys_base);
  332. }
  333. dev_priv->fb_available_size = dev_priv->vram_size;
  334. dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
  335. if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
  336. dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
  337. dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
  338. dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
  339. dev_priv->fb_aper_free = dev_priv->fb_available_size;
  340. /* mappable vram */
  341. ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
  342. dev_priv->fb_available_size >> PAGE_SHIFT);
  343. if (ret) {
  344. NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
  345. return ret;
  346. }
  347. if (dev_priv->card_type < NV_50) {
  348. ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
  349. 0, 0, &dev_priv->vga_ram);
  350. if (ret == 0)
  351. ret = nouveau_bo_pin(dev_priv->vga_ram,
  352. TTM_PL_FLAG_VRAM);
  353. if (ret) {
  354. NV_WARN(dev, "failed to reserve VGA memory\n");
  355. nouveau_bo_ref(NULL, &dev_priv->vga_ram);
  356. }
  357. }
  358. dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
  359. pci_resource_len(dev->pdev, 1),
  360. DRM_MTRR_WC);
  361. return 0;
  362. }
  363. int
  364. nouveau_mem_gart_init(struct drm_device *dev)
  365. {
  366. struct drm_nouveau_private *dev_priv = dev->dev_private;
  367. struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
  368. int ret;
  369. dev_priv->gart_info.type = NOUVEAU_GART_NONE;
  370. #if !defined(__powerpc__) && !defined(__ia64__)
  371. if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
  372. ret = nouveau_mem_init_agp(dev);
  373. if (ret)
  374. NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
  375. }
  376. #endif
  377. if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
  378. ret = nouveau_sgdma_init(dev);
  379. if (ret) {
  380. NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
  381. return ret;
  382. }
  383. }
  384. NV_INFO(dev, "%d MiB GART (aperture)\n",
  385. (int)(dev_priv->gart_info.aper_size >> 20));
  386. dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
  387. ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
  388. dev_priv->gart_info.aper_size >> PAGE_SHIFT);
  389. if (ret) {
  390. NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
  391. return ret;
  392. }
  393. return 0;
  394. }
  395. /* XXX: For now a dummy. More samples required, possibly even a card
  396. * Called from nouveau_perf.c */
  397. void nv30_mem_timing_entry(struct drm_device *dev,
  398. struct nouveau_pm_tbl_header *hdr,
  399. struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
  400. struct nouveau_pm_memtiming *timing)
  401. {
  402. NV_DEBUG(dev, "Timing entry format unknown, "
  403. "please contact nouveau developers");
  404. }
  405. void nv40_mem_timing_entry(struct drm_device *dev,
  406. struct nouveau_pm_tbl_header *hdr,
  407. struct nouveau_pm_tbl_entry *e,
  408. struct nouveau_pm_memtiming *timing)
  409. {
  410. timing->reg_0 = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
  411. /* XXX: I don't trust the -1's and +1's... they must come
  412. * from somewhere! */
  413. timing->reg_1 = (e->tWR + 2 + (timing->tCWL - 1)) << 24 |
  414. 1 << 16 |
  415. (e->tWTR + 2 + (timing->tCWL - 1)) << 8 |
  416. (e->tCL + 2 - (timing->tCWL - 1));
  417. timing->reg_2 = 0x20200000 | ((timing->tCWL - 1) << 24 |
  418. e->tRRD << 16 | e->tRCDWR << 8 | e->tRCDRD);
  419. NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id,
  420. timing->reg_0, timing->reg_1, timing->reg_2);
  421. }
  422. void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P,
  423. struct nouveau_pm_tbl_header *hdr,
  424. struct nouveau_pm_tbl_entry *e,
  425. struct nouveau_pm_memtiming *timing)
  426. {
  427. struct drm_nouveau_private *dev_priv = dev->dev_private;
  428. uint8_t unk18 = 1,
  429. unk20 = 0,
  430. unk21 = 0,
  431. tmp7_3;
  432. switch (min(hdr->entry_len, (u8) 22)) {
  433. case 22:
  434. unk21 = e->tUNK_21;
  435. case 21:
  436. unk20 = e->tUNK_20;
  437. case 20:
  438. if (e->tCWL > 0)
  439. timing->tCWL = e->tCWL;
  440. case 19:
  441. unk18 = e->tUNK_18;
  442. break;
  443. }
  444. timing->reg_0 = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
  445. timing->reg_1 = (e->tWR + 2 + (timing->tCWL - 1)) << 24 |
  446. max(unk18, (u8) 1) << 16 |
  447. (e->tWTR + 2 + (timing->tCWL - 1)) << 8;
  448. timing->reg_2 = ((timing->tCWL - 1) << 24 | e->tRRD << 16 |
  449. e->tRCDWR << 8 | e->tRCDRD);
  450. timing->reg_4 = e->tUNK_13 << 8 | e->tUNK_13;
  451. timing->reg_5 = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 |
  452. e->tRP);
  453. timing->reg_8 = (nv_rd32(dev, 0x100240) & 0xffffff00);
  454. if (P->version == 1) {
  455. timing->reg_1 |= (e->tCL + 2 - (timing->tCWL - 1));
  456. timing->reg_3 = (0x14 + e->tCL) << 24 |
  457. 0x16 << 16 |
  458. (e->tCL - 1) << 8 |
  459. (e->tCL - 1);
  460. timing->reg_4 |= (nv_rd32(dev, 0x100230) & 0xffff0000);
  461. timing->reg_6 = (0x33 - timing->tCWL) << 16 |
  462. timing->tCWL << 8 |
  463. (0x2E + e->tCL - timing->tCWL);
  464. timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16;
  465. /* XXX: P.version == 1 only has DDR2 and GDDR3? */
  466. if (dev_priv->vram_type == NV_MEM_TYPE_DDR2) {
  467. timing->reg_5 |= (e->tCL + 3) << 8;
  468. timing->reg_6 |= (timing->tCWL - 2) << 8;
  469. timing->reg_8 |= (e->tCL - 4);
  470. } else {
  471. timing->reg_5 |= (e->tCL + 2) << 8;
  472. timing->reg_6 |= timing->tCWL << 8;
  473. timing->reg_8 |= (e->tCL - 2);
  474. }
  475. } else {
  476. timing->reg_1 |= (5 + e->tCL - (timing->tCWL));
  477. /* XXX: 0xb? 0x30? */
  478. timing->reg_3 = (0x30 + e->tCL) << 24 |
  479. (nv_rd32(dev, 0x10022c) & 0x00ff0000) |
  480. (0xB + e->tCL) << 8 |
  481. (e->tCL - 1);
  482. timing->reg_4 |= (unk20 << 24 | unk21 << 16);
  483. /* XXX: +6? */
  484. timing->reg_5 |= (timing->tCWL + 6) << 8;
  485. timing->reg_6 = (0x5A + e->tCL) << 16 |
  486. (6 - e->tCL + timing->tCWL) << 8 |
  487. (0x50 + e->tCL - timing->tCWL);
  488. tmp7_3 = (nv_rd32(dev, 0x10023c) & 0xff000000) >> 24;
  489. timing->reg_7 = (tmp7_3 << 24) |
  490. ((tmp7_3 - 6 + e->tCL) << 16) |
  491. 0x202;
  492. }
  493. NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", timing->id,
  494. timing->reg_0, timing->reg_1,
  495. timing->reg_2, timing->reg_3);
  496. NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
  497. timing->reg_4, timing->reg_5,
  498. timing->reg_6, timing->reg_7);
  499. NV_DEBUG(dev, " 240: %08x\n", timing->reg_8);
  500. }
  501. void nvc0_mem_timing_entry(struct drm_device *dev,
  502. struct nouveau_pm_tbl_header *hdr,
  503. struct nouveau_pm_tbl_entry *e,
  504. struct nouveau_pm_memtiming *timing)
  505. {
  506. timing->tCWL = e->tCWL;
  507. timing->reg_0 = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
  508. e->tRFC << 8 | e->tRC);
  509. timing->reg_1 = (nv_rd32(dev, 0x10f294) & 0xff000000) |
  510. (e->tRCDWR & 0x0f) << 20 |
  511. (e->tRCDRD & 0x0f) << 14 |
  512. (e->tCWL << 7) |
  513. (e->tCL & 0x0f);
  514. timing->reg_2 = (nv_rd32(dev, 0x10f298) & 0xff0000ff) |
  515. e->tWR << 16 | e->tWTR << 8;
  516. timing->reg_3 = (e->tUNK_20&0xf) << 9 |
  517. (e->tUNK_21 & 0xf) << 5 |
  518. (e->tUNK_13 & 0x1f);
  519. timing->reg_4 = (nv_rd32(dev, 0x10f2a0) & 0xfff00fff) |
  520. (e->tRRD&0x1f) << 15;
  521. NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id,
  522. timing->reg_0, timing->reg_1,
  523. timing->reg_2, timing->reg_3);
  524. NV_DEBUG(dev, " 2a0: %08x\n",
  525. timing->reg_4);
  526. }
  527. void
  528. nouveau_mem_features_entry(uint8_t p_version, struct nouveau_pm_tbl_header *hdr,
  529. struct nouveau_pm_tbl_entry *e,
  530. struct nouveau_pm_memtiming *timing)
  531. {
  532. if (p_version == 1) {
  533. /* XXX: Todo */
  534. } else if (p_version == 2) {
  535. timing->odt = e->RAM_FT1 & 0x1;
  536. timing->dll_disable = (e->RAM_FT1 & 0x2) >> 1;
  537. timing->ron_pull = (e->RAM_FT1 & 0x4) >> 2;
  538. }
  539. }
  540. /**
  541. * Processes the Memory Timing BIOS table, stores generated
  542. * register values
  543. * @pre init scripts were run, memtiming regs are initialized
  544. */
  545. void
  546. nouveau_mem_timing_init(struct drm_device *dev)
  547. {
  548. struct drm_nouveau_private *dev_priv = dev->dev_private;
  549. struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
  550. struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
  551. struct nvbios *bios = &dev_priv->vbios;
  552. struct bit_entry P;
  553. struct nouveau_pm_tbl_header *hdr = NULL;
  554. uint8_t tCWL;
  555. u8 *entry;
  556. int i;
  557. if (bios->type == NVBIOS_BIT) {
  558. if (bit_table(dev, 'P', &P))
  559. return;
  560. if (P.version == 1)
  561. hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
  562. P.data[4]);
  563. else if (P.version == 2)
  564. hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
  565. P.data[8]);
  566. else
  567. NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
  568. } else {
  569. NV_DEBUG(dev, "BMP version too old for memory\n");
  570. return;
  571. }
  572. if (!hdr) {
  573. NV_DEBUG(dev, "memory timing table pointer invalid\n");
  574. return;
  575. }
  576. if (hdr->version != 0x10) {
  577. NV_WARN(dev, "memory timing table 0x%02x unknown\n",
  578. hdr->version);
  579. return;
  580. }
  581. /* validate record length */
  582. if (hdr->entry_len < 15) {
  583. NV_ERROR(dev, "mem timing table length unknown: %d\n",
  584. hdr->entry_len);
  585. return;
  586. }
  587. /* parse vbios entries into common format */
  588. memtimings->timing = kcalloc(hdr->entry_cnt,
  589. sizeof(*memtimings->timing), GFP_KERNEL);
  590. if (!memtimings->timing)
  591. return;
  592. /* Get tCWL from the timing reg for NV_40 and NV_50
  593. * Used in calculations later... source unknown */
  594. tCWL = 0;
  595. if (dev_priv->card_type < NV_C0)
  596. tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
  597. entry = (u8 *) hdr + hdr->header_len;
  598. for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
  599. struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
  600. struct nouveau_pm_tbl_entry *entry_struct =
  601. (struct nouveau_pm_tbl_entry *) entry;
  602. if (entry[0] == 0)
  603. continue;
  604. timing->id = i;
  605. timing->WR = entry[0];
  606. timing->CL = entry[2];
  607. timing->tCWL = tCWL;
  608. nouveau_mem_features_entry(P.version, hdr, entry_struct,
  609. &pm->memtimings.timing[i]);
  610. if (dev_priv->card_type <= NV_40) {
  611. nv40_mem_timing_entry(dev, hdr, entry_struct,
  612. &pm->memtimings.timing[i]);
  613. } else if (dev_priv->card_type == NV_50) {
  614. nv50_mem_timing_entry(dev, &P, hdr, entry_struct,
  615. &pm->memtimings.timing[i]);
  616. } else if (dev_priv->card_type == NV_C0) {
  617. nvc0_mem_timing_entry(dev, hdr, entry_struct,
  618. &pm->memtimings.timing[i]);
  619. }
  620. }
  621. memtimings->nr_timing = hdr->entry_cnt;
  622. memtimings->supported = (P.version == 1);
  623. }
  624. void
  625. nouveau_mem_timing_fini(struct drm_device *dev)
  626. {
  627. struct drm_nouveau_private *dev_priv = dev->dev_private;
  628. struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
  629. kfree(mem->timing);
  630. mem->timing = NULL;
  631. }
  632. int
  633. nouveau_mem_vbios_type(struct drm_device *dev)
  634. {
  635. struct bit_entry M;
  636. u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
  637. if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
  638. u8 *table = ROMPTR(dev, M.data[3]);
  639. if (table && table[0] == 0x10 && ramcfg < table[3]) {
  640. u8 *entry = table + table[1] + (ramcfg * table[2]);
  641. switch (entry[0] & 0x0f) {
  642. case 0: return NV_MEM_TYPE_DDR2;
  643. case 1: return NV_MEM_TYPE_DDR3;
  644. case 2: return NV_MEM_TYPE_GDDR3;
  645. case 3: return NV_MEM_TYPE_GDDR5;
  646. default:
  647. break;
  648. }
  649. }
  650. }
  651. return NV_MEM_TYPE_UNKNOWN;
  652. }
  653. static int
  654. nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
  655. {
  656. /* nothing to do */
  657. return 0;
  658. }
  659. static int
  660. nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
  661. {
  662. /* nothing to do */
  663. return 0;
  664. }
  665. static inline void
  666. nouveau_mem_node_cleanup(struct nouveau_mem *node)
  667. {
  668. if (node->vma[0].node) {
  669. nouveau_vm_unmap(&node->vma[0]);
  670. nouveau_vm_put(&node->vma[0]);
  671. }
  672. if (node->vma[1].node) {
  673. nouveau_vm_unmap(&node->vma[1]);
  674. nouveau_vm_put(&node->vma[1]);
  675. }
  676. }
  677. static void
  678. nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
  679. struct ttm_mem_reg *mem)
  680. {
  681. struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
  682. struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
  683. struct drm_device *dev = dev_priv->dev;
  684. nouveau_mem_node_cleanup(mem->mm_node);
  685. vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
  686. }
  687. static int
  688. nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
  689. struct ttm_buffer_object *bo,
  690. struct ttm_placement *placement,
  691. struct ttm_mem_reg *mem)
  692. {
  693. struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
  694. struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
  695. struct drm_device *dev = dev_priv->dev;
  696. struct nouveau_bo *nvbo = nouveau_bo(bo);
  697. struct nouveau_mem *node;
  698. u32 size_nc = 0;
  699. int ret;
  700. if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
  701. size_nc = 1 << nvbo->page_shift;
  702. ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
  703. mem->page_alignment << PAGE_SHIFT, size_nc,
  704. (nvbo->tile_flags >> 8) & 0x3ff, &node);
  705. if (ret) {
  706. mem->mm_node = NULL;
  707. return (ret == -ENOSPC) ? 0 : ret;
  708. }
  709. node->page_shift = nvbo->page_shift;
  710. mem->mm_node = node;
  711. mem->start = node->offset >> PAGE_SHIFT;
  712. return 0;
  713. }
  714. void
  715. nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
  716. {
  717. struct nouveau_mm *mm = man->priv;
  718. struct nouveau_mm_node *r;
  719. u32 total = 0, free = 0;
  720. mutex_lock(&mm->mutex);
  721. list_for_each_entry(r, &mm->nodes, nl_entry) {
  722. printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
  723. prefix, r->type, ((u64)r->offset << 12),
  724. (((u64)r->offset + r->length) << 12));
  725. total += r->length;
  726. if (!r->type)
  727. free += r->length;
  728. }
  729. mutex_unlock(&mm->mutex);
  730. printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
  731. prefix, (u64)total << 12, (u64)free << 12);
  732. printk(KERN_DEBUG "%s block: 0x%08x\n",
  733. prefix, mm->block_size << 12);
  734. }
  735. const struct ttm_mem_type_manager_func nouveau_vram_manager = {
  736. nouveau_vram_manager_init,
  737. nouveau_vram_manager_fini,
  738. nouveau_vram_manager_new,
  739. nouveau_vram_manager_del,
  740. nouveau_vram_manager_debug
  741. };
  742. static int
  743. nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
  744. {
  745. return 0;
  746. }
  747. static int
  748. nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
  749. {
  750. return 0;
  751. }
  752. static void
  753. nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
  754. struct ttm_mem_reg *mem)
  755. {
  756. nouveau_mem_node_cleanup(mem->mm_node);
  757. kfree(mem->mm_node);
  758. mem->mm_node = NULL;
  759. }
  760. static int
  761. nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
  762. struct ttm_buffer_object *bo,
  763. struct ttm_placement *placement,
  764. struct ttm_mem_reg *mem)
  765. {
  766. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  767. struct nouveau_mem *node;
  768. if (unlikely((mem->num_pages << PAGE_SHIFT) >=
  769. dev_priv->gart_info.aper_size))
  770. return -ENOMEM;
  771. node = kzalloc(sizeof(*node), GFP_KERNEL);
  772. if (!node)
  773. return -ENOMEM;
  774. node->page_shift = 12;
  775. mem->mm_node = node;
  776. mem->start = 0;
  777. return 0;
  778. }
  779. void
  780. nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
  781. {
  782. }
  783. const struct ttm_mem_type_manager_func nouveau_gart_manager = {
  784. nouveau_gart_manager_init,
  785. nouveau_gart_manager_fini,
  786. nouveau_gart_manager_new,
  787. nouveau_gart_manager_del,
  788. nouveau_gart_manager_debug
  789. };