ioapic.c 11 KB

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  1. /*
  2. * Copyright (C) 2001 MandrakeSoft S.A.
  3. *
  4. * MandrakeSoft S.A.
  5. * 43, rue d'Aboukir
  6. * 75002 Paris - France
  7. * http://www.linux-mandrake.com/
  8. * http://www.mandrakesoft.com/
  9. *
  10. * This library is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU Lesser General Public
  12. * License as published by the Free Software Foundation; either
  13. * version 2 of the License, or (at your option) any later version.
  14. *
  15. * This library is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * Lesser General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU Lesser General Public
  21. * License along with this library; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * Yunhong Jiang <yunhong.jiang@intel.com>
  25. * Yaozu (Eddie) Dong <eddie.dong@intel.com>
  26. * Based on Xen 3.1 code.
  27. */
  28. #include <linux/kvm_host.h>
  29. #include <linux/kvm.h>
  30. #include <linux/mm.h>
  31. #include <linux/highmem.h>
  32. #include <linux/smp.h>
  33. #include <linux/hrtimer.h>
  34. #include <linux/io.h>
  35. #include <asm/processor.h>
  36. #include <asm/page.h>
  37. #include <asm/current.h>
  38. #include <trace/events/kvm.h>
  39. #include "ioapic.h"
  40. #include "lapic.h"
  41. #include "irq.h"
  42. #if 0
  43. #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  44. #else
  45. #define ioapic_debug(fmt, arg...)
  46. #endif
  47. static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  48. static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  49. unsigned long addr,
  50. unsigned long length)
  51. {
  52. unsigned long result = 0;
  53. switch (ioapic->ioregsel) {
  54. case IOAPIC_REG_VERSION:
  55. result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  56. | (IOAPIC_VERSION_ID & 0xff));
  57. break;
  58. case IOAPIC_REG_APIC_ID:
  59. case IOAPIC_REG_ARB_ID:
  60. result = ((ioapic->id & 0xf) << 24);
  61. break;
  62. default:
  63. {
  64. u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  65. u64 redir_content;
  66. ASSERT(redir_index < IOAPIC_NUM_PINS);
  67. redir_content = ioapic->redirtbl[redir_index].bits;
  68. result = (ioapic->ioregsel & 0x1) ?
  69. (redir_content >> 32) & 0xffffffff :
  70. redir_content & 0xffffffff;
  71. break;
  72. }
  73. }
  74. return result;
  75. }
  76. static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  77. {
  78. union kvm_ioapic_redirect_entry *pent;
  79. int injected = -1;
  80. pent = &ioapic->redirtbl[idx];
  81. if (!pent->fields.mask) {
  82. injected = ioapic_deliver(ioapic, idx);
  83. if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  84. pent->fields.remote_irr = 1;
  85. }
  86. return injected;
  87. }
  88. static void update_handled_vectors(struct kvm_ioapic *ioapic)
  89. {
  90. DECLARE_BITMAP(handled_vectors, 256);
  91. int i;
  92. memset(handled_vectors, 0, sizeof(handled_vectors));
  93. for (i = 0; i < IOAPIC_NUM_PINS; ++i)
  94. __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
  95. memcpy(ioapic->handled_vectors, handled_vectors,
  96. sizeof(handled_vectors));
  97. smp_wmb();
  98. }
  99. static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
  100. {
  101. unsigned index;
  102. bool mask_before, mask_after;
  103. union kvm_ioapic_redirect_entry *e;
  104. switch (ioapic->ioregsel) {
  105. case IOAPIC_REG_VERSION:
  106. /* Writes are ignored. */
  107. break;
  108. case IOAPIC_REG_APIC_ID:
  109. ioapic->id = (val >> 24) & 0xf;
  110. break;
  111. case IOAPIC_REG_ARB_ID:
  112. break;
  113. default:
  114. index = (ioapic->ioregsel - 0x10) >> 1;
  115. ioapic_debug("change redir index %x val %x\n", index, val);
  116. if (index >= IOAPIC_NUM_PINS)
  117. return;
  118. e = &ioapic->redirtbl[index];
  119. mask_before = e->fields.mask;
  120. if (ioapic->ioregsel & 1) {
  121. e->bits &= 0xffffffff;
  122. e->bits |= (u64) val << 32;
  123. } else {
  124. e->bits &= ~0xffffffffULL;
  125. e->bits |= (u32) val;
  126. e->fields.remote_irr = 0;
  127. }
  128. update_handled_vectors(ioapic);
  129. mask_after = e->fields.mask;
  130. if (mask_before != mask_after)
  131. kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
  132. if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
  133. && ioapic->irr & (1 << index))
  134. ioapic_service(ioapic, index);
  135. break;
  136. }
  137. }
  138. static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
  139. {
  140. union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
  141. struct kvm_lapic_irq irqe;
  142. ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
  143. "vector=%x trig_mode=%x\n",
  144. entry->fields.dest, entry->fields.dest_mode,
  145. entry->fields.delivery_mode, entry->fields.vector,
  146. entry->fields.trig_mode);
  147. irqe.dest_id = entry->fields.dest_id;
  148. irqe.vector = entry->fields.vector;
  149. irqe.dest_mode = entry->fields.dest_mode;
  150. irqe.trig_mode = entry->fields.trig_mode;
  151. irqe.delivery_mode = entry->fields.delivery_mode << 8;
  152. irqe.level = 1;
  153. irqe.shorthand = 0;
  154. #ifdef CONFIG_X86
  155. /* Always delivery PIT interrupt to vcpu 0 */
  156. if (irq == 0) {
  157. irqe.dest_mode = 0; /* Physical mode. */
  158. /* need to read apic_id from apic regiest since
  159. * it can be rewritten */
  160. irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
  161. }
  162. #endif
  163. return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
  164. }
  165. int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
  166. {
  167. u32 old_irr = ioapic->irr;
  168. u32 mask = 1 << irq;
  169. union kvm_ioapic_redirect_entry entry;
  170. int ret = 1;
  171. mutex_lock(&ioapic->lock);
  172. if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
  173. entry = ioapic->redirtbl[irq];
  174. level ^= entry.fields.polarity;
  175. if (!level)
  176. ioapic->irr &= ~mask;
  177. else {
  178. int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
  179. ioapic->irr |= mask;
  180. if ((edge && old_irr != ioapic->irr) ||
  181. (!edge && !entry.fields.remote_irr))
  182. ret = ioapic_service(ioapic, irq);
  183. else
  184. ret = 0; /* report coalesced interrupt */
  185. }
  186. trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
  187. }
  188. mutex_unlock(&ioapic->lock);
  189. return ret;
  190. }
  191. static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
  192. int trigger_mode)
  193. {
  194. int i;
  195. for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  196. union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
  197. if (ent->fields.vector != vector)
  198. continue;
  199. /*
  200. * We are dropping lock while calling ack notifiers because ack
  201. * notifier callbacks for assigned devices call into IOAPIC
  202. * recursively. Since remote_irr is cleared only after call
  203. * to notifiers if the same vector will be delivered while lock
  204. * is dropped it will be put into irr and will be delivered
  205. * after ack notifier returns.
  206. */
  207. mutex_unlock(&ioapic->lock);
  208. kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
  209. mutex_lock(&ioapic->lock);
  210. if (trigger_mode != IOAPIC_LEVEL_TRIG)
  211. continue;
  212. ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
  213. ent->fields.remote_irr = 0;
  214. if (!ent->fields.mask && (ioapic->irr & (1 << i)))
  215. ioapic_service(ioapic, i);
  216. }
  217. }
  218. void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
  219. {
  220. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  221. smp_rmb();
  222. if (!test_bit(vector, ioapic->handled_vectors))
  223. return;
  224. mutex_lock(&ioapic->lock);
  225. __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
  226. mutex_unlock(&ioapic->lock);
  227. }
  228. static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
  229. {
  230. return container_of(dev, struct kvm_ioapic, dev);
  231. }
  232. static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
  233. {
  234. return ((addr >= ioapic->base_address &&
  235. (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
  236. }
  237. static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
  238. void *val)
  239. {
  240. struct kvm_ioapic *ioapic = to_ioapic(this);
  241. u32 result;
  242. if (!ioapic_in_range(ioapic, addr))
  243. return -EOPNOTSUPP;
  244. ioapic_debug("addr %lx\n", (unsigned long)addr);
  245. ASSERT(!(addr & 0xf)); /* check alignment */
  246. addr &= 0xff;
  247. mutex_lock(&ioapic->lock);
  248. switch (addr) {
  249. case IOAPIC_REG_SELECT:
  250. result = ioapic->ioregsel;
  251. break;
  252. case IOAPIC_REG_WINDOW:
  253. result = ioapic_read_indirect(ioapic, addr, len);
  254. break;
  255. default:
  256. result = 0;
  257. break;
  258. }
  259. mutex_unlock(&ioapic->lock);
  260. switch (len) {
  261. case 8:
  262. *(u64 *) val = result;
  263. break;
  264. case 1:
  265. case 2:
  266. case 4:
  267. memcpy(val, (char *)&result, len);
  268. break;
  269. default:
  270. printk(KERN_WARNING "ioapic: wrong length %d\n", len);
  271. }
  272. return 0;
  273. }
  274. static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
  275. const void *val)
  276. {
  277. struct kvm_ioapic *ioapic = to_ioapic(this);
  278. u32 data;
  279. if (!ioapic_in_range(ioapic, addr))
  280. return -EOPNOTSUPP;
  281. ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
  282. (void*)addr, len, val);
  283. ASSERT(!(addr & 0xf)); /* check alignment */
  284. if (len == 4 || len == 8)
  285. data = *(u32 *) val;
  286. else {
  287. printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
  288. return 0;
  289. }
  290. addr &= 0xff;
  291. mutex_lock(&ioapic->lock);
  292. switch (addr) {
  293. case IOAPIC_REG_SELECT:
  294. ioapic->ioregsel = data;
  295. break;
  296. case IOAPIC_REG_WINDOW:
  297. ioapic_write_indirect(ioapic, data);
  298. break;
  299. #ifdef CONFIG_IA64
  300. case IOAPIC_REG_EOI:
  301. __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
  302. break;
  303. #endif
  304. default:
  305. break;
  306. }
  307. mutex_unlock(&ioapic->lock);
  308. return 0;
  309. }
  310. void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
  311. {
  312. int i;
  313. for (i = 0; i < IOAPIC_NUM_PINS; i++)
  314. ioapic->redirtbl[i].fields.mask = 1;
  315. ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
  316. ioapic->ioregsel = 0;
  317. ioapic->irr = 0;
  318. ioapic->id = 0;
  319. update_handled_vectors(ioapic);
  320. }
  321. static const struct kvm_io_device_ops ioapic_mmio_ops = {
  322. .read = ioapic_mmio_read,
  323. .write = ioapic_mmio_write,
  324. };
  325. int kvm_ioapic_init(struct kvm *kvm)
  326. {
  327. struct kvm_ioapic *ioapic;
  328. int ret;
  329. ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
  330. if (!ioapic)
  331. return -ENOMEM;
  332. mutex_init(&ioapic->lock);
  333. kvm->arch.vioapic = ioapic;
  334. kvm_ioapic_reset(ioapic);
  335. kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
  336. ioapic->kvm = kvm;
  337. mutex_lock(&kvm->slots_lock);
  338. ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
  339. mutex_unlock(&kvm->slots_lock);
  340. if (ret < 0) {
  341. kvm->arch.vioapic = NULL;
  342. kfree(ioapic);
  343. }
  344. return ret;
  345. }
  346. void kvm_ioapic_destroy(struct kvm *kvm)
  347. {
  348. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  349. if (ioapic) {
  350. kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
  351. kvm->arch.vioapic = NULL;
  352. kfree(ioapic);
  353. }
  354. }
  355. int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
  356. {
  357. struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
  358. if (!ioapic)
  359. return -EINVAL;
  360. mutex_lock(&ioapic->lock);
  361. memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
  362. mutex_unlock(&ioapic->lock);
  363. return 0;
  364. }
  365. int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
  366. {
  367. struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
  368. if (!ioapic)
  369. return -EINVAL;
  370. mutex_lock(&ioapic->lock);
  371. memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
  372. update_handled_vectors(ioapic);
  373. mutex_unlock(&ioapic->lock);
  374. return 0;
  375. }