s3c-ac97.c 13 KB

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  1. /* sound/soc/s3c24xx/s3c-ac97.c
  2. *
  3. * ALSA SoC Audio Layer - S3C AC97 Controller driver
  4. * Evolved from s3c2443-ac97.c
  5. *
  6. * Copyright (c) 2010 Samsung Electronics Co. Ltd
  7. * Author: Jaswinder Singh <jassi.brar@samsung.com>
  8. * Credits: Graeme Gregory, Sean Choi
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/clk.h>
  19. #include <sound/soc.h>
  20. #include <plat/regs-ac97.h>
  21. #include <mach/dma.h>
  22. #include <plat/audio.h>
  23. #include "s3c-dma.h"
  24. #include "s3c-ac97.h"
  25. #define AC_CMD_ADDR(x) (x << 16)
  26. #define AC_CMD_DATA(x) (x & 0xffff)
  27. struct s3c_ac97_info {
  28. unsigned state;
  29. struct clk *ac97_clk;
  30. void __iomem *regs;
  31. struct mutex lock;
  32. struct completion done;
  33. };
  34. static struct s3c_ac97_info s3c_ac97;
  35. static struct s3c2410_dma_client s3c_dma_client_out = {
  36. .name = "AC97 PCMOut"
  37. };
  38. static struct s3c2410_dma_client s3c_dma_client_in = {
  39. .name = "AC97 PCMIn"
  40. };
  41. static struct s3c2410_dma_client s3c_dma_client_micin = {
  42. .name = "AC97 MicIn"
  43. };
  44. static struct s3c_dma_params s3c_ac97_pcm_out = {
  45. .client = &s3c_dma_client_out,
  46. .dma_size = 4,
  47. };
  48. static struct s3c_dma_params s3c_ac97_pcm_in = {
  49. .client = &s3c_dma_client_in,
  50. .dma_size = 4,
  51. };
  52. static struct s3c_dma_params s3c_ac97_mic_in = {
  53. .client = &s3c_dma_client_micin,
  54. .dma_size = 4,
  55. };
  56. static void s3c_ac97_activate(struct snd_ac97 *ac97)
  57. {
  58. u32 ac_glbctrl, stat;
  59. stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
  60. if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
  61. return; /* Return if already active */
  62. INIT_COMPLETION(s3c_ac97.done);
  63. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  64. ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
  65. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  66. msleep(1);
  67. ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
  68. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  69. msleep(1);
  70. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  71. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  72. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  73. if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  74. printk(KERN_ERR "AC97: Unable to activate!");
  75. }
  76. static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
  77. unsigned short reg)
  78. {
  79. u32 ac_glbctrl, ac_codec_cmd;
  80. u32 stat, addr, data;
  81. mutex_lock(&s3c_ac97.lock);
  82. s3c_ac97_activate(ac97);
  83. INIT_COMPLETION(s3c_ac97.done);
  84. ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  85. ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
  86. writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  87. udelay(50);
  88. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  89. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  90. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  91. if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  92. printk(KERN_ERR "AC97: Unable to read!");
  93. stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
  94. addr = (stat >> 16) & 0x7f;
  95. data = (stat & 0xffff);
  96. if (addr != reg)
  97. printk(KERN_ERR "s3c-ac97: req addr = %02x, rep addr = %02x\n", reg, addr);
  98. mutex_unlock(&s3c_ac97.lock);
  99. return (unsigned short)data;
  100. }
  101. static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  102. unsigned short val)
  103. {
  104. u32 ac_glbctrl, ac_codec_cmd;
  105. mutex_lock(&s3c_ac97.lock);
  106. s3c_ac97_activate(ac97);
  107. INIT_COMPLETION(s3c_ac97.done);
  108. ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  109. ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
  110. writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  111. udelay(50);
  112. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  113. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  114. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  115. if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
  116. printk(KERN_ERR "AC97: Unable to write!");
  117. ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  118. ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
  119. writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
  120. mutex_unlock(&s3c_ac97.lock);
  121. }
  122. static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
  123. {
  124. writel(S3C_AC97_GLBCTRL_COLDRESET,
  125. s3c_ac97.regs + S3C_AC97_GLBCTRL);
  126. msleep(1);
  127. writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  128. msleep(1);
  129. }
  130. static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
  131. {
  132. u32 stat;
  133. stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
  134. if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
  135. return; /* Return if already active */
  136. writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  137. msleep(1);
  138. writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  139. msleep(1);
  140. s3c_ac97_activate(ac97);
  141. }
  142. static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
  143. {
  144. u32 ac_glbctrl, ac_glbstat;
  145. ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
  146. if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
  147. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  148. ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
  149. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  150. complete(&s3c_ac97.done);
  151. }
  152. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  153. ac_glbctrl |= (1<<30); /* Clear interrupt */
  154. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  155. return IRQ_HANDLED;
  156. }
  157. struct snd_ac97_bus_ops soc_ac97_ops = {
  158. .read = s3c_ac97_read,
  159. .write = s3c_ac97_write,
  160. .warm_reset = s3c_ac97_warm_reset,
  161. .reset = s3c_ac97_cold_reset,
  162. };
  163. EXPORT_SYMBOL_GPL(soc_ac97_ops);
  164. static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
  165. struct snd_pcm_hw_params *params,
  166. struct snd_soc_dai *dai)
  167. {
  168. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  169. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  170. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  171. cpu_dai->dma_data = &s3c_ac97_pcm_out;
  172. else
  173. cpu_dai->dma_data = &s3c_ac97_pcm_in;
  174. return 0;
  175. }
  176. static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
  177. struct snd_soc_dai *dai)
  178. {
  179. u32 ac_glbctrl;
  180. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  181. int channel = ((struct s3c_dma_params *)
  182. rtd->dai->cpu_dai->dma_data)->channel;
  183. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  184. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  185. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
  186. else
  187. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
  188. switch (cmd) {
  189. case SNDRV_PCM_TRIGGER_START:
  190. case SNDRV_PCM_TRIGGER_RESUME:
  191. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  192. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  193. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
  194. else
  195. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
  196. break;
  197. case SNDRV_PCM_TRIGGER_STOP:
  198. case SNDRV_PCM_TRIGGER_SUSPEND:
  199. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  200. break;
  201. }
  202. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  203. s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
  204. return 0;
  205. }
  206. static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
  207. struct snd_pcm_hw_params *params,
  208. struct snd_soc_dai *dai)
  209. {
  210. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  211. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  212. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  213. return -ENODEV;
  214. else
  215. cpu_dai->dma_data = &s3c_ac97_mic_in;
  216. return 0;
  217. }
  218. static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
  219. int cmd, struct snd_soc_dai *dai)
  220. {
  221. u32 ac_glbctrl;
  222. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  223. int channel = ((struct s3c_dma_params *)
  224. rtd->dai->cpu_dai->dma_data)->channel;
  225. ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
  226. ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
  227. switch (cmd) {
  228. case SNDRV_PCM_TRIGGER_START:
  229. case SNDRV_PCM_TRIGGER_RESUME:
  230. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  231. ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
  232. break;
  233. case SNDRV_PCM_TRIGGER_STOP:
  234. case SNDRV_PCM_TRIGGER_SUSPEND:
  235. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  236. break;
  237. }
  238. writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
  239. s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
  240. return 0;
  241. }
  242. static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
  243. .hw_params = s3c_ac97_hw_params,
  244. .trigger = s3c_ac97_trigger,
  245. };
  246. static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
  247. .hw_params = s3c_ac97_hw_mic_params,
  248. .trigger = s3c_ac97_mic_trigger,
  249. };
  250. struct snd_soc_dai s3c_ac97_dai[] = {
  251. [S3C_AC97_DAI_PCM] = {
  252. .name = "s3c-ac97",
  253. .id = S3C_AC97_DAI_PCM,
  254. .ac97_control = 1,
  255. .playback = {
  256. .stream_name = "AC97 Playback",
  257. .channels_min = 2,
  258. .channels_max = 2,
  259. .rates = SNDRV_PCM_RATE_8000_48000,
  260. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  261. .capture = {
  262. .stream_name = "AC97 Capture",
  263. .channels_min = 2,
  264. .channels_max = 2,
  265. .rates = SNDRV_PCM_RATE_8000_48000,
  266. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  267. .ops = &s3c_ac97_dai_ops,
  268. },
  269. [S3C_AC97_DAI_MIC] = {
  270. .name = "s3c-ac97-mic",
  271. .id = S3C_AC97_DAI_MIC,
  272. .ac97_control = 1,
  273. .capture = {
  274. .stream_name = "AC97 Mic Capture",
  275. .channels_min = 1,
  276. .channels_max = 1,
  277. .rates = SNDRV_PCM_RATE_8000_48000,
  278. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  279. .ops = &s3c_ac97_mic_dai_ops,
  280. },
  281. };
  282. EXPORT_SYMBOL_GPL(s3c_ac97_dai);
  283. static __devinit int s3c_ac97_probe(struct platform_device *pdev)
  284. {
  285. struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
  286. struct s3c_audio_pdata *ac97_pdata;
  287. int ret;
  288. ac97_pdata = pdev->dev.platform_data;
  289. if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
  290. dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
  291. return -EINVAL;
  292. }
  293. /* Check for availability of necessary resource */
  294. dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  295. if (!dmatx_res) {
  296. dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
  297. return -ENXIO;
  298. }
  299. dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  300. if (!dmarx_res) {
  301. dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
  302. return -ENXIO;
  303. }
  304. dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
  305. if (!dmamic_res) {
  306. dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
  307. return -ENXIO;
  308. }
  309. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  310. if (!mem_res) {
  311. dev_err(&pdev->dev, "Unable to get register resource\n");
  312. return -ENXIO;
  313. }
  314. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  315. if (!irq_res) {
  316. dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
  317. return -ENXIO;
  318. }
  319. if (!request_mem_region(mem_res->start,
  320. resource_size(mem_res), "s3c-ac97")) {
  321. dev_err(&pdev->dev, "Unable to request register region\n");
  322. return -EBUSY;
  323. }
  324. s3c_ac97_pcm_out.channel = dmatx_res->start;
  325. s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
  326. s3c_ac97_pcm_in.channel = dmarx_res->start;
  327. s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
  328. s3c_ac97_mic_in.channel = dmamic_res->start;
  329. s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
  330. init_completion(&s3c_ac97.done);
  331. mutex_init(&s3c_ac97.lock);
  332. s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
  333. if (s3c_ac97.regs == NULL) {
  334. dev_err(&pdev->dev, "Unable to ioremap register region\n");
  335. ret = -ENXIO;
  336. goto err1;
  337. }
  338. s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
  339. if (IS_ERR(s3c_ac97.ac97_clk)) {
  340. dev_err(&pdev->dev, "s3c-ac97 failed to get ac97_clock\n");
  341. ret = -ENODEV;
  342. goto err2;
  343. }
  344. clk_enable(s3c_ac97.ac97_clk);
  345. if (ac97_pdata->cfg_gpio(pdev)) {
  346. dev_err(&pdev->dev, "Unable to configure gpio\n");
  347. ret = -EINVAL;
  348. goto err3;
  349. }
  350. ret = request_irq(irq_res->start, s3c_ac97_irq,
  351. IRQF_DISABLED, "AC97", NULL);
  352. if (ret < 0) {
  353. printk(KERN_ERR "s3c-ac97: interrupt request failed.\n");
  354. goto err4;
  355. }
  356. s3c_ac97_dai[S3C_AC97_DAI_PCM].dev = &pdev->dev;
  357. s3c_ac97_dai[S3C_AC97_DAI_MIC].dev = &pdev->dev;
  358. ret = snd_soc_register_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
  359. if (ret)
  360. goto err5;
  361. return 0;
  362. err5:
  363. free_irq(irq_res->start, NULL);
  364. err4:
  365. err3:
  366. clk_disable(s3c_ac97.ac97_clk);
  367. clk_put(s3c_ac97.ac97_clk);
  368. err2:
  369. iounmap(s3c_ac97.regs);
  370. err1:
  371. release_mem_region(mem_res->start, resource_size(mem_res));
  372. return ret;
  373. }
  374. static __devexit int s3c_ac97_remove(struct platform_device *pdev)
  375. {
  376. struct resource *mem_res, *irq_res;
  377. snd_soc_unregister_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
  378. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  379. if (irq_res)
  380. free_irq(irq_res->start, NULL);
  381. clk_disable(s3c_ac97.ac97_clk);
  382. clk_put(s3c_ac97.ac97_clk);
  383. iounmap(s3c_ac97.regs);
  384. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  385. if (mem_res)
  386. release_mem_region(mem_res->start, resource_size(mem_res));
  387. return 0;
  388. }
  389. static struct platform_driver s3c_ac97_driver = {
  390. .probe = s3c_ac97_probe,
  391. .remove = s3c_ac97_remove,
  392. .driver = {
  393. .name = "s3c-ac97",
  394. .owner = THIS_MODULE,
  395. },
  396. };
  397. static int __init s3c_ac97_init(void)
  398. {
  399. return platform_driver_register(&s3c_ac97_driver);
  400. }
  401. module_init(s3c_ac97_init);
  402. static void __exit s3c_ac97_exit(void)
  403. {
  404. platform_driver_unregister(&s3c_ac97_driver);
  405. }
  406. module_exit(s3c_ac97_exit);
  407. MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
  408. MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
  409. MODULE_LICENSE("GPL");