mcpdm.c 13 KB

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  1. /*
  2. * mcpdm.c -- McPDM interface driver
  3. *
  4. * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
  5. * Copyright (C) 2009 - Texas Instruments, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19. * 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/init.h>
  24. #include <linux/device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/wait.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/err.h>
  29. #include <linux/clk.h>
  30. #include <linux/delay.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include "mcpdm.h"
  34. static struct omap_mcpdm *mcpdm;
  35. static inline void omap_mcpdm_write(u16 reg, u32 val)
  36. {
  37. __raw_writel(val, mcpdm->io_base + reg);
  38. }
  39. static inline int omap_mcpdm_read(u16 reg)
  40. {
  41. return __raw_readl(mcpdm->io_base + reg);
  42. }
  43. static void omap_mcpdm_reg_dump(void)
  44. {
  45. dev_dbg(mcpdm->dev, "***********************\n");
  46. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  47. omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
  48. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  49. omap_mcpdm_read(MCPDM_IRQSTATUS));
  50. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  51. omap_mcpdm_read(MCPDM_IRQENABLE_SET));
  52. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  53. omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
  54. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  55. omap_mcpdm_read(MCPDM_IRQWAKE_EN));
  56. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  57. omap_mcpdm_read(MCPDM_DMAENABLE_SET));
  58. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  59. omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
  60. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  61. omap_mcpdm_read(MCPDM_DMAWAKEEN));
  62. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  63. omap_mcpdm_read(MCPDM_CTRL));
  64. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  65. omap_mcpdm_read(MCPDM_DN_DATA));
  66. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  67. omap_mcpdm_read(MCPDM_UP_DATA));
  68. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  69. omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
  70. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  71. omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
  72. dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n",
  73. omap_mcpdm_read(MCPDM_DN_OFFSET));
  74. dev_dbg(mcpdm->dev, "***********************\n");
  75. }
  76. /*
  77. * Takes the McPDM module in and out of reset state.
  78. * Uplink and downlink can be reset individually.
  79. */
  80. static void omap_mcpdm_reset_capture(int reset)
  81. {
  82. int ctrl = omap_mcpdm_read(MCPDM_CTRL);
  83. if (reset)
  84. ctrl |= SW_UP_RST;
  85. else
  86. ctrl &= ~SW_UP_RST;
  87. omap_mcpdm_write(MCPDM_CTRL, ctrl);
  88. }
  89. static void omap_mcpdm_reset_playback(int reset)
  90. {
  91. int ctrl = omap_mcpdm_read(MCPDM_CTRL);
  92. if (reset)
  93. ctrl |= SW_DN_RST;
  94. else
  95. ctrl &= ~SW_DN_RST;
  96. omap_mcpdm_write(MCPDM_CTRL, ctrl);
  97. }
  98. /*
  99. * Enables the transfer through the PDM interface to/from the Phoenix
  100. * codec by enabling the corresponding UP or DN channels.
  101. */
  102. void omap_mcpdm_start(int stream)
  103. {
  104. int ctrl = omap_mcpdm_read(MCPDM_CTRL);
  105. if (stream)
  106. ctrl |= mcpdm->up_channels;
  107. else
  108. ctrl |= mcpdm->dn_channels;
  109. omap_mcpdm_write(MCPDM_CTRL, ctrl);
  110. }
  111. /*
  112. * Disables the transfer through the PDM interface to/from the Phoenix
  113. * codec by disabling the corresponding UP or DN channels.
  114. */
  115. void omap_mcpdm_stop(int stream)
  116. {
  117. int ctrl = omap_mcpdm_read(MCPDM_CTRL);
  118. if (stream)
  119. ctrl &= ~mcpdm->up_channels;
  120. else
  121. ctrl &= ~mcpdm->dn_channels;
  122. omap_mcpdm_write(MCPDM_CTRL, ctrl);
  123. }
  124. /*
  125. * Configures McPDM uplink for audio recording.
  126. * This function should be called before omap_mcpdm_start.
  127. */
  128. int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
  129. {
  130. int irq_mask = 0;
  131. int ctrl;
  132. if (!uplink)
  133. return -EINVAL;
  134. mcpdm->uplink = uplink;
  135. /* Enable irq request generation */
  136. irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
  137. omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
  138. /* Configure uplink threshold */
  139. if (uplink->threshold > UP_THRES_MAX)
  140. uplink->threshold = UP_THRES_MAX;
  141. omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
  142. /* Configure DMA controller */
  143. omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
  144. /* Set pdm out format */
  145. ctrl = omap_mcpdm_read(MCPDM_CTRL);
  146. ctrl &= ~PDMOUTFORMAT;
  147. ctrl |= uplink->format & PDMOUTFORMAT;
  148. /* Uplink channels */
  149. mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
  150. omap_mcpdm_write(MCPDM_CTRL, ctrl);
  151. return 0;
  152. }
  153. /*
  154. * Configures McPDM downlink for audio playback.
  155. * This function should be called before omap_mcpdm_start.
  156. */
  157. int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
  158. {
  159. int irq_mask = 0;
  160. int ctrl;
  161. if (!downlink)
  162. return -EINVAL;
  163. mcpdm->downlink = downlink;
  164. /* Enable irq request generation */
  165. irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
  166. omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
  167. /* Configure uplink threshold */
  168. if (downlink->threshold > DN_THRES_MAX)
  169. downlink->threshold = DN_THRES_MAX;
  170. omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
  171. /* Enable DMA request generation */
  172. omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
  173. /* Set pdm out format */
  174. ctrl = omap_mcpdm_read(MCPDM_CTRL);
  175. ctrl &= ~PDMOUTFORMAT;
  176. ctrl |= downlink->format & PDMOUTFORMAT;
  177. /* Downlink channels */
  178. mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
  179. omap_mcpdm_write(MCPDM_CTRL, ctrl);
  180. return 0;
  181. }
  182. /*
  183. * Cleans McPDM uplink configuration.
  184. * This function should be called when the stream is closed.
  185. */
  186. int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
  187. {
  188. int irq_mask = 0;
  189. if (!uplink)
  190. return -EINVAL;
  191. /* Disable irq request generation */
  192. irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
  193. omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
  194. /* Disable DMA request generation */
  195. omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
  196. /* Clear Downlink channels */
  197. mcpdm->up_channels = 0;
  198. mcpdm->uplink = NULL;
  199. return 0;
  200. }
  201. /*
  202. * Cleans McPDM downlink configuration.
  203. * This function should be called when the stream is closed.
  204. */
  205. int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink)
  206. {
  207. int irq_mask = 0;
  208. if (!downlink)
  209. return -EINVAL;
  210. /* Disable irq request generation */
  211. irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
  212. omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
  213. /* Disable DMA request generation */
  214. omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
  215. /* clear Downlink channels */
  216. mcpdm->dn_channels = 0;
  217. mcpdm->downlink = NULL;
  218. return 0;
  219. }
  220. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  221. {
  222. struct omap_mcpdm *mcpdm_irq = dev_id;
  223. int irq_status;
  224. irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
  225. /* Acknowledge irq event */
  226. omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
  227. if (irq & MCPDM_DN_IRQ_FULL) {
  228. dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
  229. omap_mcpdm_reset_playback(1);
  230. omap_mcpdm_playback_open(mcpdm_irq->downlink);
  231. omap_mcpdm_reset_playback(0);
  232. }
  233. if (irq & MCPDM_DN_IRQ_EMPTY) {
  234. dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
  235. omap_mcpdm_reset_playback(1);
  236. omap_mcpdm_playback_open(mcpdm_irq->downlink);
  237. omap_mcpdm_reset_playback(0);
  238. }
  239. if (irq & MCPDM_DN_IRQ) {
  240. dev_dbg(mcpdm_irq->dev, "DN write request\n");
  241. }
  242. if (irq & MCPDM_UP_IRQ_FULL) {
  243. dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
  244. omap_mcpdm_reset_capture(1);
  245. omap_mcpdm_capture_open(mcpdm_irq->uplink);
  246. omap_mcpdm_reset_capture(0);
  247. }
  248. if (irq & MCPDM_UP_IRQ_EMPTY) {
  249. dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
  250. omap_mcpdm_reset_capture(1);
  251. omap_mcpdm_capture_open(mcpdm_irq->uplink);
  252. omap_mcpdm_reset_capture(0);
  253. }
  254. if (irq & MCPDM_UP_IRQ) {
  255. dev_dbg(mcpdm_irq->dev, "UP write request\n");
  256. }
  257. return IRQ_HANDLED;
  258. }
  259. int omap_mcpdm_request(void)
  260. {
  261. int ret;
  262. clk_enable(mcpdm->clk);
  263. spin_lock(&mcpdm->lock);
  264. if (!mcpdm->free) {
  265. dev_err(mcpdm->dev, "McPDM interface is in use\n");
  266. spin_unlock(&mcpdm->lock);
  267. ret = -EBUSY;
  268. goto err;
  269. }
  270. mcpdm->free = 0;
  271. spin_unlock(&mcpdm->lock);
  272. /* Disable lines while request is ongoing */
  273. omap_mcpdm_write(MCPDM_CTRL, 0x00);
  274. ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
  275. 0, "McPDM", (void *)mcpdm);
  276. if (ret) {
  277. dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
  278. goto err;
  279. }
  280. return 0;
  281. err:
  282. clk_disable(mcpdm->clk);
  283. return ret;
  284. }
  285. void omap_mcpdm_free(void)
  286. {
  287. spin_lock(&mcpdm->lock);
  288. if (mcpdm->free) {
  289. dev_err(mcpdm->dev, "McPDM interface is already free\n");
  290. spin_unlock(&mcpdm->lock);
  291. return;
  292. }
  293. mcpdm->free = 1;
  294. spin_unlock(&mcpdm->lock);
  295. clk_disable(mcpdm->clk);
  296. free_irq(mcpdm->irq, (void *)mcpdm);
  297. }
  298. /* Enable/disable DC offset cancelation for the analog
  299. * headset path (PDM channels 1 and 2).
  300. */
  301. int omap_mcpdm_set_offset(int offset1, int offset2)
  302. {
  303. int offset;
  304. if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
  305. return -EINVAL;
  306. offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
  307. /* offset cancellation for channel 1 */
  308. if (offset1)
  309. offset |= DN_OFST_RX1_EN;
  310. else
  311. offset &= ~DN_OFST_RX1_EN;
  312. /* offset cancellation for channel 2 */
  313. if (offset2)
  314. offset |= DN_OFST_RX2_EN;
  315. else
  316. offset &= ~DN_OFST_RX2_EN;
  317. omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
  318. return 0;
  319. }
  320. static int __devinit omap_mcpdm_probe(struct platform_device *pdev)
  321. {
  322. struct resource *res;
  323. int ret = 0;
  324. mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
  325. if (!mcpdm) {
  326. ret = -ENOMEM;
  327. goto exit;
  328. }
  329. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  330. if (res == NULL) {
  331. dev_err(&pdev->dev, "no resource\n");
  332. goto err_resource;
  333. }
  334. spin_lock_init(&mcpdm->lock);
  335. mcpdm->free = 1;
  336. mcpdm->io_base = ioremap(res->start, resource_size(res));
  337. if (!mcpdm->io_base) {
  338. ret = -ENOMEM;
  339. goto err_resource;
  340. }
  341. mcpdm->irq = platform_get_irq(pdev, 0);
  342. mcpdm->clk = clk_get(&pdev->dev, "pdm_ck");
  343. if (IS_ERR(mcpdm->clk)) {
  344. ret = PTR_ERR(mcpdm->clk);
  345. dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret);
  346. goto err_clk;
  347. }
  348. mcpdm->dev = &pdev->dev;
  349. platform_set_drvdata(pdev, mcpdm);
  350. return 0;
  351. err_clk:
  352. iounmap(mcpdm->io_base);
  353. err_resource:
  354. kfree(mcpdm);
  355. exit:
  356. return ret;
  357. }
  358. static int __devexit omap_mcpdm_remove(struct platform_device *pdev)
  359. {
  360. struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
  361. platform_set_drvdata(pdev, NULL);
  362. clk_put(mcpdm_ptr->clk);
  363. iounmap(mcpdm_ptr->io_base);
  364. mcpdm_ptr->clk = NULL;
  365. mcpdm_ptr->free = 0;
  366. mcpdm_ptr->dev = NULL;
  367. kfree(mcpdm_ptr);
  368. return 0;
  369. }
  370. static struct platform_driver omap_mcpdm_driver = {
  371. .probe = omap_mcpdm_probe,
  372. .remove = __devexit_p(omap_mcpdm_remove),
  373. .driver = {
  374. .name = "omap-mcpdm",
  375. },
  376. };
  377. static struct platform_device *omap_mcpdm_device;
  378. static int __init omap_mcpdm_init(void)
  379. {
  380. return platform_driver_register(&omap_mcpdm_driver);
  381. }
  382. arch_initcall(omap_mcpdm_init);