twl4030.c 69 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x00, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x00, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x00, /* REG_HS_SEL (0x22) */
  76. 0x00, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x06, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. struct snd_soc_codec codec;
  120. unsigned int codec_powered;
  121. unsigned int apll_enabled;
  122. struct snd_pcm_substream *master_substream;
  123. struct snd_pcm_substream *slave_substream;
  124. unsigned int configured;
  125. unsigned int rate;
  126. unsigned int sample_bits;
  127. unsigned int channels;
  128. unsigned int sysclk;
  129. /* Headset output state handling */
  130. unsigned int hsl_enabled;
  131. unsigned int hsr_enabled;
  132. };
  133. /*
  134. * read twl4030 register cache
  135. */
  136. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  137. unsigned int reg)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return -EIO;
  142. return cache[reg];
  143. }
  144. /*
  145. * write twl4030 register cache
  146. */
  147. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  148. u8 reg, u8 value)
  149. {
  150. u8 *cache = codec->reg_cache;
  151. if (reg >= TWL4030_CACHEREGNUM)
  152. return;
  153. cache[reg] = value;
  154. }
  155. /*
  156. * write to the twl4030 register space
  157. */
  158. static int twl4030_write(struct snd_soc_codec *codec,
  159. unsigned int reg, unsigned int value)
  160. {
  161. twl4030_write_reg_cache(codec, reg, value);
  162. if (likely(reg < TWL4030_REG_SW_SHADOW))
  163. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  164. reg);
  165. else
  166. return 0;
  167. }
  168. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  169. {
  170. struct twl4030_priv *twl4030 = codec->private_data;
  171. int mode;
  172. if (enable == twl4030->codec_powered)
  173. return;
  174. if (enable)
  175. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  176. else
  177. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  178. if (mode >= 0) {
  179. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  180. twl4030->codec_powered = enable;
  181. }
  182. /* REVISIT: this delay is present in TI sample drivers */
  183. /* but there seems to be no TRM requirement for it */
  184. udelay(10);
  185. }
  186. static void twl4030_init_chip(struct snd_soc_codec *codec)
  187. {
  188. u8 *cache = codec->reg_cache;
  189. int i;
  190. /* clear CODECPDZ prior to setting register defaults */
  191. twl4030_codec_enable(codec, 0);
  192. /* set all audio section registers to reasonable defaults */
  193. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  194. if (i != TWL4030_REG_APLL_CTL)
  195. twl4030_write(codec, i, cache[i]);
  196. }
  197. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  198. {
  199. struct twl4030_priv *twl4030 = codec->private_data;
  200. int status;
  201. if (enable == twl4030->apll_enabled)
  202. return;
  203. if (enable)
  204. /* Enable PLL */
  205. status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
  206. else
  207. /* Disable PLL */
  208. status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
  209. if (status >= 0)
  210. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  211. twl4030->apll_enabled = enable;
  212. }
  213. static void twl4030_power_up(struct snd_soc_codec *codec)
  214. {
  215. struct twl4030_priv *twl4030 = codec->private_data;
  216. u8 anamicl, regmisc1, byte;
  217. int i = 0;
  218. if (twl4030->codec_powered)
  219. return;
  220. /* set CODECPDZ to turn on codec */
  221. twl4030_codec_enable(codec, 1);
  222. /* initiate offset cancellation */
  223. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  224. twl4030_write(codec, TWL4030_REG_ANAMICL,
  225. anamicl | TWL4030_CNCL_OFFSET_START);
  226. /* wait for offset cancellation to complete */
  227. do {
  228. /* this takes a little while, so don't slam i2c */
  229. udelay(2000);
  230. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  231. TWL4030_REG_ANAMICL);
  232. } while ((i++ < 100) &&
  233. ((byte & TWL4030_CNCL_OFFSET_START) ==
  234. TWL4030_CNCL_OFFSET_START));
  235. /* Make sure that the reg_cache has the same value as the HW */
  236. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  237. /* anti-pop when changing analog gain */
  238. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  239. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  240. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  241. /* toggle CODECPDZ as per TRM */
  242. twl4030_codec_enable(codec, 0);
  243. twl4030_codec_enable(codec, 1);
  244. }
  245. /*
  246. * Unconditional power down
  247. */
  248. static void twl4030_power_down(struct snd_soc_codec *codec)
  249. {
  250. /* power down */
  251. twl4030_codec_enable(codec, 0);
  252. }
  253. /* Earpiece */
  254. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  255. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  256. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  257. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  258. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  259. };
  260. /* PreDrive Left */
  261. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  262. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  263. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  264. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  265. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  266. };
  267. /* PreDrive Right */
  268. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  269. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  270. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  271. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  272. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  273. };
  274. /* Headset Left */
  275. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  276. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  277. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  278. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  279. };
  280. /* Headset Right */
  281. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  282. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  283. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  284. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  285. };
  286. /* Carkit Left */
  287. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  288. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  289. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  290. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  291. };
  292. /* Carkit Right */
  293. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  294. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  295. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  296. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  297. };
  298. /* Handsfree Left */
  299. static const char *twl4030_handsfreel_texts[] =
  300. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  301. static const struct soc_enum twl4030_handsfreel_enum =
  302. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  303. ARRAY_SIZE(twl4030_handsfreel_texts),
  304. twl4030_handsfreel_texts);
  305. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  306. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  307. /* Handsfree Left virtual mute */
  308. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  309. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  310. /* Handsfree Right */
  311. static const char *twl4030_handsfreer_texts[] =
  312. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  313. static const struct soc_enum twl4030_handsfreer_enum =
  314. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  315. ARRAY_SIZE(twl4030_handsfreer_texts),
  316. twl4030_handsfreer_texts);
  317. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  318. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  319. /* Handsfree Right virtual mute */
  320. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  321. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  322. /* Vibra */
  323. /* Vibra audio path selection */
  324. static const char *twl4030_vibra_texts[] =
  325. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  326. static const struct soc_enum twl4030_vibra_enum =
  327. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  328. ARRAY_SIZE(twl4030_vibra_texts),
  329. twl4030_vibra_texts);
  330. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  331. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  332. /* Vibra path selection: local vibrator (PWM) or audio driven */
  333. static const char *twl4030_vibrapath_texts[] =
  334. {"Local vibrator", "Audio"};
  335. static const struct soc_enum twl4030_vibrapath_enum =
  336. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  337. ARRAY_SIZE(twl4030_vibrapath_texts),
  338. twl4030_vibrapath_texts);
  339. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  340. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  341. /* Left analog microphone selection */
  342. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  343. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  344. TWL4030_REG_ANAMICL, 0, 1, 0),
  345. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  346. TWL4030_REG_ANAMICL, 1, 1, 0),
  347. SOC_DAPM_SINGLE("AUXL Capture Switch",
  348. TWL4030_REG_ANAMICL, 2, 1, 0),
  349. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  350. TWL4030_REG_ANAMICL, 3, 1, 0),
  351. };
  352. /* Right analog microphone selection */
  353. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  354. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  355. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  356. };
  357. /* TX1 L/R Analog/Digital microphone selection */
  358. static const char *twl4030_micpathtx1_texts[] =
  359. {"Analog", "Digimic0"};
  360. static const struct soc_enum twl4030_micpathtx1_enum =
  361. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  362. ARRAY_SIZE(twl4030_micpathtx1_texts),
  363. twl4030_micpathtx1_texts);
  364. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  365. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  366. /* TX2 L/R Analog/Digital microphone selection */
  367. static const char *twl4030_micpathtx2_texts[] =
  368. {"Analog", "Digimic1"};
  369. static const struct soc_enum twl4030_micpathtx2_enum =
  370. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  371. ARRAY_SIZE(twl4030_micpathtx2_texts),
  372. twl4030_micpathtx2_texts);
  373. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  374. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  375. /* Analog bypass for AudioR1 */
  376. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  377. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  378. /* Analog bypass for AudioL1 */
  379. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  380. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  381. /* Analog bypass for AudioR2 */
  382. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  383. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  384. /* Analog bypass for AudioL2 */
  385. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  386. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  387. /* Analog bypass for Voice */
  388. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  389. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  390. /* Digital bypass gain, 0 mutes the bypass */
  391. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  392. TLV_DB_RANGE_HEAD(2),
  393. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  394. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  395. };
  396. /* Digital bypass left (TX1L -> RX2L) */
  397. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  398. SOC_DAPM_SINGLE_TLV("Volume",
  399. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  400. twl4030_dapm_dbypass_tlv);
  401. /* Digital bypass right (TX1R -> RX2R) */
  402. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  403. SOC_DAPM_SINGLE_TLV("Volume",
  404. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  405. twl4030_dapm_dbypass_tlv);
  406. /*
  407. * Voice Sidetone GAIN volume control:
  408. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  409. */
  410. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  411. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  412. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  413. SOC_DAPM_SINGLE_TLV("Volume",
  414. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  415. twl4030_dapm_dbypassv_tlv);
  416. static int micpath_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol, int event)
  418. {
  419. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  420. unsigned char adcmicsel, micbias_ctl;
  421. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  422. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  423. /* Prepare the bits for the given TX path:
  424. * shift_l == 0: TX1 microphone path
  425. * shift_l == 2: TX2 microphone path */
  426. if (e->shift_l) {
  427. /* TX2 microphone path */
  428. if (adcmicsel & TWL4030_TX2IN_SEL)
  429. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  430. else
  431. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  432. } else {
  433. /* TX1 microphone path */
  434. if (adcmicsel & TWL4030_TX1IN_SEL)
  435. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  436. else
  437. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  438. }
  439. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  440. return 0;
  441. }
  442. /*
  443. * Output PGA builder:
  444. * Handle the muting and unmuting of the given output (turning off the
  445. * amplifier associated with the output pin)
  446. * On mute bypass the reg_cache and mute the volume
  447. * On unmute: restore the register content
  448. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  449. */
  450. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  451. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  452. struct snd_kcontrol *kcontrol, int event) \
  453. { \
  454. u8 reg_val; \
  455. \
  456. switch (event) { \
  457. case SND_SOC_DAPM_POST_PMU: \
  458. twl4030_write(w->codec, reg, \
  459. twl4030_read_reg_cache(w->codec, reg)); \
  460. break; \
  461. case SND_SOC_DAPM_POST_PMD: \
  462. reg_val = twl4030_read_reg_cache(w->codec, reg); \
  463. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  464. reg_val & (~mask), \
  465. reg); \
  466. break; \
  467. } \
  468. return 0; \
  469. }
  470. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  471. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  472. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  473. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  474. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  475. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  476. {
  477. unsigned char hs_ctl;
  478. hs_ctl = twl4030_read_reg_cache(codec, reg);
  479. if (ramp) {
  480. /* HF ramp-up */
  481. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  482. twl4030_write(codec, reg, hs_ctl);
  483. udelay(10);
  484. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  485. twl4030_write(codec, reg, hs_ctl);
  486. udelay(40);
  487. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  488. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  489. twl4030_write(codec, reg, hs_ctl);
  490. } else {
  491. /* HF ramp-down */
  492. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  493. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  494. twl4030_write(codec, reg, hs_ctl);
  495. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  496. twl4030_write(codec, reg, hs_ctl);
  497. udelay(40);
  498. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  499. twl4030_write(codec, reg, hs_ctl);
  500. }
  501. }
  502. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  503. struct snd_kcontrol *kcontrol, int event)
  504. {
  505. switch (event) {
  506. case SND_SOC_DAPM_POST_PMU:
  507. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  508. break;
  509. case SND_SOC_DAPM_POST_PMD:
  510. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  511. break;
  512. }
  513. return 0;
  514. }
  515. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  516. struct snd_kcontrol *kcontrol, int event)
  517. {
  518. switch (event) {
  519. case SND_SOC_DAPM_POST_PMU:
  520. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  521. break;
  522. case SND_SOC_DAPM_POST_PMD:
  523. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  524. break;
  525. }
  526. return 0;
  527. }
  528. static int vibramux_event(struct snd_soc_dapm_widget *w,
  529. struct snd_kcontrol *kcontrol, int event)
  530. {
  531. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  532. return 0;
  533. }
  534. static int apll_event(struct snd_soc_dapm_widget *w,
  535. struct snd_kcontrol *kcontrol, int event)
  536. {
  537. switch (event) {
  538. case SND_SOC_DAPM_PRE_PMU:
  539. twl4030_apll_enable(w->codec, 1);
  540. break;
  541. case SND_SOC_DAPM_POST_PMD:
  542. twl4030_apll_enable(w->codec, 0);
  543. break;
  544. }
  545. return 0;
  546. }
  547. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  548. {
  549. struct snd_soc_device *socdev = codec->socdev;
  550. struct twl4030_setup_data *setup = socdev->codec_data;
  551. unsigned char hs_gain, hs_pop;
  552. struct twl4030_priv *twl4030 = codec->private_data;
  553. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  554. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  555. 8388608, 16777216, 33554432, 67108864};
  556. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  557. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  558. /* Enable external mute control, this dramatically reduces
  559. * the pop-noise */
  560. if (setup && setup->hs_extmute) {
  561. if (setup->set_hs_extmute) {
  562. setup->set_hs_extmute(1);
  563. } else {
  564. hs_pop |= TWL4030_EXTMUTE;
  565. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  566. }
  567. }
  568. if (ramp) {
  569. /* Headset ramp-up according to the TRM */
  570. hs_pop |= TWL4030_VMID_EN;
  571. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  572. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  573. hs_pop |= TWL4030_RAMP_EN;
  574. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  575. /* Wait ramp delay time + 1, so the VMID can settle */
  576. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  577. twl4030->sysclk) + 1);
  578. } else {
  579. /* Headset ramp-down _not_ according to
  580. * the TRM, but in a way that it is working */
  581. hs_pop &= ~TWL4030_RAMP_EN;
  582. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  583. /* Wait ramp delay time + 1, so the VMID can settle */
  584. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  585. twl4030->sysclk) + 1);
  586. /* Bypass the reg_cache to mute the headset */
  587. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  588. hs_gain & (~0x0f),
  589. TWL4030_REG_HS_GAIN_SET);
  590. hs_pop &= ~TWL4030_VMID_EN;
  591. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  592. }
  593. /* Disable external mute */
  594. if (setup && setup->hs_extmute) {
  595. if (setup->set_hs_extmute) {
  596. setup->set_hs_extmute(0);
  597. } else {
  598. hs_pop &= ~TWL4030_EXTMUTE;
  599. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  600. }
  601. }
  602. }
  603. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  604. struct snd_kcontrol *kcontrol, int event)
  605. {
  606. struct twl4030_priv *twl4030 = w->codec->private_data;
  607. switch (event) {
  608. case SND_SOC_DAPM_POST_PMU:
  609. /* Do the ramp-up only once */
  610. if (!twl4030->hsr_enabled)
  611. headset_ramp(w->codec, 1);
  612. twl4030->hsl_enabled = 1;
  613. break;
  614. case SND_SOC_DAPM_POST_PMD:
  615. /* Do the ramp-down only if both headsetL/R is disabled */
  616. if (!twl4030->hsr_enabled)
  617. headset_ramp(w->codec, 0);
  618. twl4030->hsl_enabled = 0;
  619. break;
  620. }
  621. return 0;
  622. }
  623. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  624. struct snd_kcontrol *kcontrol, int event)
  625. {
  626. struct twl4030_priv *twl4030 = w->codec->private_data;
  627. switch (event) {
  628. case SND_SOC_DAPM_POST_PMU:
  629. /* Do the ramp-up only once */
  630. if (!twl4030->hsl_enabled)
  631. headset_ramp(w->codec, 1);
  632. twl4030->hsr_enabled = 1;
  633. break;
  634. case SND_SOC_DAPM_POST_PMD:
  635. /* Do the ramp-down only if both headsetL/R is disabled */
  636. if (!twl4030->hsl_enabled)
  637. headset_ramp(w->codec, 0);
  638. twl4030->hsr_enabled = 0;
  639. break;
  640. }
  641. return 0;
  642. }
  643. /*
  644. * Some of the gain controls in TWL (mostly those which are associated with
  645. * the outputs) are implemented in an interesting way:
  646. * 0x0 : Power down (mute)
  647. * 0x1 : 6dB
  648. * 0x2 : 0 dB
  649. * 0x3 : -6 dB
  650. * Inverting not going to help with these.
  651. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  652. */
  653. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  654. xinvert, tlv_array) \
  655. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  656. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  657. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  658. .tlv.p = (tlv_array), \
  659. .info = snd_soc_info_volsw, \
  660. .get = snd_soc_get_volsw_twl4030, \
  661. .put = snd_soc_put_volsw_twl4030, \
  662. .private_value = (unsigned long)&(struct soc_mixer_control) \
  663. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  664. .max = xmax, .invert = xinvert} }
  665. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  666. xinvert, tlv_array) \
  667. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  668. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  669. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  670. .tlv.p = (tlv_array), \
  671. .info = snd_soc_info_volsw_2r, \
  672. .get = snd_soc_get_volsw_r2_twl4030,\
  673. .put = snd_soc_put_volsw_r2_twl4030, \
  674. .private_value = (unsigned long)&(struct soc_mixer_control) \
  675. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  676. .rshift = xshift, .max = xmax, .invert = xinvert} }
  677. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  678. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  679. xinvert, tlv_array)
  680. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  681. struct snd_ctl_elem_value *ucontrol)
  682. {
  683. struct soc_mixer_control *mc =
  684. (struct soc_mixer_control *)kcontrol->private_value;
  685. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  686. unsigned int reg = mc->reg;
  687. unsigned int shift = mc->shift;
  688. unsigned int rshift = mc->rshift;
  689. int max = mc->max;
  690. int mask = (1 << fls(max)) - 1;
  691. ucontrol->value.integer.value[0] =
  692. (snd_soc_read(codec, reg) >> shift) & mask;
  693. if (ucontrol->value.integer.value[0])
  694. ucontrol->value.integer.value[0] =
  695. max + 1 - ucontrol->value.integer.value[0];
  696. if (shift != rshift) {
  697. ucontrol->value.integer.value[1] =
  698. (snd_soc_read(codec, reg) >> rshift) & mask;
  699. if (ucontrol->value.integer.value[1])
  700. ucontrol->value.integer.value[1] =
  701. max + 1 - ucontrol->value.integer.value[1];
  702. }
  703. return 0;
  704. }
  705. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  706. struct snd_ctl_elem_value *ucontrol)
  707. {
  708. struct soc_mixer_control *mc =
  709. (struct soc_mixer_control *)kcontrol->private_value;
  710. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  711. unsigned int reg = mc->reg;
  712. unsigned int shift = mc->shift;
  713. unsigned int rshift = mc->rshift;
  714. int max = mc->max;
  715. int mask = (1 << fls(max)) - 1;
  716. unsigned short val, val2, val_mask;
  717. val = (ucontrol->value.integer.value[0] & mask);
  718. val_mask = mask << shift;
  719. if (val)
  720. val = max + 1 - val;
  721. val = val << shift;
  722. if (shift != rshift) {
  723. val2 = (ucontrol->value.integer.value[1] & mask);
  724. val_mask |= mask << rshift;
  725. if (val2)
  726. val2 = max + 1 - val2;
  727. val |= val2 << rshift;
  728. }
  729. return snd_soc_update_bits(codec, reg, val_mask, val);
  730. }
  731. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  732. struct snd_ctl_elem_value *ucontrol)
  733. {
  734. struct soc_mixer_control *mc =
  735. (struct soc_mixer_control *)kcontrol->private_value;
  736. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  737. unsigned int reg = mc->reg;
  738. unsigned int reg2 = mc->rreg;
  739. unsigned int shift = mc->shift;
  740. int max = mc->max;
  741. int mask = (1<<fls(max))-1;
  742. ucontrol->value.integer.value[0] =
  743. (snd_soc_read(codec, reg) >> shift) & mask;
  744. ucontrol->value.integer.value[1] =
  745. (snd_soc_read(codec, reg2) >> shift) & mask;
  746. if (ucontrol->value.integer.value[0])
  747. ucontrol->value.integer.value[0] =
  748. max + 1 - ucontrol->value.integer.value[0];
  749. if (ucontrol->value.integer.value[1])
  750. ucontrol->value.integer.value[1] =
  751. max + 1 - ucontrol->value.integer.value[1];
  752. return 0;
  753. }
  754. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  755. struct snd_ctl_elem_value *ucontrol)
  756. {
  757. struct soc_mixer_control *mc =
  758. (struct soc_mixer_control *)kcontrol->private_value;
  759. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  760. unsigned int reg = mc->reg;
  761. unsigned int reg2 = mc->rreg;
  762. unsigned int shift = mc->shift;
  763. int max = mc->max;
  764. int mask = (1 << fls(max)) - 1;
  765. int err;
  766. unsigned short val, val2, val_mask;
  767. val_mask = mask << shift;
  768. val = (ucontrol->value.integer.value[0] & mask);
  769. val2 = (ucontrol->value.integer.value[1] & mask);
  770. if (val)
  771. val = max + 1 - val;
  772. if (val2)
  773. val2 = max + 1 - val2;
  774. val = val << shift;
  775. val2 = val2 << shift;
  776. err = snd_soc_update_bits(codec, reg, val_mask, val);
  777. if (err < 0)
  778. return err;
  779. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  780. return err;
  781. }
  782. /* Codec operation modes */
  783. static const char *twl4030_op_modes_texts[] = {
  784. "Option 2 (voice/audio)", "Option 1 (audio)"
  785. };
  786. static const struct soc_enum twl4030_op_modes_enum =
  787. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  788. ARRAY_SIZE(twl4030_op_modes_texts),
  789. twl4030_op_modes_texts);
  790. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  791. struct snd_ctl_elem_value *ucontrol)
  792. {
  793. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  794. struct twl4030_priv *twl4030 = codec->private_data;
  795. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  796. unsigned short val;
  797. unsigned short mask, bitmask;
  798. if (twl4030->configured) {
  799. printk(KERN_ERR "twl4030 operation mode cannot be "
  800. "changed on-the-fly\n");
  801. return -EBUSY;
  802. }
  803. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  804. ;
  805. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  806. return -EINVAL;
  807. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  808. mask = (bitmask - 1) << e->shift_l;
  809. if (e->shift_l != e->shift_r) {
  810. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  811. return -EINVAL;
  812. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  813. mask |= (bitmask - 1) << e->shift_r;
  814. }
  815. return snd_soc_update_bits(codec, e->reg, mask, val);
  816. }
  817. /*
  818. * FGAIN volume control:
  819. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  820. */
  821. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  822. /*
  823. * CGAIN volume control:
  824. * 0 dB to 12 dB in 6 dB steps
  825. * value 2 and 3 means 12 dB
  826. */
  827. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  828. /*
  829. * Voice Downlink GAIN volume control:
  830. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  831. */
  832. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  833. /*
  834. * Analog playback gain
  835. * -24 dB to 12 dB in 2 dB steps
  836. */
  837. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  838. /*
  839. * Gain controls tied to outputs
  840. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  841. */
  842. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  843. /*
  844. * Gain control for earpiece amplifier
  845. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  846. */
  847. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  848. /*
  849. * Capture gain after the ADCs
  850. * from 0 dB to 31 dB in 1 dB steps
  851. */
  852. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  853. /*
  854. * Gain control for input amplifiers
  855. * 0 dB to 30 dB in 6 dB steps
  856. */
  857. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  858. /* AVADC clock priority */
  859. static const char *twl4030_avadc_clk_priority_texts[] = {
  860. "Voice high priority", "HiFi high priority"
  861. };
  862. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  863. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  864. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  865. twl4030_avadc_clk_priority_texts);
  866. static const char *twl4030_rampdelay_texts[] = {
  867. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  868. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  869. "3495/2581/1748 ms"
  870. };
  871. static const struct soc_enum twl4030_rampdelay_enum =
  872. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  873. ARRAY_SIZE(twl4030_rampdelay_texts),
  874. twl4030_rampdelay_texts);
  875. /* Vibra H-bridge direction mode */
  876. static const char *twl4030_vibradirmode_texts[] = {
  877. "Vibra H-bridge direction", "Audio data MSB",
  878. };
  879. static const struct soc_enum twl4030_vibradirmode_enum =
  880. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  881. ARRAY_SIZE(twl4030_vibradirmode_texts),
  882. twl4030_vibradirmode_texts);
  883. /* Vibra H-bridge direction */
  884. static const char *twl4030_vibradir_texts[] = {
  885. "Positive polarity", "Negative polarity",
  886. };
  887. static const struct soc_enum twl4030_vibradir_enum =
  888. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  889. ARRAY_SIZE(twl4030_vibradir_texts),
  890. twl4030_vibradir_texts);
  891. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  892. /* Codec operation mode control */
  893. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  894. snd_soc_get_enum_double,
  895. snd_soc_put_twl4030_opmode_enum_double),
  896. /* Common playback gain controls */
  897. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  898. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  899. 0, 0x3f, 0, digital_fine_tlv),
  900. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  901. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  902. 0, 0x3f, 0, digital_fine_tlv),
  903. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  904. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  905. 6, 0x2, 0, digital_coarse_tlv),
  906. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  907. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  908. 6, 0x2, 0, digital_coarse_tlv),
  909. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  910. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  911. 3, 0x12, 1, analog_tlv),
  912. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  913. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  914. 3, 0x12, 1, analog_tlv),
  915. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  916. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  917. 1, 1, 0),
  918. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  919. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  920. 1, 1, 0),
  921. /* Common voice downlink gain controls */
  922. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  923. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  924. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  925. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  926. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  927. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  928. /* Separate output gain controls */
  929. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  930. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  931. 4, 3, 0, output_tvl),
  932. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  933. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  934. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  935. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  936. 4, 3, 0, output_tvl),
  937. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  938. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  939. /* Common capture gain controls */
  940. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  941. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  942. 0, 0x1f, 0, digital_capture_tlv),
  943. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  944. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  945. 0, 0x1f, 0, digital_capture_tlv),
  946. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  947. 0, 3, 5, 0, input_gain_tlv),
  948. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  949. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  950. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  951. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  952. };
  953. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  954. /* Left channel inputs */
  955. SND_SOC_DAPM_INPUT("MAINMIC"),
  956. SND_SOC_DAPM_INPUT("HSMIC"),
  957. SND_SOC_DAPM_INPUT("AUXL"),
  958. SND_SOC_DAPM_INPUT("CARKITMIC"),
  959. /* Right channel inputs */
  960. SND_SOC_DAPM_INPUT("SUBMIC"),
  961. SND_SOC_DAPM_INPUT("AUXR"),
  962. /* Digital microphones (Stereo) */
  963. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  964. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  965. /* Outputs */
  966. SND_SOC_DAPM_OUTPUT("OUTL"),
  967. SND_SOC_DAPM_OUTPUT("OUTR"),
  968. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  969. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  970. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  971. SND_SOC_DAPM_OUTPUT("HSOL"),
  972. SND_SOC_DAPM_OUTPUT("HSOR"),
  973. SND_SOC_DAPM_OUTPUT("CARKITL"),
  974. SND_SOC_DAPM_OUTPUT("CARKITR"),
  975. SND_SOC_DAPM_OUTPUT("HFL"),
  976. SND_SOC_DAPM_OUTPUT("HFR"),
  977. SND_SOC_DAPM_OUTPUT("VIBRA"),
  978. /* DACs */
  979. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  980. SND_SOC_NOPM, 0, 0),
  981. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  982. SND_SOC_NOPM, 0, 0),
  983. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  984. SND_SOC_NOPM, 0, 0),
  985. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  986. SND_SOC_NOPM, 0, 0),
  987. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  988. SND_SOC_NOPM, 0, 0),
  989. /* Analog bypasses */
  990. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  991. &twl4030_dapm_abypassr1_control),
  992. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  993. &twl4030_dapm_abypassl1_control),
  994. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  995. &twl4030_dapm_abypassr2_control),
  996. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  997. &twl4030_dapm_abypassl2_control),
  998. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  999. &twl4030_dapm_abypassv_control),
  1000. /* Master analog loopback switch */
  1001. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1002. NULL, 0),
  1003. /* Digital bypasses */
  1004. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1005. &twl4030_dapm_dbypassl_control),
  1006. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1007. &twl4030_dapm_dbypassr_control),
  1008. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1009. &twl4030_dapm_dbypassv_control),
  1010. /* Digital mixers, power control for the physical DACs */
  1011. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1012. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1013. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1014. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1015. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1016. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1017. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1018. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1019. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1020. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1021. /* Analog mixers, power control for the physical PGAs */
  1022. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1023. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1024. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1025. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1026. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1027. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1028. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1029. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1030. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1031. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1032. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1033. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1034. SND_SOC_DAPM_SUPPLY("AIF Enable", TWL4030_REG_AUDIO_IF, 0, 0, NULL, 0),
  1035. /* Output MIXER controls */
  1036. /* Earpiece */
  1037. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1038. &twl4030_dapm_earpiece_controls[0],
  1039. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1040. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1041. 0, 0, NULL, 0, earpiecepga_event,
  1042. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1043. /* PreDrivL/R */
  1044. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1045. &twl4030_dapm_predrivel_controls[0],
  1046. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1047. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1048. 0, 0, NULL, 0, predrivelpga_event,
  1049. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1050. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1051. &twl4030_dapm_predriver_controls[0],
  1052. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1053. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1054. 0, 0, NULL, 0, predriverpga_event,
  1055. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1056. /* HeadsetL/R */
  1057. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1058. &twl4030_dapm_hsol_controls[0],
  1059. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1060. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1061. 0, 0, NULL, 0, headsetlpga_event,
  1062. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1063. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1064. &twl4030_dapm_hsor_controls[0],
  1065. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1066. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1067. 0, 0, NULL, 0, headsetrpga_event,
  1068. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1069. /* CarkitL/R */
  1070. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1071. &twl4030_dapm_carkitl_controls[0],
  1072. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1073. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1074. 0, 0, NULL, 0, carkitlpga_event,
  1075. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1076. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1077. &twl4030_dapm_carkitr_controls[0],
  1078. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1079. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1080. 0, 0, NULL, 0, carkitrpga_event,
  1081. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1082. /* Output MUX controls */
  1083. /* HandsfreeL/R */
  1084. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1085. &twl4030_dapm_handsfreel_control),
  1086. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1087. &twl4030_dapm_handsfreelmute_control),
  1088. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1089. 0, 0, NULL, 0, handsfreelpga_event,
  1090. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1091. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1092. &twl4030_dapm_handsfreer_control),
  1093. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1094. &twl4030_dapm_handsfreermute_control),
  1095. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1096. 0, 0, NULL, 0, handsfreerpga_event,
  1097. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1098. /* Vibra */
  1099. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1100. &twl4030_dapm_vibra_control, vibramux_event,
  1101. SND_SOC_DAPM_PRE_PMU),
  1102. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_vibrapath_control),
  1104. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1105. capture */
  1106. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1107. SND_SOC_NOPM, 0, 0),
  1108. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1109. SND_SOC_NOPM, 0, 0),
  1110. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1111. SND_SOC_NOPM, 0, 0),
  1112. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1113. SND_SOC_NOPM, 0, 0),
  1114. /* Analog/Digital mic path selection.
  1115. TX1 Left/Right: either analog Left/Right or Digimic0
  1116. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1117. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1118. &twl4030_dapm_micpathtx1_control, micpath_event,
  1119. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1120. SND_SOC_DAPM_POST_REG),
  1121. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1122. &twl4030_dapm_micpathtx2_control, micpath_event,
  1123. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1124. SND_SOC_DAPM_POST_REG),
  1125. /* Analog input mixers for the capture amplifiers */
  1126. SND_SOC_DAPM_MIXER("Analog Left",
  1127. TWL4030_REG_ANAMICL, 4, 0,
  1128. &twl4030_dapm_analoglmic_controls[0],
  1129. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1130. SND_SOC_DAPM_MIXER("Analog Right",
  1131. TWL4030_REG_ANAMICR, 4, 0,
  1132. &twl4030_dapm_analogrmic_controls[0],
  1133. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1134. SND_SOC_DAPM_PGA("ADC Physical Left",
  1135. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1136. SND_SOC_DAPM_PGA("ADC Physical Right",
  1137. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1138. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1139. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1140. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1141. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1142. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1143. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1144. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1145. };
  1146. static const struct snd_soc_dapm_route intercon[] = {
  1147. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1148. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1149. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1150. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1151. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1152. /* Supply for the digital part (APLL) */
  1153. {"Digital R1 Playback Mixer", NULL, "APLL Enable"},
  1154. {"Digital L1 Playback Mixer", NULL, "APLL Enable"},
  1155. {"Digital R2 Playback Mixer", NULL, "APLL Enable"},
  1156. {"Digital L2 Playback Mixer", NULL, "APLL Enable"},
  1157. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1158. {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
  1159. {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
  1160. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1161. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1162. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1163. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1164. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1165. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1166. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1167. /* Internal playback routings */
  1168. /* Earpiece */
  1169. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1170. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1171. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1172. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1173. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1174. /* PreDrivL */
  1175. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1176. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1177. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1178. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1179. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1180. /* PreDrivR */
  1181. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1182. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1183. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1184. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1185. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1186. /* HeadsetL */
  1187. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1188. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1189. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1190. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1191. /* HeadsetR */
  1192. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1193. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1194. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1195. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1196. /* CarkitL */
  1197. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1198. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1199. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1200. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1201. /* CarkitR */
  1202. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1203. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1204. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1205. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1206. /* HandsfreeL */
  1207. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1208. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1209. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1210. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1211. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1212. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1213. /* HandsfreeR */
  1214. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1215. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1216. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1217. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1218. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1219. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1220. /* Vibra */
  1221. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1222. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1223. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1224. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1225. /* outputs */
  1226. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1227. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1228. {"EARPIECE", NULL, "Earpiece PGA"},
  1229. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1230. {"PREDRIVER", NULL, "PredriveR PGA"},
  1231. {"HSOL", NULL, "HeadsetL PGA"},
  1232. {"HSOR", NULL, "HeadsetR PGA"},
  1233. {"CARKITL", NULL, "CarkitL PGA"},
  1234. {"CARKITR", NULL, "CarkitR PGA"},
  1235. {"HFL", NULL, "HandsfreeL PGA"},
  1236. {"HFR", NULL, "HandsfreeR PGA"},
  1237. {"Vibra Route", "Audio", "Vibra Mux"},
  1238. {"VIBRA", NULL, "Vibra Route"},
  1239. /* Capture path */
  1240. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1241. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1242. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1243. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1244. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1245. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1246. {"ADC Physical Left", NULL, "Analog Left"},
  1247. {"ADC Physical Right", NULL, "Analog Right"},
  1248. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1249. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1250. /* TX1 Left capture path */
  1251. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1252. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1253. /* TX1 Right capture path */
  1254. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1255. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1256. /* TX2 Left capture path */
  1257. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1258. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1259. /* TX2 Right capture path */
  1260. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1261. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1262. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1263. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1264. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1265. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1266. {"ADC Virtual Left1", NULL, "APLL Enable"},
  1267. {"ADC Virtual Right1", NULL, "APLL Enable"},
  1268. {"ADC Virtual Left2", NULL, "APLL Enable"},
  1269. {"ADC Virtual Right2", NULL, "APLL Enable"},
  1270. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1271. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1272. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1273. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1274. /* Analog bypass routes */
  1275. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1276. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1277. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1278. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1279. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1280. /* Supply for the Analog loopbacks */
  1281. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1282. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1283. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1284. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1285. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1286. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1287. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1288. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1289. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1290. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1291. /* Digital bypass routes */
  1292. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1293. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1294. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1295. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1296. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1297. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1298. };
  1299. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1300. {
  1301. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1302. ARRAY_SIZE(twl4030_dapm_widgets));
  1303. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1304. return 0;
  1305. }
  1306. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1307. enum snd_soc_bias_level level)
  1308. {
  1309. switch (level) {
  1310. case SND_SOC_BIAS_ON:
  1311. break;
  1312. case SND_SOC_BIAS_PREPARE:
  1313. break;
  1314. case SND_SOC_BIAS_STANDBY:
  1315. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1316. twl4030_power_up(codec);
  1317. break;
  1318. case SND_SOC_BIAS_OFF:
  1319. twl4030_power_down(codec);
  1320. break;
  1321. }
  1322. codec->bias_level = level;
  1323. return 0;
  1324. }
  1325. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1326. struct snd_pcm_substream *mst_substream)
  1327. {
  1328. struct snd_pcm_substream *slv_substream;
  1329. /* Pick the stream, which need to be constrained */
  1330. if (mst_substream == twl4030->master_substream)
  1331. slv_substream = twl4030->slave_substream;
  1332. else if (mst_substream == twl4030->slave_substream)
  1333. slv_substream = twl4030->master_substream;
  1334. else /* This should not happen.. */
  1335. return;
  1336. /* Set the constraints according to the already configured stream */
  1337. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1338. SNDRV_PCM_HW_PARAM_RATE,
  1339. twl4030->rate,
  1340. twl4030->rate);
  1341. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1342. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1343. twl4030->sample_bits,
  1344. twl4030->sample_bits);
  1345. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1346. SNDRV_PCM_HW_PARAM_CHANNELS,
  1347. twl4030->channels,
  1348. twl4030->channels);
  1349. }
  1350. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1351. * capture has to be enabled/disabled. */
  1352. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1353. int enable)
  1354. {
  1355. u8 reg, mask;
  1356. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1357. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1358. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1359. else
  1360. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1361. if (enable)
  1362. reg |= mask;
  1363. else
  1364. reg &= ~mask;
  1365. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1366. }
  1367. static int twl4030_startup(struct snd_pcm_substream *substream,
  1368. struct snd_soc_dai *dai)
  1369. {
  1370. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1371. struct snd_soc_device *socdev = rtd->socdev;
  1372. struct snd_soc_codec *codec = socdev->card->codec;
  1373. struct twl4030_priv *twl4030 = codec->private_data;
  1374. if (twl4030->master_substream) {
  1375. twl4030->slave_substream = substream;
  1376. /* The DAI has one configuration for playback and capture, so
  1377. * if the DAI has been already configured then constrain this
  1378. * substream to match it. */
  1379. if (twl4030->configured)
  1380. twl4030_constraints(twl4030, twl4030->master_substream);
  1381. } else {
  1382. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1383. TWL4030_OPTION_1)) {
  1384. /* In option2 4 channel is not supported, set the
  1385. * constraint for the first stream for channels, the
  1386. * second stream will 'inherit' this cosntraint */
  1387. snd_pcm_hw_constraint_minmax(substream->runtime,
  1388. SNDRV_PCM_HW_PARAM_CHANNELS,
  1389. 2, 2);
  1390. }
  1391. twl4030->master_substream = substream;
  1392. }
  1393. return 0;
  1394. }
  1395. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1396. struct snd_soc_dai *dai)
  1397. {
  1398. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1399. struct snd_soc_device *socdev = rtd->socdev;
  1400. struct snd_soc_codec *codec = socdev->card->codec;
  1401. struct twl4030_priv *twl4030 = codec->private_data;
  1402. if (twl4030->master_substream == substream)
  1403. twl4030->master_substream = twl4030->slave_substream;
  1404. twl4030->slave_substream = NULL;
  1405. /* If all streams are closed, or the remaining stream has not yet
  1406. * been configured than set the DAI as not configured. */
  1407. if (!twl4030->master_substream)
  1408. twl4030->configured = 0;
  1409. else if (!twl4030->master_substream->runtime->channels)
  1410. twl4030->configured = 0;
  1411. /* If the closing substream had 4 channel, do the necessary cleanup */
  1412. if (substream->runtime->channels == 4)
  1413. twl4030_tdm_enable(codec, substream->stream, 0);
  1414. }
  1415. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1416. struct snd_pcm_hw_params *params,
  1417. struct snd_soc_dai *dai)
  1418. {
  1419. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1420. struct snd_soc_device *socdev = rtd->socdev;
  1421. struct snd_soc_codec *codec = socdev->card->codec;
  1422. struct twl4030_priv *twl4030 = codec->private_data;
  1423. u8 mode, old_mode, format, old_format;
  1424. /* If the substream has 4 channel, do the necessary setup */
  1425. if (params_channels(params) == 4) {
  1426. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1427. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1428. /* Safety check: are we in the correct operating mode and
  1429. * the interface is in TDM mode? */
  1430. if ((mode & TWL4030_OPTION_1) &&
  1431. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1432. twl4030_tdm_enable(codec, substream->stream, 1);
  1433. else
  1434. return -EINVAL;
  1435. }
  1436. if (twl4030->configured)
  1437. /* Ignoring hw_params for already configured DAI */
  1438. return 0;
  1439. /* bit rate */
  1440. old_mode = twl4030_read_reg_cache(codec,
  1441. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1442. mode = old_mode & ~TWL4030_APLL_RATE;
  1443. switch (params_rate(params)) {
  1444. case 8000:
  1445. mode |= TWL4030_APLL_RATE_8000;
  1446. break;
  1447. case 11025:
  1448. mode |= TWL4030_APLL_RATE_11025;
  1449. break;
  1450. case 12000:
  1451. mode |= TWL4030_APLL_RATE_12000;
  1452. break;
  1453. case 16000:
  1454. mode |= TWL4030_APLL_RATE_16000;
  1455. break;
  1456. case 22050:
  1457. mode |= TWL4030_APLL_RATE_22050;
  1458. break;
  1459. case 24000:
  1460. mode |= TWL4030_APLL_RATE_24000;
  1461. break;
  1462. case 32000:
  1463. mode |= TWL4030_APLL_RATE_32000;
  1464. break;
  1465. case 44100:
  1466. mode |= TWL4030_APLL_RATE_44100;
  1467. break;
  1468. case 48000:
  1469. mode |= TWL4030_APLL_RATE_48000;
  1470. break;
  1471. case 96000:
  1472. mode |= TWL4030_APLL_RATE_96000;
  1473. break;
  1474. default:
  1475. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1476. params_rate(params));
  1477. return -EINVAL;
  1478. }
  1479. if (mode != old_mode) {
  1480. /* change rate and set CODECPDZ */
  1481. twl4030_codec_enable(codec, 0);
  1482. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1483. twl4030_codec_enable(codec, 1);
  1484. }
  1485. /* sample size */
  1486. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1487. format = old_format;
  1488. format &= ~TWL4030_DATA_WIDTH;
  1489. switch (params_format(params)) {
  1490. case SNDRV_PCM_FORMAT_S16_LE:
  1491. format |= TWL4030_DATA_WIDTH_16S_16W;
  1492. break;
  1493. case SNDRV_PCM_FORMAT_S24_LE:
  1494. format |= TWL4030_DATA_WIDTH_32S_24W;
  1495. break;
  1496. default:
  1497. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1498. params_format(params));
  1499. return -EINVAL;
  1500. }
  1501. if (format != old_format) {
  1502. /* clear CODECPDZ before changing format (codec requirement) */
  1503. twl4030_codec_enable(codec, 0);
  1504. /* change format */
  1505. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1506. /* set CODECPDZ afterwards */
  1507. twl4030_codec_enable(codec, 1);
  1508. }
  1509. /* Store the important parameters for the DAI configuration and set
  1510. * the DAI as configured */
  1511. twl4030->configured = 1;
  1512. twl4030->rate = params_rate(params);
  1513. twl4030->sample_bits = hw_param_interval(params,
  1514. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1515. twl4030->channels = params_channels(params);
  1516. /* If both playback and capture streams are open, and one of them
  1517. * is setting the hw parameters right now (since we are here), set
  1518. * constraints to the other stream to match the current one. */
  1519. if (twl4030->slave_substream)
  1520. twl4030_constraints(twl4030, substream);
  1521. return 0;
  1522. }
  1523. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1524. int clk_id, unsigned int freq, int dir)
  1525. {
  1526. struct snd_soc_codec *codec = codec_dai->codec;
  1527. struct twl4030_priv *twl4030 = codec->private_data;
  1528. switch (freq) {
  1529. case 19200000:
  1530. case 26000000:
  1531. case 38400000:
  1532. break;
  1533. default:
  1534. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1535. return -EINVAL;
  1536. }
  1537. if ((freq / 1000) != twl4030->sysclk) {
  1538. dev_err(codec->dev,
  1539. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1540. freq, twl4030->sysclk * 1000);
  1541. return -EINVAL;
  1542. }
  1543. return 0;
  1544. }
  1545. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1546. unsigned int fmt)
  1547. {
  1548. struct snd_soc_codec *codec = codec_dai->codec;
  1549. u8 old_format, format;
  1550. /* get format */
  1551. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1552. format = old_format;
  1553. /* set master/slave audio interface */
  1554. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1555. case SND_SOC_DAIFMT_CBM_CFM:
  1556. format &= ~(TWL4030_AIF_SLAVE_EN);
  1557. format &= ~(TWL4030_CLK256FS_EN);
  1558. break;
  1559. case SND_SOC_DAIFMT_CBS_CFS:
  1560. format |= TWL4030_AIF_SLAVE_EN;
  1561. format |= TWL4030_CLK256FS_EN;
  1562. break;
  1563. default:
  1564. return -EINVAL;
  1565. }
  1566. /* interface format */
  1567. format &= ~TWL4030_AIF_FORMAT;
  1568. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1569. case SND_SOC_DAIFMT_I2S:
  1570. format |= TWL4030_AIF_FORMAT_CODEC;
  1571. break;
  1572. case SND_SOC_DAIFMT_DSP_A:
  1573. format |= TWL4030_AIF_FORMAT_TDM;
  1574. break;
  1575. default:
  1576. return -EINVAL;
  1577. }
  1578. if (format != old_format) {
  1579. /* clear CODECPDZ before changing format (codec requirement) */
  1580. twl4030_codec_enable(codec, 0);
  1581. /* change format */
  1582. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1583. /* set CODECPDZ afterwards */
  1584. twl4030_codec_enable(codec, 1);
  1585. }
  1586. return 0;
  1587. }
  1588. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1589. {
  1590. struct snd_soc_codec *codec = dai->codec;
  1591. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1592. if (tristate)
  1593. reg |= TWL4030_AIF_TRI_EN;
  1594. else
  1595. reg &= ~TWL4030_AIF_TRI_EN;
  1596. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1597. }
  1598. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1599. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1600. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1601. int enable)
  1602. {
  1603. u8 reg, mask;
  1604. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1605. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1606. mask = TWL4030_ARXL1_VRX_EN;
  1607. else
  1608. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1609. if (enable)
  1610. reg |= mask;
  1611. else
  1612. reg &= ~mask;
  1613. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1614. }
  1615. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1616. struct snd_soc_dai *dai)
  1617. {
  1618. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1619. struct snd_soc_device *socdev = rtd->socdev;
  1620. struct snd_soc_codec *codec = socdev->card->codec;
  1621. struct twl4030_priv *twl4030 = codec->private_data;
  1622. u8 mode;
  1623. /* If the system master clock is not 26MHz, the voice PCM interface is
  1624. * not avilable.
  1625. */
  1626. if (twl4030->sysclk != 26000) {
  1627. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1628. "the Voice interface needs 26MHz APLL mclk\n",
  1629. twl4030->sysclk * 1000);
  1630. return -EINVAL;
  1631. }
  1632. /* If the codec mode is not option2, the voice PCM interface is not
  1633. * avilable.
  1634. */
  1635. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1636. & TWL4030_OPT_MODE;
  1637. if (mode != TWL4030_OPTION_2) {
  1638. printk(KERN_ERR "TWL4030 voice startup: "
  1639. "the codec mode is not option2\n");
  1640. return -EINVAL;
  1641. }
  1642. return 0;
  1643. }
  1644. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1645. struct snd_soc_dai *dai)
  1646. {
  1647. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1648. struct snd_soc_device *socdev = rtd->socdev;
  1649. struct snd_soc_codec *codec = socdev->card->codec;
  1650. /* Enable voice digital filters */
  1651. twl4030_voice_enable(codec, substream->stream, 0);
  1652. }
  1653. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1654. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1655. {
  1656. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1657. struct snd_soc_device *socdev = rtd->socdev;
  1658. struct snd_soc_codec *codec = socdev->card->codec;
  1659. u8 old_mode, mode;
  1660. /* Enable voice digital filters */
  1661. twl4030_voice_enable(codec, substream->stream, 1);
  1662. /* bit rate */
  1663. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1664. & ~(TWL4030_CODECPDZ);
  1665. mode = old_mode;
  1666. switch (params_rate(params)) {
  1667. case 8000:
  1668. mode &= ~(TWL4030_SEL_16K);
  1669. break;
  1670. case 16000:
  1671. mode |= TWL4030_SEL_16K;
  1672. break;
  1673. default:
  1674. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1675. params_rate(params));
  1676. return -EINVAL;
  1677. }
  1678. if (mode != old_mode) {
  1679. /* change rate and set CODECPDZ */
  1680. twl4030_codec_enable(codec, 0);
  1681. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1682. twl4030_codec_enable(codec, 1);
  1683. }
  1684. return 0;
  1685. }
  1686. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1687. int clk_id, unsigned int freq, int dir)
  1688. {
  1689. struct snd_soc_codec *codec = codec_dai->codec;
  1690. struct twl4030_priv *twl4030 = codec->private_data;
  1691. if (freq != 26000000) {
  1692. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1693. "interface needs 26MHz APLL mclk\n", freq);
  1694. return -EINVAL;
  1695. }
  1696. if ((freq / 1000) != twl4030->sysclk) {
  1697. dev_err(codec->dev,
  1698. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1699. freq, twl4030->sysclk * 1000);
  1700. return -EINVAL;
  1701. }
  1702. return 0;
  1703. }
  1704. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1705. unsigned int fmt)
  1706. {
  1707. struct snd_soc_codec *codec = codec_dai->codec;
  1708. u8 old_format, format;
  1709. /* get format */
  1710. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1711. format = old_format;
  1712. /* set master/slave audio interface */
  1713. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1714. case SND_SOC_DAIFMT_CBM_CFM:
  1715. format &= ~(TWL4030_VIF_SLAVE_EN);
  1716. break;
  1717. case SND_SOC_DAIFMT_CBS_CFS:
  1718. format |= TWL4030_VIF_SLAVE_EN;
  1719. break;
  1720. default:
  1721. return -EINVAL;
  1722. }
  1723. /* clock inversion */
  1724. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1725. case SND_SOC_DAIFMT_IB_NF:
  1726. format &= ~(TWL4030_VIF_FORMAT);
  1727. break;
  1728. case SND_SOC_DAIFMT_NB_IF:
  1729. format |= TWL4030_VIF_FORMAT;
  1730. break;
  1731. default:
  1732. return -EINVAL;
  1733. }
  1734. if (format != old_format) {
  1735. /* change format and set CODECPDZ */
  1736. twl4030_codec_enable(codec, 0);
  1737. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1738. twl4030_codec_enable(codec, 1);
  1739. }
  1740. return 0;
  1741. }
  1742. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1743. {
  1744. struct snd_soc_codec *codec = dai->codec;
  1745. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1746. if (tristate)
  1747. reg |= TWL4030_VIF_TRI_EN;
  1748. else
  1749. reg &= ~TWL4030_VIF_TRI_EN;
  1750. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1751. }
  1752. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1753. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1754. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1755. .startup = twl4030_startup,
  1756. .shutdown = twl4030_shutdown,
  1757. .hw_params = twl4030_hw_params,
  1758. .set_sysclk = twl4030_set_dai_sysclk,
  1759. .set_fmt = twl4030_set_dai_fmt,
  1760. .set_tristate = twl4030_set_tristate,
  1761. };
  1762. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1763. .startup = twl4030_voice_startup,
  1764. .shutdown = twl4030_voice_shutdown,
  1765. .hw_params = twl4030_voice_hw_params,
  1766. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1767. .set_fmt = twl4030_voice_set_dai_fmt,
  1768. .set_tristate = twl4030_voice_set_tristate,
  1769. };
  1770. struct snd_soc_dai twl4030_dai[] = {
  1771. {
  1772. .name = "twl4030",
  1773. .playback = {
  1774. .stream_name = "HiFi Playback",
  1775. .channels_min = 2,
  1776. .channels_max = 4,
  1777. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1778. .formats = TWL4030_FORMATS,},
  1779. .capture = {
  1780. .stream_name = "Capture",
  1781. .channels_min = 2,
  1782. .channels_max = 4,
  1783. .rates = TWL4030_RATES,
  1784. .formats = TWL4030_FORMATS,},
  1785. .ops = &twl4030_dai_ops,
  1786. },
  1787. {
  1788. .name = "twl4030 Voice",
  1789. .playback = {
  1790. .stream_name = "Voice Playback",
  1791. .channels_min = 1,
  1792. .channels_max = 1,
  1793. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1794. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1795. .capture = {
  1796. .stream_name = "Capture",
  1797. .channels_min = 1,
  1798. .channels_max = 2,
  1799. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1800. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1801. .ops = &twl4030_dai_voice_ops,
  1802. },
  1803. };
  1804. EXPORT_SYMBOL_GPL(twl4030_dai);
  1805. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1806. {
  1807. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1808. struct snd_soc_codec *codec = socdev->card->codec;
  1809. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1810. return 0;
  1811. }
  1812. static int twl4030_soc_resume(struct platform_device *pdev)
  1813. {
  1814. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1815. struct snd_soc_codec *codec = socdev->card->codec;
  1816. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1817. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1818. return 0;
  1819. }
  1820. static struct snd_soc_codec *twl4030_codec;
  1821. static int twl4030_soc_probe(struct platform_device *pdev)
  1822. {
  1823. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1824. struct twl4030_setup_data *setup = socdev->codec_data;
  1825. struct snd_soc_codec *codec;
  1826. struct twl4030_priv *twl4030;
  1827. int ret;
  1828. BUG_ON(!twl4030_codec);
  1829. codec = twl4030_codec;
  1830. twl4030 = codec->private_data;
  1831. socdev->card->codec = codec;
  1832. /* Configuration for headset ramp delay from setup data */
  1833. if (setup) {
  1834. unsigned char hs_pop;
  1835. if (setup->sysclk != twl4030->sysclk)
  1836. dev_warn(&pdev->dev,
  1837. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1838. setup->sysclk, twl4030->sysclk);
  1839. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1840. hs_pop &= ~TWL4030_RAMP_DELAY;
  1841. hs_pop |= (setup->ramp_delay_value << 2);
  1842. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1843. }
  1844. /* register pcms */
  1845. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1846. if (ret < 0) {
  1847. dev_err(&pdev->dev, "failed to create pcms\n");
  1848. return ret;
  1849. }
  1850. snd_soc_add_controls(codec, twl4030_snd_controls,
  1851. ARRAY_SIZE(twl4030_snd_controls));
  1852. twl4030_add_widgets(codec);
  1853. return 0;
  1854. }
  1855. static int twl4030_soc_remove(struct platform_device *pdev)
  1856. {
  1857. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1858. struct snd_soc_codec *codec = socdev->card->codec;
  1859. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1860. snd_soc_free_pcms(socdev);
  1861. snd_soc_dapm_free(socdev);
  1862. return 0;
  1863. }
  1864. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1865. {
  1866. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1867. struct snd_soc_codec *codec;
  1868. struct twl4030_priv *twl4030;
  1869. int ret;
  1870. if (!pdata) {
  1871. dev_err(&pdev->dev, "platform_data is missing\n");
  1872. return -EINVAL;
  1873. }
  1874. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1875. if (twl4030 == NULL) {
  1876. dev_err(&pdev->dev, "Can not allocate memroy\n");
  1877. return -ENOMEM;
  1878. }
  1879. codec = &twl4030->codec;
  1880. codec->private_data = twl4030;
  1881. codec->dev = &pdev->dev;
  1882. twl4030_dai[0].dev = &pdev->dev;
  1883. twl4030_dai[1].dev = &pdev->dev;
  1884. mutex_init(&codec->mutex);
  1885. INIT_LIST_HEAD(&codec->dapm_widgets);
  1886. INIT_LIST_HEAD(&codec->dapm_paths);
  1887. codec->name = "twl4030";
  1888. codec->owner = THIS_MODULE;
  1889. codec->read = twl4030_read_reg_cache;
  1890. codec->write = twl4030_write;
  1891. codec->set_bias_level = twl4030_set_bias_level;
  1892. codec->dai = twl4030_dai;
  1893. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  1894. codec->reg_cache_size = sizeof(twl4030_reg);
  1895. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1896. GFP_KERNEL);
  1897. if (codec->reg_cache == NULL) {
  1898. ret = -ENOMEM;
  1899. goto error_cache;
  1900. }
  1901. platform_set_drvdata(pdev, twl4030);
  1902. twl4030_codec = codec;
  1903. /* Set the defaults, and power up the codec */
  1904. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  1905. twl4030_init_chip(codec);
  1906. codec->bias_level = SND_SOC_BIAS_OFF;
  1907. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1908. ret = snd_soc_register_codec(codec);
  1909. if (ret != 0) {
  1910. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  1911. goto error_codec;
  1912. }
  1913. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1914. if (ret != 0) {
  1915. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  1916. snd_soc_unregister_codec(codec);
  1917. goto error_codec;
  1918. }
  1919. return 0;
  1920. error_codec:
  1921. twl4030_power_down(codec);
  1922. kfree(codec->reg_cache);
  1923. error_cache:
  1924. kfree(twl4030);
  1925. return ret;
  1926. }
  1927. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  1928. {
  1929. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  1930. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1931. snd_soc_unregister_codec(&twl4030->codec);
  1932. kfree(twl4030->codec.reg_cache);
  1933. kfree(twl4030);
  1934. twl4030_codec = NULL;
  1935. return 0;
  1936. }
  1937. MODULE_ALIAS("platform:twl4030_codec_audio");
  1938. static struct platform_driver twl4030_codec_driver = {
  1939. .probe = twl4030_codec_probe,
  1940. .remove = __devexit_p(twl4030_codec_remove),
  1941. .driver = {
  1942. .name = "twl4030_codec_audio",
  1943. .owner = THIS_MODULE,
  1944. },
  1945. };
  1946. static int __init twl4030_modinit(void)
  1947. {
  1948. return platform_driver_register(&twl4030_codec_driver);
  1949. }
  1950. module_init(twl4030_modinit);
  1951. static void __exit twl4030_exit(void)
  1952. {
  1953. platform_driver_unregister(&twl4030_codec_driver);
  1954. }
  1955. module_exit(twl4030_exit);
  1956. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1957. .probe = twl4030_soc_probe,
  1958. .remove = twl4030_soc_remove,
  1959. .suspend = twl4030_soc_suspend,
  1960. .resume = twl4030_soc_resume,
  1961. };
  1962. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1963. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1964. MODULE_AUTHOR("Steve Sakoman");
  1965. MODULE_LICENSE("GPL");