i82092.c 18 KB

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  1. /*
  2. * Driver for Intel I82092AA PCI-PCMCIA bridge.
  3. *
  4. * (C) 2001 Red Hat, Inc.
  5. *
  6. * Author: Arjan Van De Ven <arjanv@redhat.com>
  7. * Loosly based on i82365.c from the pcmcia-cs package
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/pci.h>
  12. #include <linux/init.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/device.h>
  16. #include <pcmcia/cs_types.h>
  17. #include <pcmcia/ss.h>
  18. #include <pcmcia/cs.h>
  19. #include <asm/system.h>
  20. #include <asm/io.h>
  21. #include "i82092aa.h"
  22. #include "i82365.h"
  23. MODULE_LICENSE("GPL");
  24. /* PCI core routines */
  25. static struct pci_device_id i82092aa_pci_ids[] = {
  26. {
  27. .vendor = PCI_VENDOR_ID_INTEL,
  28. .device = PCI_DEVICE_ID_INTEL_82092AA_0,
  29. .subvendor = PCI_ANY_ID,
  30. .subdevice = PCI_ANY_ID,
  31. },
  32. {}
  33. };
  34. MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
  35. #ifdef CONFIG_PM
  36. static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state)
  37. {
  38. return pcmcia_socket_dev_suspend(&dev->dev);
  39. }
  40. static int i82092aa_socket_resume (struct pci_dev *dev)
  41. {
  42. return pcmcia_socket_dev_resume(&dev->dev);
  43. }
  44. #endif
  45. static struct pci_driver i82092aa_pci_driver = {
  46. .name = "i82092aa",
  47. .id_table = i82092aa_pci_ids,
  48. .probe = i82092aa_pci_probe,
  49. .remove = __devexit_p(i82092aa_pci_remove),
  50. #ifdef CONFIG_PM
  51. .suspend = i82092aa_socket_suspend,
  52. .resume = i82092aa_socket_resume,
  53. #endif
  54. };
  55. /* the pccard structure and its functions */
  56. static struct pccard_operations i82092aa_operations = {
  57. .init = i82092aa_init,
  58. .get_status = i82092aa_get_status,
  59. .set_socket = i82092aa_set_socket,
  60. .set_io_map = i82092aa_set_io_map,
  61. .set_mem_map = i82092aa_set_mem_map,
  62. };
  63. /* The card can do upto 4 sockets, allocate a structure for each of them */
  64. struct socket_info {
  65. int number;
  66. int card_state; /* 0 = no socket,
  67. 1 = empty socket,
  68. 2 = card but not initialized,
  69. 3 = operational card */
  70. unsigned int io_base; /* base io address of the socket */
  71. struct pcmcia_socket socket;
  72. struct pci_dev *dev; /* The PCI device for the socket */
  73. };
  74. #define MAX_SOCKETS 4
  75. static struct socket_info sockets[MAX_SOCKETS];
  76. static int socket_count; /* shortcut */
  77. static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  78. {
  79. unsigned char configbyte;
  80. int i, ret;
  81. enter("i82092aa_pci_probe");
  82. if ((ret = pci_enable_device(dev)))
  83. return ret;
  84. pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */
  85. switch(configbyte&6) {
  86. case 0:
  87. socket_count = 2;
  88. break;
  89. case 2:
  90. socket_count = 1;
  91. break;
  92. case 4:
  93. case 6:
  94. socket_count = 4;
  95. break;
  96. default:
  97. printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n");
  98. ret = -EIO;
  99. goto err_out_disable;
  100. }
  101. printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count);
  102. if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
  103. ret = -EBUSY;
  104. goto err_out_disable;
  105. }
  106. for (i = 0;i<socket_count;i++) {
  107. sockets[i].card_state = 1; /* 1 = present but empty */
  108. sockets[i].io_base = pci_resource_start(dev, 0);
  109. sockets[i].socket.features |= SS_CAP_PCCARD;
  110. sockets[i].socket.map_size = 0x1000;
  111. sockets[i].socket.irq_mask = 0;
  112. sockets[i].socket.pci_irq = dev->irq;
  113. sockets[i].socket.cb_dev = dev;
  114. sockets[i].socket.owner = THIS_MODULE;
  115. sockets[i].number = i;
  116. if (card_present(i)) {
  117. sockets[i].card_state = 3;
  118. dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i);
  119. } else {
  120. dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i);
  121. }
  122. }
  123. /* Now, specifiy that all interrupts are to be done as PCI interrupts */
  124. configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */
  125. pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */
  126. /* Register the interrupt handler */
  127. dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq);
  128. if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) {
  129. printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq);
  130. goto err_out_free_res;
  131. }
  132. pci_set_drvdata(dev, &sockets[i].socket);
  133. for (i = 0; i<socket_count; i++) {
  134. sockets[i].socket.dev.parent = &dev->dev;
  135. sockets[i].socket.ops = &i82092aa_operations;
  136. sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
  137. ret = pcmcia_register_socket(&sockets[i].socket);
  138. if (ret) {
  139. goto err_out_free_sockets;
  140. }
  141. }
  142. leave("i82092aa_pci_probe");
  143. return 0;
  144. err_out_free_sockets:
  145. if (i) {
  146. for (i--;i>=0;i--) {
  147. pcmcia_unregister_socket(&sockets[i].socket);
  148. }
  149. }
  150. free_irq(dev->irq, i82092aa_interrupt);
  151. err_out_free_res:
  152. release_region(pci_resource_start(dev, 0), 2);
  153. err_out_disable:
  154. pci_disable_device(dev);
  155. return ret;
  156. }
  157. static void __devexit i82092aa_pci_remove(struct pci_dev *dev)
  158. {
  159. struct pcmcia_socket *socket = pci_get_drvdata(dev);
  160. enter("i82092aa_pci_remove");
  161. free_irq(dev->irq, i82092aa_interrupt);
  162. if (socket)
  163. pcmcia_unregister_socket(socket);
  164. leave("i82092aa_pci_remove");
  165. }
  166. static DEFINE_SPINLOCK(port_lock);
  167. /* basic value read/write functions */
  168. static unsigned char indirect_read(int socket, unsigned short reg)
  169. {
  170. unsigned short int port;
  171. unsigned char val;
  172. unsigned long flags;
  173. spin_lock_irqsave(&port_lock,flags);
  174. reg += socket * 0x40;
  175. port = sockets[socket].io_base;
  176. outb(reg,port);
  177. val = inb(port+1);
  178. spin_unlock_irqrestore(&port_lock,flags);
  179. return val;
  180. }
  181. #if 0
  182. static unsigned short indirect_read16(int socket, unsigned short reg)
  183. {
  184. unsigned short int port;
  185. unsigned short tmp;
  186. unsigned long flags;
  187. spin_lock_irqsave(&port_lock,flags);
  188. reg = reg + socket * 0x40;
  189. port = sockets[socket].io_base;
  190. outb(reg,port);
  191. tmp = inb(port+1);
  192. reg++;
  193. outb(reg,port);
  194. tmp = tmp | (inb(port+1)<<8);
  195. spin_unlock_irqrestore(&port_lock,flags);
  196. return tmp;
  197. }
  198. #endif
  199. static void indirect_write(int socket, unsigned short reg, unsigned char value)
  200. {
  201. unsigned short int port;
  202. unsigned long flags;
  203. spin_lock_irqsave(&port_lock,flags);
  204. reg = reg + socket * 0x40;
  205. port = sockets[socket].io_base;
  206. outb(reg,port);
  207. outb(value,port+1);
  208. spin_unlock_irqrestore(&port_lock,flags);
  209. }
  210. static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
  211. {
  212. unsigned short int port;
  213. unsigned char val;
  214. unsigned long flags;
  215. spin_lock_irqsave(&port_lock,flags);
  216. reg = reg + socket * 0x40;
  217. port = sockets[socket].io_base;
  218. outb(reg,port);
  219. val = inb(port+1);
  220. val |= mask;
  221. outb(reg,port);
  222. outb(val,port+1);
  223. spin_unlock_irqrestore(&port_lock,flags);
  224. }
  225. static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask)
  226. {
  227. unsigned short int port;
  228. unsigned char val;
  229. unsigned long flags;
  230. spin_lock_irqsave(&port_lock,flags);
  231. reg = reg + socket * 0x40;
  232. port = sockets[socket].io_base;
  233. outb(reg,port);
  234. val = inb(port+1);
  235. val &= ~mask;
  236. outb(reg,port);
  237. outb(val,port+1);
  238. spin_unlock_irqrestore(&port_lock,flags);
  239. }
  240. static void indirect_write16(int socket, unsigned short reg, unsigned short value)
  241. {
  242. unsigned short int port;
  243. unsigned char val;
  244. unsigned long flags;
  245. spin_lock_irqsave(&port_lock,flags);
  246. reg = reg + socket * 0x40;
  247. port = sockets[socket].io_base;
  248. outb(reg,port);
  249. val = value & 255;
  250. outb(val,port+1);
  251. reg++;
  252. outb(reg,port);
  253. val = value>>8;
  254. outb(val,port+1);
  255. spin_unlock_irqrestore(&port_lock,flags);
  256. }
  257. /* simple helper functions */
  258. /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
  259. static int cycle_time = 120;
  260. static int to_cycles(int ns)
  261. {
  262. if (cycle_time!=0)
  263. return ns/cycle_time;
  264. else
  265. return 0;
  266. }
  267. /* Interrupt handler functionality */
  268. static irqreturn_t i82092aa_interrupt(int irq, void *dev)
  269. {
  270. int i;
  271. int loopcount = 0;
  272. int handled = 0;
  273. unsigned int events, active=0;
  274. /* enter("i82092aa_interrupt");*/
  275. while (1) {
  276. loopcount++;
  277. if (loopcount>20) {
  278. printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n");
  279. break;
  280. }
  281. active = 0;
  282. for (i=0;i<socket_count;i++) {
  283. int csc;
  284. if (sockets[i].card_state==0) /* Inactive socket, should not happen */
  285. continue;
  286. csc = indirect_read(i,I365_CSC); /* card status change register */
  287. if (csc==0) /* no events on this socket */
  288. continue;
  289. handled = 1;
  290. events = 0;
  291. if (csc & I365_CSC_DETECT) {
  292. events |= SS_DETECT;
  293. printk("Card detected in socket %i!\n",i);
  294. }
  295. if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) {
  296. /* For IO/CARDS, bit 0 means "read the card" */
  297. events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
  298. } else {
  299. /* Check for battery/ready events */
  300. events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
  301. events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
  302. events |= (csc & I365_CSC_READY) ? SS_READY : 0;
  303. }
  304. if (events) {
  305. pcmcia_parse_events(&sockets[i].socket, events);
  306. }
  307. active |= events;
  308. }
  309. if (active==0) /* no more events to handle */
  310. break;
  311. }
  312. return IRQ_RETVAL(handled);
  313. /* leave("i82092aa_interrupt");*/
  314. }
  315. /* socket functions */
  316. static int card_present(int socketno)
  317. {
  318. unsigned int val;
  319. enter("card_present");
  320. if ((socketno<0) || (socketno >= MAX_SOCKETS))
  321. return 0;
  322. if (sockets[socketno].io_base == 0)
  323. return 0;
  324. val = indirect_read(socketno, 1); /* Interface status register */
  325. if ((val&12)==12) {
  326. leave("card_present 1");
  327. return 1;
  328. }
  329. leave("card_present 0");
  330. return 0;
  331. }
  332. static void set_bridge_state(int sock)
  333. {
  334. enter("set_bridge_state");
  335. indirect_write(sock, I365_GBLCTL,0x00);
  336. indirect_write(sock, I365_GENCTL,0x00);
  337. indirect_setbit(sock, I365_INTCTL,0x08);
  338. leave("set_bridge_state");
  339. }
  340. static int i82092aa_init(struct pcmcia_socket *sock)
  341. {
  342. int i;
  343. struct resource res = { .start = 0, .end = 0x0fff };
  344. pccard_io_map io = { 0, 0, 0, 0, 1 };
  345. pccard_mem_map mem = { .res = &res, };
  346. enter("i82092aa_init");
  347. for (i = 0; i < 2; i++) {
  348. io.map = i;
  349. i82092aa_set_io_map(sock, &io);
  350. }
  351. for (i = 0; i < 5; i++) {
  352. mem.map = i;
  353. i82092aa_set_mem_map(sock, &mem);
  354. }
  355. leave("i82092aa_init");
  356. return 0;
  357. }
  358. static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
  359. {
  360. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  361. unsigned int status;
  362. enter("i82092aa_get_status");
  363. status = indirect_read(sock,I365_STATUS); /* Interface Status Register */
  364. *value = 0;
  365. if ((status & I365_CS_DETECT) == I365_CS_DETECT) {
  366. *value |= SS_DETECT;
  367. }
  368. /* IO cards have a different meaning of bits 0,1 */
  369. /* Also notice the inverse-logic on the bits */
  370. if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
  371. /* IO card */
  372. if (!(status & I365_CS_STSCHG))
  373. *value |= SS_STSCHG;
  374. } else { /* non I/O card */
  375. if (!(status & I365_CS_BVD1))
  376. *value |= SS_BATDEAD;
  377. if (!(status & I365_CS_BVD2))
  378. *value |= SS_BATWARN;
  379. }
  380. if (status & I365_CS_WRPROT)
  381. (*value) |= SS_WRPROT; /* card is write protected */
  382. if (status & I365_CS_READY)
  383. (*value) |= SS_READY; /* card is not busy */
  384. if (status & I365_CS_POWERON)
  385. (*value) |= SS_POWERON; /* power is applied to the card */
  386. leave("i82092aa_get_status");
  387. return 0;
  388. }
  389. static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state)
  390. {
  391. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  392. unsigned char reg;
  393. enter("i82092aa_set_socket");
  394. /* First, set the global controller options */
  395. set_bridge_state(sock);
  396. /* Values for the IGENC register */
  397. reg = 0;
  398. if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */
  399. reg = reg | I365_PC_RESET;
  400. if (state->flags & SS_IOCARD)
  401. reg = reg | I365_PC_IOCARD;
  402. indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */
  403. /* Power registers */
  404. reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
  405. if (state->flags & SS_PWR_AUTO) {
  406. printk("Auto power\n");
  407. reg |= I365_PWR_AUTO; /* automatic power mngmnt */
  408. }
  409. if (state->flags & SS_OUTPUT_ENA) {
  410. printk("Power Enabled \n");
  411. reg |= I365_PWR_OUT; /* enable power */
  412. }
  413. switch (state->Vcc) {
  414. case 0:
  415. break;
  416. case 50:
  417. printk("setting voltage to Vcc to 5V on socket %i\n",sock);
  418. reg |= I365_VCC_5V;
  419. break;
  420. default:
  421. printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc);
  422. leave("i82092aa_set_socket");
  423. return -EINVAL;
  424. }
  425. switch (state->Vpp) {
  426. case 0:
  427. printk("not setting Vpp on socket %i\n",sock);
  428. break;
  429. case 50:
  430. printk("setting Vpp to 5.0 for socket %i\n",sock);
  431. reg |= I365_VPP1_5V | I365_VPP2_5V;
  432. break;
  433. case 120:
  434. printk("setting Vpp to 12.0\n");
  435. reg |= I365_VPP1_12V | I365_VPP2_12V;
  436. break;
  437. default:
  438. printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc);
  439. leave("i82092aa_set_socket");
  440. return -EINVAL;
  441. }
  442. if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */
  443. indirect_write(sock,I365_POWER,reg);
  444. /* Enable specific interrupt events */
  445. reg = 0x00;
  446. if (state->csc_mask & SS_DETECT) {
  447. reg |= I365_CSC_DETECT;
  448. }
  449. if (state->flags & SS_IOCARD) {
  450. if (state->csc_mask & SS_STSCHG)
  451. reg |= I365_CSC_STSCHG;
  452. } else {
  453. if (state->csc_mask & SS_BATDEAD)
  454. reg |= I365_CSC_BVD1;
  455. if (state->csc_mask & SS_BATWARN)
  456. reg |= I365_CSC_BVD2;
  457. if (state->csc_mask & SS_READY)
  458. reg |= I365_CSC_READY;
  459. }
  460. /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/
  461. indirect_write(sock,I365_CSCINT,reg);
  462. (void)indirect_read(sock,I365_CSC);
  463. leave("i82092aa_set_socket");
  464. return 0;
  465. }
  466. static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io)
  467. {
  468. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  469. unsigned char map, ioctl;
  470. enter("i82092aa_set_io_map");
  471. map = io->map;
  472. /* Check error conditions */
  473. if (map > 1) {
  474. leave("i82092aa_set_io_map with invalid map");
  475. return -EINVAL;
  476. }
  477. if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){
  478. leave("i82092aa_set_io_map with invalid io");
  479. return -EINVAL;
  480. }
  481. /* Turn off the window before changing anything */
  482. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
  483. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
  484. /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */
  485. /* write the new values */
  486. indirect_write16(sock,I365_IO(map)+I365_W_START,io->start);
  487. indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop);
  488. ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map);
  489. if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
  490. ioctl |= I365_IOCTL_16BIT(map);
  491. indirect_write(sock,I365_IOCTL,ioctl);
  492. /* Turn the window back on if needed */
  493. if (io->flags & MAP_ACTIVE)
  494. indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map));
  495. leave("i82092aa_set_io_map");
  496. return 0;
  497. }
  498. static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem)
  499. {
  500. struct socket_info *sock_info = container_of(socket, struct socket_info, socket);
  501. unsigned int sock = sock_info->number;
  502. struct pci_bus_region region;
  503. unsigned short base, i;
  504. unsigned char map;
  505. enter("i82092aa_set_mem_map");
  506. pcibios_resource_to_bus(sock_info->dev, &region, mem->res);
  507. map = mem->map;
  508. if (map > 4) {
  509. leave("i82092aa_set_mem_map: invalid map");
  510. return -EINVAL;
  511. }
  512. if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) ||
  513. (mem->speed > 1000) ) {
  514. leave("i82092aa_set_mem_map: invalid address / speed");
  515. printk("invalid mem map for socket %i: %llx to %llx with a "
  516. "start of %x\n",
  517. sock,
  518. (unsigned long long)region.start,
  519. (unsigned long long)region.end,
  520. mem->card_start);
  521. return -EINVAL;
  522. }
  523. /* Turn off the window before changing anything */
  524. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
  525. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  526. /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */
  527. /* write the start address */
  528. base = I365_MEM(map);
  529. i = (region.start >> 12) & 0x0fff;
  530. if (mem->flags & MAP_16BIT)
  531. i |= I365_MEM_16BIT;
  532. if (mem->flags & MAP_0WS)
  533. i |= I365_MEM_0WS;
  534. indirect_write16(sock,base+I365_W_START,i);
  535. /* write the stop address */
  536. i= (region.end >> 12) & 0x0fff;
  537. switch (to_cycles(mem->speed)) {
  538. case 0:
  539. break;
  540. case 1:
  541. i |= I365_MEM_WS0;
  542. break;
  543. case 2:
  544. i |= I365_MEM_WS1;
  545. break;
  546. default:
  547. i |= I365_MEM_WS1 | I365_MEM_WS0;
  548. break;
  549. }
  550. indirect_write16(sock,base+I365_W_STOP,i);
  551. /* card start */
  552. i = ((mem->card_start - region.start) >> 12) & 0x3fff;
  553. if (mem->flags & MAP_WRPROT)
  554. i |= I365_MEM_WRPROT;
  555. if (mem->flags & MAP_ATTRIB) {
  556. /* printk("requesting attribute memory for socket %i\n",sock);*/
  557. i |= I365_MEM_REG;
  558. } else {
  559. /* printk("requesting normal memory for socket %i\n",sock);*/
  560. }
  561. indirect_write16(sock,base+I365_W_OFF,i);
  562. /* Enable the window if necessary */
  563. if (mem->flags & MAP_ACTIVE)
  564. indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  565. leave("i82092aa_set_mem_map");
  566. return 0;
  567. }
  568. static int i82092aa_module_init(void)
  569. {
  570. return pci_register_driver(&i82092aa_pci_driver);
  571. }
  572. static void i82092aa_module_exit(void)
  573. {
  574. enter("i82092aa_module_exit");
  575. pci_unregister_driver(&i82092aa_pci_driver);
  576. if (sockets[0].io_base>0)
  577. release_region(sockets[0].io_base, 2);
  578. leave("i82092aa_module_exit");
  579. }
  580. module_init(i82092aa_module_init);
  581. module_exit(i82092aa_module_exit);