plx_pci.c 12 KB

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  1. /*
  2. * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
  3. *
  4. * Derived from the ems_pci.c driver:
  5. * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
  6. * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
  7. * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the version 2 of the GNU General Public License
  11. * as published by the Free Software Foundation
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/pci.h>
  28. #include <linux/can.h>
  29. #include <linux/can/dev.h>
  30. #include <linux/io.h>
  31. #include "sja1000.h"
  32. #define DRV_NAME "sja1000_plx_pci"
  33. MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
  34. MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
  35. "the SJA1000 chips");
  36. MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
  37. "Adlink PCI-7841/cPCI-7841 SE, "
  38. "Marathon CAN-bus-PCI, "
  39. "TEWS TECHNOLOGIES TPMC810");
  40. MODULE_LICENSE("GPL v2");
  41. #define PLX_PCI_MAX_CHAN 2
  42. struct plx_pci_card {
  43. int channels; /* detected channels count */
  44. struct net_device *net_dev[PLX_PCI_MAX_CHAN];
  45. void __iomem *conf_addr;
  46. };
  47. #define PLX_PCI_CAN_CLOCK (16000000 / 2)
  48. /* PLX90xx registers */
  49. #define PLX_INTCSR 0x4c /* Interrupt Control/Status */
  50. #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
  51. * Serial EEPROM, and Initialization
  52. * Control register
  53. */
  54. #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
  55. #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
  56. #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
  57. #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
  58. /*
  59. * The board configuration is probably following:
  60. * RX1 is connected to ground.
  61. * TX1 is not connected.
  62. * CLKO is not connected.
  63. * Setting the OCR register to 0xDA is a good idea.
  64. * This means normal output mode, push-pull and the correct polarity.
  65. */
  66. #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  67. /*
  68. * In the CDR register, you should set CBP to 1.
  69. * You will probably also want to set the clock divider value to 7
  70. * (meaning direct oscillator output) because the second SJA1000 chip
  71. * is driven by the first one CLKOUT output.
  72. */
  73. #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
  74. /* SJA1000 Control Register in the BasicCAN Mode */
  75. #define REG_CR 0x00
  76. /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
  77. #define REG_CR_BASICCAN_INITIAL 0x21
  78. #define REG_CR_BASICCAN_INITIAL_MASK 0xa1
  79. #define REG_SR_BASICCAN_INITIAL 0x0c
  80. #define REG_IR_BASICCAN_INITIAL 0xe0
  81. /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
  82. #define REG_MOD_PELICAN_INITIAL 0x01
  83. #define REG_SR_PELICAN_INITIAL 0x3c
  84. #define REG_IR_PELICAN_INITIAL 0x00
  85. #define ADLINK_PCI_VENDOR_ID 0x144A
  86. #define ADLINK_PCI_DEVICE_ID 0x7841
  87. #define MARATHON_PCI_DEVICE_ID 0x2715
  88. #define TEWS_PCI_VENDOR_ID 0x1498
  89. #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
  90. static void plx_pci_reset_common(struct pci_dev *pdev);
  91. static void plx_pci_reset_marathon(struct pci_dev *pdev);
  92. struct plx_pci_channel_map {
  93. u32 bar;
  94. u32 offset;
  95. u32 size; /* 0x00 - auto, e.g. length of entire bar */
  96. };
  97. struct plx_pci_card_info {
  98. const char *name;
  99. int channel_count;
  100. u32 can_clock;
  101. u8 ocr; /* output control register */
  102. u8 cdr; /* clock divider register */
  103. /* Parameters for mapping local configuration space */
  104. struct plx_pci_channel_map conf_map;
  105. /* Parameters for mapping the SJA1000 chips */
  106. struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
  107. /* Pointer to device-dependent reset function */
  108. void (*reset_func)(struct pci_dev *pdev);
  109. };
  110. static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = {
  111. "Adlink PCI-7841/cPCI-7841", 2,
  112. PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
  113. {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
  114. &plx_pci_reset_common
  115. /* based on PLX9052 */
  116. };
  117. static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = {
  118. "Adlink PCI-7841/cPCI-7841 SE", 2,
  119. PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
  120. {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
  121. &plx_pci_reset_common
  122. /* based on PLX9052 */
  123. };
  124. static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = {
  125. "Marathon CAN-bus-PCI", 2,
  126. PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
  127. {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
  128. &plx_pci_reset_marathon
  129. /* based on PLX9052 */
  130. };
  131. static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = {
  132. "TEWS TECHNOLOGIES TPMC810", 2,
  133. PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
  134. {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
  135. &plx_pci_reset_common
  136. /* based on PLX9030 */
  137. };
  138. static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
  139. {
  140. /* Adlink PCI-7841/cPCI-7841 */
  141. ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
  142. PCI_ANY_ID, PCI_ANY_ID,
  143. PCI_CLASS_NETWORK_OTHER << 8, ~0,
  144. (kernel_ulong_t)&plx_pci_card_info_adlink
  145. },
  146. {
  147. /* Adlink PCI-7841/cPCI-7841 SE */
  148. ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
  149. PCI_ANY_ID, PCI_ANY_ID,
  150. PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
  151. (kernel_ulong_t)&plx_pci_card_info_adlink_se
  152. },
  153. {
  154. /* Marathon CAN-bus-PCI card */
  155. PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
  156. PCI_ANY_ID, PCI_ANY_ID,
  157. 0, 0,
  158. (kernel_ulong_t)&plx_pci_card_info_marathon
  159. },
  160. {
  161. /* TEWS TECHNOLOGIES TPMC810 card */
  162. TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
  163. PCI_ANY_ID, PCI_ANY_ID,
  164. 0, 0,
  165. (kernel_ulong_t)&plx_pci_card_info_tews
  166. },
  167. { 0,}
  168. };
  169. MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
  170. static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
  171. {
  172. return ioread8(priv->reg_base + port);
  173. }
  174. static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
  175. {
  176. iowrite8(val, priv->reg_base + port);
  177. }
  178. /*
  179. * Check if a CAN controller is present at the specified location
  180. * by trying to switch 'em from the Basic mode into the PeliCAN mode.
  181. * Also check states of some registers in reset mode.
  182. */
  183. static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
  184. {
  185. int flag = 0;
  186. /*
  187. * Check registers after hardware reset (the Basic mode)
  188. * See states on p. 10 of the Datasheet.
  189. */
  190. if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
  191. REG_CR_BASICCAN_INITIAL &&
  192. (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
  193. (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
  194. flag = 1;
  195. /* Bring the SJA1000 into the PeliCAN mode*/
  196. priv->write_reg(priv, REG_CDR, CDR_PELICAN);
  197. /*
  198. * Check registers after reset in the PeliCAN mode.
  199. * See states on p. 23 of the Datasheet.
  200. */
  201. if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
  202. priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
  203. priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
  204. return flag;
  205. return 0;
  206. }
  207. /*
  208. * PLX90xx software reset
  209. * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
  210. * For most cards it's enough for reset the SJA1000 chips.
  211. */
  212. static void plx_pci_reset_common(struct pci_dev *pdev)
  213. {
  214. struct plx_pci_card *card = pci_get_drvdata(pdev);
  215. u32 cntrl;
  216. cntrl = ioread32(card->conf_addr + PLX_CNTRL);
  217. cntrl |= PLX_PCI_RESET;
  218. iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
  219. udelay(100);
  220. cntrl ^= PLX_PCI_RESET;
  221. iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
  222. };
  223. /* Special reset function for Marathon card */
  224. static void plx_pci_reset_marathon(struct pci_dev *pdev)
  225. {
  226. void __iomem *reset_addr;
  227. int i;
  228. int reset_bar[2] = {3, 5};
  229. plx_pci_reset_common(pdev);
  230. for (i = 0; i < 2; i++) {
  231. reset_addr = pci_iomap(pdev, reset_bar[i], 0);
  232. if (!reset_addr) {
  233. dev_err(&pdev->dev, "Failed to remap reset "
  234. "space %d (BAR%d)\n", i, reset_bar[i]);
  235. } else {
  236. /* reset the SJA1000 chip */
  237. iowrite8(0x1, reset_addr);
  238. udelay(100);
  239. pci_iounmap(pdev, reset_addr);
  240. }
  241. }
  242. }
  243. static void plx_pci_del_card(struct pci_dev *pdev)
  244. {
  245. struct plx_pci_card *card = pci_get_drvdata(pdev);
  246. struct net_device *dev;
  247. struct sja1000_priv *priv;
  248. int i = 0;
  249. for (i = 0; i < card->channels; i++) {
  250. dev = card->net_dev[i];
  251. if (!dev)
  252. continue;
  253. dev_info(&pdev->dev, "Removing %s\n", dev->name);
  254. unregister_sja1000dev(dev);
  255. priv = netdev_priv(dev);
  256. if (priv->reg_base)
  257. pci_iounmap(pdev, priv->reg_base);
  258. free_sja1000dev(dev);
  259. }
  260. plx_pci_reset_common(pdev);
  261. /*
  262. * Disable interrupts from PCI-card (PLX90xx) and disable Local_1,
  263. * Local_2 interrupts
  264. */
  265. iowrite32(0x0, card->conf_addr + PLX_INTCSR);
  266. if (card->conf_addr)
  267. pci_iounmap(pdev, card->conf_addr);
  268. kfree(card);
  269. pci_disable_device(pdev);
  270. pci_set_drvdata(pdev, NULL);
  271. }
  272. /*
  273. * Probe PLX90xx based device for the SJA1000 chips and register each
  274. * available CAN channel to SJA1000 Socket-CAN subsystem.
  275. */
  276. static int __devinit plx_pci_add_card(struct pci_dev *pdev,
  277. const struct pci_device_id *ent)
  278. {
  279. struct sja1000_priv *priv;
  280. struct net_device *dev;
  281. struct plx_pci_card *card;
  282. struct plx_pci_card_info *ci;
  283. int err, i;
  284. u32 val;
  285. void __iomem *addr;
  286. ci = (struct plx_pci_card_info *)ent->driver_data;
  287. if (pci_enable_device(pdev) < 0) {
  288. dev_err(&pdev->dev, "Failed to enable PCI device\n");
  289. return -ENODEV;
  290. }
  291. dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
  292. ci->name, PCI_SLOT(pdev->devfn));
  293. /* Allocate card structures to hold addresses, ... */
  294. card = kzalloc(sizeof(*card), GFP_KERNEL);
  295. if (!card) {
  296. dev_err(&pdev->dev, "Unable to allocate memory\n");
  297. pci_disable_device(pdev);
  298. return -ENOMEM;
  299. }
  300. pci_set_drvdata(pdev, card);
  301. card->channels = 0;
  302. /* Remap PLX90xx configuration space */
  303. addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
  304. if (!addr) {
  305. err = -ENOMEM;
  306. dev_err(&pdev->dev, "Failed to remap configuration space "
  307. "(BAR%d)\n", ci->conf_map.bar);
  308. goto failure_cleanup;
  309. }
  310. card->conf_addr = addr + ci->conf_map.offset;
  311. ci->reset_func(pdev);
  312. /* Detect available channels */
  313. for (i = 0; i < ci->channel_count; i++) {
  314. struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
  315. dev = alloc_sja1000dev(0);
  316. if (!dev) {
  317. err = -ENOMEM;
  318. goto failure_cleanup;
  319. }
  320. card->net_dev[i] = dev;
  321. priv = netdev_priv(dev);
  322. priv->priv = card;
  323. priv->irq_flags = IRQF_SHARED;
  324. dev->irq = pdev->irq;
  325. /*
  326. * Remap IO space of the SJA1000 chips
  327. * This is device-dependent mapping
  328. */
  329. addr = pci_iomap(pdev, cm->bar, cm->size);
  330. if (!addr) {
  331. err = -ENOMEM;
  332. dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
  333. goto failure_cleanup;
  334. }
  335. priv->reg_base = addr + cm->offset;
  336. priv->read_reg = plx_pci_read_reg;
  337. priv->write_reg = plx_pci_write_reg;
  338. /* Check if channel is present */
  339. if (plx_pci_check_sja1000(priv)) {
  340. priv->can.clock.freq = ci->can_clock;
  341. priv->ocr = ci->ocr;
  342. priv->cdr = ci->cdr;
  343. SET_NETDEV_DEV(dev, &pdev->dev);
  344. /* Register SJA1000 device */
  345. err = register_sja1000dev(dev);
  346. if (err) {
  347. dev_err(&pdev->dev, "Registering device failed "
  348. "(err=%d)\n", err);
  349. free_sja1000dev(dev);
  350. goto failure_cleanup;
  351. }
  352. card->channels++;
  353. dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
  354. "registered as %s\n", i + 1, priv->reg_base,
  355. dev->irq, dev->name);
  356. } else {
  357. dev_err(&pdev->dev, "Channel #%d not detected\n",
  358. i + 1);
  359. free_sja1000dev(dev);
  360. }
  361. }
  362. if (!card->channels) {
  363. err = -ENODEV;
  364. goto failure_cleanup;
  365. }
  366. /*
  367. * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
  368. * Local_2 interrupts from the SJA1000 chips
  369. */
  370. val = ioread32(card->conf_addr + PLX_INTCSR);
  371. val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
  372. iowrite32(val, card->conf_addr + PLX_INTCSR);
  373. return 0;
  374. failure_cleanup:
  375. dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
  376. plx_pci_del_card(pdev);
  377. return err;
  378. }
  379. static struct pci_driver plx_pci_driver = {
  380. .name = DRV_NAME,
  381. .id_table = plx_pci_tbl,
  382. .probe = plx_pci_add_card,
  383. .remove = plx_pci_del_card,
  384. };
  385. static int __init plx_pci_init(void)
  386. {
  387. return pci_register_driver(&plx_pci_driver);
  388. }
  389. static void __exit plx_pci_exit(void)
  390. {
  391. pci_unregister_driver(&plx_pci_driver);
  392. }
  393. module_init(plx_pci_init);
  394. module_exit(plx_pci_exit);