timbgpio.c 8.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357
  1. /*
  2. * timbgpio.c timberdale FPGA GPIO driver
  3. * Copyright (c) 2009 Intel Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* Supports:
  19. * Timberdale FPGA GPIO
  20. */
  21. #include <linux/module.h>
  22. #include <linux/gpio.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/irq.h>
  25. #include <linux/io.h>
  26. #include <linux/timb_gpio.h>
  27. #include <linux/interrupt.h>
  28. #define DRIVER_NAME "timb-gpio"
  29. #define TGPIOVAL 0x00
  30. #define TGPIODIR 0x04
  31. #define TGPIO_IER 0x08
  32. #define TGPIO_ISR 0x0c
  33. #define TGPIO_IPR 0x10
  34. #define TGPIO_ICR 0x14
  35. #define TGPIO_FLR 0x18
  36. #define TGPIO_LVR 0x1c
  37. #define TGPIO_VER 0x20
  38. #define TGPIO_BFLR 0x24
  39. struct timbgpio {
  40. void __iomem *membase;
  41. spinlock_t lock; /* mutual exclusion */
  42. struct gpio_chip gpio;
  43. int irq_base;
  44. };
  45. static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
  46. unsigned offset, bool enabled)
  47. {
  48. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  49. u32 reg;
  50. spin_lock(&tgpio->lock);
  51. reg = ioread32(tgpio->membase + offset);
  52. if (enabled)
  53. reg |= (1 << index);
  54. else
  55. reg &= ~(1 << index);
  56. iowrite32(reg, tgpio->membase + offset);
  57. spin_unlock(&tgpio->lock);
  58. return 0;
  59. }
  60. static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  61. {
  62. return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
  63. }
  64. static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
  65. {
  66. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  67. u32 value;
  68. value = ioread32(tgpio->membase + TGPIOVAL);
  69. return (value & (1 << nr)) ? 1 : 0;
  70. }
  71. static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
  72. unsigned nr, int val)
  73. {
  74. return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
  75. }
  76. static void timbgpio_gpio_set(struct gpio_chip *gpio,
  77. unsigned nr, int val)
  78. {
  79. timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
  80. }
  81. static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  82. {
  83. struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
  84. if (tgpio->irq_base <= 0)
  85. return -EINVAL;
  86. return tgpio->irq_base + offset;
  87. }
  88. /*
  89. * GPIO IRQ
  90. */
  91. static void timbgpio_irq_disable(unsigned irq)
  92. {
  93. struct timbgpio *tgpio = get_irq_chip_data(irq);
  94. int offset = irq - tgpio->irq_base;
  95. timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
  96. }
  97. static void timbgpio_irq_enable(unsigned irq)
  98. {
  99. struct timbgpio *tgpio = get_irq_chip_data(irq);
  100. int offset = irq - tgpio->irq_base;
  101. timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
  102. }
  103. static int timbgpio_irq_type(unsigned irq, unsigned trigger)
  104. {
  105. struct timbgpio *tgpio = get_irq_chip_data(irq);
  106. int offset = irq - tgpio->irq_base;
  107. unsigned long flags;
  108. u32 lvr, flr, bflr = 0;
  109. u32 ver;
  110. if (offset < 0 || offset > tgpio->gpio.ngpio)
  111. return -EINVAL;
  112. ver = ioread32(tgpio->membase + TGPIO_VER);
  113. spin_lock_irqsave(&tgpio->lock, flags);
  114. lvr = ioread32(tgpio->membase + TGPIO_LVR);
  115. flr = ioread32(tgpio->membase + TGPIO_FLR);
  116. if (ver > 2)
  117. bflr = ioread32(tgpio->membase + TGPIO_BFLR);
  118. if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  119. bflr &= ~(1 << offset);
  120. flr &= ~(1 << offset);
  121. if (trigger & IRQ_TYPE_LEVEL_HIGH)
  122. lvr |= 1 << offset;
  123. else
  124. lvr &= ~(1 << offset);
  125. }
  126. if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  127. if (ver < 3)
  128. return -EINVAL;
  129. else {
  130. flr |= 1 << offset;
  131. bflr |= 1 << offset;
  132. }
  133. } else {
  134. bflr &= ~(1 << offset);
  135. flr |= 1 << offset;
  136. if (trigger & IRQ_TYPE_EDGE_FALLING)
  137. lvr &= ~(1 << offset);
  138. else
  139. lvr |= 1 << offset;
  140. }
  141. iowrite32(lvr, tgpio->membase + TGPIO_LVR);
  142. iowrite32(flr, tgpio->membase + TGPIO_FLR);
  143. if (ver > 2)
  144. iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
  145. iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
  146. spin_unlock_irqrestore(&tgpio->lock, flags);
  147. return 0;
  148. }
  149. static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
  150. {
  151. struct timbgpio *tgpio = get_irq_data(irq);
  152. unsigned long ipr;
  153. int offset;
  154. desc->chip->ack(irq);
  155. ipr = ioread32(tgpio->membase + TGPIO_IPR);
  156. iowrite32(ipr, tgpio->membase + TGPIO_ICR);
  157. for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
  158. generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
  159. }
  160. static struct irq_chip timbgpio_irqchip = {
  161. .name = "GPIO",
  162. .enable = timbgpio_irq_enable,
  163. .disable = timbgpio_irq_disable,
  164. .set_type = timbgpio_irq_type,
  165. };
  166. static int __devinit timbgpio_probe(struct platform_device *pdev)
  167. {
  168. int err, i;
  169. struct gpio_chip *gc;
  170. struct timbgpio *tgpio;
  171. struct resource *iomem;
  172. struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
  173. int irq = platform_get_irq(pdev, 0);
  174. if (!pdata || pdata->nr_pins > 32) {
  175. err = -EINVAL;
  176. goto err_mem;
  177. }
  178. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  179. if (!iomem) {
  180. err = -EINVAL;
  181. goto err_mem;
  182. }
  183. tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
  184. if (!tgpio) {
  185. err = -EINVAL;
  186. goto err_mem;
  187. }
  188. tgpio->irq_base = pdata->irq_base;
  189. spin_lock_init(&tgpio->lock);
  190. if (!request_mem_region(iomem->start, resource_size(iomem),
  191. DRIVER_NAME)) {
  192. err = -EBUSY;
  193. goto err_request;
  194. }
  195. tgpio->membase = ioremap(iomem->start, resource_size(iomem));
  196. if (!tgpio->membase) {
  197. err = -ENOMEM;
  198. goto err_ioremap;
  199. }
  200. gc = &tgpio->gpio;
  201. gc->label = dev_name(&pdev->dev);
  202. gc->owner = THIS_MODULE;
  203. gc->dev = &pdev->dev;
  204. gc->direction_input = timbgpio_gpio_direction_input;
  205. gc->get = timbgpio_gpio_get;
  206. gc->direction_output = timbgpio_gpio_direction_output;
  207. gc->set = timbgpio_gpio_set;
  208. gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
  209. gc->dbg_show = NULL;
  210. gc->base = pdata->gpio_base;
  211. gc->ngpio = pdata->nr_pins;
  212. gc->can_sleep = 0;
  213. err = gpiochip_add(gc);
  214. if (err)
  215. goto err_chipadd;
  216. platform_set_drvdata(pdev, tgpio);
  217. /* make sure to disable interrupts */
  218. iowrite32(0x0, tgpio->membase + TGPIO_IER);
  219. if (irq < 0 || tgpio->irq_base <= 0)
  220. return 0;
  221. for (i = 0; i < pdata->nr_pins; i++) {
  222. set_irq_chip_and_handler_name(tgpio->irq_base + i,
  223. &timbgpio_irqchip, handle_simple_irq, "mux");
  224. set_irq_chip_data(tgpio->irq_base + i, tgpio);
  225. #ifdef CONFIG_ARM
  226. set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
  227. #endif
  228. }
  229. set_irq_data(irq, tgpio);
  230. set_irq_chained_handler(irq, timbgpio_irq);
  231. return 0;
  232. err_chipadd:
  233. iounmap(tgpio->membase);
  234. err_ioremap:
  235. release_mem_region(iomem->start, resource_size(iomem));
  236. err_request:
  237. kfree(tgpio);
  238. err_mem:
  239. printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
  240. return err;
  241. }
  242. static int __devexit timbgpio_remove(struct platform_device *pdev)
  243. {
  244. int err;
  245. struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
  246. struct timbgpio *tgpio = platform_get_drvdata(pdev);
  247. struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  248. int irq = platform_get_irq(pdev, 0);
  249. if (irq >= 0 && tgpio->irq_base > 0) {
  250. int i;
  251. for (i = 0; i < pdata->nr_pins; i++) {
  252. set_irq_chip(tgpio->irq_base + i, NULL);
  253. set_irq_chip_data(tgpio->irq_base + i, NULL);
  254. }
  255. set_irq_handler(irq, NULL);
  256. set_irq_data(irq, NULL);
  257. }
  258. err = gpiochip_remove(&tgpio->gpio);
  259. if (err)
  260. printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
  261. iounmap(tgpio->membase);
  262. release_mem_region(iomem->start, resource_size(iomem));
  263. kfree(tgpio);
  264. platform_set_drvdata(pdev, NULL);
  265. return 0;
  266. }
  267. static struct platform_driver timbgpio_platform_driver = {
  268. .driver = {
  269. .name = DRIVER_NAME,
  270. .owner = THIS_MODULE,
  271. },
  272. .probe = timbgpio_probe,
  273. .remove = timbgpio_remove,
  274. };
  275. /*--------------------------------------------------------------------------*/
  276. static int __init timbgpio_init(void)
  277. {
  278. return platform_driver_register(&timbgpio_platform_driver);
  279. }
  280. static void __exit timbgpio_exit(void)
  281. {
  282. platform_driver_unregister(&timbgpio_platform_driver);
  283. }
  284. module_init(timbgpio_init);
  285. module_exit(timbgpio_exit);
  286. MODULE_DESCRIPTION("Timberdale GPIO driver");
  287. MODULE_LICENSE("GPL v2");
  288. MODULE_AUTHOR("Mocean Laboratories");
  289. MODULE_ALIAS("platform:"DRIVER_NAME);