mce.c 49 KB

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  1. /*
  2. * Machine check handler.
  3. *
  4. * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
  5. * Rest from unknown author(s).
  6. * 2004 Andi Kleen. Rewrote most of it.
  7. * Copyright 2008 Intel Corporation
  8. * Author: Andi Kleen
  9. */
  10. #include <linux/thread_info.h>
  11. #include <linux/capability.h>
  12. #include <linux/miscdevice.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ratelimit.h>
  15. #include <linux/kallsyms.h>
  16. #include <linux/rcupdate.h>
  17. #include <linux/kobject.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/kdebug.h>
  20. #include <linux/kernel.h>
  21. #include <linux/percpu.h>
  22. #include <linux/string.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/delay.h>
  25. #include <linux/ctype.h>
  26. #include <linux/sched.h>
  27. #include <linux/sysfs.h>
  28. #include <linux/types.h>
  29. #include <linux/init.h>
  30. #include <linux/kmod.h>
  31. #include <linux/poll.h>
  32. #include <linux/nmi.h>
  33. #include <linux/cpu.h>
  34. #include <linux/smp.h>
  35. #include <linux/fs.h>
  36. #include <linux/mm.h>
  37. #include <linux/debugfs.h>
  38. #include <asm/processor.h>
  39. #include <asm/hw_irq.h>
  40. #include <asm/apic.h>
  41. #include <asm/idle.h>
  42. #include <asm/ipi.h>
  43. #include <asm/mce.h>
  44. #include <asm/msr.h>
  45. #include "mce-internal.h"
  46. static DEFINE_MUTEX(mce_read_mutex);
  47. #define rcu_dereference_check_mce(p) \
  48. rcu_dereference_check((p), \
  49. rcu_read_lock_sched_held() || \
  50. lockdep_is_held(&mce_read_mutex))
  51. #define CREATE_TRACE_POINTS
  52. #include <trace/events/mce.h>
  53. int mce_disabled __read_mostly;
  54. #define MISC_MCELOG_MINOR 227
  55. #define SPINUNIT 100 /* 100ns */
  56. atomic_t mce_entry;
  57. DEFINE_PER_CPU(unsigned, mce_exception_count);
  58. /*
  59. * Tolerant levels:
  60. * 0: always panic on uncorrected errors, log corrected errors
  61. * 1: panic or SIGBUS on uncorrected errors, log corrected errors
  62. * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
  63. * 3: never panic or SIGBUS, log all errors (for testing only)
  64. */
  65. static int tolerant __read_mostly = 1;
  66. static int banks __read_mostly;
  67. static int rip_msr __read_mostly;
  68. static int mce_bootlog __read_mostly = -1;
  69. static int monarch_timeout __read_mostly = -1;
  70. static int mce_panic_timeout __read_mostly;
  71. static int mce_dont_log_ce __read_mostly;
  72. int mce_cmci_disabled __read_mostly;
  73. int mce_ignore_ce __read_mostly;
  74. int mce_ser __read_mostly;
  75. struct mce_bank *mce_banks __read_mostly;
  76. /* User mode helper program triggered by machine check event */
  77. static unsigned long mce_need_notify;
  78. static char mce_helper[128];
  79. static char *mce_helper_argv[2] = { mce_helper, NULL };
  80. static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
  81. static DEFINE_PER_CPU(struct mce, mces_seen);
  82. static int cpu_missing;
  83. /*
  84. * CPU/chipset specific EDAC code can register a notifier call here to print
  85. * MCE errors in a human-readable form.
  86. */
  87. ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
  88. EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
  89. static int default_decode_mce(struct notifier_block *nb, unsigned long val,
  90. void *data)
  91. {
  92. pr_emerg("No human readable MCE decoding support on this CPU type.\n");
  93. pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
  94. return NOTIFY_STOP;
  95. }
  96. static struct notifier_block mce_dec_nb = {
  97. .notifier_call = default_decode_mce,
  98. .priority = -1,
  99. };
  100. /* MCA banks polled by the period polling timer for corrected events */
  101. DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
  102. [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
  103. };
  104. static DEFINE_PER_CPU(struct work_struct, mce_work);
  105. /* Do initial initialization of a struct mce */
  106. void mce_setup(struct mce *m)
  107. {
  108. memset(m, 0, sizeof(struct mce));
  109. m->cpu = m->extcpu = smp_processor_id();
  110. rdtscll(m->tsc);
  111. /* We hope get_seconds stays lockless */
  112. m->time = get_seconds();
  113. m->cpuvendor = boot_cpu_data.x86_vendor;
  114. m->cpuid = cpuid_eax(1);
  115. #ifdef CONFIG_SMP
  116. m->socketid = cpu_data(m->extcpu).phys_proc_id;
  117. #endif
  118. m->apicid = cpu_data(m->extcpu).initial_apicid;
  119. rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
  120. }
  121. DEFINE_PER_CPU(struct mce, injectm);
  122. EXPORT_PER_CPU_SYMBOL_GPL(injectm);
  123. /*
  124. * Lockless MCE logging infrastructure.
  125. * This avoids deadlocks on printk locks without having to break locks. Also
  126. * separate MCEs from kernel messages to avoid bogus bug reports.
  127. */
  128. static struct mce_log mcelog = {
  129. .signature = MCE_LOG_SIGNATURE,
  130. .len = MCE_LOG_LEN,
  131. .recordlen = sizeof(struct mce),
  132. };
  133. void mce_log(struct mce *mce)
  134. {
  135. unsigned next, entry;
  136. /* Emit the trace record: */
  137. trace_mce_record(mce);
  138. mce->finished = 0;
  139. wmb();
  140. for (;;) {
  141. entry = rcu_dereference_check_mce(mcelog.next);
  142. for (;;) {
  143. /*
  144. * When the buffer fills up discard new entries.
  145. * Assume that the earlier errors are the more
  146. * interesting ones:
  147. */
  148. if (entry >= MCE_LOG_LEN) {
  149. set_bit(MCE_OVERFLOW,
  150. (unsigned long *)&mcelog.flags);
  151. return;
  152. }
  153. /* Old left over entry. Skip: */
  154. if (mcelog.entry[entry].finished) {
  155. entry++;
  156. continue;
  157. }
  158. break;
  159. }
  160. smp_rmb();
  161. next = entry + 1;
  162. if (cmpxchg(&mcelog.next, entry, next) == entry)
  163. break;
  164. }
  165. memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
  166. wmb();
  167. mcelog.entry[entry].finished = 1;
  168. wmb();
  169. mce->finished = 1;
  170. set_bit(0, &mce_need_notify);
  171. }
  172. static void print_mce(struct mce *m)
  173. {
  174. pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
  175. m->extcpu, m->mcgstatus, m->bank, m->status);
  176. if (m->ip) {
  177. pr_emerg("RIP%s %02x:<%016Lx> ",
  178. !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
  179. m->cs, m->ip);
  180. if (m->cs == __KERNEL_CS)
  181. print_symbol("{%s}", m->ip);
  182. pr_cont("\n");
  183. }
  184. pr_emerg("TSC %llx ", m->tsc);
  185. if (m->addr)
  186. pr_cont("ADDR %llx ", m->addr);
  187. if (m->misc)
  188. pr_cont("MISC %llx ", m->misc);
  189. pr_cont("\n");
  190. pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
  191. m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
  192. /*
  193. * Print out human-readable details about the MCE error,
  194. * (if the CPU has an implementation for that)
  195. */
  196. atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
  197. }
  198. static void print_mce_head(void)
  199. {
  200. pr_emerg("\nHARDWARE ERROR\n");
  201. }
  202. static void print_mce_tail(void)
  203. {
  204. pr_emerg("This is not a software problem!\n");
  205. }
  206. #define PANIC_TIMEOUT 5 /* 5 seconds */
  207. static atomic_t mce_paniced;
  208. static int fake_panic;
  209. static atomic_t mce_fake_paniced;
  210. /* Panic in progress. Enable interrupts and wait for final IPI */
  211. static void wait_for_panic(void)
  212. {
  213. long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
  214. preempt_disable();
  215. local_irq_enable();
  216. while (timeout-- > 0)
  217. udelay(1);
  218. if (panic_timeout == 0)
  219. panic_timeout = mce_panic_timeout;
  220. panic("Panicing machine check CPU died");
  221. }
  222. static void mce_panic(char *msg, struct mce *final, char *exp)
  223. {
  224. int i;
  225. if (!fake_panic) {
  226. /*
  227. * Make sure only one CPU runs in machine check panic
  228. */
  229. if (atomic_inc_return(&mce_paniced) > 1)
  230. wait_for_panic();
  231. barrier();
  232. bust_spinlocks(1);
  233. console_verbose();
  234. } else {
  235. /* Don't log too much for fake panic */
  236. if (atomic_inc_return(&mce_fake_paniced) > 1)
  237. return;
  238. }
  239. print_mce_head();
  240. /* First print corrected ones that are still unlogged */
  241. for (i = 0; i < MCE_LOG_LEN; i++) {
  242. struct mce *m = &mcelog.entry[i];
  243. if (!(m->status & MCI_STATUS_VAL))
  244. continue;
  245. if (!(m->status & MCI_STATUS_UC))
  246. print_mce(m);
  247. }
  248. /* Now print uncorrected but with the final one last */
  249. for (i = 0; i < MCE_LOG_LEN; i++) {
  250. struct mce *m = &mcelog.entry[i];
  251. if (!(m->status & MCI_STATUS_VAL))
  252. continue;
  253. if (!(m->status & MCI_STATUS_UC))
  254. continue;
  255. if (!final || memcmp(m, final, sizeof(struct mce)))
  256. print_mce(m);
  257. }
  258. if (final)
  259. print_mce(final);
  260. if (cpu_missing)
  261. printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
  262. print_mce_tail();
  263. if (exp)
  264. printk(KERN_EMERG "Machine check: %s\n", exp);
  265. if (!fake_panic) {
  266. if (panic_timeout == 0)
  267. panic_timeout = mce_panic_timeout;
  268. panic(msg);
  269. } else
  270. printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
  271. }
  272. /* Support code for software error injection */
  273. static int msr_to_offset(u32 msr)
  274. {
  275. unsigned bank = __get_cpu_var(injectm.bank);
  276. if (msr == rip_msr)
  277. return offsetof(struct mce, ip);
  278. if (msr == MSR_IA32_MCx_STATUS(bank))
  279. return offsetof(struct mce, status);
  280. if (msr == MSR_IA32_MCx_ADDR(bank))
  281. return offsetof(struct mce, addr);
  282. if (msr == MSR_IA32_MCx_MISC(bank))
  283. return offsetof(struct mce, misc);
  284. if (msr == MSR_IA32_MCG_STATUS)
  285. return offsetof(struct mce, mcgstatus);
  286. return -1;
  287. }
  288. /* MSR access wrappers used for error injection */
  289. static u64 mce_rdmsrl(u32 msr)
  290. {
  291. u64 v;
  292. if (__get_cpu_var(injectm).finished) {
  293. int offset = msr_to_offset(msr);
  294. if (offset < 0)
  295. return 0;
  296. return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
  297. }
  298. if (rdmsrl_safe(msr, &v)) {
  299. WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
  300. /*
  301. * Return zero in case the access faulted. This should
  302. * not happen normally but can happen if the CPU does
  303. * something weird, or if the code is buggy.
  304. */
  305. v = 0;
  306. }
  307. return v;
  308. }
  309. static void mce_wrmsrl(u32 msr, u64 v)
  310. {
  311. if (__get_cpu_var(injectm).finished) {
  312. int offset = msr_to_offset(msr);
  313. if (offset >= 0)
  314. *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
  315. return;
  316. }
  317. wrmsrl(msr, v);
  318. }
  319. /*
  320. * Simple lockless ring to communicate PFNs from the exception handler with the
  321. * process context work function. This is vastly simplified because there's
  322. * only a single reader and a single writer.
  323. */
  324. #define MCE_RING_SIZE 16 /* we use one entry less */
  325. struct mce_ring {
  326. unsigned short start;
  327. unsigned short end;
  328. unsigned long ring[MCE_RING_SIZE];
  329. };
  330. static DEFINE_PER_CPU(struct mce_ring, mce_ring);
  331. /* Runs with CPU affinity in workqueue */
  332. static int mce_ring_empty(void)
  333. {
  334. struct mce_ring *r = &__get_cpu_var(mce_ring);
  335. return r->start == r->end;
  336. }
  337. static int mce_ring_get(unsigned long *pfn)
  338. {
  339. struct mce_ring *r;
  340. int ret = 0;
  341. *pfn = 0;
  342. get_cpu();
  343. r = &__get_cpu_var(mce_ring);
  344. if (r->start == r->end)
  345. goto out;
  346. *pfn = r->ring[r->start];
  347. r->start = (r->start + 1) % MCE_RING_SIZE;
  348. ret = 1;
  349. out:
  350. put_cpu();
  351. return ret;
  352. }
  353. /* Always runs in MCE context with preempt off */
  354. static int mce_ring_add(unsigned long pfn)
  355. {
  356. struct mce_ring *r = &__get_cpu_var(mce_ring);
  357. unsigned next;
  358. next = (r->end + 1) % MCE_RING_SIZE;
  359. if (next == r->start)
  360. return -1;
  361. r->ring[r->end] = pfn;
  362. wmb();
  363. r->end = next;
  364. return 0;
  365. }
  366. int mce_available(struct cpuinfo_x86 *c)
  367. {
  368. if (mce_disabled)
  369. return 0;
  370. return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
  371. }
  372. static void mce_schedule_work(void)
  373. {
  374. if (!mce_ring_empty()) {
  375. struct work_struct *work = &__get_cpu_var(mce_work);
  376. if (!work_pending(work))
  377. schedule_work(work);
  378. }
  379. }
  380. /*
  381. * Get the address of the instruction at the time of the machine check
  382. * error.
  383. */
  384. static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
  385. {
  386. if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
  387. m->ip = regs->ip;
  388. m->cs = regs->cs;
  389. } else {
  390. m->ip = 0;
  391. m->cs = 0;
  392. }
  393. if (rip_msr)
  394. m->ip = mce_rdmsrl(rip_msr);
  395. }
  396. #ifdef CONFIG_X86_LOCAL_APIC
  397. /*
  398. * Called after interrupts have been reenabled again
  399. * when a MCE happened during an interrupts off region
  400. * in the kernel.
  401. */
  402. asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
  403. {
  404. ack_APIC_irq();
  405. exit_idle();
  406. irq_enter();
  407. mce_notify_irq();
  408. mce_schedule_work();
  409. irq_exit();
  410. }
  411. #endif
  412. static void mce_report_event(struct pt_regs *regs)
  413. {
  414. if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
  415. mce_notify_irq();
  416. /*
  417. * Triggering the work queue here is just an insurance
  418. * policy in case the syscall exit notify handler
  419. * doesn't run soon enough or ends up running on the
  420. * wrong CPU (can happen when audit sleeps)
  421. */
  422. mce_schedule_work();
  423. return;
  424. }
  425. #ifdef CONFIG_X86_LOCAL_APIC
  426. /*
  427. * Without APIC do not notify. The event will be picked
  428. * up eventually.
  429. */
  430. if (!cpu_has_apic)
  431. return;
  432. /*
  433. * When interrupts are disabled we cannot use
  434. * kernel services safely. Trigger an self interrupt
  435. * through the APIC to instead do the notification
  436. * after interrupts are reenabled again.
  437. */
  438. apic->send_IPI_self(MCE_SELF_VECTOR);
  439. /*
  440. * Wait for idle afterwards again so that we don't leave the
  441. * APIC in a non idle state because the normal APIC writes
  442. * cannot exclude us.
  443. */
  444. apic_wait_icr_idle();
  445. #endif
  446. }
  447. DEFINE_PER_CPU(unsigned, mce_poll_count);
  448. /*
  449. * Poll for corrected events or events that happened before reset.
  450. * Those are just logged through /dev/mcelog.
  451. *
  452. * This is executed in standard interrupt context.
  453. *
  454. * Note: spec recommends to panic for fatal unsignalled
  455. * errors here. However this would be quite problematic --
  456. * we would need to reimplement the Monarch handling and
  457. * it would mess up the exclusion between exception handler
  458. * and poll hander -- * so we skip this for now.
  459. * These cases should not happen anyways, or only when the CPU
  460. * is already totally * confused. In this case it's likely it will
  461. * not fully execute the machine check handler either.
  462. */
  463. void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
  464. {
  465. struct mce m;
  466. int i;
  467. __get_cpu_var(mce_poll_count)++;
  468. mce_setup(&m);
  469. m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
  470. for (i = 0; i < banks; i++) {
  471. if (!mce_banks[i].ctl || !test_bit(i, *b))
  472. continue;
  473. m.misc = 0;
  474. m.addr = 0;
  475. m.bank = i;
  476. m.tsc = 0;
  477. barrier();
  478. m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
  479. if (!(m.status & MCI_STATUS_VAL))
  480. continue;
  481. /*
  482. * Uncorrected or signalled events are handled by the exception
  483. * handler when it is enabled, so don't process those here.
  484. *
  485. * TBD do the same check for MCI_STATUS_EN here?
  486. */
  487. if (!(flags & MCP_UC) &&
  488. (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
  489. continue;
  490. if (m.status & MCI_STATUS_MISCV)
  491. m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
  492. if (m.status & MCI_STATUS_ADDRV)
  493. m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
  494. if (!(flags & MCP_TIMESTAMP))
  495. m.tsc = 0;
  496. /*
  497. * Don't get the IP here because it's unlikely to
  498. * have anything to do with the actual error location.
  499. */
  500. if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
  501. mce_log(&m);
  502. add_taint(TAINT_MACHINE_CHECK);
  503. }
  504. /*
  505. * Clear state for this bank.
  506. */
  507. mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
  508. }
  509. /*
  510. * Don't clear MCG_STATUS here because it's only defined for
  511. * exceptions.
  512. */
  513. sync_core();
  514. }
  515. EXPORT_SYMBOL_GPL(machine_check_poll);
  516. /*
  517. * Do a quick check if any of the events requires a panic.
  518. * This decides if we keep the events around or clear them.
  519. */
  520. static int mce_no_way_out(struct mce *m, char **msg)
  521. {
  522. int i;
  523. for (i = 0; i < banks; i++) {
  524. m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
  525. if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
  526. return 1;
  527. }
  528. return 0;
  529. }
  530. /*
  531. * Variable to establish order between CPUs while scanning.
  532. * Each CPU spins initially until executing is equal its number.
  533. */
  534. static atomic_t mce_executing;
  535. /*
  536. * Defines order of CPUs on entry. First CPU becomes Monarch.
  537. */
  538. static atomic_t mce_callin;
  539. /*
  540. * Check if a timeout waiting for other CPUs happened.
  541. */
  542. static int mce_timed_out(u64 *t)
  543. {
  544. /*
  545. * The others already did panic for some reason.
  546. * Bail out like in a timeout.
  547. * rmb() to tell the compiler that system_state
  548. * might have been modified by someone else.
  549. */
  550. rmb();
  551. if (atomic_read(&mce_paniced))
  552. wait_for_panic();
  553. if (!monarch_timeout)
  554. goto out;
  555. if ((s64)*t < SPINUNIT) {
  556. /* CHECKME: Make panic default for 1 too? */
  557. if (tolerant < 1)
  558. mce_panic("Timeout synchronizing machine check over CPUs",
  559. NULL, NULL);
  560. cpu_missing = 1;
  561. return 1;
  562. }
  563. *t -= SPINUNIT;
  564. out:
  565. touch_nmi_watchdog();
  566. return 0;
  567. }
  568. /*
  569. * The Monarch's reign. The Monarch is the CPU who entered
  570. * the machine check handler first. It waits for the others to
  571. * raise the exception too and then grades them. When any
  572. * error is fatal panic. Only then let the others continue.
  573. *
  574. * The other CPUs entering the MCE handler will be controlled by the
  575. * Monarch. They are called Subjects.
  576. *
  577. * This way we prevent any potential data corruption in a unrecoverable case
  578. * and also makes sure always all CPU's errors are examined.
  579. *
  580. * Also this detects the case of a machine check event coming from outer
  581. * space (not detected by any CPUs) In this case some external agent wants
  582. * us to shut down, so panic too.
  583. *
  584. * The other CPUs might still decide to panic if the handler happens
  585. * in a unrecoverable place, but in this case the system is in a semi-stable
  586. * state and won't corrupt anything by itself. It's ok to let the others
  587. * continue for a bit first.
  588. *
  589. * All the spin loops have timeouts; when a timeout happens a CPU
  590. * typically elects itself to be Monarch.
  591. */
  592. static void mce_reign(void)
  593. {
  594. int cpu;
  595. struct mce *m = NULL;
  596. int global_worst = 0;
  597. char *msg = NULL;
  598. char *nmsg = NULL;
  599. /*
  600. * This CPU is the Monarch and the other CPUs have run
  601. * through their handlers.
  602. * Grade the severity of the errors of all the CPUs.
  603. */
  604. for_each_possible_cpu(cpu) {
  605. int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
  606. &nmsg);
  607. if (severity > global_worst) {
  608. msg = nmsg;
  609. global_worst = severity;
  610. m = &per_cpu(mces_seen, cpu);
  611. }
  612. }
  613. /*
  614. * Cannot recover? Panic here then.
  615. * This dumps all the mces in the log buffer and stops the
  616. * other CPUs.
  617. */
  618. if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
  619. mce_panic("Fatal Machine check", m, msg);
  620. /*
  621. * For UC somewhere we let the CPU who detects it handle it.
  622. * Also must let continue the others, otherwise the handling
  623. * CPU could deadlock on a lock.
  624. */
  625. /*
  626. * No machine check event found. Must be some external
  627. * source or one CPU is hung. Panic.
  628. */
  629. if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
  630. mce_panic("Machine check from unknown source", NULL, NULL);
  631. /*
  632. * Now clear all the mces_seen so that they don't reappear on
  633. * the next mce.
  634. */
  635. for_each_possible_cpu(cpu)
  636. memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
  637. }
  638. static atomic_t global_nwo;
  639. /*
  640. * Start of Monarch synchronization. This waits until all CPUs have
  641. * entered the exception handler and then determines if any of them
  642. * saw a fatal event that requires panic. Then it executes them
  643. * in the entry order.
  644. * TBD double check parallel CPU hotunplug
  645. */
  646. static int mce_start(int *no_way_out)
  647. {
  648. int order;
  649. int cpus = num_online_cpus();
  650. u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
  651. if (!timeout)
  652. return -1;
  653. atomic_add(*no_way_out, &global_nwo);
  654. /*
  655. * global_nwo should be updated before mce_callin
  656. */
  657. smp_wmb();
  658. order = atomic_inc_return(&mce_callin);
  659. /*
  660. * Wait for everyone.
  661. */
  662. while (atomic_read(&mce_callin) != cpus) {
  663. if (mce_timed_out(&timeout)) {
  664. atomic_set(&global_nwo, 0);
  665. return -1;
  666. }
  667. ndelay(SPINUNIT);
  668. }
  669. /*
  670. * mce_callin should be read before global_nwo
  671. */
  672. smp_rmb();
  673. if (order == 1) {
  674. /*
  675. * Monarch: Starts executing now, the others wait.
  676. */
  677. atomic_set(&mce_executing, 1);
  678. } else {
  679. /*
  680. * Subject: Now start the scanning loop one by one in
  681. * the original callin order.
  682. * This way when there are any shared banks it will be
  683. * only seen by one CPU before cleared, avoiding duplicates.
  684. */
  685. while (atomic_read(&mce_executing) < order) {
  686. if (mce_timed_out(&timeout)) {
  687. atomic_set(&global_nwo, 0);
  688. return -1;
  689. }
  690. ndelay(SPINUNIT);
  691. }
  692. }
  693. /*
  694. * Cache the global no_way_out state.
  695. */
  696. *no_way_out = atomic_read(&global_nwo);
  697. return order;
  698. }
  699. /*
  700. * Synchronize between CPUs after main scanning loop.
  701. * This invokes the bulk of the Monarch processing.
  702. */
  703. static int mce_end(int order)
  704. {
  705. int ret = -1;
  706. u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
  707. if (!timeout)
  708. goto reset;
  709. if (order < 0)
  710. goto reset;
  711. /*
  712. * Allow others to run.
  713. */
  714. atomic_inc(&mce_executing);
  715. if (order == 1) {
  716. /* CHECKME: Can this race with a parallel hotplug? */
  717. int cpus = num_online_cpus();
  718. /*
  719. * Monarch: Wait for everyone to go through their scanning
  720. * loops.
  721. */
  722. while (atomic_read(&mce_executing) <= cpus) {
  723. if (mce_timed_out(&timeout))
  724. goto reset;
  725. ndelay(SPINUNIT);
  726. }
  727. mce_reign();
  728. barrier();
  729. ret = 0;
  730. } else {
  731. /*
  732. * Subject: Wait for Monarch to finish.
  733. */
  734. while (atomic_read(&mce_executing) != 0) {
  735. if (mce_timed_out(&timeout))
  736. goto reset;
  737. ndelay(SPINUNIT);
  738. }
  739. /*
  740. * Don't reset anything. That's done by the Monarch.
  741. */
  742. return 0;
  743. }
  744. /*
  745. * Reset all global state.
  746. */
  747. reset:
  748. atomic_set(&global_nwo, 0);
  749. atomic_set(&mce_callin, 0);
  750. barrier();
  751. /*
  752. * Let others run again.
  753. */
  754. atomic_set(&mce_executing, 0);
  755. return ret;
  756. }
  757. /*
  758. * Check if the address reported by the CPU is in a format we can parse.
  759. * It would be possible to add code for most other cases, but all would
  760. * be somewhat complicated (e.g. segment offset would require an instruction
  761. * parser). So only support physical addresses upto page granuality for now.
  762. */
  763. static int mce_usable_address(struct mce *m)
  764. {
  765. if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
  766. return 0;
  767. if ((m->misc & 0x3f) > PAGE_SHIFT)
  768. return 0;
  769. if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
  770. return 0;
  771. return 1;
  772. }
  773. static void mce_clear_state(unsigned long *toclear)
  774. {
  775. int i;
  776. for (i = 0; i < banks; i++) {
  777. if (test_bit(i, toclear))
  778. mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
  779. }
  780. }
  781. /*
  782. * The actual machine check handler. This only handles real
  783. * exceptions when something got corrupted coming in through int 18.
  784. *
  785. * This is executed in NMI context not subject to normal locking rules. This
  786. * implies that most kernel services cannot be safely used. Don't even
  787. * think about putting a printk in there!
  788. *
  789. * On Intel systems this is entered on all CPUs in parallel through
  790. * MCE broadcast. However some CPUs might be broken beyond repair,
  791. * so be always careful when synchronizing with others.
  792. */
  793. void do_machine_check(struct pt_regs *regs, long error_code)
  794. {
  795. struct mce m, *final;
  796. int i;
  797. int worst = 0;
  798. int severity;
  799. /*
  800. * Establish sequential order between the CPUs entering the machine
  801. * check handler.
  802. */
  803. int order;
  804. /*
  805. * If no_way_out gets set, there is no safe way to recover from this
  806. * MCE. If tolerant is cranked up, we'll try anyway.
  807. */
  808. int no_way_out = 0;
  809. /*
  810. * If kill_it gets set, there might be a way to recover from this
  811. * error.
  812. */
  813. int kill_it = 0;
  814. DECLARE_BITMAP(toclear, MAX_NR_BANKS);
  815. char *msg = "Unknown";
  816. atomic_inc(&mce_entry);
  817. __get_cpu_var(mce_exception_count)++;
  818. if (notify_die(DIE_NMI, "machine check", regs, error_code,
  819. 18, SIGKILL) == NOTIFY_STOP)
  820. goto out;
  821. if (!banks)
  822. goto out;
  823. mce_setup(&m);
  824. m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
  825. final = &__get_cpu_var(mces_seen);
  826. *final = m;
  827. no_way_out = mce_no_way_out(&m, &msg);
  828. barrier();
  829. /*
  830. * When no restart IP must always kill or panic.
  831. */
  832. if (!(m.mcgstatus & MCG_STATUS_RIPV))
  833. kill_it = 1;
  834. /*
  835. * Go through all the banks in exclusion of the other CPUs.
  836. * This way we don't report duplicated events on shared banks
  837. * because the first one to see it will clear it.
  838. */
  839. order = mce_start(&no_way_out);
  840. for (i = 0; i < banks; i++) {
  841. __clear_bit(i, toclear);
  842. if (!mce_banks[i].ctl)
  843. continue;
  844. m.misc = 0;
  845. m.addr = 0;
  846. m.bank = i;
  847. m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
  848. if ((m.status & MCI_STATUS_VAL) == 0)
  849. continue;
  850. /*
  851. * Non uncorrected or non signaled errors are handled by
  852. * machine_check_poll. Leave them alone, unless this panics.
  853. */
  854. if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
  855. !no_way_out)
  856. continue;
  857. /*
  858. * Set taint even when machine check was not enabled.
  859. */
  860. add_taint(TAINT_MACHINE_CHECK);
  861. severity = mce_severity(&m, tolerant, NULL);
  862. /*
  863. * When machine check was for corrected handler don't touch,
  864. * unless we're panicing.
  865. */
  866. if (severity == MCE_KEEP_SEVERITY && !no_way_out)
  867. continue;
  868. __set_bit(i, toclear);
  869. if (severity == MCE_NO_SEVERITY) {
  870. /*
  871. * Machine check event was not enabled. Clear, but
  872. * ignore.
  873. */
  874. continue;
  875. }
  876. /*
  877. * Kill on action required.
  878. */
  879. if (severity == MCE_AR_SEVERITY)
  880. kill_it = 1;
  881. if (m.status & MCI_STATUS_MISCV)
  882. m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
  883. if (m.status & MCI_STATUS_ADDRV)
  884. m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
  885. /*
  886. * Action optional error. Queue address for later processing.
  887. * When the ring overflows we just ignore the AO error.
  888. * RED-PEN add some logging mechanism when
  889. * usable_address or mce_add_ring fails.
  890. * RED-PEN don't ignore overflow for tolerant == 0
  891. */
  892. if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
  893. mce_ring_add(m.addr >> PAGE_SHIFT);
  894. mce_get_rip(&m, regs);
  895. mce_log(&m);
  896. if (severity > worst) {
  897. *final = m;
  898. worst = severity;
  899. }
  900. }
  901. if (!no_way_out)
  902. mce_clear_state(toclear);
  903. /*
  904. * Do most of the synchronization with other CPUs.
  905. * When there's any problem use only local no_way_out state.
  906. */
  907. if (mce_end(order) < 0)
  908. no_way_out = worst >= MCE_PANIC_SEVERITY;
  909. /*
  910. * If we have decided that we just CAN'T continue, and the user
  911. * has not set tolerant to an insane level, give up and die.
  912. *
  913. * This is mainly used in the case when the system doesn't
  914. * support MCE broadcasting or it has been disabled.
  915. */
  916. if (no_way_out && tolerant < 3)
  917. mce_panic("Fatal machine check on current CPU", final, msg);
  918. /*
  919. * If the error seems to be unrecoverable, something should be
  920. * done. Try to kill as little as possible. If we can kill just
  921. * one task, do that. If the user has set the tolerance very
  922. * high, don't try to do anything at all.
  923. */
  924. if (kill_it && tolerant < 3)
  925. force_sig(SIGBUS, current);
  926. /* notify userspace ASAP */
  927. set_thread_flag(TIF_MCE_NOTIFY);
  928. if (worst > 0)
  929. mce_report_event(regs);
  930. mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
  931. out:
  932. atomic_dec(&mce_entry);
  933. sync_core();
  934. }
  935. EXPORT_SYMBOL_GPL(do_machine_check);
  936. /* dummy to break dependency. actual code is in mm/memory-failure.c */
  937. void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
  938. {
  939. printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
  940. }
  941. /*
  942. * Called after mce notification in process context. This code
  943. * is allowed to sleep. Call the high level VM handler to process
  944. * any corrupted pages.
  945. * Assume that the work queue code only calls this one at a time
  946. * per CPU.
  947. * Note we don't disable preemption, so this code might run on the wrong
  948. * CPU. In this case the event is picked up by the scheduled work queue.
  949. * This is merely a fast path to expedite processing in some common
  950. * cases.
  951. */
  952. void mce_notify_process(void)
  953. {
  954. unsigned long pfn;
  955. mce_notify_irq();
  956. while (mce_ring_get(&pfn))
  957. memory_failure(pfn, MCE_VECTOR);
  958. }
  959. static void mce_process_work(struct work_struct *dummy)
  960. {
  961. mce_notify_process();
  962. }
  963. #ifdef CONFIG_X86_MCE_INTEL
  964. /***
  965. * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
  966. * @cpu: The CPU on which the event occurred.
  967. * @status: Event status information
  968. *
  969. * This function should be called by the thermal interrupt after the
  970. * event has been processed and the decision was made to log the event
  971. * further.
  972. *
  973. * The status parameter will be saved to the 'status' field of 'struct mce'
  974. * and historically has been the register value of the
  975. * MSR_IA32_THERMAL_STATUS (Intel) msr.
  976. */
  977. void mce_log_therm_throt_event(__u64 status)
  978. {
  979. struct mce m;
  980. mce_setup(&m);
  981. m.bank = MCE_THERMAL_BANK;
  982. m.status = status;
  983. mce_log(&m);
  984. }
  985. #endif /* CONFIG_X86_MCE_INTEL */
  986. /*
  987. * Periodic polling timer for "silent" machine check errors. If the
  988. * poller finds an MCE, poll 2x faster. When the poller finds no more
  989. * errors, poll 2x slower (up to check_interval seconds).
  990. */
  991. static int check_interval = 5 * 60; /* 5 minutes */
  992. static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
  993. static DEFINE_PER_CPU(struct timer_list, mce_timer);
  994. static void mce_start_timer(unsigned long data)
  995. {
  996. struct timer_list *t = &per_cpu(mce_timer, data);
  997. int *n;
  998. WARN_ON(smp_processor_id() != data);
  999. if (mce_available(&current_cpu_data)) {
  1000. machine_check_poll(MCP_TIMESTAMP,
  1001. &__get_cpu_var(mce_poll_banks));
  1002. }
  1003. /*
  1004. * Alert userspace if needed. If we logged an MCE, reduce the
  1005. * polling interval, otherwise increase the polling interval.
  1006. */
  1007. n = &__get_cpu_var(mce_next_interval);
  1008. if (mce_notify_irq())
  1009. *n = max(*n/2, HZ/100);
  1010. else
  1011. *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
  1012. t->expires = jiffies + *n;
  1013. add_timer_on(t, smp_processor_id());
  1014. }
  1015. static void mce_do_trigger(struct work_struct *work)
  1016. {
  1017. call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
  1018. }
  1019. static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
  1020. /*
  1021. * Notify the user(s) about new machine check events.
  1022. * Can be called from interrupt context, but not from machine check/NMI
  1023. * context.
  1024. */
  1025. int mce_notify_irq(void)
  1026. {
  1027. /* Not more than two messages every minute */
  1028. static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
  1029. clear_thread_flag(TIF_MCE_NOTIFY);
  1030. if (test_and_clear_bit(0, &mce_need_notify)) {
  1031. wake_up_interruptible(&mce_wait);
  1032. /*
  1033. * There is no risk of missing notifications because
  1034. * work_pending is always cleared before the function is
  1035. * executed.
  1036. */
  1037. if (mce_helper[0] && !work_pending(&mce_trigger_work))
  1038. schedule_work(&mce_trigger_work);
  1039. if (__ratelimit(&ratelimit))
  1040. printk(KERN_INFO "Machine check events logged\n");
  1041. return 1;
  1042. }
  1043. return 0;
  1044. }
  1045. EXPORT_SYMBOL_GPL(mce_notify_irq);
  1046. static int __cpuinit __mcheck_cpu_mce_banks_init(void)
  1047. {
  1048. int i;
  1049. mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
  1050. if (!mce_banks)
  1051. return -ENOMEM;
  1052. for (i = 0; i < banks; i++) {
  1053. struct mce_bank *b = &mce_banks[i];
  1054. b->ctl = -1ULL;
  1055. b->init = 1;
  1056. }
  1057. return 0;
  1058. }
  1059. /*
  1060. * Initialize Machine Checks for a CPU.
  1061. */
  1062. static int __cpuinit __mcheck_cpu_cap_init(void)
  1063. {
  1064. unsigned b;
  1065. u64 cap;
  1066. rdmsrl(MSR_IA32_MCG_CAP, cap);
  1067. b = cap & MCG_BANKCNT_MASK;
  1068. if (!banks)
  1069. printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
  1070. if (b > MAX_NR_BANKS) {
  1071. printk(KERN_WARNING
  1072. "MCE: Using only %u machine check banks out of %u\n",
  1073. MAX_NR_BANKS, b);
  1074. b = MAX_NR_BANKS;
  1075. }
  1076. /* Don't support asymmetric configurations today */
  1077. WARN_ON(banks != 0 && b != banks);
  1078. banks = b;
  1079. if (!mce_banks) {
  1080. int err = __mcheck_cpu_mce_banks_init();
  1081. if (err)
  1082. return err;
  1083. }
  1084. /* Use accurate RIP reporting if available. */
  1085. if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
  1086. rip_msr = MSR_IA32_MCG_EIP;
  1087. if (cap & MCG_SER_P)
  1088. mce_ser = 1;
  1089. return 0;
  1090. }
  1091. static void __mcheck_cpu_init_generic(void)
  1092. {
  1093. mce_banks_t all_banks;
  1094. u64 cap;
  1095. int i;
  1096. /*
  1097. * Log the machine checks left over from the previous reset.
  1098. */
  1099. bitmap_fill(all_banks, MAX_NR_BANKS);
  1100. machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
  1101. set_in_cr4(X86_CR4_MCE);
  1102. rdmsrl(MSR_IA32_MCG_CAP, cap);
  1103. if (cap & MCG_CTL_P)
  1104. wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
  1105. for (i = 0; i < banks; i++) {
  1106. struct mce_bank *b = &mce_banks[i];
  1107. if (!b->init)
  1108. continue;
  1109. wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
  1110. wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
  1111. }
  1112. }
  1113. /* Add per CPU specific workarounds here */
  1114. static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
  1115. {
  1116. if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
  1117. pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
  1118. return -EOPNOTSUPP;
  1119. }
  1120. /* This should be disabled by the BIOS, but isn't always */
  1121. if (c->x86_vendor == X86_VENDOR_AMD) {
  1122. if (c->x86 == 15 && banks > 4) {
  1123. /*
  1124. * disable GART TBL walk error reporting, which
  1125. * trips off incorrectly with the IOMMU & 3ware
  1126. * & Cerberus:
  1127. */
  1128. clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
  1129. }
  1130. if (c->x86 <= 17 && mce_bootlog < 0) {
  1131. /*
  1132. * Lots of broken BIOS around that don't clear them
  1133. * by default and leave crap in there. Don't log:
  1134. */
  1135. mce_bootlog = 0;
  1136. }
  1137. /*
  1138. * Various K7s with broken bank 0 around. Always disable
  1139. * by default.
  1140. */
  1141. if (c->x86 == 6 && banks > 0)
  1142. mce_banks[0].ctl = 0;
  1143. }
  1144. if (c->x86_vendor == X86_VENDOR_INTEL) {
  1145. /*
  1146. * SDM documents that on family 6 bank 0 should not be written
  1147. * because it aliases to another special BIOS controlled
  1148. * register.
  1149. * But it's not aliased anymore on model 0x1a+
  1150. * Don't ignore bank 0 completely because there could be a
  1151. * valid event later, merely don't write CTL0.
  1152. */
  1153. if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
  1154. mce_banks[0].init = 0;
  1155. /*
  1156. * All newer Intel systems support MCE broadcasting. Enable
  1157. * synchronization with a one second timeout.
  1158. */
  1159. if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
  1160. monarch_timeout < 0)
  1161. monarch_timeout = USEC_PER_SEC;
  1162. /*
  1163. * There are also broken BIOSes on some Pentium M and
  1164. * earlier systems:
  1165. */
  1166. if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
  1167. mce_bootlog = 0;
  1168. }
  1169. if (monarch_timeout < 0)
  1170. monarch_timeout = 0;
  1171. if (mce_bootlog != 0)
  1172. mce_panic_timeout = 30;
  1173. return 0;
  1174. }
  1175. static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
  1176. {
  1177. if (c->x86 != 5)
  1178. return;
  1179. switch (c->x86_vendor) {
  1180. case X86_VENDOR_INTEL:
  1181. intel_p5_mcheck_init(c);
  1182. break;
  1183. case X86_VENDOR_CENTAUR:
  1184. winchip_mcheck_init(c);
  1185. break;
  1186. }
  1187. }
  1188. static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
  1189. {
  1190. switch (c->x86_vendor) {
  1191. case X86_VENDOR_INTEL:
  1192. mce_intel_feature_init(c);
  1193. break;
  1194. case X86_VENDOR_AMD:
  1195. mce_amd_feature_init(c);
  1196. break;
  1197. default:
  1198. break;
  1199. }
  1200. }
  1201. static void __mcheck_cpu_init_timer(void)
  1202. {
  1203. struct timer_list *t = &__get_cpu_var(mce_timer);
  1204. int *n = &__get_cpu_var(mce_next_interval);
  1205. setup_timer(t, mce_start_timer, smp_processor_id());
  1206. if (mce_ignore_ce)
  1207. return;
  1208. *n = check_interval * HZ;
  1209. if (!*n)
  1210. return;
  1211. t->expires = round_jiffies(jiffies + *n);
  1212. add_timer_on(t, smp_processor_id());
  1213. }
  1214. /* Handle unconfigured int18 (should never happen) */
  1215. static void unexpected_machine_check(struct pt_regs *regs, long error_code)
  1216. {
  1217. printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
  1218. smp_processor_id());
  1219. }
  1220. /* Call the installed machine check handler for this CPU setup. */
  1221. void (*machine_check_vector)(struct pt_regs *, long error_code) =
  1222. unexpected_machine_check;
  1223. /*
  1224. * Called for each booted CPU to set up machine checks.
  1225. * Must be called with preempt off:
  1226. */
  1227. void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
  1228. {
  1229. if (mce_disabled)
  1230. return;
  1231. __mcheck_cpu_ancient_init(c);
  1232. if (!mce_available(c))
  1233. return;
  1234. if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
  1235. mce_disabled = 1;
  1236. return;
  1237. }
  1238. machine_check_vector = do_machine_check;
  1239. __mcheck_cpu_init_generic();
  1240. __mcheck_cpu_init_vendor(c);
  1241. __mcheck_cpu_init_timer();
  1242. INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
  1243. }
  1244. /*
  1245. * Character device to read and clear the MCE log.
  1246. */
  1247. static DEFINE_SPINLOCK(mce_state_lock);
  1248. static int open_count; /* #times opened */
  1249. static int open_exclu; /* already open exclusive? */
  1250. static int mce_open(struct inode *inode, struct file *file)
  1251. {
  1252. spin_lock(&mce_state_lock);
  1253. if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
  1254. spin_unlock(&mce_state_lock);
  1255. return -EBUSY;
  1256. }
  1257. if (file->f_flags & O_EXCL)
  1258. open_exclu = 1;
  1259. open_count++;
  1260. spin_unlock(&mce_state_lock);
  1261. return nonseekable_open(inode, file);
  1262. }
  1263. static int mce_release(struct inode *inode, struct file *file)
  1264. {
  1265. spin_lock(&mce_state_lock);
  1266. open_count--;
  1267. open_exclu = 0;
  1268. spin_unlock(&mce_state_lock);
  1269. return 0;
  1270. }
  1271. static void collect_tscs(void *data)
  1272. {
  1273. unsigned long *cpu_tsc = (unsigned long *)data;
  1274. rdtscll(cpu_tsc[smp_processor_id()]);
  1275. }
  1276. static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
  1277. loff_t *off)
  1278. {
  1279. char __user *buf = ubuf;
  1280. unsigned long *cpu_tsc;
  1281. unsigned prev, next;
  1282. int i, err;
  1283. cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
  1284. if (!cpu_tsc)
  1285. return -ENOMEM;
  1286. mutex_lock(&mce_read_mutex);
  1287. next = rcu_dereference_check_mce(mcelog.next);
  1288. /* Only supports full reads right now */
  1289. if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
  1290. mutex_unlock(&mce_read_mutex);
  1291. kfree(cpu_tsc);
  1292. return -EINVAL;
  1293. }
  1294. err = 0;
  1295. prev = 0;
  1296. do {
  1297. for (i = prev; i < next; i++) {
  1298. unsigned long start = jiffies;
  1299. while (!mcelog.entry[i].finished) {
  1300. if (time_after_eq(jiffies, start + 2)) {
  1301. memset(mcelog.entry + i, 0,
  1302. sizeof(struct mce));
  1303. goto timeout;
  1304. }
  1305. cpu_relax();
  1306. }
  1307. smp_rmb();
  1308. err |= copy_to_user(buf, mcelog.entry + i,
  1309. sizeof(struct mce));
  1310. buf += sizeof(struct mce);
  1311. timeout:
  1312. ;
  1313. }
  1314. memset(mcelog.entry + prev, 0,
  1315. (next - prev) * sizeof(struct mce));
  1316. prev = next;
  1317. next = cmpxchg(&mcelog.next, prev, 0);
  1318. } while (next != prev);
  1319. synchronize_sched();
  1320. /*
  1321. * Collect entries that were still getting written before the
  1322. * synchronize.
  1323. */
  1324. on_each_cpu(collect_tscs, cpu_tsc, 1);
  1325. for (i = next; i < MCE_LOG_LEN; i++) {
  1326. if (mcelog.entry[i].finished &&
  1327. mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
  1328. err |= copy_to_user(buf, mcelog.entry+i,
  1329. sizeof(struct mce));
  1330. smp_rmb();
  1331. buf += sizeof(struct mce);
  1332. memset(&mcelog.entry[i], 0, sizeof(struct mce));
  1333. }
  1334. }
  1335. mutex_unlock(&mce_read_mutex);
  1336. kfree(cpu_tsc);
  1337. return err ? -EFAULT : buf - ubuf;
  1338. }
  1339. static unsigned int mce_poll(struct file *file, poll_table *wait)
  1340. {
  1341. poll_wait(file, &mce_wait, wait);
  1342. if (rcu_dereference_check_mce(mcelog.next))
  1343. return POLLIN | POLLRDNORM;
  1344. return 0;
  1345. }
  1346. static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
  1347. {
  1348. int __user *p = (int __user *)arg;
  1349. if (!capable(CAP_SYS_ADMIN))
  1350. return -EPERM;
  1351. switch (cmd) {
  1352. case MCE_GET_RECORD_LEN:
  1353. return put_user(sizeof(struct mce), p);
  1354. case MCE_GET_LOG_LEN:
  1355. return put_user(MCE_LOG_LEN, p);
  1356. case MCE_GETCLEAR_FLAGS: {
  1357. unsigned flags;
  1358. do {
  1359. flags = mcelog.flags;
  1360. } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
  1361. return put_user(flags, p);
  1362. }
  1363. default:
  1364. return -ENOTTY;
  1365. }
  1366. }
  1367. /* Modified in mce-inject.c, so not static or const */
  1368. struct file_operations mce_chrdev_ops = {
  1369. .open = mce_open,
  1370. .release = mce_release,
  1371. .read = mce_read,
  1372. .poll = mce_poll,
  1373. .unlocked_ioctl = mce_ioctl,
  1374. };
  1375. EXPORT_SYMBOL_GPL(mce_chrdev_ops);
  1376. static struct miscdevice mce_log_device = {
  1377. MISC_MCELOG_MINOR,
  1378. "mcelog",
  1379. &mce_chrdev_ops,
  1380. };
  1381. /*
  1382. * mce=off Disables machine check
  1383. * mce=no_cmci Disables CMCI
  1384. * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
  1385. * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
  1386. * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
  1387. * monarchtimeout is how long to wait for other CPUs on machine
  1388. * check, or 0 to not wait
  1389. * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
  1390. * mce=nobootlog Don't log MCEs from before booting.
  1391. */
  1392. static int __init mcheck_enable(char *str)
  1393. {
  1394. if (*str == 0) {
  1395. enable_p5_mce();
  1396. return 1;
  1397. }
  1398. if (*str == '=')
  1399. str++;
  1400. if (!strcmp(str, "off"))
  1401. mce_disabled = 1;
  1402. else if (!strcmp(str, "no_cmci"))
  1403. mce_cmci_disabled = 1;
  1404. else if (!strcmp(str, "dont_log_ce"))
  1405. mce_dont_log_ce = 1;
  1406. else if (!strcmp(str, "ignore_ce"))
  1407. mce_ignore_ce = 1;
  1408. else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
  1409. mce_bootlog = (str[0] == 'b');
  1410. else if (isdigit(str[0])) {
  1411. get_option(&str, &tolerant);
  1412. if (*str == ',') {
  1413. ++str;
  1414. get_option(&str, &monarch_timeout);
  1415. }
  1416. } else {
  1417. printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
  1418. str);
  1419. return 0;
  1420. }
  1421. return 1;
  1422. }
  1423. __setup("mce", mcheck_enable);
  1424. int __init mcheck_init(void)
  1425. {
  1426. atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
  1427. mcheck_intel_therm_init();
  1428. return 0;
  1429. }
  1430. /*
  1431. * Sysfs support
  1432. */
  1433. /*
  1434. * Disable machine checks on suspend and shutdown. We can't really handle
  1435. * them later.
  1436. */
  1437. static int mce_disable_error_reporting(void)
  1438. {
  1439. int i;
  1440. for (i = 0; i < banks; i++) {
  1441. struct mce_bank *b = &mce_banks[i];
  1442. if (b->init)
  1443. wrmsrl(MSR_IA32_MCx_CTL(i), 0);
  1444. }
  1445. return 0;
  1446. }
  1447. static int mce_suspend(struct sys_device *dev, pm_message_t state)
  1448. {
  1449. return mce_disable_error_reporting();
  1450. }
  1451. static int mce_shutdown(struct sys_device *dev)
  1452. {
  1453. return mce_disable_error_reporting();
  1454. }
  1455. /*
  1456. * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
  1457. * Only one CPU is active at this time, the others get re-added later using
  1458. * CPU hotplug:
  1459. */
  1460. static int mce_resume(struct sys_device *dev)
  1461. {
  1462. __mcheck_cpu_init_generic();
  1463. __mcheck_cpu_init_vendor(&current_cpu_data);
  1464. return 0;
  1465. }
  1466. static void mce_cpu_restart(void *data)
  1467. {
  1468. del_timer_sync(&__get_cpu_var(mce_timer));
  1469. if (!mce_available(&current_cpu_data))
  1470. return;
  1471. __mcheck_cpu_init_generic();
  1472. __mcheck_cpu_init_timer();
  1473. }
  1474. /* Reinit MCEs after user configuration changes */
  1475. static void mce_restart(void)
  1476. {
  1477. on_each_cpu(mce_cpu_restart, NULL, 1);
  1478. }
  1479. /* Toggle features for corrected errors */
  1480. static void mce_disable_ce(void *all)
  1481. {
  1482. if (!mce_available(&current_cpu_data))
  1483. return;
  1484. if (all)
  1485. del_timer_sync(&__get_cpu_var(mce_timer));
  1486. cmci_clear();
  1487. }
  1488. static void mce_enable_ce(void *all)
  1489. {
  1490. if (!mce_available(&current_cpu_data))
  1491. return;
  1492. cmci_reenable();
  1493. cmci_recheck();
  1494. if (all)
  1495. __mcheck_cpu_init_timer();
  1496. }
  1497. static struct sysdev_class mce_sysclass = {
  1498. .suspend = mce_suspend,
  1499. .shutdown = mce_shutdown,
  1500. .resume = mce_resume,
  1501. .name = "machinecheck",
  1502. };
  1503. DEFINE_PER_CPU(struct sys_device, mce_dev);
  1504. __cpuinitdata
  1505. void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
  1506. static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
  1507. {
  1508. return container_of(attr, struct mce_bank, attr);
  1509. }
  1510. static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
  1511. char *buf)
  1512. {
  1513. return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
  1514. }
  1515. static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
  1516. const char *buf, size_t size)
  1517. {
  1518. u64 new;
  1519. if (strict_strtoull(buf, 0, &new) < 0)
  1520. return -EINVAL;
  1521. attr_to_bank(attr)->ctl = new;
  1522. mce_restart();
  1523. return size;
  1524. }
  1525. static ssize_t
  1526. show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
  1527. {
  1528. strcpy(buf, mce_helper);
  1529. strcat(buf, "\n");
  1530. return strlen(mce_helper) + 1;
  1531. }
  1532. static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
  1533. const char *buf, size_t siz)
  1534. {
  1535. char *p;
  1536. strncpy(mce_helper, buf, sizeof(mce_helper));
  1537. mce_helper[sizeof(mce_helper)-1] = 0;
  1538. p = strchr(mce_helper, '\n');
  1539. if (p)
  1540. *p = 0;
  1541. return strlen(mce_helper) + !!p;
  1542. }
  1543. static ssize_t set_ignore_ce(struct sys_device *s,
  1544. struct sysdev_attribute *attr,
  1545. const char *buf, size_t size)
  1546. {
  1547. u64 new;
  1548. if (strict_strtoull(buf, 0, &new) < 0)
  1549. return -EINVAL;
  1550. if (mce_ignore_ce ^ !!new) {
  1551. if (new) {
  1552. /* disable ce features */
  1553. on_each_cpu(mce_disable_ce, (void *)1, 1);
  1554. mce_ignore_ce = 1;
  1555. } else {
  1556. /* enable ce features */
  1557. mce_ignore_ce = 0;
  1558. on_each_cpu(mce_enable_ce, (void *)1, 1);
  1559. }
  1560. }
  1561. return size;
  1562. }
  1563. static ssize_t set_cmci_disabled(struct sys_device *s,
  1564. struct sysdev_attribute *attr,
  1565. const char *buf, size_t size)
  1566. {
  1567. u64 new;
  1568. if (strict_strtoull(buf, 0, &new) < 0)
  1569. return -EINVAL;
  1570. if (mce_cmci_disabled ^ !!new) {
  1571. if (new) {
  1572. /* disable cmci */
  1573. on_each_cpu(mce_disable_ce, NULL, 1);
  1574. mce_cmci_disabled = 1;
  1575. } else {
  1576. /* enable cmci */
  1577. mce_cmci_disabled = 0;
  1578. on_each_cpu(mce_enable_ce, NULL, 1);
  1579. }
  1580. }
  1581. return size;
  1582. }
  1583. static ssize_t store_int_with_restart(struct sys_device *s,
  1584. struct sysdev_attribute *attr,
  1585. const char *buf, size_t size)
  1586. {
  1587. ssize_t ret = sysdev_store_int(s, attr, buf, size);
  1588. mce_restart();
  1589. return ret;
  1590. }
  1591. static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
  1592. static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
  1593. static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
  1594. static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
  1595. static struct sysdev_ext_attribute attr_check_interval = {
  1596. _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
  1597. store_int_with_restart),
  1598. &check_interval
  1599. };
  1600. static struct sysdev_ext_attribute attr_ignore_ce = {
  1601. _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
  1602. &mce_ignore_ce
  1603. };
  1604. static struct sysdev_ext_attribute attr_cmci_disabled = {
  1605. _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
  1606. &mce_cmci_disabled
  1607. };
  1608. static struct sysdev_attribute *mce_attrs[] = {
  1609. &attr_tolerant.attr,
  1610. &attr_check_interval.attr,
  1611. &attr_trigger,
  1612. &attr_monarch_timeout.attr,
  1613. &attr_dont_log_ce.attr,
  1614. &attr_ignore_ce.attr,
  1615. &attr_cmci_disabled.attr,
  1616. NULL
  1617. };
  1618. static cpumask_var_t mce_dev_initialized;
  1619. /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
  1620. static __cpuinit int mce_create_device(unsigned int cpu)
  1621. {
  1622. int err;
  1623. int i, j;
  1624. if (!mce_available(&boot_cpu_data))
  1625. return -EIO;
  1626. memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
  1627. per_cpu(mce_dev, cpu).id = cpu;
  1628. per_cpu(mce_dev, cpu).cls = &mce_sysclass;
  1629. err = sysdev_register(&per_cpu(mce_dev, cpu));
  1630. if (err)
  1631. return err;
  1632. for (i = 0; mce_attrs[i]; i++) {
  1633. err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
  1634. if (err)
  1635. goto error;
  1636. }
  1637. for (j = 0; j < banks; j++) {
  1638. err = sysdev_create_file(&per_cpu(mce_dev, cpu),
  1639. &mce_banks[j].attr);
  1640. if (err)
  1641. goto error2;
  1642. }
  1643. cpumask_set_cpu(cpu, mce_dev_initialized);
  1644. return 0;
  1645. error2:
  1646. while (--j >= 0)
  1647. sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
  1648. error:
  1649. while (--i >= 0)
  1650. sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
  1651. sysdev_unregister(&per_cpu(mce_dev, cpu));
  1652. return err;
  1653. }
  1654. static __cpuinit void mce_remove_device(unsigned int cpu)
  1655. {
  1656. int i;
  1657. if (!cpumask_test_cpu(cpu, mce_dev_initialized))
  1658. return;
  1659. for (i = 0; mce_attrs[i]; i++)
  1660. sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
  1661. for (i = 0; i < banks; i++)
  1662. sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
  1663. sysdev_unregister(&per_cpu(mce_dev, cpu));
  1664. cpumask_clear_cpu(cpu, mce_dev_initialized);
  1665. }
  1666. /* Make sure there are no machine checks on offlined CPUs. */
  1667. static void __cpuinit mce_disable_cpu(void *h)
  1668. {
  1669. unsigned long action = *(unsigned long *)h;
  1670. int i;
  1671. if (!mce_available(&current_cpu_data))
  1672. return;
  1673. if (!(action & CPU_TASKS_FROZEN))
  1674. cmci_clear();
  1675. for (i = 0; i < banks; i++) {
  1676. struct mce_bank *b = &mce_banks[i];
  1677. if (b->init)
  1678. wrmsrl(MSR_IA32_MCx_CTL(i), 0);
  1679. }
  1680. }
  1681. static void __cpuinit mce_reenable_cpu(void *h)
  1682. {
  1683. unsigned long action = *(unsigned long *)h;
  1684. int i;
  1685. if (!mce_available(&current_cpu_data))
  1686. return;
  1687. if (!(action & CPU_TASKS_FROZEN))
  1688. cmci_reenable();
  1689. for (i = 0; i < banks; i++) {
  1690. struct mce_bank *b = &mce_banks[i];
  1691. if (b->init)
  1692. wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
  1693. }
  1694. }
  1695. /* Get notified when a cpu comes on/off. Be hotplug friendly. */
  1696. static int __cpuinit
  1697. mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
  1698. {
  1699. unsigned int cpu = (unsigned long)hcpu;
  1700. struct timer_list *t = &per_cpu(mce_timer, cpu);
  1701. switch (action) {
  1702. case CPU_ONLINE:
  1703. case CPU_ONLINE_FROZEN:
  1704. mce_create_device(cpu);
  1705. if (threshold_cpu_callback)
  1706. threshold_cpu_callback(action, cpu);
  1707. break;
  1708. case CPU_DEAD:
  1709. case CPU_DEAD_FROZEN:
  1710. if (threshold_cpu_callback)
  1711. threshold_cpu_callback(action, cpu);
  1712. mce_remove_device(cpu);
  1713. break;
  1714. case CPU_DOWN_PREPARE:
  1715. case CPU_DOWN_PREPARE_FROZEN:
  1716. del_timer_sync(t);
  1717. smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
  1718. break;
  1719. case CPU_DOWN_FAILED:
  1720. case CPU_DOWN_FAILED_FROZEN:
  1721. if (!mce_ignore_ce && check_interval) {
  1722. t->expires = round_jiffies(jiffies +
  1723. __get_cpu_var(mce_next_interval));
  1724. add_timer_on(t, cpu);
  1725. }
  1726. smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
  1727. break;
  1728. case CPU_POST_DEAD:
  1729. /* intentionally ignoring frozen here */
  1730. cmci_rediscover(cpu);
  1731. break;
  1732. }
  1733. return NOTIFY_OK;
  1734. }
  1735. static struct notifier_block mce_cpu_notifier __cpuinitdata = {
  1736. .notifier_call = mce_cpu_callback,
  1737. };
  1738. static __init void mce_init_banks(void)
  1739. {
  1740. int i;
  1741. for (i = 0; i < banks; i++) {
  1742. struct mce_bank *b = &mce_banks[i];
  1743. struct sysdev_attribute *a = &b->attr;
  1744. sysfs_attr_init(&a->attr);
  1745. a->attr.name = b->attrname;
  1746. snprintf(b->attrname, ATTR_LEN, "bank%d", i);
  1747. a->attr.mode = 0644;
  1748. a->show = show_bank;
  1749. a->store = set_bank;
  1750. }
  1751. }
  1752. static __init int mcheck_init_device(void)
  1753. {
  1754. int err;
  1755. int i = 0;
  1756. if (!mce_available(&boot_cpu_data))
  1757. return -EIO;
  1758. zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
  1759. mce_init_banks();
  1760. err = sysdev_class_register(&mce_sysclass);
  1761. if (err)
  1762. return err;
  1763. for_each_online_cpu(i) {
  1764. err = mce_create_device(i);
  1765. if (err)
  1766. return err;
  1767. }
  1768. register_hotcpu_notifier(&mce_cpu_notifier);
  1769. misc_register(&mce_log_device);
  1770. return err;
  1771. }
  1772. device_initcall(mcheck_init_device);
  1773. /*
  1774. * Old style boot options parsing. Only for compatibility.
  1775. */
  1776. static int __init mcheck_disable(char *str)
  1777. {
  1778. mce_disabled = 1;
  1779. return 1;
  1780. }
  1781. __setup("nomce", mcheck_disable);
  1782. #ifdef CONFIG_DEBUG_FS
  1783. struct dentry *mce_get_debugfs_dir(void)
  1784. {
  1785. static struct dentry *dmce;
  1786. if (!dmce)
  1787. dmce = debugfs_create_dir("mce", NULL);
  1788. return dmce;
  1789. }
  1790. static void mce_reset(void)
  1791. {
  1792. cpu_missing = 0;
  1793. atomic_set(&mce_fake_paniced, 0);
  1794. atomic_set(&mce_executing, 0);
  1795. atomic_set(&mce_callin, 0);
  1796. atomic_set(&global_nwo, 0);
  1797. }
  1798. static int fake_panic_get(void *data, u64 *val)
  1799. {
  1800. *val = fake_panic;
  1801. return 0;
  1802. }
  1803. static int fake_panic_set(void *data, u64 val)
  1804. {
  1805. mce_reset();
  1806. fake_panic = val;
  1807. return 0;
  1808. }
  1809. DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
  1810. fake_panic_set, "%llu\n");
  1811. static int __init mcheck_debugfs_init(void)
  1812. {
  1813. struct dentry *dmce, *ffake_panic;
  1814. dmce = mce_get_debugfs_dir();
  1815. if (!dmce)
  1816. return -ENOMEM;
  1817. ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
  1818. &fake_panic_fops);
  1819. if (!ffake_panic)
  1820. return -ENOMEM;
  1821. return 0;
  1822. }
  1823. late_initcall(mcheck_debugfs_init);
  1824. #endif