fec_main.c 49 KB

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  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * Right now, I am very wasteful with the buffers. I allocate memory
  6. * pages and then divide them into 2K frame buffers. This way I know I
  7. * have buffers large enough to hold one frame within one buffer descriptor.
  8. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  9. * will be much more memory efficient and will easily handle lots of
  10. * small packets.
  11. *
  12. * Much better multiple PHY support by Magnus Damm.
  13. * Copyright (c) 2000 Ericsson Radio Systems AB.
  14. *
  15. * Support for FEC controller of ColdFire processors.
  16. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
  17. *
  18. * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  19. * Copyright (c) 2004-2006 Macq Electronique SA.
  20. *
  21. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/string.h>
  26. #include <linux/ptrace.h>
  27. #include <linux/errno.h>
  28. #include <linux/ioport.h>
  29. #include <linux/slab.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/init.h>
  32. #include <linux/delay.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/spinlock.h>
  37. #include <linux/workqueue.h>
  38. #include <linux/bitops.h>
  39. #include <linux/io.h>
  40. #include <linux/irq.h>
  41. #include <linux/clk.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/phy.h>
  44. #include <linux/fec.h>
  45. #include <linux/of.h>
  46. #include <linux/of_device.h>
  47. #include <linux/of_gpio.h>
  48. #include <linux/of_net.h>
  49. #include <linux/pinctrl/consumer.h>
  50. #include <linux/regulator/consumer.h>
  51. #include <asm/cacheflush.h>
  52. #ifndef CONFIG_ARM
  53. #include <asm/coldfire.h>
  54. #include <asm/mcfsim.h>
  55. #endif
  56. #include "fec.h"
  57. #if defined(CONFIG_ARM)
  58. #define FEC_ALIGNMENT 0xf
  59. #else
  60. #define FEC_ALIGNMENT 0x3
  61. #endif
  62. #define DRIVER_NAME "fec"
  63. #define FEC_NAPI_WEIGHT 64
  64. /* Pause frame feild and FIFO threshold */
  65. #define FEC_ENET_FCE (1 << 5)
  66. #define FEC_ENET_RSEM_V 0x84
  67. #define FEC_ENET_RSFL_V 16
  68. #define FEC_ENET_RAEM_V 0x8
  69. #define FEC_ENET_RAFL_V 0x8
  70. #define FEC_ENET_OPD_V 0xFFF0
  71. /* Controller is ENET-MAC */
  72. #define FEC_QUIRK_ENET_MAC (1 << 0)
  73. /* Controller needs driver to swap frame */
  74. #define FEC_QUIRK_SWAP_FRAME (1 << 1)
  75. /* Controller uses gasket */
  76. #define FEC_QUIRK_USE_GASKET (1 << 2)
  77. /* Controller has GBIT support */
  78. #define FEC_QUIRK_HAS_GBIT (1 << 3)
  79. /* Controller has extend desc buffer */
  80. #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
  81. static struct platform_device_id fec_devtype[] = {
  82. {
  83. /* keep it for coldfire */
  84. .name = DRIVER_NAME,
  85. .driver_data = 0,
  86. }, {
  87. .name = "imx25-fec",
  88. .driver_data = FEC_QUIRK_USE_GASKET,
  89. }, {
  90. .name = "imx27-fec",
  91. .driver_data = 0,
  92. }, {
  93. .name = "imx28-fec",
  94. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
  95. }, {
  96. .name = "imx6q-fec",
  97. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
  98. FEC_QUIRK_HAS_BUFDESC_EX,
  99. }, {
  100. .name = "mvf-fec",
  101. .driver_data = FEC_QUIRK_ENET_MAC,
  102. }, {
  103. /* sentinel */
  104. }
  105. };
  106. MODULE_DEVICE_TABLE(platform, fec_devtype);
  107. enum imx_fec_type {
  108. IMX25_FEC = 1, /* runs on i.mx25/50/53 */
  109. IMX27_FEC, /* runs on i.mx27/35/51 */
  110. IMX28_FEC,
  111. IMX6Q_FEC,
  112. MVF_FEC,
  113. };
  114. static const struct of_device_id fec_dt_ids[] = {
  115. { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
  116. { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
  117. { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
  118. { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
  119. { .compatible = "fsl,mvf-fec", .data = &fec_devtype[MVF_FEC], },
  120. { /* sentinel */ }
  121. };
  122. MODULE_DEVICE_TABLE(of, fec_dt_ids);
  123. static unsigned char macaddr[ETH_ALEN];
  124. module_param_array(macaddr, byte, NULL, 0);
  125. MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
  126. #if defined(CONFIG_M5272)
  127. /*
  128. * Some hardware gets it MAC address out of local flash memory.
  129. * if this is non-zero then assume it is the address to get MAC from.
  130. */
  131. #if defined(CONFIG_NETtel)
  132. #define FEC_FLASHMAC 0xf0006006
  133. #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
  134. #define FEC_FLASHMAC 0xf0006000
  135. #elif defined(CONFIG_CANCam)
  136. #define FEC_FLASHMAC 0xf0020000
  137. #elif defined (CONFIG_M5272C3)
  138. #define FEC_FLASHMAC (0xffe04000 + 4)
  139. #elif defined(CONFIG_MOD5272)
  140. #define FEC_FLASHMAC 0xffc0406b
  141. #else
  142. #define FEC_FLASHMAC 0
  143. #endif
  144. #endif /* CONFIG_M5272 */
  145. #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
  146. #error "FEC: descriptor ring size constants too large"
  147. #endif
  148. /* Interrupt events/masks. */
  149. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  150. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  151. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  152. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  153. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  154. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  155. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  156. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  157. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  158. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  159. #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
  160. #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
  161. /* The FEC stores dest/src/type, data, and checksum for receive packets.
  162. */
  163. #define PKT_MAXBUF_SIZE 1518
  164. #define PKT_MINBUF_SIZE 64
  165. #define PKT_MAXBLR_SIZE 1520
  166. /*
  167. * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
  168. * size bits. Other FEC hardware does not, so we need to take that into
  169. * account when setting it.
  170. */
  171. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  172. defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
  173. #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
  174. #else
  175. #define OPT_FRAME_SIZE 0
  176. #endif
  177. /* FEC MII MMFR bits definition */
  178. #define FEC_MMFR_ST (1 << 30)
  179. #define FEC_MMFR_OP_READ (2 << 28)
  180. #define FEC_MMFR_OP_WRITE (1 << 28)
  181. #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
  182. #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
  183. #define FEC_MMFR_TA (2 << 16)
  184. #define FEC_MMFR_DATA(v) (v & 0xffff)
  185. #define FEC_MII_TIMEOUT 30000 /* us */
  186. /* Transmitter timeout */
  187. #define TX_TIMEOUT (2 * HZ)
  188. #define FEC_PAUSE_FLAG_AUTONEG 0x1
  189. #define FEC_PAUSE_FLAG_ENABLE 0x2
  190. static int mii_cnt;
  191. static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
  192. {
  193. struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
  194. if (is_ex)
  195. return (struct bufdesc *)(ex + 1);
  196. else
  197. return bdp + 1;
  198. }
  199. static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
  200. {
  201. struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
  202. if (is_ex)
  203. return (struct bufdesc *)(ex - 1);
  204. else
  205. return bdp - 1;
  206. }
  207. static void *swap_buffer(void *bufaddr, int len)
  208. {
  209. int i;
  210. unsigned int *buf = bufaddr;
  211. for (i = 0; i < (len + 3) / 4; i++, buf++)
  212. *buf = cpu_to_be32(*buf);
  213. return bufaddr;
  214. }
  215. static netdev_tx_t
  216. fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  217. {
  218. struct fec_enet_private *fep = netdev_priv(ndev);
  219. const struct platform_device_id *id_entry =
  220. platform_get_device_id(fep->pdev);
  221. struct bufdesc *bdp;
  222. void *bufaddr;
  223. unsigned short status;
  224. unsigned int index;
  225. if (!fep->link) {
  226. /* Link is down or autonegotiation is in progress. */
  227. return NETDEV_TX_BUSY;
  228. }
  229. /* Fill in a Tx ring entry */
  230. bdp = fep->cur_tx;
  231. status = bdp->cbd_sc;
  232. if (status & BD_ENET_TX_READY) {
  233. /* Ooops. All transmit buffers are full. Bail out.
  234. * This should not happen, since ndev->tbusy should be set.
  235. */
  236. netdev_err(ndev, "tx queue full!\n");
  237. return NETDEV_TX_BUSY;
  238. }
  239. /* Clear all of the status flags */
  240. status &= ~BD_ENET_TX_STATS;
  241. /* Set buffer length and buffer pointer */
  242. bufaddr = skb->data;
  243. bdp->cbd_datlen = skb->len;
  244. /*
  245. * On some FEC implementations data must be aligned on
  246. * 4-byte boundaries. Use bounce buffers to copy data
  247. * and get it aligned. Ugh.
  248. */
  249. if (fep->bufdesc_ex)
  250. index = (struct bufdesc_ex *)bdp -
  251. (struct bufdesc_ex *)fep->tx_bd_base;
  252. else
  253. index = bdp - fep->tx_bd_base;
  254. if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
  255. memcpy(fep->tx_bounce[index], skb->data, skb->len);
  256. bufaddr = fep->tx_bounce[index];
  257. }
  258. /*
  259. * Some design made an incorrect assumption on endian mode of
  260. * the system that it's running on. As the result, driver has to
  261. * swap every frame going to and coming from the controller.
  262. */
  263. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  264. swap_buffer(bufaddr, skb->len);
  265. /* Save skb pointer */
  266. fep->tx_skbuff[index] = skb;
  267. /* Push the data cache so the CPM does not get stale memory
  268. * data.
  269. */
  270. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
  271. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  272. /* Send it on its way. Tell FEC it's ready, interrupt when done,
  273. * it's the last BD of the frame, and to put the CRC on the end.
  274. */
  275. status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
  276. | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  277. bdp->cbd_sc = status;
  278. if (fep->bufdesc_ex) {
  279. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  280. ebdp->cbd_bdu = 0;
  281. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
  282. fep->hwts_tx_en)) {
  283. ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
  284. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  285. } else {
  286. ebdp->cbd_esc = BD_ENET_TX_INT;
  287. }
  288. }
  289. /* If this was the last BD in the ring, start at the beginning again. */
  290. if (status & BD_ENET_TX_WRAP)
  291. bdp = fep->tx_bd_base;
  292. else
  293. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  294. fep->cur_tx = bdp;
  295. if (fep->cur_tx == fep->dirty_tx)
  296. netif_stop_queue(ndev);
  297. /* Trigger transmission start */
  298. writel(0, fep->hwp + FEC_X_DES_ACTIVE);
  299. skb_tx_timestamp(skb);
  300. return NETDEV_TX_OK;
  301. }
  302. /* Init RX & TX buffer descriptors
  303. */
  304. static void fec_enet_bd_init(struct net_device *dev)
  305. {
  306. struct fec_enet_private *fep = netdev_priv(dev);
  307. struct bufdesc *bdp;
  308. unsigned int i;
  309. /* Initialize the receive buffer descriptors. */
  310. bdp = fep->rx_bd_base;
  311. for (i = 0; i < RX_RING_SIZE; i++) {
  312. /* Initialize the BD for every fragment in the page. */
  313. if (bdp->cbd_bufaddr)
  314. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  315. else
  316. bdp->cbd_sc = 0;
  317. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  318. }
  319. /* Set the last buffer to wrap */
  320. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  321. bdp->cbd_sc |= BD_SC_WRAP;
  322. fep->cur_rx = fep->rx_bd_base;
  323. /* ...and the same for transmit */
  324. bdp = fep->tx_bd_base;
  325. fep->cur_tx = bdp;
  326. for (i = 0; i < TX_RING_SIZE; i++) {
  327. /* Initialize the BD for every fragment in the page. */
  328. bdp->cbd_sc = 0;
  329. if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
  330. dev_kfree_skb_any(fep->tx_skbuff[i]);
  331. fep->tx_skbuff[i] = NULL;
  332. }
  333. bdp->cbd_bufaddr = 0;
  334. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  335. }
  336. /* Set the last buffer to wrap */
  337. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  338. bdp->cbd_sc |= BD_SC_WRAP;
  339. fep->dirty_tx = bdp;
  340. }
  341. /* This function is called to start or restart the FEC during a link
  342. * change. This only happens when switching between half and full
  343. * duplex.
  344. */
  345. static void
  346. fec_restart(struct net_device *ndev, int duplex)
  347. {
  348. struct fec_enet_private *fep = netdev_priv(ndev);
  349. const struct platform_device_id *id_entry =
  350. platform_get_device_id(fep->pdev);
  351. int i;
  352. u32 temp_mac[2];
  353. u32 rcntl = OPT_FRAME_SIZE | 0x04;
  354. u32 ecntl = 0x2; /* ETHEREN */
  355. /* Whack a reset. We should wait for this. */
  356. writel(1, fep->hwp + FEC_ECNTRL);
  357. udelay(10);
  358. /*
  359. * enet-mac reset will reset mac address registers too,
  360. * so need to reconfigure it.
  361. */
  362. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  363. memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
  364. writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
  365. writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
  366. }
  367. /* Clear any outstanding interrupt. */
  368. writel(0xffc00000, fep->hwp + FEC_IEVENT);
  369. /* Reset all multicast. */
  370. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  371. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  372. #ifndef CONFIG_M5272
  373. writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
  374. writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
  375. #endif
  376. /* Set maximum receive buffer size. */
  377. writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
  378. fec_enet_bd_init(ndev);
  379. /* Set receive and transmit descriptor base. */
  380. writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
  381. if (fep->bufdesc_ex)
  382. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
  383. * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  384. else
  385. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
  386. * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
  387. for (i = 0; i <= TX_RING_MOD_MASK; i++) {
  388. if (fep->tx_skbuff[i]) {
  389. dev_kfree_skb_any(fep->tx_skbuff[i]);
  390. fep->tx_skbuff[i] = NULL;
  391. }
  392. }
  393. /* Enable MII mode */
  394. if (duplex) {
  395. /* FD enable */
  396. writel(0x04, fep->hwp + FEC_X_CNTRL);
  397. } else {
  398. /* No Rcv on Xmit */
  399. rcntl |= 0x02;
  400. writel(0x0, fep->hwp + FEC_X_CNTRL);
  401. }
  402. fep->full_duplex = duplex;
  403. /* Set MII speed */
  404. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  405. /*
  406. * The phy interface and speed need to get configured
  407. * differently on enet-mac.
  408. */
  409. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  410. /* Enable flow control and length check */
  411. rcntl |= 0x40000000 | 0x00000020;
  412. /* RGMII, RMII or MII */
  413. if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
  414. rcntl |= (1 << 6);
  415. else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  416. rcntl |= (1 << 8);
  417. else
  418. rcntl &= ~(1 << 8);
  419. /* 1G, 100M or 10M */
  420. if (fep->phy_dev) {
  421. if (fep->phy_dev->speed == SPEED_1000)
  422. ecntl |= (1 << 5);
  423. else if (fep->phy_dev->speed == SPEED_100)
  424. rcntl &= ~(1 << 9);
  425. else
  426. rcntl |= (1 << 9);
  427. }
  428. } else {
  429. #ifdef FEC_MIIGSK_ENR
  430. if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
  431. u32 cfgr;
  432. /* disable the gasket and wait */
  433. writel(0, fep->hwp + FEC_MIIGSK_ENR);
  434. while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
  435. udelay(1);
  436. /*
  437. * configure the gasket:
  438. * RMII, 50 MHz, no loopback, no echo
  439. * MII, 25 MHz, no loopback, no echo
  440. */
  441. cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  442. ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
  443. if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
  444. cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
  445. writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
  446. /* re-enable the gasket */
  447. writel(2, fep->hwp + FEC_MIIGSK_ENR);
  448. }
  449. #endif
  450. }
  451. /* enable pause frame*/
  452. if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
  453. ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
  454. fep->phy_dev && fep->phy_dev->pause)) {
  455. rcntl |= FEC_ENET_FCE;
  456. /* set FIFO thresh hold parameter to reduce overrun */
  457. writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
  458. writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
  459. writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
  460. writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
  461. /* OPD */
  462. writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
  463. } else {
  464. rcntl &= ~FEC_ENET_FCE;
  465. }
  466. writel(rcntl, fep->hwp + FEC_R_CNTRL);
  467. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  468. /* enable ENET endian swap */
  469. ecntl |= (1 << 8);
  470. /* enable ENET store and forward mode */
  471. writel(1 << 8, fep->hwp + FEC_X_WMRK);
  472. }
  473. if (fep->bufdesc_ex)
  474. ecntl |= (1 << 4);
  475. /* And last, enable the transmit and receive processing */
  476. writel(ecntl, fep->hwp + FEC_ECNTRL);
  477. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  478. if (fep->bufdesc_ex)
  479. fec_ptp_start_cyclecounter(ndev);
  480. /* Enable interrupts we wish to service */
  481. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  482. }
  483. static void
  484. fec_stop(struct net_device *ndev)
  485. {
  486. struct fec_enet_private *fep = netdev_priv(ndev);
  487. const struct platform_device_id *id_entry =
  488. platform_get_device_id(fep->pdev);
  489. u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
  490. /* We cannot expect a graceful transmit stop without link !!! */
  491. if (fep->link) {
  492. writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
  493. udelay(10);
  494. if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
  495. netdev_err(ndev, "Graceful transmit stop did not complete!\n");
  496. }
  497. /* Whack a reset. We should wait for this. */
  498. writel(1, fep->hwp + FEC_ECNTRL);
  499. udelay(10);
  500. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  501. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  502. /* We have to keep ENET enabled to have MII interrupt stay working */
  503. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  504. writel(2, fep->hwp + FEC_ECNTRL);
  505. writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
  506. }
  507. }
  508. static void
  509. fec_timeout(struct net_device *ndev)
  510. {
  511. struct fec_enet_private *fep = netdev_priv(ndev);
  512. ndev->stats.tx_errors++;
  513. fec_restart(ndev, fep->full_duplex);
  514. netif_wake_queue(ndev);
  515. }
  516. static void
  517. fec_enet_tx(struct net_device *ndev)
  518. {
  519. struct fec_enet_private *fep;
  520. struct bufdesc *bdp;
  521. unsigned short status;
  522. struct sk_buff *skb;
  523. int index = 0;
  524. fep = netdev_priv(ndev);
  525. bdp = fep->dirty_tx;
  526. /* get next bdp of dirty_tx */
  527. if (bdp->cbd_sc & BD_ENET_TX_WRAP)
  528. bdp = fep->tx_bd_base;
  529. else
  530. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  531. while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
  532. /* current queue is empty */
  533. if (bdp == fep->cur_tx)
  534. break;
  535. if (fep->bufdesc_ex)
  536. index = (struct bufdesc_ex *)bdp -
  537. (struct bufdesc_ex *)fep->tx_bd_base;
  538. else
  539. index = bdp - fep->tx_bd_base;
  540. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  541. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  542. bdp->cbd_bufaddr = 0;
  543. skb = fep->tx_skbuff[index];
  544. /* Check for errors. */
  545. if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
  546. BD_ENET_TX_RL | BD_ENET_TX_UN |
  547. BD_ENET_TX_CSL)) {
  548. ndev->stats.tx_errors++;
  549. if (status & BD_ENET_TX_HB) /* No heartbeat */
  550. ndev->stats.tx_heartbeat_errors++;
  551. if (status & BD_ENET_TX_LC) /* Late collision */
  552. ndev->stats.tx_window_errors++;
  553. if (status & BD_ENET_TX_RL) /* Retrans limit */
  554. ndev->stats.tx_aborted_errors++;
  555. if (status & BD_ENET_TX_UN) /* Underrun */
  556. ndev->stats.tx_fifo_errors++;
  557. if (status & BD_ENET_TX_CSL) /* Carrier lost */
  558. ndev->stats.tx_carrier_errors++;
  559. } else {
  560. ndev->stats.tx_packets++;
  561. }
  562. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
  563. fep->bufdesc_ex) {
  564. struct skb_shared_hwtstamps shhwtstamps;
  565. unsigned long flags;
  566. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  567. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  568. spin_lock_irqsave(&fep->tmreg_lock, flags);
  569. shhwtstamps.hwtstamp = ns_to_ktime(
  570. timecounter_cyc2time(&fep->tc, ebdp->ts));
  571. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  572. skb_tstamp_tx(skb, &shhwtstamps);
  573. }
  574. if (status & BD_ENET_TX_READY)
  575. netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
  576. /* Deferred means some collisions occurred during transmit,
  577. * but we eventually sent the packet OK.
  578. */
  579. if (status & BD_ENET_TX_DEF)
  580. ndev->stats.collisions++;
  581. /* Free the sk buffer associated with this last transmit */
  582. dev_kfree_skb_any(skb);
  583. fep->tx_skbuff[index] = NULL;
  584. fep->dirty_tx = bdp;
  585. /* Update pointer to next buffer descriptor to be transmitted */
  586. if (status & BD_ENET_TX_WRAP)
  587. bdp = fep->tx_bd_base;
  588. else
  589. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  590. /* Since we have freed up a buffer, the ring is no longer full
  591. */
  592. if (fep->dirty_tx != fep->cur_tx) {
  593. if (netif_queue_stopped(ndev))
  594. netif_wake_queue(ndev);
  595. }
  596. }
  597. return;
  598. }
  599. /* During a receive, the cur_rx points to the current incoming buffer.
  600. * When we update through the ring, if the next incoming buffer has
  601. * not been given to the system, we just set the empty indicator,
  602. * effectively tossing the packet.
  603. */
  604. static int
  605. fec_enet_rx(struct net_device *ndev, int budget)
  606. {
  607. struct fec_enet_private *fep = netdev_priv(ndev);
  608. const struct platform_device_id *id_entry =
  609. platform_get_device_id(fep->pdev);
  610. struct bufdesc *bdp;
  611. unsigned short status;
  612. struct sk_buff *skb;
  613. ushort pkt_len;
  614. __u8 *data;
  615. int pkt_received = 0;
  616. #ifdef CONFIG_M532x
  617. flush_cache_all();
  618. #endif
  619. /* First, grab all of the stats for the incoming packet.
  620. * These get messed up if we get called due to a busy condition.
  621. */
  622. bdp = fep->cur_rx;
  623. while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
  624. if (pkt_received >= budget)
  625. break;
  626. pkt_received++;
  627. /* Since we have allocated space to hold a complete frame,
  628. * the last indicator should be set.
  629. */
  630. if ((status & BD_ENET_RX_LAST) == 0)
  631. netdev_err(ndev, "rcv is not +last\n");
  632. if (!fep->opened)
  633. goto rx_processing_done;
  634. /* Check for errors. */
  635. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
  636. BD_ENET_RX_CR | BD_ENET_RX_OV)) {
  637. ndev->stats.rx_errors++;
  638. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
  639. /* Frame too long or too short. */
  640. ndev->stats.rx_length_errors++;
  641. }
  642. if (status & BD_ENET_RX_NO) /* Frame alignment */
  643. ndev->stats.rx_frame_errors++;
  644. if (status & BD_ENET_RX_CR) /* CRC Error */
  645. ndev->stats.rx_crc_errors++;
  646. if (status & BD_ENET_RX_OV) /* FIFO overrun */
  647. ndev->stats.rx_fifo_errors++;
  648. }
  649. /* Report late collisions as a frame error.
  650. * On this error, the BD is closed, but we don't know what we
  651. * have in the buffer. So, just drop this frame on the floor.
  652. */
  653. if (status & BD_ENET_RX_CL) {
  654. ndev->stats.rx_errors++;
  655. ndev->stats.rx_frame_errors++;
  656. goto rx_processing_done;
  657. }
  658. /* Process the incoming frame. */
  659. ndev->stats.rx_packets++;
  660. pkt_len = bdp->cbd_datlen;
  661. ndev->stats.rx_bytes += pkt_len;
  662. data = (__u8*)__va(bdp->cbd_bufaddr);
  663. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  664. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  665. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  666. swap_buffer(data, pkt_len);
  667. /* This does 16 byte alignment, exactly what we need.
  668. * The packet length includes FCS, but we don't want to
  669. * include that when passing upstream as it messes up
  670. * bridging applications.
  671. */
  672. skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
  673. if (unlikely(!skb)) {
  674. ndev->stats.rx_dropped++;
  675. } else {
  676. skb_reserve(skb, NET_IP_ALIGN);
  677. skb_put(skb, pkt_len - 4); /* Make room */
  678. skb_copy_to_linear_data(skb, data, pkt_len - 4);
  679. skb->protocol = eth_type_trans(skb, ndev);
  680. /* Get receive timestamp from the skb */
  681. if (fep->hwts_rx_en && fep->bufdesc_ex) {
  682. struct skb_shared_hwtstamps *shhwtstamps =
  683. skb_hwtstamps(skb);
  684. unsigned long flags;
  685. struct bufdesc_ex *ebdp =
  686. (struct bufdesc_ex *)bdp;
  687. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  688. spin_lock_irqsave(&fep->tmreg_lock, flags);
  689. shhwtstamps->hwtstamp = ns_to_ktime(
  690. timecounter_cyc2time(&fep->tc, ebdp->ts));
  691. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  692. }
  693. if (!skb_defer_rx_timestamp(skb))
  694. napi_gro_receive(&fep->napi, skb);
  695. }
  696. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
  697. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  698. rx_processing_done:
  699. /* Clear the status flags for this buffer */
  700. status &= ~BD_ENET_RX_STATS;
  701. /* Mark the buffer empty */
  702. status |= BD_ENET_RX_EMPTY;
  703. bdp->cbd_sc = status;
  704. if (fep->bufdesc_ex) {
  705. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  706. ebdp->cbd_esc = BD_ENET_RX_INT;
  707. ebdp->cbd_prot = 0;
  708. ebdp->cbd_bdu = 0;
  709. }
  710. /* Update BD pointer to next entry */
  711. if (status & BD_ENET_RX_WRAP)
  712. bdp = fep->rx_bd_base;
  713. else
  714. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  715. /* Doing this here will keep the FEC running while we process
  716. * incoming frames. On a heavily loaded network, we should be
  717. * able to keep up at the expense of system resources.
  718. */
  719. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  720. }
  721. fep->cur_rx = bdp;
  722. return pkt_received;
  723. }
  724. static irqreturn_t
  725. fec_enet_interrupt(int irq, void *dev_id)
  726. {
  727. struct net_device *ndev = dev_id;
  728. struct fec_enet_private *fep = netdev_priv(ndev);
  729. uint int_events;
  730. irqreturn_t ret = IRQ_NONE;
  731. do {
  732. int_events = readl(fep->hwp + FEC_IEVENT);
  733. writel(int_events, fep->hwp + FEC_IEVENT);
  734. if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
  735. ret = IRQ_HANDLED;
  736. /* Disable the RX interrupt */
  737. if (napi_schedule_prep(&fep->napi)) {
  738. writel(FEC_RX_DISABLED_IMASK,
  739. fep->hwp + FEC_IMASK);
  740. __napi_schedule(&fep->napi);
  741. }
  742. }
  743. if (int_events & FEC_ENET_MII) {
  744. ret = IRQ_HANDLED;
  745. complete(&fep->mdio_done);
  746. }
  747. } while (int_events);
  748. return ret;
  749. }
  750. static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
  751. {
  752. struct net_device *ndev = napi->dev;
  753. int pkts = fec_enet_rx(ndev, budget);
  754. struct fec_enet_private *fep = netdev_priv(ndev);
  755. fec_enet_tx(ndev);
  756. if (pkts < budget) {
  757. napi_complete(napi);
  758. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  759. }
  760. return pkts;
  761. }
  762. /* ------------------------------------------------------------------------- */
  763. static void fec_get_mac(struct net_device *ndev)
  764. {
  765. struct fec_enet_private *fep = netdev_priv(ndev);
  766. struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
  767. unsigned char *iap, tmpaddr[ETH_ALEN];
  768. /*
  769. * try to get mac address in following order:
  770. *
  771. * 1) module parameter via kernel command line in form
  772. * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
  773. */
  774. iap = macaddr;
  775. /*
  776. * 2) from device tree data
  777. */
  778. if (!is_valid_ether_addr(iap)) {
  779. struct device_node *np = fep->pdev->dev.of_node;
  780. if (np) {
  781. const char *mac = of_get_mac_address(np);
  782. if (mac)
  783. iap = (unsigned char *) mac;
  784. }
  785. }
  786. /*
  787. * 3) from flash or fuse (via platform data)
  788. */
  789. if (!is_valid_ether_addr(iap)) {
  790. #ifdef CONFIG_M5272
  791. if (FEC_FLASHMAC)
  792. iap = (unsigned char *)FEC_FLASHMAC;
  793. #else
  794. if (pdata)
  795. iap = (unsigned char *)&pdata->mac;
  796. #endif
  797. }
  798. /*
  799. * 4) FEC mac registers set by bootloader
  800. */
  801. if (!is_valid_ether_addr(iap)) {
  802. *((unsigned long *) &tmpaddr[0]) =
  803. be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
  804. *((unsigned short *) &tmpaddr[4]) =
  805. be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
  806. iap = &tmpaddr[0];
  807. }
  808. memcpy(ndev->dev_addr, iap, ETH_ALEN);
  809. /* Adjust MAC if using macaddr */
  810. if (iap == macaddr)
  811. ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
  812. }
  813. /* ------------------------------------------------------------------------- */
  814. /*
  815. * Phy section
  816. */
  817. static void fec_enet_adjust_link(struct net_device *ndev)
  818. {
  819. struct fec_enet_private *fep = netdev_priv(ndev);
  820. struct phy_device *phy_dev = fep->phy_dev;
  821. unsigned long flags;
  822. int status_change = 0;
  823. spin_lock_irqsave(&fep->hw_lock, flags);
  824. /* Prevent a state halted on mii error */
  825. if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
  826. phy_dev->state = PHY_RESUMING;
  827. goto spin_unlock;
  828. }
  829. if (phy_dev->link) {
  830. if (!fep->link) {
  831. fep->link = phy_dev->link;
  832. status_change = 1;
  833. }
  834. if (fep->full_duplex != phy_dev->duplex)
  835. status_change = 1;
  836. if (phy_dev->speed != fep->speed) {
  837. fep->speed = phy_dev->speed;
  838. status_change = 1;
  839. }
  840. /* if any of the above changed restart the FEC */
  841. if (status_change)
  842. fec_restart(ndev, phy_dev->duplex);
  843. } else {
  844. if (fep->link) {
  845. fec_stop(ndev);
  846. status_change = 1;
  847. }
  848. }
  849. spin_unlock:
  850. spin_unlock_irqrestore(&fep->hw_lock, flags);
  851. if (status_change)
  852. phy_print_status(phy_dev);
  853. }
  854. static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  855. {
  856. struct fec_enet_private *fep = bus->priv;
  857. unsigned long time_left;
  858. fep->mii_timeout = 0;
  859. init_completion(&fep->mdio_done);
  860. /* start a read op */
  861. writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
  862. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  863. FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
  864. /* wait for end of transfer */
  865. time_left = wait_for_completion_timeout(&fep->mdio_done,
  866. usecs_to_jiffies(FEC_MII_TIMEOUT));
  867. if (time_left == 0) {
  868. fep->mii_timeout = 1;
  869. netdev_err(fep->netdev, "MDIO read timeout\n");
  870. return -ETIMEDOUT;
  871. }
  872. /* return value */
  873. return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
  874. }
  875. static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  876. u16 value)
  877. {
  878. struct fec_enet_private *fep = bus->priv;
  879. unsigned long time_left;
  880. fep->mii_timeout = 0;
  881. init_completion(&fep->mdio_done);
  882. /* start a write op */
  883. writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
  884. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  885. FEC_MMFR_TA | FEC_MMFR_DATA(value),
  886. fep->hwp + FEC_MII_DATA);
  887. /* wait for end of transfer */
  888. time_left = wait_for_completion_timeout(&fep->mdio_done,
  889. usecs_to_jiffies(FEC_MII_TIMEOUT));
  890. if (time_left == 0) {
  891. fep->mii_timeout = 1;
  892. netdev_err(fep->netdev, "MDIO write timeout\n");
  893. return -ETIMEDOUT;
  894. }
  895. return 0;
  896. }
  897. static int fec_enet_mdio_reset(struct mii_bus *bus)
  898. {
  899. return 0;
  900. }
  901. static int fec_enet_mii_probe(struct net_device *ndev)
  902. {
  903. struct fec_enet_private *fep = netdev_priv(ndev);
  904. const struct platform_device_id *id_entry =
  905. platform_get_device_id(fep->pdev);
  906. struct phy_device *phy_dev = NULL;
  907. char mdio_bus_id[MII_BUS_ID_SIZE];
  908. char phy_name[MII_BUS_ID_SIZE + 3];
  909. int phy_id;
  910. int dev_id = fep->dev_id;
  911. fep->phy_dev = NULL;
  912. /* check for attached phy */
  913. for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
  914. if ((fep->mii_bus->phy_mask & (1 << phy_id)))
  915. continue;
  916. if (fep->mii_bus->phy_map[phy_id] == NULL)
  917. continue;
  918. if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
  919. continue;
  920. if (dev_id--)
  921. continue;
  922. strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
  923. break;
  924. }
  925. if (phy_id >= PHY_MAX_ADDR) {
  926. netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
  927. strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
  928. phy_id = 0;
  929. }
  930. snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
  931. phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
  932. fep->phy_interface);
  933. if (IS_ERR(phy_dev)) {
  934. netdev_err(ndev, "could not attach to PHY\n");
  935. return PTR_ERR(phy_dev);
  936. }
  937. /* mask with MAC supported features */
  938. if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
  939. phy_dev->supported &= PHY_GBIT_FEATURES;
  940. phy_dev->supported |= SUPPORTED_Pause;
  941. }
  942. else
  943. phy_dev->supported &= PHY_BASIC_FEATURES;
  944. phy_dev->advertising = phy_dev->supported;
  945. fep->phy_dev = phy_dev;
  946. fep->link = 0;
  947. fep->full_duplex = 0;
  948. netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  949. fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
  950. fep->phy_dev->irq);
  951. return 0;
  952. }
  953. static int fec_enet_mii_init(struct platform_device *pdev)
  954. {
  955. static struct mii_bus *fec0_mii_bus;
  956. struct net_device *ndev = platform_get_drvdata(pdev);
  957. struct fec_enet_private *fep = netdev_priv(ndev);
  958. const struct platform_device_id *id_entry =
  959. platform_get_device_id(fep->pdev);
  960. int err = -ENXIO, i;
  961. /*
  962. * The dual fec interfaces are not equivalent with enet-mac.
  963. * Here are the differences:
  964. *
  965. * - fec0 supports MII & RMII modes while fec1 only supports RMII
  966. * - fec0 acts as the 1588 time master while fec1 is slave
  967. * - external phys can only be configured by fec0
  968. *
  969. * That is to say fec1 can not work independently. It only works
  970. * when fec0 is working. The reason behind this design is that the
  971. * second interface is added primarily for Switch mode.
  972. *
  973. * Because of the last point above, both phys are attached on fec0
  974. * mdio interface in board design, and need to be configured by
  975. * fec0 mii_bus.
  976. */
  977. if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
  978. /* fec1 uses fec0 mii_bus */
  979. if (mii_cnt && fec0_mii_bus) {
  980. fep->mii_bus = fec0_mii_bus;
  981. mii_cnt++;
  982. return 0;
  983. }
  984. return -ENOENT;
  985. }
  986. fep->mii_timeout = 0;
  987. /*
  988. * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
  989. *
  990. * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
  991. * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
  992. * Reference Manual has an error on this, and gets fixed on i.MX6Q
  993. * document.
  994. */
  995. fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
  996. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  997. fep->phy_speed--;
  998. fep->phy_speed <<= 1;
  999. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  1000. fep->mii_bus = mdiobus_alloc();
  1001. if (fep->mii_bus == NULL) {
  1002. err = -ENOMEM;
  1003. goto err_out;
  1004. }
  1005. fep->mii_bus->name = "fec_enet_mii_bus";
  1006. fep->mii_bus->read = fec_enet_mdio_read;
  1007. fep->mii_bus->write = fec_enet_mdio_write;
  1008. fep->mii_bus->reset = fec_enet_mdio_reset;
  1009. snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  1010. pdev->name, fep->dev_id + 1);
  1011. fep->mii_bus->priv = fep;
  1012. fep->mii_bus->parent = &pdev->dev;
  1013. fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  1014. if (!fep->mii_bus->irq) {
  1015. err = -ENOMEM;
  1016. goto err_out_free_mdiobus;
  1017. }
  1018. for (i = 0; i < PHY_MAX_ADDR; i++)
  1019. fep->mii_bus->irq[i] = PHY_POLL;
  1020. if (mdiobus_register(fep->mii_bus))
  1021. goto err_out_free_mdio_irq;
  1022. mii_cnt++;
  1023. /* save fec0 mii_bus */
  1024. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  1025. fec0_mii_bus = fep->mii_bus;
  1026. return 0;
  1027. err_out_free_mdio_irq:
  1028. kfree(fep->mii_bus->irq);
  1029. err_out_free_mdiobus:
  1030. mdiobus_free(fep->mii_bus);
  1031. err_out:
  1032. return err;
  1033. }
  1034. static void fec_enet_mii_remove(struct fec_enet_private *fep)
  1035. {
  1036. if (--mii_cnt == 0) {
  1037. mdiobus_unregister(fep->mii_bus);
  1038. kfree(fep->mii_bus->irq);
  1039. mdiobus_free(fep->mii_bus);
  1040. }
  1041. }
  1042. static int fec_enet_get_settings(struct net_device *ndev,
  1043. struct ethtool_cmd *cmd)
  1044. {
  1045. struct fec_enet_private *fep = netdev_priv(ndev);
  1046. struct phy_device *phydev = fep->phy_dev;
  1047. if (!phydev)
  1048. return -ENODEV;
  1049. return phy_ethtool_gset(phydev, cmd);
  1050. }
  1051. static int fec_enet_set_settings(struct net_device *ndev,
  1052. struct ethtool_cmd *cmd)
  1053. {
  1054. struct fec_enet_private *fep = netdev_priv(ndev);
  1055. struct phy_device *phydev = fep->phy_dev;
  1056. if (!phydev)
  1057. return -ENODEV;
  1058. return phy_ethtool_sset(phydev, cmd);
  1059. }
  1060. static void fec_enet_get_drvinfo(struct net_device *ndev,
  1061. struct ethtool_drvinfo *info)
  1062. {
  1063. struct fec_enet_private *fep = netdev_priv(ndev);
  1064. strlcpy(info->driver, fep->pdev->dev.driver->name,
  1065. sizeof(info->driver));
  1066. strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
  1067. strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
  1068. }
  1069. static int fec_enet_get_ts_info(struct net_device *ndev,
  1070. struct ethtool_ts_info *info)
  1071. {
  1072. struct fec_enet_private *fep = netdev_priv(ndev);
  1073. if (fep->bufdesc_ex) {
  1074. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  1075. SOF_TIMESTAMPING_RX_SOFTWARE |
  1076. SOF_TIMESTAMPING_SOFTWARE |
  1077. SOF_TIMESTAMPING_TX_HARDWARE |
  1078. SOF_TIMESTAMPING_RX_HARDWARE |
  1079. SOF_TIMESTAMPING_RAW_HARDWARE;
  1080. if (fep->ptp_clock)
  1081. info->phc_index = ptp_clock_index(fep->ptp_clock);
  1082. else
  1083. info->phc_index = -1;
  1084. info->tx_types = (1 << HWTSTAMP_TX_OFF) |
  1085. (1 << HWTSTAMP_TX_ON);
  1086. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  1087. (1 << HWTSTAMP_FILTER_ALL);
  1088. return 0;
  1089. } else {
  1090. return ethtool_op_get_ts_info(ndev, info);
  1091. }
  1092. }
  1093. static void fec_enet_get_pauseparam(struct net_device *ndev,
  1094. struct ethtool_pauseparam *pause)
  1095. {
  1096. struct fec_enet_private *fep = netdev_priv(ndev);
  1097. pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
  1098. pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
  1099. pause->rx_pause = pause->tx_pause;
  1100. }
  1101. static int fec_enet_set_pauseparam(struct net_device *ndev,
  1102. struct ethtool_pauseparam *pause)
  1103. {
  1104. struct fec_enet_private *fep = netdev_priv(ndev);
  1105. if (pause->tx_pause != pause->rx_pause) {
  1106. netdev_info(ndev,
  1107. "hardware only support enable/disable both tx and rx");
  1108. return -EINVAL;
  1109. }
  1110. fep->pause_flag = 0;
  1111. /* tx pause must be same as rx pause */
  1112. fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
  1113. fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
  1114. if (pause->rx_pause || pause->autoneg) {
  1115. fep->phy_dev->supported |= ADVERTISED_Pause;
  1116. fep->phy_dev->advertising |= ADVERTISED_Pause;
  1117. } else {
  1118. fep->phy_dev->supported &= ~ADVERTISED_Pause;
  1119. fep->phy_dev->advertising &= ~ADVERTISED_Pause;
  1120. }
  1121. if (pause->autoneg) {
  1122. if (netif_running(ndev))
  1123. fec_stop(ndev);
  1124. phy_start_aneg(fep->phy_dev);
  1125. }
  1126. if (netif_running(ndev))
  1127. fec_restart(ndev, 0);
  1128. return 0;
  1129. }
  1130. static const struct ethtool_ops fec_enet_ethtool_ops = {
  1131. .get_pauseparam = fec_enet_get_pauseparam,
  1132. .set_pauseparam = fec_enet_set_pauseparam,
  1133. .get_settings = fec_enet_get_settings,
  1134. .set_settings = fec_enet_set_settings,
  1135. .get_drvinfo = fec_enet_get_drvinfo,
  1136. .get_link = ethtool_op_get_link,
  1137. .get_ts_info = fec_enet_get_ts_info,
  1138. };
  1139. static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
  1140. {
  1141. struct fec_enet_private *fep = netdev_priv(ndev);
  1142. struct phy_device *phydev = fep->phy_dev;
  1143. if (!netif_running(ndev))
  1144. return -EINVAL;
  1145. if (!phydev)
  1146. return -ENODEV;
  1147. if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
  1148. return fec_ptp_ioctl(ndev, rq, cmd);
  1149. return phy_mii_ioctl(phydev, rq, cmd);
  1150. }
  1151. static void fec_enet_free_buffers(struct net_device *ndev)
  1152. {
  1153. struct fec_enet_private *fep = netdev_priv(ndev);
  1154. unsigned int i;
  1155. struct sk_buff *skb;
  1156. struct bufdesc *bdp;
  1157. bdp = fep->rx_bd_base;
  1158. for (i = 0; i < RX_RING_SIZE; i++) {
  1159. skb = fep->rx_skbuff[i];
  1160. if (bdp->cbd_bufaddr)
  1161. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  1162. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1163. if (skb)
  1164. dev_kfree_skb(skb);
  1165. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1166. }
  1167. bdp = fep->tx_bd_base;
  1168. for (i = 0; i < TX_RING_SIZE; i++)
  1169. kfree(fep->tx_bounce[i]);
  1170. }
  1171. static int fec_enet_alloc_buffers(struct net_device *ndev)
  1172. {
  1173. struct fec_enet_private *fep = netdev_priv(ndev);
  1174. unsigned int i;
  1175. struct sk_buff *skb;
  1176. struct bufdesc *bdp;
  1177. bdp = fep->rx_bd_base;
  1178. for (i = 0; i < RX_RING_SIZE; i++) {
  1179. skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
  1180. if (!skb) {
  1181. fec_enet_free_buffers(ndev);
  1182. return -ENOMEM;
  1183. }
  1184. fep->rx_skbuff[i] = skb;
  1185. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
  1186. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1187. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  1188. if (fep->bufdesc_ex) {
  1189. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1190. ebdp->cbd_esc = BD_ENET_RX_INT;
  1191. }
  1192. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1193. }
  1194. /* Set the last buffer to wrap. */
  1195. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1196. bdp->cbd_sc |= BD_SC_WRAP;
  1197. bdp = fep->tx_bd_base;
  1198. for (i = 0; i < TX_RING_SIZE; i++) {
  1199. fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
  1200. bdp->cbd_sc = 0;
  1201. bdp->cbd_bufaddr = 0;
  1202. if (fep->bufdesc_ex) {
  1203. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1204. ebdp->cbd_esc = BD_ENET_TX_INT;
  1205. }
  1206. bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
  1207. }
  1208. /* Set the last buffer to wrap. */
  1209. bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
  1210. bdp->cbd_sc |= BD_SC_WRAP;
  1211. return 0;
  1212. }
  1213. static int
  1214. fec_enet_open(struct net_device *ndev)
  1215. {
  1216. struct fec_enet_private *fep = netdev_priv(ndev);
  1217. int ret;
  1218. napi_enable(&fep->napi);
  1219. /* I should reset the ring buffers here, but I don't yet know
  1220. * a simple way to do that.
  1221. */
  1222. ret = fec_enet_alloc_buffers(ndev);
  1223. if (ret)
  1224. return ret;
  1225. /* Probe and connect to PHY when open the interface */
  1226. ret = fec_enet_mii_probe(ndev);
  1227. if (ret) {
  1228. fec_enet_free_buffers(ndev);
  1229. return ret;
  1230. }
  1231. phy_start(fep->phy_dev);
  1232. netif_start_queue(ndev);
  1233. fep->opened = 1;
  1234. return 0;
  1235. }
  1236. static int
  1237. fec_enet_close(struct net_device *ndev)
  1238. {
  1239. struct fec_enet_private *fep = netdev_priv(ndev);
  1240. /* Don't know what to do yet. */
  1241. napi_disable(&fep->napi);
  1242. fep->opened = 0;
  1243. netif_stop_queue(ndev);
  1244. fec_stop(ndev);
  1245. if (fep->phy_dev) {
  1246. phy_stop(fep->phy_dev);
  1247. phy_disconnect(fep->phy_dev);
  1248. }
  1249. fec_enet_free_buffers(ndev);
  1250. return 0;
  1251. }
  1252. /* Set or clear the multicast filter for this adaptor.
  1253. * Skeleton taken from sunlance driver.
  1254. * The CPM Ethernet implementation allows Multicast as well as individual
  1255. * MAC address filtering. Some of the drivers check to make sure it is
  1256. * a group multicast address, and discard those that are not. I guess I
  1257. * will do the same for now, but just remove the test if you want
  1258. * individual filtering as well (do the upper net layers want or support
  1259. * this kind of feature?).
  1260. */
  1261. #define HASH_BITS 6 /* #bits in hash */
  1262. #define CRC32_POLY 0xEDB88320
  1263. static void set_multicast_list(struct net_device *ndev)
  1264. {
  1265. struct fec_enet_private *fep = netdev_priv(ndev);
  1266. struct netdev_hw_addr *ha;
  1267. unsigned int i, bit, data, crc, tmp;
  1268. unsigned char hash;
  1269. if (ndev->flags & IFF_PROMISC) {
  1270. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1271. tmp |= 0x8;
  1272. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1273. return;
  1274. }
  1275. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1276. tmp &= ~0x8;
  1277. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1278. if (ndev->flags & IFF_ALLMULTI) {
  1279. /* Catch all multicast addresses, so set the
  1280. * filter to all 1's
  1281. */
  1282. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1283. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1284. return;
  1285. }
  1286. /* Clear filter and add the addresses in hash register
  1287. */
  1288. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1289. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1290. netdev_for_each_mc_addr(ha, ndev) {
  1291. /* calculate crc32 value of mac address */
  1292. crc = 0xffffffff;
  1293. for (i = 0; i < ndev->addr_len; i++) {
  1294. data = ha->addr[i];
  1295. for (bit = 0; bit < 8; bit++, data >>= 1) {
  1296. crc = (crc >> 1) ^
  1297. (((crc ^ data) & 1) ? CRC32_POLY : 0);
  1298. }
  1299. }
  1300. /* only upper 6 bits (HASH_BITS) are used
  1301. * which point to specific bit in he hash registers
  1302. */
  1303. hash = (crc >> (32 - HASH_BITS)) & 0x3f;
  1304. if (hash > 31) {
  1305. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1306. tmp |= 1 << (hash - 32);
  1307. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1308. } else {
  1309. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1310. tmp |= 1 << hash;
  1311. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1312. }
  1313. }
  1314. }
  1315. /* Set a MAC change in hardware. */
  1316. static int
  1317. fec_set_mac_address(struct net_device *ndev, void *p)
  1318. {
  1319. struct fec_enet_private *fep = netdev_priv(ndev);
  1320. struct sockaddr *addr = p;
  1321. if (!is_valid_ether_addr(addr->sa_data))
  1322. return -EADDRNOTAVAIL;
  1323. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  1324. writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
  1325. (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
  1326. fep->hwp + FEC_ADDR_LOW);
  1327. writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
  1328. fep->hwp + FEC_ADDR_HIGH);
  1329. return 0;
  1330. }
  1331. #ifdef CONFIG_NET_POLL_CONTROLLER
  1332. /**
  1333. * fec_poll_controller - FEC Poll controller function
  1334. * @dev: The FEC network adapter
  1335. *
  1336. * Polled functionality used by netconsole and others in non interrupt mode
  1337. *
  1338. */
  1339. static void fec_poll_controller(struct net_device *dev)
  1340. {
  1341. int i;
  1342. struct fec_enet_private *fep = netdev_priv(dev);
  1343. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1344. if (fep->irq[i] > 0) {
  1345. disable_irq(fep->irq[i]);
  1346. fec_enet_interrupt(fep->irq[i], dev);
  1347. enable_irq(fep->irq[i]);
  1348. }
  1349. }
  1350. }
  1351. #endif
  1352. static const struct net_device_ops fec_netdev_ops = {
  1353. .ndo_open = fec_enet_open,
  1354. .ndo_stop = fec_enet_close,
  1355. .ndo_start_xmit = fec_enet_start_xmit,
  1356. .ndo_set_rx_mode = set_multicast_list,
  1357. .ndo_change_mtu = eth_change_mtu,
  1358. .ndo_validate_addr = eth_validate_addr,
  1359. .ndo_tx_timeout = fec_timeout,
  1360. .ndo_set_mac_address = fec_set_mac_address,
  1361. .ndo_do_ioctl = fec_enet_ioctl,
  1362. #ifdef CONFIG_NET_POLL_CONTROLLER
  1363. .ndo_poll_controller = fec_poll_controller,
  1364. #endif
  1365. };
  1366. /*
  1367. * XXX: We need to clean up on failure exits here.
  1368. *
  1369. */
  1370. static int fec_enet_init(struct net_device *ndev)
  1371. {
  1372. struct fec_enet_private *fep = netdev_priv(ndev);
  1373. struct bufdesc *cbd_base;
  1374. /* Allocate memory for buffer descriptors. */
  1375. cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
  1376. GFP_KERNEL);
  1377. if (!cbd_base)
  1378. return -ENOMEM;
  1379. memset(cbd_base, 0, PAGE_SIZE);
  1380. spin_lock_init(&fep->hw_lock);
  1381. fep->netdev = ndev;
  1382. /* Get the Ethernet address */
  1383. fec_get_mac(ndev);
  1384. /* Set receive and transmit descriptor base. */
  1385. fep->rx_bd_base = cbd_base;
  1386. if (fep->bufdesc_ex)
  1387. fep->tx_bd_base = (struct bufdesc *)
  1388. (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
  1389. else
  1390. fep->tx_bd_base = cbd_base + RX_RING_SIZE;
  1391. /* The FEC Ethernet specific entries in the device structure */
  1392. ndev->watchdog_timeo = TX_TIMEOUT;
  1393. ndev->netdev_ops = &fec_netdev_ops;
  1394. ndev->ethtool_ops = &fec_enet_ethtool_ops;
  1395. writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
  1396. netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
  1397. fec_restart(ndev, 0);
  1398. return 0;
  1399. }
  1400. #ifdef CONFIG_OF
  1401. static void fec_reset_phy(struct platform_device *pdev)
  1402. {
  1403. int err, phy_reset;
  1404. int msec = 1;
  1405. struct device_node *np = pdev->dev.of_node;
  1406. if (!np)
  1407. return;
  1408. of_property_read_u32(np, "phy-reset-duration", &msec);
  1409. /* A sane reset duration should not be longer than 1s */
  1410. if (msec > 1000)
  1411. msec = 1;
  1412. phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
  1413. if (!gpio_is_valid(phy_reset))
  1414. return;
  1415. err = devm_gpio_request_one(&pdev->dev, phy_reset,
  1416. GPIOF_OUT_INIT_LOW, "phy-reset");
  1417. if (err) {
  1418. dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
  1419. return;
  1420. }
  1421. msleep(msec);
  1422. gpio_set_value(phy_reset, 1);
  1423. }
  1424. #else /* CONFIG_OF */
  1425. static void fec_reset_phy(struct platform_device *pdev)
  1426. {
  1427. /*
  1428. * In case of platform probe, the reset has been done
  1429. * by machine code.
  1430. */
  1431. }
  1432. #endif /* CONFIG_OF */
  1433. static int
  1434. fec_probe(struct platform_device *pdev)
  1435. {
  1436. struct fec_enet_private *fep;
  1437. struct fec_platform_data *pdata;
  1438. struct net_device *ndev;
  1439. int i, irq, ret = 0;
  1440. struct resource *r;
  1441. const struct of_device_id *of_id;
  1442. static int dev_id;
  1443. struct pinctrl *pinctrl;
  1444. struct regulator *reg_phy;
  1445. of_id = of_match_device(fec_dt_ids, &pdev->dev);
  1446. if (of_id)
  1447. pdev->id_entry = of_id->data;
  1448. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1449. if (!r)
  1450. return -ENXIO;
  1451. /* Init network device */
  1452. ndev = alloc_etherdev(sizeof(struct fec_enet_private));
  1453. if (!ndev)
  1454. return -ENOMEM;
  1455. SET_NETDEV_DEV(ndev, &pdev->dev);
  1456. /* setup board info structure */
  1457. fep = netdev_priv(ndev);
  1458. /* default enable pause frame auto negotiation */
  1459. if (pdev->id_entry &&
  1460. (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
  1461. fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
  1462. fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
  1463. fep->pdev = pdev;
  1464. fep->dev_id = dev_id++;
  1465. fep->bufdesc_ex = 0;
  1466. if (!fep->hwp) {
  1467. ret = -ENOMEM;
  1468. goto failed_ioremap;
  1469. }
  1470. platform_set_drvdata(pdev, ndev);
  1471. ret = of_get_phy_mode(pdev->dev.of_node);
  1472. if (ret < 0) {
  1473. pdata = pdev->dev.platform_data;
  1474. if (pdata)
  1475. fep->phy_interface = pdata->phy;
  1476. else
  1477. fep->phy_interface = PHY_INTERFACE_MODE_MII;
  1478. } else {
  1479. fep->phy_interface = ret;
  1480. }
  1481. pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  1482. if (IS_ERR(pinctrl)) {
  1483. ret = PTR_ERR(pinctrl);
  1484. goto failed_pin;
  1485. }
  1486. fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1487. if (IS_ERR(fep->clk_ipg)) {
  1488. ret = PTR_ERR(fep->clk_ipg);
  1489. goto failed_clk;
  1490. }
  1491. fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1492. if (IS_ERR(fep->clk_ahb)) {
  1493. ret = PTR_ERR(fep->clk_ahb);
  1494. goto failed_clk;
  1495. }
  1496. fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
  1497. fep->bufdesc_ex =
  1498. pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
  1499. if (IS_ERR(fep->clk_ptp)) {
  1500. ret = PTR_ERR(fep->clk_ptp);
  1501. fep->bufdesc_ex = 0;
  1502. }
  1503. clk_prepare_enable(fep->clk_ahb);
  1504. clk_prepare_enable(fep->clk_ipg);
  1505. if (!IS_ERR(fep->clk_ptp))
  1506. clk_prepare_enable(fep->clk_ptp);
  1507. reg_phy = devm_regulator_get(&pdev->dev, "phy");
  1508. if (!IS_ERR(reg_phy)) {
  1509. ret = regulator_enable(reg_phy);
  1510. if (ret) {
  1511. dev_err(&pdev->dev,
  1512. "Failed to enable phy regulator: %d\n", ret);
  1513. goto failed_regulator;
  1514. }
  1515. }
  1516. fec_reset_phy(pdev);
  1517. if (fep->bufdesc_ex)
  1518. fec_ptp_init(ndev, pdev);
  1519. ret = fec_enet_init(ndev);
  1520. if (ret)
  1521. goto failed_init;
  1522. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1523. irq = platform_get_irq(pdev, i);
  1524. if (irq < 0) {
  1525. if (i)
  1526. break;
  1527. ret = irq;
  1528. goto failed_irq;
  1529. }
  1530. ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
  1531. if (ret) {
  1532. while (--i >= 0) {
  1533. irq = platform_get_irq(pdev, i);
  1534. free_irq(irq, ndev);
  1535. }
  1536. goto failed_irq;
  1537. }
  1538. }
  1539. ret = fec_enet_mii_init(pdev);
  1540. if (ret)
  1541. goto failed_mii_init;
  1542. /* Carrier starts down, phylib will bring it up */
  1543. netif_carrier_off(ndev);
  1544. ret = register_netdev(ndev);
  1545. if (ret)
  1546. goto failed_register;
  1547. if (fep->bufdesc_ex && fep->ptp_clock)
  1548. netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
  1549. return 0;
  1550. failed_register:
  1551. fec_enet_mii_remove(fep);
  1552. failed_mii_init:
  1553. failed_init:
  1554. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1555. irq = platform_get_irq(pdev, i);
  1556. if (irq > 0)
  1557. free_irq(irq, ndev);
  1558. }
  1559. failed_irq:
  1560. failed_regulator:
  1561. clk_disable_unprepare(fep->clk_ahb);
  1562. clk_disable_unprepare(fep->clk_ipg);
  1563. if (!IS_ERR(fep->clk_ptp))
  1564. clk_disable_unprepare(fep->clk_ptp);
  1565. failed_pin:
  1566. failed_clk:
  1567. failed_ioremap:
  1568. free_netdev(ndev);
  1569. return ret;
  1570. }
  1571. static int
  1572. fec_drv_remove(struct platform_device *pdev)
  1573. {
  1574. struct net_device *ndev = platform_get_drvdata(pdev);
  1575. struct fec_enet_private *fep = netdev_priv(ndev);
  1576. int i;
  1577. unregister_netdev(ndev);
  1578. fec_enet_mii_remove(fep);
  1579. del_timer_sync(&fep->time_keep);
  1580. clk_disable_unprepare(fep->clk_ptp);
  1581. if (fep->ptp_clock)
  1582. ptp_clock_unregister(fep->ptp_clock);
  1583. clk_disable_unprepare(fep->clk_ahb);
  1584. clk_disable_unprepare(fep->clk_ipg);
  1585. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1586. int irq = platform_get_irq(pdev, i);
  1587. if (irq > 0)
  1588. free_irq(irq, ndev);
  1589. }
  1590. free_netdev(ndev);
  1591. platform_set_drvdata(pdev, NULL);
  1592. return 0;
  1593. }
  1594. #ifdef CONFIG_PM_SLEEP
  1595. static int
  1596. fec_suspend(struct device *dev)
  1597. {
  1598. struct net_device *ndev = dev_get_drvdata(dev);
  1599. struct fec_enet_private *fep = netdev_priv(ndev);
  1600. if (netif_running(ndev)) {
  1601. fec_stop(ndev);
  1602. netif_device_detach(ndev);
  1603. }
  1604. clk_disable_unprepare(fep->clk_ahb);
  1605. clk_disable_unprepare(fep->clk_ipg);
  1606. return 0;
  1607. }
  1608. static int
  1609. fec_resume(struct device *dev)
  1610. {
  1611. struct net_device *ndev = dev_get_drvdata(dev);
  1612. struct fec_enet_private *fep = netdev_priv(ndev);
  1613. clk_prepare_enable(fep->clk_ahb);
  1614. clk_prepare_enable(fep->clk_ipg);
  1615. if (netif_running(ndev)) {
  1616. fec_restart(ndev, fep->full_duplex);
  1617. netif_device_attach(ndev);
  1618. }
  1619. return 0;
  1620. }
  1621. #endif /* CONFIG_PM_SLEEP */
  1622. static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
  1623. static struct platform_driver fec_driver = {
  1624. .driver = {
  1625. .name = DRIVER_NAME,
  1626. .owner = THIS_MODULE,
  1627. .pm = &fec_pm_ops,
  1628. .of_match_table = fec_dt_ids,
  1629. },
  1630. .id_table = fec_devtype,
  1631. .probe = fec_probe,
  1632. .remove = fec_drv_remove,
  1633. };
  1634. module_platform_driver(fec_driver);
  1635. MODULE_LICENSE("GPL");