mthca_main.c 33 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  52. int mthca_debug_level = 0;
  53. module_param_named(debug_level, mthca_debug_level, int, 0644);
  54. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  55. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  56. #ifdef CONFIG_PCI_MSI
  57. static int msi_x = 0;
  58. module_param(msi_x, int, 0444);
  59. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  60. static int msi = 0;
  61. module_param(msi, int, 0444);
  62. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  63. #else /* CONFIG_PCI_MSI */
  64. #define msi_x (0)
  65. #define msi (0)
  66. #endif /* CONFIG_PCI_MSI */
  67. static const char mthca_version[] __devinitdata =
  68. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  69. DRV_VERSION " (" DRV_RELDATE ")\n";
  70. static struct mthca_profile default_profile = {
  71. .num_qp = 1 << 16,
  72. .rdb_per_qp = 4,
  73. .num_cq = 1 << 16,
  74. .num_mcg = 1 << 13,
  75. .num_mpt = 1 << 17,
  76. .num_mtt = 1 << 20,
  77. .num_udav = 1 << 15, /* Tavor only */
  78. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  79. .uarc_size = 1 << 18, /* Arbel only */
  80. };
  81. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  82. {
  83. int cap;
  84. u16 val;
  85. /* First try to max out Read Byte Count */
  86. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  87. if (cap) {
  88. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  89. mthca_err(mdev, "Couldn't read PCI-X command register, "
  90. "aborting.\n");
  91. return -ENODEV;
  92. }
  93. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  94. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  95. mthca_err(mdev, "Couldn't write PCI-X command register, "
  96. "aborting.\n");
  97. return -ENODEV;
  98. }
  99. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  100. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  101. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  102. if (cap) {
  103. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  104. mthca_err(mdev, "Couldn't read PCI Express device control "
  105. "register, aborting.\n");
  106. return -ENODEV;
  107. }
  108. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  109. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  110. mthca_err(mdev, "Couldn't write PCI Express device control "
  111. "register, aborting.\n");
  112. return -ENODEV;
  113. }
  114. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  115. mthca_info(mdev, "No PCI Express capability, "
  116. "not setting Max Read Request Size.\n");
  117. return 0;
  118. }
  119. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  120. {
  121. int err;
  122. u8 status;
  123. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  124. if (err) {
  125. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  126. return err;
  127. }
  128. if (status) {
  129. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  130. "aborting.\n", status);
  131. return -EINVAL;
  132. }
  133. if (dev_lim->min_page_sz > PAGE_SIZE) {
  134. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  135. "kernel PAGE_SIZE of %ld, aborting.\n",
  136. dev_lim->min_page_sz, PAGE_SIZE);
  137. return -ENODEV;
  138. }
  139. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  140. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  141. "aborting.\n",
  142. dev_lim->num_ports, MTHCA_MAX_PORTS);
  143. return -ENODEV;
  144. }
  145. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  146. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  147. "PCI resource 2 size of 0x%lx, aborting.\n",
  148. dev_lim->uar_size, pci_resource_len(mdev->pdev, 2));
  149. return -ENODEV;
  150. }
  151. mdev->limits.num_ports = dev_lim->num_ports;
  152. mdev->limits.vl_cap = dev_lim->max_vl;
  153. mdev->limits.mtu_cap = dev_lim->max_mtu;
  154. mdev->limits.gid_table_len = dev_lim->max_gids;
  155. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  156. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  157. mdev->limits.max_sg = dev_lim->max_sg;
  158. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  159. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  160. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  161. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  162. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  163. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  164. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  165. /*
  166. * Subtract 1 from the limit because we need to allocate a
  167. * spare CQE so the HCA HW can tell the difference between an
  168. * empty CQ and a full CQ.
  169. */
  170. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  171. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  172. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  173. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  174. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  175. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  176. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  177. mdev->limits.port_width_cap = dev_lim->max_port_width;
  178. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  179. mdev->limits.flags = dev_lim->flags;
  180. /*
  181. * For old FW that doesn't return static rate support, use a
  182. * value of 0x3 (only static rate values of 0 or 1 are handled),
  183. * except on Sinai, where even old FW can handle static rate
  184. * values of 2 and 3.
  185. */
  186. if (dev_lim->stat_rate_support)
  187. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  188. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  189. mdev->limits.stat_rate_support = 0xf;
  190. else
  191. mdev->limits.stat_rate_support = 0x3;
  192. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  193. May be doable since hardware supports it for SRQ.
  194. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  195. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  196. supported by driver. */
  197. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  198. IB_DEVICE_PORT_ACTIVE_EVENT |
  199. IB_DEVICE_SYS_IMAGE_GUID |
  200. IB_DEVICE_RC_RNR_NAK_GEN;
  201. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  202. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  203. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  204. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  205. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  206. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  207. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  208. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  209. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  210. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  211. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  212. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  213. return 0;
  214. }
  215. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  216. {
  217. u8 status;
  218. int err;
  219. struct mthca_dev_lim dev_lim;
  220. struct mthca_profile profile;
  221. struct mthca_init_hca_param init_hca;
  222. err = mthca_SYS_EN(mdev, &status);
  223. if (err) {
  224. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  225. return err;
  226. }
  227. if (status) {
  228. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  229. "aborting.\n", status);
  230. return -EINVAL;
  231. }
  232. err = mthca_QUERY_FW(mdev, &status);
  233. if (err) {
  234. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  235. goto err_disable;
  236. }
  237. if (status) {
  238. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  239. "aborting.\n", status);
  240. err = -EINVAL;
  241. goto err_disable;
  242. }
  243. err = mthca_QUERY_DDR(mdev, &status);
  244. if (err) {
  245. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  246. goto err_disable;
  247. }
  248. if (status) {
  249. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  250. "aborting.\n", status);
  251. err = -EINVAL;
  252. goto err_disable;
  253. }
  254. err = mthca_dev_lim(mdev, &dev_lim);
  255. if (err) {
  256. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  257. goto err_disable;
  258. }
  259. profile = default_profile;
  260. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  261. profile.uarc_size = 0;
  262. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  263. profile.num_srq = dev_lim.max_srqs;
  264. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  265. if (err < 0)
  266. goto err_disable;
  267. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  268. if (err) {
  269. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  270. goto err_disable;
  271. }
  272. if (status) {
  273. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  274. "aborting.\n", status);
  275. err = -EINVAL;
  276. goto err_disable;
  277. }
  278. return 0;
  279. err_disable:
  280. mthca_SYS_DIS(mdev, &status);
  281. return err;
  282. }
  283. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  284. {
  285. u8 status;
  286. int err;
  287. /* FIXME: use HCA-attached memory for FW if present */
  288. mdev->fw.arbel.fw_icm =
  289. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  290. GFP_HIGHUSER | __GFP_NOWARN);
  291. if (!mdev->fw.arbel.fw_icm) {
  292. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  293. return -ENOMEM;
  294. }
  295. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  296. if (err) {
  297. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  298. goto err_free;
  299. }
  300. if (status) {
  301. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  302. err = -EINVAL;
  303. goto err_free;
  304. }
  305. err = mthca_RUN_FW(mdev, &status);
  306. if (err) {
  307. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  308. goto err_unmap_fa;
  309. }
  310. if (status) {
  311. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  312. err = -EINVAL;
  313. goto err_unmap_fa;
  314. }
  315. return 0;
  316. err_unmap_fa:
  317. mthca_UNMAP_FA(mdev, &status);
  318. err_free:
  319. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  320. return err;
  321. }
  322. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  323. struct mthca_dev_lim *dev_lim,
  324. struct mthca_init_hca_param *init_hca,
  325. u64 icm_size)
  326. {
  327. u64 aux_pages;
  328. u8 status;
  329. int err;
  330. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  331. if (err) {
  332. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  333. return err;
  334. }
  335. if (status) {
  336. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  337. "aborting.\n", status);
  338. return -EINVAL;
  339. }
  340. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  341. (unsigned long long) icm_size >> 10,
  342. (unsigned long long) aux_pages << 2);
  343. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  344. GFP_HIGHUSER | __GFP_NOWARN);
  345. if (!mdev->fw.arbel.aux_icm) {
  346. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  347. return -ENOMEM;
  348. }
  349. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  350. if (err) {
  351. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  352. goto err_free_aux;
  353. }
  354. if (status) {
  355. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  356. err = -EINVAL;
  357. goto err_free_aux;
  358. }
  359. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  360. if (err) {
  361. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  362. goto err_unmap_aux;
  363. }
  364. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  365. MTHCA_MTT_SEG_SIZE,
  366. mdev->limits.num_mtt_segs,
  367. mdev->limits.reserved_mtts, 1);
  368. if (!mdev->mr_table.mtt_table) {
  369. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  370. err = -ENOMEM;
  371. goto err_unmap_eq;
  372. }
  373. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  374. dev_lim->mpt_entry_sz,
  375. mdev->limits.num_mpts,
  376. mdev->limits.reserved_mrws, 1);
  377. if (!mdev->mr_table.mpt_table) {
  378. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  379. err = -ENOMEM;
  380. goto err_unmap_mtt;
  381. }
  382. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  383. dev_lim->qpc_entry_sz,
  384. mdev->limits.num_qps,
  385. mdev->limits.reserved_qps, 0);
  386. if (!mdev->qp_table.qp_table) {
  387. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  388. err = -ENOMEM;
  389. goto err_unmap_mpt;
  390. }
  391. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  392. dev_lim->eqpc_entry_sz,
  393. mdev->limits.num_qps,
  394. mdev->limits.reserved_qps, 0);
  395. if (!mdev->qp_table.eqp_table) {
  396. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  397. err = -ENOMEM;
  398. goto err_unmap_qp;
  399. }
  400. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  401. MTHCA_RDB_ENTRY_SIZE,
  402. mdev->limits.num_qps <<
  403. mdev->qp_table.rdb_shift,
  404. 0, 0);
  405. if (!mdev->qp_table.rdb_table) {
  406. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  407. err = -ENOMEM;
  408. goto err_unmap_eqp;
  409. }
  410. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  411. dev_lim->cqc_entry_sz,
  412. mdev->limits.num_cqs,
  413. mdev->limits.reserved_cqs, 0);
  414. if (!mdev->cq_table.table) {
  415. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  416. err = -ENOMEM;
  417. goto err_unmap_rdb;
  418. }
  419. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  420. mdev->srq_table.table =
  421. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  422. dev_lim->srq_entry_sz,
  423. mdev->limits.num_srqs,
  424. mdev->limits.reserved_srqs, 0);
  425. if (!mdev->srq_table.table) {
  426. mthca_err(mdev, "Failed to map SRQ context memory, "
  427. "aborting.\n");
  428. err = -ENOMEM;
  429. goto err_unmap_cq;
  430. }
  431. }
  432. /*
  433. * It's not strictly required, but for simplicity just map the
  434. * whole multicast group table now. The table isn't very big
  435. * and it's a lot easier than trying to track ref counts.
  436. */
  437. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  438. MTHCA_MGM_ENTRY_SIZE,
  439. mdev->limits.num_mgms +
  440. mdev->limits.num_amgms,
  441. mdev->limits.num_mgms +
  442. mdev->limits.num_amgms,
  443. 0);
  444. if (!mdev->mcg_table.table) {
  445. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  446. err = -ENOMEM;
  447. goto err_unmap_srq;
  448. }
  449. return 0;
  450. err_unmap_srq:
  451. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  452. mthca_free_icm_table(mdev, mdev->srq_table.table);
  453. err_unmap_cq:
  454. mthca_free_icm_table(mdev, mdev->cq_table.table);
  455. err_unmap_rdb:
  456. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  457. err_unmap_eqp:
  458. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  459. err_unmap_qp:
  460. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  461. err_unmap_mpt:
  462. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  463. err_unmap_mtt:
  464. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  465. err_unmap_eq:
  466. mthca_unmap_eq_icm(mdev);
  467. err_unmap_aux:
  468. mthca_UNMAP_ICM_AUX(mdev, &status);
  469. err_free_aux:
  470. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  471. return err;
  472. }
  473. static void mthca_free_icms(struct mthca_dev *mdev)
  474. {
  475. u8 status;
  476. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  477. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  478. mthca_free_icm_table(mdev, mdev->srq_table.table);
  479. mthca_free_icm_table(mdev, mdev->cq_table.table);
  480. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  481. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  482. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  483. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  484. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  485. mthca_unmap_eq_icm(mdev);
  486. mthca_UNMAP_ICM_AUX(mdev, &status);
  487. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  488. }
  489. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  490. {
  491. struct mthca_dev_lim dev_lim;
  492. struct mthca_profile profile;
  493. struct mthca_init_hca_param init_hca;
  494. u64 icm_size;
  495. u8 status;
  496. int err;
  497. err = mthca_QUERY_FW(mdev, &status);
  498. if (err) {
  499. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  500. return err;
  501. }
  502. if (status) {
  503. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  504. "aborting.\n", status);
  505. return -EINVAL;
  506. }
  507. err = mthca_ENABLE_LAM(mdev, &status);
  508. if (err) {
  509. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  510. return err;
  511. }
  512. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  513. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  514. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  515. } else if (status) {
  516. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  517. "aborting.\n", status);
  518. return -EINVAL;
  519. }
  520. err = mthca_load_fw(mdev);
  521. if (err) {
  522. mthca_err(mdev, "Failed to start FW, aborting.\n");
  523. goto err_disable;
  524. }
  525. err = mthca_dev_lim(mdev, &dev_lim);
  526. if (err) {
  527. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  528. goto err_stop_fw;
  529. }
  530. profile = default_profile;
  531. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  532. profile.num_udav = 0;
  533. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  534. profile.num_srq = dev_lim.max_srqs;
  535. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  536. if ((int) icm_size < 0) {
  537. err = icm_size;
  538. goto err_stop_fw;
  539. }
  540. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  541. if (err)
  542. goto err_stop_fw;
  543. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  544. if (err) {
  545. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  546. goto err_free_icm;
  547. }
  548. if (status) {
  549. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  550. "aborting.\n", status);
  551. err = -EINVAL;
  552. goto err_free_icm;
  553. }
  554. return 0;
  555. err_free_icm:
  556. mthca_free_icms(mdev);
  557. err_stop_fw:
  558. mthca_UNMAP_FA(mdev, &status);
  559. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  560. err_disable:
  561. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  562. mthca_DISABLE_LAM(mdev, &status);
  563. return err;
  564. }
  565. static void mthca_close_hca(struct mthca_dev *mdev)
  566. {
  567. u8 status;
  568. mthca_CLOSE_HCA(mdev, 0, &status);
  569. if (mthca_is_memfree(mdev)) {
  570. mthca_free_icms(mdev);
  571. mthca_UNMAP_FA(mdev, &status);
  572. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  573. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  574. mthca_DISABLE_LAM(mdev, &status);
  575. } else
  576. mthca_SYS_DIS(mdev, &status);
  577. }
  578. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  579. {
  580. u8 status;
  581. int err;
  582. struct mthca_adapter adapter;
  583. if (mthca_is_memfree(mdev))
  584. err = mthca_init_arbel(mdev);
  585. else
  586. err = mthca_init_tavor(mdev);
  587. if (err)
  588. return err;
  589. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  590. if (err) {
  591. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  592. goto err_close;
  593. }
  594. if (status) {
  595. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  596. "aborting.\n", status);
  597. err = -EINVAL;
  598. goto err_close;
  599. }
  600. mdev->eq_table.inta_pin = adapter.inta_pin;
  601. mdev->rev_id = adapter.revision_id;
  602. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  603. return 0;
  604. err_close:
  605. mthca_close_hca(mdev);
  606. return err;
  607. }
  608. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  609. {
  610. int err;
  611. u8 status;
  612. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  613. err = mthca_init_uar_table(dev);
  614. if (err) {
  615. mthca_err(dev, "Failed to initialize "
  616. "user access region table, aborting.\n");
  617. return err;
  618. }
  619. err = mthca_uar_alloc(dev, &dev->driver_uar);
  620. if (err) {
  621. mthca_err(dev, "Failed to allocate driver access region, "
  622. "aborting.\n");
  623. goto err_uar_table_free;
  624. }
  625. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  626. if (!dev->kar) {
  627. mthca_err(dev, "Couldn't map kernel access region, "
  628. "aborting.\n");
  629. err = -ENOMEM;
  630. goto err_uar_free;
  631. }
  632. err = mthca_init_pd_table(dev);
  633. if (err) {
  634. mthca_err(dev, "Failed to initialize "
  635. "protection domain table, aborting.\n");
  636. goto err_kar_unmap;
  637. }
  638. err = mthca_init_mr_table(dev);
  639. if (err) {
  640. mthca_err(dev, "Failed to initialize "
  641. "memory region table, aborting.\n");
  642. goto err_pd_table_free;
  643. }
  644. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  645. if (err) {
  646. mthca_err(dev, "Failed to create driver PD, "
  647. "aborting.\n");
  648. goto err_mr_table_free;
  649. }
  650. err = mthca_init_eq_table(dev);
  651. if (err) {
  652. mthca_err(dev, "Failed to initialize "
  653. "event queue table, aborting.\n");
  654. goto err_pd_free;
  655. }
  656. err = mthca_cmd_use_events(dev);
  657. if (err) {
  658. mthca_err(dev, "Failed to switch to event-driven "
  659. "firmware commands, aborting.\n");
  660. goto err_eq_table_free;
  661. }
  662. err = mthca_NOP(dev, &status);
  663. if (err || status) {
  664. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  665. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  666. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  667. dev->pdev->irq);
  668. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  669. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  670. else
  671. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  672. goto err_cmd_poll;
  673. }
  674. mthca_dbg(dev, "NOP command IRQ test passed\n");
  675. err = mthca_init_cq_table(dev);
  676. if (err) {
  677. mthca_err(dev, "Failed to initialize "
  678. "completion queue table, aborting.\n");
  679. goto err_cmd_poll;
  680. }
  681. err = mthca_init_srq_table(dev);
  682. if (err) {
  683. mthca_err(dev, "Failed to initialize "
  684. "shared receive queue table, aborting.\n");
  685. goto err_cq_table_free;
  686. }
  687. err = mthca_init_qp_table(dev);
  688. if (err) {
  689. mthca_err(dev, "Failed to initialize "
  690. "queue pair table, aborting.\n");
  691. goto err_srq_table_free;
  692. }
  693. err = mthca_init_av_table(dev);
  694. if (err) {
  695. mthca_err(dev, "Failed to initialize "
  696. "address vector table, aborting.\n");
  697. goto err_qp_table_free;
  698. }
  699. err = mthca_init_mcg_table(dev);
  700. if (err) {
  701. mthca_err(dev, "Failed to initialize "
  702. "multicast group table, aborting.\n");
  703. goto err_av_table_free;
  704. }
  705. return 0;
  706. err_av_table_free:
  707. mthca_cleanup_av_table(dev);
  708. err_qp_table_free:
  709. mthca_cleanup_qp_table(dev);
  710. err_srq_table_free:
  711. mthca_cleanup_srq_table(dev);
  712. err_cq_table_free:
  713. mthca_cleanup_cq_table(dev);
  714. err_cmd_poll:
  715. mthca_cmd_use_polling(dev);
  716. err_eq_table_free:
  717. mthca_cleanup_eq_table(dev);
  718. err_pd_free:
  719. mthca_pd_free(dev, &dev->driver_pd);
  720. err_mr_table_free:
  721. mthca_cleanup_mr_table(dev);
  722. err_pd_table_free:
  723. mthca_cleanup_pd_table(dev);
  724. err_kar_unmap:
  725. iounmap(dev->kar);
  726. err_uar_free:
  727. mthca_uar_free(dev, &dev->driver_uar);
  728. err_uar_table_free:
  729. mthca_cleanup_uar_table(dev);
  730. return err;
  731. }
  732. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  733. int ddr_hidden)
  734. {
  735. int err;
  736. /*
  737. * We can't just use pci_request_regions() because the MSI-X
  738. * table is right in the middle of the first BAR. If we did
  739. * pci_request_region and grab all of the first BAR, then
  740. * setting up MSI-X would fail, since the PCI core wants to do
  741. * request_mem_region on the MSI-X vector table.
  742. *
  743. * So just request what we need right now, and request any
  744. * other regions we need when setting up EQs.
  745. */
  746. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  747. MTHCA_HCR_SIZE, DRV_NAME))
  748. return -EBUSY;
  749. err = pci_request_region(pdev, 2, DRV_NAME);
  750. if (err)
  751. goto err_bar2_failed;
  752. if (!ddr_hidden) {
  753. err = pci_request_region(pdev, 4, DRV_NAME);
  754. if (err)
  755. goto err_bar4_failed;
  756. }
  757. return 0;
  758. err_bar4_failed:
  759. pci_release_region(pdev, 2);
  760. err_bar2_failed:
  761. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  762. MTHCA_HCR_SIZE);
  763. return err;
  764. }
  765. static void mthca_release_regions(struct pci_dev *pdev,
  766. int ddr_hidden)
  767. {
  768. if (!ddr_hidden)
  769. pci_release_region(pdev, 4);
  770. pci_release_region(pdev, 2);
  771. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  772. MTHCA_HCR_SIZE);
  773. }
  774. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  775. {
  776. struct msix_entry entries[3];
  777. int err;
  778. entries[0].entry = 0;
  779. entries[1].entry = 1;
  780. entries[2].entry = 2;
  781. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  782. if (err) {
  783. if (err > 0)
  784. mthca_info(mdev, "Only %d MSI-X vectors available, "
  785. "not using MSI-X\n", err);
  786. return err;
  787. }
  788. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  789. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  790. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  791. return 0;
  792. }
  793. /* Types of supported HCA */
  794. enum {
  795. TAVOR, /* MT23108 */
  796. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  797. ARBEL_NATIVE, /* MT25208 with extended features */
  798. SINAI /* MT25204 */
  799. };
  800. #define MTHCA_FW_VER(major, minor, subminor) \
  801. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  802. static struct {
  803. u64 latest_fw;
  804. u32 flags;
  805. } mthca_hca_table[] = {
  806. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 4, 0),
  807. .flags = 0 },
  808. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 400),
  809. .flags = MTHCA_FLAG_PCIE },
  810. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0),
  811. .flags = MTHCA_FLAG_MEMFREE |
  812. MTHCA_FLAG_PCIE },
  813. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 800),
  814. .flags = MTHCA_FLAG_MEMFREE |
  815. MTHCA_FLAG_PCIE |
  816. MTHCA_FLAG_SINAI_OPT }
  817. };
  818. static int __devinit mthca_init_one(struct pci_dev *pdev,
  819. const struct pci_device_id *id)
  820. {
  821. static int mthca_version_printed = 0;
  822. int ddr_hidden = 0;
  823. int err;
  824. struct mthca_dev *mdev;
  825. if (!mthca_version_printed) {
  826. printk(KERN_INFO "%s", mthca_version);
  827. ++mthca_version_printed;
  828. }
  829. printk(KERN_INFO PFX "Initializing %s\n",
  830. pci_name(pdev));
  831. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  832. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  833. pci_name(pdev), id->driver_data);
  834. return -ENODEV;
  835. }
  836. err = pci_enable_device(pdev);
  837. if (err) {
  838. dev_err(&pdev->dev, "Cannot enable PCI device, "
  839. "aborting.\n");
  840. return err;
  841. }
  842. /*
  843. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  844. * be present)
  845. */
  846. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  847. pci_resource_len(pdev, 0) != 1 << 20) {
  848. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  849. err = -ENODEV;
  850. goto err_disable_pdev;
  851. }
  852. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  853. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  854. err = -ENODEV;
  855. goto err_disable_pdev;
  856. }
  857. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  858. ddr_hidden = 1;
  859. err = mthca_request_regions(pdev, ddr_hidden);
  860. if (err) {
  861. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  862. "aborting.\n");
  863. goto err_disable_pdev;
  864. }
  865. pci_set_master(pdev);
  866. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  867. if (err) {
  868. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  869. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  870. if (err) {
  871. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  872. goto err_free_res;
  873. }
  874. }
  875. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  876. if (err) {
  877. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  878. "consistent PCI DMA mask.\n");
  879. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  880. if (err) {
  881. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  882. "aborting.\n");
  883. goto err_free_res;
  884. }
  885. }
  886. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  887. if (!mdev) {
  888. dev_err(&pdev->dev, "Device struct alloc failed, "
  889. "aborting.\n");
  890. err = -ENOMEM;
  891. goto err_free_res;
  892. }
  893. mdev->pdev = pdev;
  894. mdev->mthca_flags = mthca_hca_table[id->driver_data].flags;
  895. if (ddr_hidden)
  896. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  897. /*
  898. * Now reset the HCA before we touch the PCI capabilities or
  899. * attempt a firmware command, since a boot ROM may have left
  900. * the HCA in an undefined state.
  901. */
  902. err = mthca_reset(mdev);
  903. if (err) {
  904. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  905. goto err_free_dev;
  906. }
  907. if (msi_x && !mthca_enable_msi_x(mdev))
  908. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  909. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  910. !pci_enable_msi(pdev))
  911. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  912. if (mthca_cmd_init(mdev)) {
  913. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  914. goto err_free_dev;
  915. }
  916. err = mthca_tune_pci(mdev);
  917. if (err)
  918. goto err_cmd;
  919. err = mthca_init_hca(mdev);
  920. if (err)
  921. goto err_cmd;
  922. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  923. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  924. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  925. (int) (mdev->fw_ver & 0xffff),
  926. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  927. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  928. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  929. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  930. }
  931. err = mthca_setup_hca(mdev);
  932. if (err)
  933. goto err_close;
  934. err = mthca_register_device(mdev);
  935. if (err)
  936. goto err_cleanup;
  937. err = mthca_create_agents(mdev);
  938. if (err)
  939. goto err_unregister;
  940. pci_set_drvdata(pdev, mdev);
  941. return 0;
  942. err_unregister:
  943. mthca_unregister_device(mdev);
  944. err_cleanup:
  945. mthca_cleanup_mcg_table(mdev);
  946. mthca_cleanup_av_table(mdev);
  947. mthca_cleanup_qp_table(mdev);
  948. mthca_cleanup_srq_table(mdev);
  949. mthca_cleanup_cq_table(mdev);
  950. mthca_cmd_use_polling(mdev);
  951. mthca_cleanup_eq_table(mdev);
  952. mthca_pd_free(mdev, &mdev->driver_pd);
  953. mthca_cleanup_mr_table(mdev);
  954. mthca_cleanup_pd_table(mdev);
  955. mthca_cleanup_uar_table(mdev);
  956. err_close:
  957. mthca_close_hca(mdev);
  958. err_cmd:
  959. mthca_cmd_cleanup(mdev);
  960. err_free_dev:
  961. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  962. pci_disable_msix(pdev);
  963. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  964. pci_disable_msi(pdev);
  965. ib_dealloc_device(&mdev->ib_dev);
  966. err_free_res:
  967. mthca_release_regions(pdev, ddr_hidden);
  968. err_disable_pdev:
  969. pci_disable_device(pdev);
  970. pci_set_drvdata(pdev, NULL);
  971. return err;
  972. }
  973. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  974. {
  975. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  976. u8 status;
  977. int p;
  978. if (mdev) {
  979. mthca_free_agents(mdev);
  980. mthca_unregister_device(mdev);
  981. for (p = 1; p <= mdev->limits.num_ports; ++p)
  982. mthca_CLOSE_IB(mdev, p, &status);
  983. mthca_cleanup_mcg_table(mdev);
  984. mthca_cleanup_av_table(mdev);
  985. mthca_cleanup_qp_table(mdev);
  986. mthca_cleanup_srq_table(mdev);
  987. mthca_cleanup_cq_table(mdev);
  988. mthca_cmd_use_polling(mdev);
  989. mthca_cleanup_eq_table(mdev);
  990. mthca_pd_free(mdev, &mdev->driver_pd);
  991. mthca_cleanup_mr_table(mdev);
  992. mthca_cleanup_pd_table(mdev);
  993. iounmap(mdev->kar);
  994. mthca_uar_free(mdev, &mdev->driver_uar);
  995. mthca_cleanup_uar_table(mdev);
  996. mthca_close_hca(mdev);
  997. mthca_cmd_cleanup(mdev);
  998. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  999. pci_disable_msix(pdev);
  1000. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  1001. pci_disable_msi(pdev);
  1002. ib_dealloc_device(&mdev->ib_dev);
  1003. mthca_release_regions(pdev, mdev->mthca_flags &
  1004. MTHCA_FLAG_DDR_HIDDEN);
  1005. pci_disable_device(pdev);
  1006. pci_set_drvdata(pdev, NULL);
  1007. }
  1008. }
  1009. static struct pci_device_id mthca_pci_table[] = {
  1010. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1011. .driver_data = TAVOR },
  1012. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1013. .driver_data = TAVOR },
  1014. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1015. .driver_data = ARBEL_COMPAT },
  1016. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1017. .driver_data = ARBEL_COMPAT },
  1018. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1019. .driver_data = ARBEL_NATIVE },
  1020. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1021. .driver_data = ARBEL_NATIVE },
  1022. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1023. .driver_data = SINAI },
  1024. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1025. .driver_data = SINAI },
  1026. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1027. .driver_data = SINAI },
  1028. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1029. .driver_data = SINAI },
  1030. { 0, }
  1031. };
  1032. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1033. static struct pci_driver mthca_driver = {
  1034. .name = DRV_NAME,
  1035. .id_table = mthca_pci_table,
  1036. .probe = mthca_init_one,
  1037. .remove = __devexit_p(mthca_remove_one)
  1038. };
  1039. static int __init mthca_init(void)
  1040. {
  1041. int ret;
  1042. ret = pci_register_driver(&mthca_driver);
  1043. return ret < 0 ? ret : 0;
  1044. }
  1045. static void __exit mthca_cleanup(void)
  1046. {
  1047. pci_unregister_driver(&mthca_driver);
  1048. }
  1049. module_init(mthca_init);
  1050. module_exit(mthca_cleanup);