qla_isr.c 80 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2012 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  16. struct req_que *, uint32_t);
  17. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  18. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  19. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  20. sts_entry_t *);
  21. /**
  22. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  23. * @irq:
  24. * @dev_id: SCSI driver HA context
  25. *
  26. * Called by system whenever the host adapter generates an interrupt.
  27. *
  28. * Returns handled flag.
  29. */
  30. irqreturn_t
  31. qla2100_intr_handler(int irq, void *dev_id)
  32. {
  33. scsi_qla_host_t *vha;
  34. struct qla_hw_data *ha;
  35. struct device_reg_2xxx __iomem *reg;
  36. int status;
  37. unsigned long iter;
  38. uint16_t hccr;
  39. uint16_t mb[4];
  40. struct rsp_que *rsp;
  41. unsigned long flags;
  42. rsp = (struct rsp_que *) dev_id;
  43. if (!rsp) {
  44. ql_log(ql_log_info, NULL, 0x505d,
  45. "%s: NULL response queue pointer.\n", __func__);
  46. return (IRQ_NONE);
  47. }
  48. ha = rsp->hw;
  49. reg = &ha->iobase->isp;
  50. status = 0;
  51. spin_lock_irqsave(&ha->hardware_lock, flags);
  52. vha = pci_get_drvdata(ha->pdev);
  53. for (iter = 50; iter--; ) {
  54. hccr = RD_REG_WORD(&reg->hccr);
  55. if (hccr & HCCR_RISC_PAUSE) {
  56. if (pci_channel_offline(ha->pdev))
  57. break;
  58. /*
  59. * Issue a "HARD" reset in order for the RISC interrupt
  60. * bit to be cleared. Schedule a big hammer to get
  61. * out of the RISC PAUSED state.
  62. */
  63. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  64. RD_REG_WORD(&reg->hccr);
  65. ha->isp_ops->fw_dump(vha, 1);
  66. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  67. break;
  68. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  69. break;
  70. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  71. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  72. RD_REG_WORD(&reg->hccr);
  73. /* Get mailbox data. */
  74. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  75. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  76. qla2x00_mbx_completion(vha, mb[0]);
  77. status |= MBX_INTERRUPT;
  78. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  79. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  80. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  81. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  82. qla2x00_async_event(vha, rsp, mb);
  83. } else {
  84. /*EMPTY*/
  85. ql_dbg(ql_dbg_async, vha, 0x5025,
  86. "Unrecognized interrupt type (%d).\n",
  87. mb[0]);
  88. }
  89. /* Release mailbox registers. */
  90. WRT_REG_WORD(&reg->semaphore, 0);
  91. RD_REG_WORD(&reg->semaphore);
  92. } else {
  93. qla2x00_process_response_queue(rsp);
  94. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  95. RD_REG_WORD(&reg->hccr);
  96. }
  97. }
  98. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  99. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  100. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  101. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  102. complete(&ha->mbx_intr_comp);
  103. }
  104. return (IRQ_HANDLED);
  105. }
  106. /**
  107. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  108. * @irq:
  109. * @dev_id: SCSI driver HA context
  110. *
  111. * Called by system whenever the host adapter generates an interrupt.
  112. *
  113. * Returns handled flag.
  114. */
  115. irqreturn_t
  116. qla2300_intr_handler(int irq, void *dev_id)
  117. {
  118. scsi_qla_host_t *vha;
  119. struct device_reg_2xxx __iomem *reg;
  120. int status;
  121. unsigned long iter;
  122. uint32_t stat;
  123. uint16_t hccr;
  124. uint16_t mb[4];
  125. struct rsp_que *rsp;
  126. struct qla_hw_data *ha;
  127. unsigned long flags;
  128. rsp = (struct rsp_que *) dev_id;
  129. if (!rsp) {
  130. ql_log(ql_log_info, NULL, 0x5058,
  131. "%s: NULL response queue pointer.\n", __func__);
  132. return (IRQ_NONE);
  133. }
  134. ha = rsp->hw;
  135. reg = &ha->iobase->isp;
  136. status = 0;
  137. spin_lock_irqsave(&ha->hardware_lock, flags);
  138. vha = pci_get_drvdata(ha->pdev);
  139. for (iter = 50; iter--; ) {
  140. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  141. if (stat & HSR_RISC_PAUSED) {
  142. if (unlikely(pci_channel_offline(ha->pdev)))
  143. break;
  144. hccr = RD_REG_WORD(&reg->hccr);
  145. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  146. ql_log(ql_log_warn, vha, 0x5026,
  147. "Parity error -- HCCR=%x, Dumping "
  148. "firmware.\n", hccr);
  149. else
  150. ql_log(ql_log_warn, vha, 0x5027,
  151. "RISC paused -- HCCR=%x, Dumping "
  152. "firmware.\n", hccr);
  153. /*
  154. * Issue a "HARD" reset in order for the RISC
  155. * interrupt bit to be cleared. Schedule a big
  156. * hammer to get out of the RISC PAUSED state.
  157. */
  158. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  159. RD_REG_WORD(&reg->hccr);
  160. ha->isp_ops->fw_dump(vha, 1);
  161. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  162. break;
  163. } else if ((stat & HSR_RISC_INT) == 0)
  164. break;
  165. switch (stat & 0xff) {
  166. case 0x1:
  167. case 0x2:
  168. case 0x10:
  169. case 0x11:
  170. qla2x00_mbx_completion(vha, MSW(stat));
  171. status |= MBX_INTERRUPT;
  172. /* Release mailbox registers. */
  173. WRT_REG_WORD(&reg->semaphore, 0);
  174. break;
  175. case 0x12:
  176. mb[0] = MSW(stat);
  177. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  178. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  179. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  180. qla2x00_async_event(vha, rsp, mb);
  181. break;
  182. case 0x13:
  183. qla2x00_process_response_queue(rsp);
  184. break;
  185. case 0x15:
  186. mb[0] = MBA_CMPLT_1_16BIT;
  187. mb[1] = MSW(stat);
  188. qla2x00_async_event(vha, rsp, mb);
  189. break;
  190. case 0x16:
  191. mb[0] = MBA_SCSI_COMPLETION;
  192. mb[1] = MSW(stat);
  193. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  194. qla2x00_async_event(vha, rsp, mb);
  195. break;
  196. default:
  197. ql_dbg(ql_dbg_async, vha, 0x5028,
  198. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  199. break;
  200. }
  201. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  202. RD_REG_WORD_RELAXED(&reg->hccr);
  203. }
  204. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  205. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  206. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  207. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  208. complete(&ha->mbx_intr_comp);
  209. }
  210. return (IRQ_HANDLED);
  211. }
  212. /**
  213. * qla2x00_mbx_completion() - Process mailbox command completions.
  214. * @ha: SCSI driver HA context
  215. * @mb0: Mailbox0 register
  216. */
  217. static void
  218. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  219. {
  220. uint16_t cnt;
  221. uint32_t mboxes;
  222. uint16_t __iomem *wptr;
  223. struct qla_hw_data *ha = vha->hw;
  224. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  225. /* Read all mbox registers? */
  226. mboxes = (1 << ha->mbx_count) - 1;
  227. if (!ha->mcp)
  228. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERRROR.\n");
  229. else
  230. mboxes = ha->mcp->in_mb;
  231. /* Load return mailbox registers. */
  232. ha->flags.mbox_int = 1;
  233. ha->mailbox_out[0] = mb0;
  234. mboxes >>= 1;
  235. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  236. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  237. if (IS_QLA2200(ha) && cnt == 8)
  238. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  239. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  240. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  241. else if (mboxes & BIT_0)
  242. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  243. wptr++;
  244. mboxes >>= 1;
  245. }
  246. }
  247. static void
  248. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  249. {
  250. static char *event[] =
  251. { "Complete", "Request Notification", "Time Extension" };
  252. int rval;
  253. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  254. uint16_t __iomem *wptr;
  255. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  256. /* Seed data -- mailbox1 -> mailbox7. */
  257. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  258. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  259. mb[cnt] = RD_REG_WORD(wptr);
  260. ql_dbg(ql_dbg_async, vha, 0x5021,
  261. "Inter-Driver Communication %s -- "
  262. "%04x %04x %04x %04x %04x %04x %04x.\n",
  263. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  264. mb[4], mb[5], mb[6]);
  265. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  266. vha->hw->flags.idc_compl_status = 1;
  267. if (vha->hw->notify_dcbx_comp)
  268. complete(&vha->hw->dcbx_comp);
  269. }
  270. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  271. timeout = (descr >> 8) & 0xf;
  272. if (aen != MBA_IDC_NOTIFY || !timeout)
  273. return;
  274. ql_dbg(ql_dbg_async, vha, 0x5022,
  275. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  276. vha->host_no, event[aen & 0xff], timeout);
  277. rval = qla2x00_post_idc_ack_work(vha, mb);
  278. if (rval != QLA_SUCCESS)
  279. ql_log(ql_log_warn, vha, 0x5023,
  280. "IDC failed to post ACK.\n");
  281. }
  282. #define LS_UNKNOWN 2
  283. char *
  284. qla2x00_get_link_speed_str(struct qla_hw_data *ha)
  285. {
  286. static char *link_speeds[] = {"1", "2", "?", "4", "8", "16", "10"};
  287. char *link_speed;
  288. int fw_speed = ha->link_data_rate;
  289. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  290. link_speed = link_speeds[0];
  291. else if (fw_speed == 0x13)
  292. link_speed = link_speeds[6];
  293. else {
  294. link_speed = link_speeds[LS_UNKNOWN];
  295. if (fw_speed < 6)
  296. link_speed =
  297. link_speeds[fw_speed];
  298. }
  299. return link_speed;
  300. }
  301. void
  302. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  303. {
  304. struct qla_hw_data *ha = vha->hw;
  305. /*
  306. * 8200 AEN Interpretation:
  307. * mb[0] = AEN code
  308. * mb[1] = AEN Reason code
  309. * mb[2] = LSW of Peg-Halt Status-1 Register
  310. * mb[6] = MSW of Peg-Halt Status-1 Register
  311. * mb[3] = LSW of Peg-Halt Status-2 register
  312. * mb[7] = MSW of Peg-Halt Status-2 register
  313. * mb[4] = IDC Device-State Register value
  314. * mb[5] = IDC Driver-Presence Register value
  315. */
  316. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  317. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  318. mb[0], mb[1], mb[2], mb[6]);
  319. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  320. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  321. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  322. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  323. IDC_HEARTBEAT_FAILURE)) {
  324. ha->flags.nic_core_hung = 1;
  325. ql_log(ql_log_warn, vha, 0x5060,
  326. "83XX: F/W Error Reported: Check if reset required.\n");
  327. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  328. uint32_t protocol_engine_id, fw_err_code, err_level;
  329. /*
  330. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  331. * - PEG-Halt Status-1 Register:
  332. * (LSW = mb[2], MSW = mb[6])
  333. * Bits 0-7 = protocol-engine ID
  334. * Bits 8-28 = f/w error code
  335. * Bits 29-31 = Error-level
  336. * Error-level 0x1 = Non-Fatal error
  337. * Error-level 0x2 = Recoverable Fatal error
  338. * Error-level 0x4 = UnRecoverable Fatal error
  339. * - PEG-Halt Status-2 Register:
  340. * (LSW = mb[3], MSW = mb[7])
  341. */
  342. protocol_engine_id = (mb[2] & 0xff);
  343. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  344. ((mb[6] & 0x1fff) << 8));
  345. err_level = ((mb[6] & 0xe000) >> 13);
  346. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  347. "Register: protocol_engine_id=0x%x "
  348. "fw_err_code=0x%x err_level=0x%x.\n",
  349. protocol_engine_id, fw_err_code, err_level);
  350. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  351. "Register: 0x%x%x.\n", mb[7], mb[3]);
  352. if (err_level == ERR_LEVEL_NON_FATAL) {
  353. ql_log(ql_log_warn, vha, 0x5063,
  354. "Not a fatal error, f/w has recovered "
  355. "iteself.\n");
  356. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  357. ql_log(ql_log_fatal, vha, 0x5064,
  358. "Recoverable Fatal error: Chip reset "
  359. "required.\n");
  360. qla83xx_schedule_work(vha,
  361. QLA83XX_NIC_CORE_RESET);
  362. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  363. ql_log(ql_log_fatal, vha, 0x5065,
  364. "Unrecoverable Fatal error: Set FAILED "
  365. "state, reboot required.\n");
  366. qla83xx_schedule_work(vha,
  367. QLA83XX_NIC_CORE_UNRECOVERABLE);
  368. }
  369. }
  370. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  371. uint16_t peg_fw_state, nw_interface_link_up;
  372. uint16_t nw_interface_signal_detect, sfp_status;
  373. uint16_t htbt_counter, htbt_monitor_enable;
  374. uint16_t sfp_additonal_info, sfp_multirate;
  375. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  376. /*
  377. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  378. * - PEG-to-FC Status Register:
  379. * (LSW = mb[2], MSW = mb[6])
  380. * Bits 0-7 = Peg-Firmware state
  381. * Bit 8 = N/W Interface Link-up
  382. * Bit 9 = N/W Interface signal detected
  383. * Bits 10-11 = SFP Status
  384. * SFP Status 0x0 = SFP+ transceiver not expected
  385. * SFP Status 0x1 = SFP+ transceiver not present
  386. * SFP Status 0x2 = SFP+ transceiver invalid
  387. * SFP Status 0x3 = SFP+ transceiver present and
  388. * valid
  389. * Bits 12-14 = Heartbeat Counter
  390. * Bit 15 = Heartbeat Monitor Enable
  391. * Bits 16-17 = SFP Additional Info
  392. * SFP info 0x0 = Unregocnized transceiver for
  393. * Ethernet
  394. * SFP info 0x1 = SFP+ brand validation failed
  395. * SFP info 0x2 = SFP+ speed validation failed
  396. * SFP info 0x3 = SFP+ access error
  397. * Bit 18 = SFP Multirate
  398. * Bit 19 = SFP Tx Fault
  399. * Bits 20-22 = Link Speed
  400. * Bits 23-27 = Reserved
  401. * Bits 28-30 = DCBX Status
  402. * DCBX Status 0x0 = DCBX Disabled
  403. * DCBX Status 0x1 = DCBX Enabled
  404. * DCBX Status 0x2 = DCBX Exchange error
  405. * Bit 31 = Reserved
  406. */
  407. peg_fw_state = (mb[2] & 0x00ff);
  408. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  409. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  410. sfp_status = ((mb[2] & 0x0c00) >> 10);
  411. htbt_counter = ((mb[2] & 0x7000) >> 12);
  412. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  413. sfp_additonal_info = (mb[6] & 0x0003);
  414. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  415. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  416. link_speed = ((mb[6] & 0x0070) >> 4);
  417. dcbx_status = ((mb[6] & 0x7000) >> 12);
  418. ql_log(ql_log_warn, vha, 0x5066,
  419. "Peg-to-Fc Status Register:\n"
  420. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  421. "nw_interface_signal_detect=0x%x"
  422. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  423. nw_interface_link_up, nw_interface_signal_detect,
  424. sfp_status);
  425. ql_log(ql_log_warn, vha, 0x5067,
  426. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  427. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  428. htbt_counter, htbt_monitor_enable,
  429. sfp_additonal_info, sfp_multirate);
  430. ql_log(ql_log_warn, vha, 0x5068,
  431. "sfp_tx_fault=0x%x, link_state=0x%x, "
  432. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  433. dcbx_status);
  434. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  435. }
  436. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  437. ql_log(ql_log_warn, vha, 0x5069,
  438. "Heartbeat Failure encountered, chip reset "
  439. "required.\n");
  440. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  441. }
  442. }
  443. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  444. ql_log(ql_log_info, vha, 0x506a,
  445. "IDC Device-State changed = 0x%x.\n", mb[4]);
  446. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  447. }
  448. }
  449. /**
  450. * qla2x00_async_event() - Process aynchronous events.
  451. * @ha: SCSI driver HA context
  452. * @mb: Mailbox registers (0 - 3)
  453. */
  454. void
  455. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  456. {
  457. uint16_t handle_cnt;
  458. uint16_t cnt, mbx;
  459. uint32_t handles[5];
  460. struct qla_hw_data *ha = vha->hw;
  461. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  462. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  463. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  464. uint32_t rscn_entry, host_pid;
  465. unsigned long flags;
  466. /* Setup to process RIO completion. */
  467. handle_cnt = 0;
  468. if (IS_CNA_CAPABLE(ha))
  469. goto skip_rio;
  470. switch (mb[0]) {
  471. case MBA_SCSI_COMPLETION:
  472. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  473. handle_cnt = 1;
  474. break;
  475. case MBA_CMPLT_1_16BIT:
  476. handles[0] = mb[1];
  477. handle_cnt = 1;
  478. mb[0] = MBA_SCSI_COMPLETION;
  479. break;
  480. case MBA_CMPLT_2_16BIT:
  481. handles[0] = mb[1];
  482. handles[1] = mb[2];
  483. handle_cnt = 2;
  484. mb[0] = MBA_SCSI_COMPLETION;
  485. break;
  486. case MBA_CMPLT_3_16BIT:
  487. handles[0] = mb[1];
  488. handles[1] = mb[2];
  489. handles[2] = mb[3];
  490. handle_cnt = 3;
  491. mb[0] = MBA_SCSI_COMPLETION;
  492. break;
  493. case MBA_CMPLT_4_16BIT:
  494. handles[0] = mb[1];
  495. handles[1] = mb[2];
  496. handles[2] = mb[3];
  497. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  498. handle_cnt = 4;
  499. mb[0] = MBA_SCSI_COMPLETION;
  500. break;
  501. case MBA_CMPLT_5_16BIT:
  502. handles[0] = mb[1];
  503. handles[1] = mb[2];
  504. handles[2] = mb[3];
  505. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  506. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  507. handle_cnt = 5;
  508. mb[0] = MBA_SCSI_COMPLETION;
  509. break;
  510. case MBA_CMPLT_2_32BIT:
  511. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  512. handles[1] = le32_to_cpu(
  513. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  514. RD_MAILBOX_REG(ha, reg, 6));
  515. handle_cnt = 2;
  516. mb[0] = MBA_SCSI_COMPLETION;
  517. break;
  518. default:
  519. break;
  520. }
  521. skip_rio:
  522. switch (mb[0]) {
  523. case MBA_SCSI_COMPLETION: /* Fast Post */
  524. if (!vha->flags.online)
  525. break;
  526. for (cnt = 0; cnt < handle_cnt; cnt++)
  527. qla2x00_process_completed_request(vha, rsp->req,
  528. handles[cnt]);
  529. break;
  530. case MBA_RESET: /* Reset */
  531. ql_dbg(ql_dbg_async, vha, 0x5002,
  532. "Asynchronous RESET.\n");
  533. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  534. break;
  535. case MBA_SYSTEM_ERR: /* System Error */
  536. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  537. RD_REG_WORD(&reg24->mailbox7) : 0;
  538. ql_log(ql_log_warn, vha, 0x5003,
  539. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  540. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  541. ha->isp_ops->fw_dump(vha, 1);
  542. if (IS_FWI2_CAPABLE(ha)) {
  543. if (mb[1] == 0 && mb[2] == 0) {
  544. ql_log(ql_log_fatal, vha, 0x5004,
  545. "Unrecoverable Hardware Error: adapter "
  546. "marked OFFLINE!\n");
  547. vha->flags.online = 0;
  548. vha->device_flags |= DFLG_DEV_FAILED;
  549. } else {
  550. /* Check to see if MPI timeout occurred */
  551. if ((mbx & MBX_3) && (ha->flags.port0))
  552. set_bit(MPI_RESET_NEEDED,
  553. &vha->dpc_flags);
  554. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  555. }
  556. } else if (mb[1] == 0) {
  557. ql_log(ql_log_fatal, vha, 0x5005,
  558. "Unrecoverable Hardware Error: adapter marked "
  559. "OFFLINE!\n");
  560. vha->flags.online = 0;
  561. vha->device_flags |= DFLG_DEV_FAILED;
  562. } else
  563. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  564. break;
  565. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  566. ql_log(ql_log_warn, vha, 0x5006,
  567. "ISP Request Transfer Error (%x).\n", mb[1]);
  568. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  569. break;
  570. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  571. ql_log(ql_log_warn, vha, 0x5007,
  572. "ISP Response Transfer Error.\n");
  573. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  574. break;
  575. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  576. ql_dbg(ql_dbg_async, vha, 0x5008,
  577. "Asynchronous WAKEUP_THRES.\n");
  578. break;
  579. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  580. ql_dbg(ql_dbg_async, vha, 0x5009,
  581. "LIP occurred (%x).\n", mb[1]);
  582. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  583. atomic_set(&vha->loop_state, LOOP_DOWN);
  584. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  585. qla2x00_mark_all_devices_lost(vha, 1);
  586. }
  587. if (vha->vp_idx) {
  588. atomic_set(&vha->vp_state, VP_FAILED);
  589. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  590. }
  591. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  592. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  593. vha->flags.management_server_logged_in = 0;
  594. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  595. break;
  596. case MBA_LOOP_UP: /* Loop Up Event */
  597. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  598. ha->link_data_rate = PORT_SPEED_1GB;
  599. else
  600. ha->link_data_rate = mb[1];
  601. ql_dbg(ql_dbg_async, vha, 0x500a,
  602. "LOOP UP detected (%s Gbps).\n",
  603. qla2x00_get_link_speed_str(ha));
  604. vha->flags.management_server_logged_in = 0;
  605. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  606. break;
  607. case MBA_LOOP_DOWN: /* Loop Down Event */
  608. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  609. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  610. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  611. ql_dbg(ql_dbg_async, vha, 0x500b,
  612. "LOOP DOWN detected (%x %x %x %x).\n",
  613. mb[1], mb[2], mb[3], mbx);
  614. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  615. atomic_set(&vha->loop_state, LOOP_DOWN);
  616. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  617. vha->device_flags |= DFLG_NO_CABLE;
  618. qla2x00_mark_all_devices_lost(vha, 1);
  619. }
  620. if (vha->vp_idx) {
  621. atomic_set(&vha->vp_state, VP_FAILED);
  622. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  623. }
  624. vha->flags.management_server_logged_in = 0;
  625. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  626. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  627. break;
  628. case MBA_LIP_RESET: /* LIP reset occurred */
  629. ql_dbg(ql_dbg_async, vha, 0x500c,
  630. "LIP reset occurred (%x).\n", mb[1]);
  631. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  632. atomic_set(&vha->loop_state, LOOP_DOWN);
  633. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  634. qla2x00_mark_all_devices_lost(vha, 1);
  635. }
  636. if (vha->vp_idx) {
  637. atomic_set(&vha->vp_state, VP_FAILED);
  638. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  639. }
  640. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  641. ha->operating_mode = LOOP;
  642. vha->flags.management_server_logged_in = 0;
  643. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  644. break;
  645. /* case MBA_DCBX_COMPLETE: */
  646. case MBA_POINT_TO_POINT: /* Point-to-Point */
  647. if (IS_QLA2100(ha))
  648. break;
  649. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  650. ql_dbg(ql_dbg_async, vha, 0x500d,
  651. "DCBX Completed -- %04x %04x %04x.\n",
  652. mb[1], mb[2], mb[3]);
  653. if (ha->notify_dcbx_comp)
  654. complete(&ha->dcbx_comp);
  655. } else
  656. ql_dbg(ql_dbg_async, vha, 0x500e,
  657. "Asynchronous P2P MODE received.\n");
  658. /*
  659. * Until there's a transition from loop down to loop up, treat
  660. * this as loop down only.
  661. */
  662. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  663. atomic_set(&vha->loop_state, LOOP_DOWN);
  664. if (!atomic_read(&vha->loop_down_timer))
  665. atomic_set(&vha->loop_down_timer,
  666. LOOP_DOWN_TIME);
  667. qla2x00_mark_all_devices_lost(vha, 1);
  668. }
  669. if (vha->vp_idx) {
  670. atomic_set(&vha->vp_state, VP_FAILED);
  671. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  672. }
  673. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  674. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  675. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  676. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  677. ha->flags.gpsc_supported = 1;
  678. vha->flags.management_server_logged_in = 0;
  679. break;
  680. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  681. if (IS_QLA2100(ha))
  682. break;
  683. ql_dbg(ql_dbg_async, vha, 0x500f,
  684. "Configuration change detected: value=%x.\n", mb[1]);
  685. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  686. atomic_set(&vha->loop_state, LOOP_DOWN);
  687. if (!atomic_read(&vha->loop_down_timer))
  688. atomic_set(&vha->loop_down_timer,
  689. LOOP_DOWN_TIME);
  690. qla2x00_mark_all_devices_lost(vha, 1);
  691. }
  692. if (vha->vp_idx) {
  693. atomic_set(&vha->vp_state, VP_FAILED);
  694. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  695. }
  696. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  697. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  698. break;
  699. case MBA_PORT_UPDATE: /* Port database update */
  700. /*
  701. * Handle only global and vn-port update events
  702. *
  703. * Relevant inputs:
  704. * mb[1] = N_Port handle of changed port
  705. * OR 0xffff for global event
  706. * mb[2] = New login state
  707. * 7 = Port logged out
  708. * mb[3] = LSB is vp_idx, 0xff = all vps
  709. *
  710. * Skip processing if:
  711. * Event is global, vp_idx is NOT all vps,
  712. * vp_idx does not match
  713. * Event is not global, vp_idx does not match
  714. */
  715. if (IS_QLA2XXX_MIDTYPE(ha) &&
  716. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  717. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  718. break;
  719. /* Global event -- port logout or port unavailable. */
  720. if (mb[1] == 0xffff && mb[2] == 0x7) {
  721. ql_dbg(ql_dbg_async, vha, 0x5010,
  722. "Port unavailable %04x %04x %04x.\n",
  723. mb[1], mb[2], mb[3]);
  724. ql_log(ql_log_warn, vha, 0x505e,
  725. "Link is offline.\n");
  726. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  727. atomic_set(&vha->loop_state, LOOP_DOWN);
  728. atomic_set(&vha->loop_down_timer,
  729. LOOP_DOWN_TIME);
  730. vha->device_flags |= DFLG_NO_CABLE;
  731. qla2x00_mark_all_devices_lost(vha, 1);
  732. }
  733. if (vha->vp_idx) {
  734. atomic_set(&vha->vp_state, VP_FAILED);
  735. fc_vport_set_state(vha->fc_vport,
  736. FC_VPORT_FAILED);
  737. qla2x00_mark_all_devices_lost(vha, 1);
  738. }
  739. vha->flags.management_server_logged_in = 0;
  740. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  741. break;
  742. }
  743. /*
  744. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  745. * event etc. earlier indicating loop is down) then process
  746. * it. Otherwise ignore it and Wait for RSCN to come in.
  747. */
  748. atomic_set(&vha->loop_down_timer, 0);
  749. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  750. ql_dbg(ql_dbg_async, vha, 0x5011,
  751. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  752. mb[1], mb[2], mb[3]);
  753. qlt_async_event(mb[0], vha, mb);
  754. break;
  755. }
  756. ql_dbg(ql_dbg_async, vha, 0x5012,
  757. "Port database changed %04x %04x %04x.\n",
  758. mb[1], mb[2], mb[3]);
  759. ql_log(ql_log_warn, vha, 0x505f,
  760. "Link is operational (%s Gbps).\n",
  761. qla2x00_get_link_speed_str(ha));
  762. /*
  763. * Mark all devices as missing so we will login again.
  764. */
  765. atomic_set(&vha->loop_state, LOOP_UP);
  766. qla2x00_mark_all_devices_lost(vha, 1);
  767. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  768. set_bit(SCR_PENDING, &vha->dpc_flags);
  769. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  770. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  771. qlt_async_event(mb[0], vha, mb);
  772. break;
  773. case MBA_RSCN_UPDATE: /* State Change Registration */
  774. /* Check if the Vport has issued a SCR */
  775. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  776. break;
  777. /* Only handle SCNs for our Vport index. */
  778. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  779. break;
  780. ql_dbg(ql_dbg_async, vha, 0x5013,
  781. "RSCN database changed -- %04x %04x %04x.\n",
  782. mb[1], mb[2], mb[3]);
  783. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  784. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  785. | vha->d_id.b.al_pa;
  786. if (rscn_entry == host_pid) {
  787. ql_dbg(ql_dbg_async, vha, 0x5014,
  788. "Ignoring RSCN update to local host "
  789. "port ID (%06x).\n", host_pid);
  790. break;
  791. }
  792. /* Ignore reserved bits from RSCN-payload. */
  793. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  794. atomic_set(&vha->loop_down_timer, 0);
  795. vha->flags.management_server_logged_in = 0;
  796. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  797. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  798. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  799. break;
  800. /* case MBA_RIO_RESPONSE: */
  801. case MBA_ZIO_RESPONSE:
  802. ql_dbg(ql_dbg_async, vha, 0x5015,
  803. "[R|Z]IO update completion.\n");
  804. if (IS_FWI2_CAPABLE(ha))
  805. qla24xx_process_response_queue(vha, rsp);
  806. else
  807. qla2x00_process_response_queue(rsp);
  808. break;
  809. case MBA_DISCARD_RND_FRAME:
  810. ql_dbg(ql_dbg_async, vha, 0x5016,
  811. "Discard RND Frame -- %04x %04x %04x.\n",
  812. mb[1], mb[2], mb[3]);
  813. break;
  814. case MBA_TRACE_NOTIFICATION:
  815. ql_dbg(ql_dbg_async, vha, 0x5017,
  816. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  817. break;
  818. case MBA_ISP84XX_ALERT:
  819. ql_dbg(ql_dbg_async, vha, 0x5018,
  820. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  821. mb[1], mb[2], mb[3]);
  822. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  823. switch (mb[1]) {
  824. case A84_PANIC_RECOVERY:
  825. ql_log(ql_log_info, vha, 0x5019,
  826. "Alert 84XX: panic recovery %04x %04x.\n",
  827. mb[2], mb[3]);
  828. break;
  829. case A84_OP_LOGIN_COMPLETE:
  830. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  831. ql_log(ql_log_info, vha, 0x501a,
  832. "Alert 84XX: firmware version %x.\n",
  833. ha->cs84xx->op_fw_version);
  834. break;
  835. case A84_DIAG_LOGIN_COMPLETE:
  836. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  837. ql_log(ql_log_info, vha, 0x501b,
  838. "Alert 84XX: diagnostic firmware version %x.\n",
  839. ha->cs84xx->diag_fw_version);
  840. break;
  841. case A84_GOLD_LOGIN_COMPLETE:
  842. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  843. ha->cs84xx->fw_update = 1;
  844. ql_log(ql_log_info, vha, 0x501c,
  845. "Alert 84XX: gold firmware version %x.\n",
  846. ha->cs84xx->gold_fw_version);
  847. break;
  848. default:
  849. ql_log(ql_log_warn, vha, 0x501d,
  850. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  851. mb[1], mb[2], mb[3]);
  852. }
  853. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  854. break;
  855. case MBA_DCBX_START:
  856. ql_dbg(ql_dbg_async, vha, 0x501e,
  857. "DCBX Started -- %04x %04x %04x.\n",
  858. mb[1], mb[2], mb[3]);
  859. break;
  860. case MBA_DCBX_PARAM_UPDATE:
  861. ql_dbg(ql_dbg_async, vha, 0x501f,
  862. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  863. mb[1], mb[2], mb[3]);
  864. break;
  865. case MBA_FCF_CONF_ERR:
  866. ql_dbg(ql_dbg_async, vha, 0x5020,
  867. "FCF Configuration Error -- %04x %04x %04x.\n",
  868. mb[1], mb[2], mb[3]);
  869. break;
  870. case MBA_IDC_NOTIFY:
  871. /* See if we need to quiesce any I/O */
  872. if (IS_QLA8031(vha->hw))
  873. if ((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  874. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) {
  875. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  876. qla2xxx_wake_dpc(vha);
  877. }
  878. case MBA_IDC_COMPLETE:
  879. case MBA_IDC_TIME_EXT:
  880. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  881. qla81xx_idc_event(vha, mb[0], mb[1]);
  882. break;
  883. case MBA_IDC_AEN:
  884. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  885. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  886. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  887. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  888. qla83xx_handle_8200_aen(vha, mb);
  889. break;
  890. default:
  891. ql_dbg(ql_dbg_async, vha, 0x5057,
  892. "Unknown AEN:%04x %04x %04x %04x\n",
  893. mb[0], mb[1], mb[2], mb[3]);
  894. }
  895. qlt_async_event(mb[0], vha, mb);
  896. if (!vha->vp_idx && ha->num_vhosts)
  897. qla2x00_alert_all_vps(rsp, mb);
  898. }
  899. /**
  900. * qla2x00_process_completed_request() - Process a Fast Post response.
  901. * @ha: SCSI driver HA context
  902. * @index: SRB index
  903. */
  904. static void
  905. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  906. struct req_que *req, uint32_t index)
  907. {
  908. srb_t *sp;
  909. struct qla_hw_data *ha = vha->hw;
  910. /* Validate handle. */
  911. if (index >= MAX_OUTSTANDING_COMMANDS) {
  912. ql_log(ql_log_warn, vha, 0x3014,
  913. "Invalid SCSI command index (%x).\n", index);
  914. if (IS_QLA82XX(ha))
  915. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  916. else
  917. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  918. return;
  919. }
  920. sp = req->outstanding_cmds[index];
  921. if (sp) {
  922. /* Free outstanding command slot. */
  923. req->outstanding_cmds[index] = NULL;
  924. /* Save ISP completion status */
  925. sp->done(ha, sp, DID_OK << 16);
  926. } else {
  927. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  928. if (IS_QLA82XX(ha))
  929. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  930. else
  931. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  932. }
  933. }
  934. static srb_t *
  935. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  936. struct req_que *req, void *iocb)
  937. {
  938. struct qla_hw_data *ha = vha->hw;
  939. sts_entry_t *pkt = iocb;
  940. srb_t *sp = NULL;
  941. uint16_t index;
  942. index = LSW(pkt->handle);
  943. if (index >= MAX_OUTSTANDING_COMMANDS) {
  944. ql_log(ql_log_warn, vha, 0x5031,
  945. "Invalid command index (%x).\n", index);
  946. if (IS_QLA82XX(ha))
  947. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  948. else
  949. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  950. goto done;
  951. }
  952. sp = req->outstanding_cmds[index];
  953. if (!sp) {
  954. ql_log(ql_log_warn, vha, 0x5032,
  955. "Invalid completion handle (%x) -- timed-out.\n", index);
  956. return sp;
  957. }
  958. if (sp->handle != index) {
  959. ql_log(ql_log_warn, vha, 0x5033,
  960. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  961. return NULL;
  962. }
  963. req->outstanding_cmds[index] = NULL;
  964. done:
  965. return sp;
  966. }
  967. static void
  968. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  969. struct mbx_entry *mbx)
  970. {
  971. const char func[] = "MBX-IOCB";
  972. const char *type;
  973. fc_port_t *fcport;
  974. srb_t *sp;
  975. struct srb_iocb *lio;
  976. uint16_t *data;
  977. uint16_t status;
  978. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  979. if (!sp)
  980. return;
  981. lio = &sp->u.iocb_cmd;
  982. type = sp->name;
  983. fcport = sp->fcport;
  984. data = lio->u.logio.data;
  985. data[0] = MBS_COMMAND_ERROR;
  986. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  987. QLA_LOGIO_LOGIN_RETRIED : 0;
  988. if (mbx->entry_status) {
  989. ql_dbg(ql_dbg_async, vha, 0x5043,
  990. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  991. "entry-status=%x status=%x state-flag=%x "
  992. "status-flags=%x.\n", type, sp->handle,
  993. fcport->d_id.b.domain, fcport->d_id.b.area,
  994. fcport->d_id.b.al_pa, mbx->entry_status,
  995. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  996. le16_to_cpu(mbx->status_flags));
  997. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  998. (uint8_t *)mbx, sizeof(*mbx));
  999. goto logio_done;
  1000. }
  1001. status = le16_to_cpu(mbx->status);
  1002. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1003. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1004. status = 0;
  1005. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1006. ql_dbg(ql_dbg_async, vha, 0x5045,
  1007. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1008. type, sp->handle, fcport->d_id.b.domain,
  1009. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1010. le16_to_cpu(mbx->mb1));
  1011. data[0] = MBS_COMMAND_COMPLETE;
  1012. if (sp->type == SRB_LOGIN_CMD) {
  1013. fcport->port_type = FCT_TARGET;
  1014. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1015. fcport->port_type = FCT_INITIATOR;
  1016. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1017. fcport->flags |= FCF_FCP2_DEVICE;
  1018. }
  1019. goto logio_done;
  1020. }
  1021. data[0] = le16_to_cpu(mbx->mb0);
  1022. switch (data[0]) {
  1023. case MBS_PORT_ID_USED:
  1024. data[1] = le16_to_cpu(mbx->mb1);
  1025. break;
  1026. case MBS_LOOP_ID_USED:
  1027. break;
  1028. default:
  1029. data[0] = MBS_COMMAND_ERROR;
  1030. break;
  1031. }
  1032. ql_log(ql_log_warn, vha, 0x5046,
  1033. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1034. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1035. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1036. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1037. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1038. le16_to_cpu(mbx->mb7));
  1039. logio_done:
  1040. sp->done(vha, sp, 0);
  1041. }
  1042. static void
  1043. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1044. sts_entry_t *pkt, int iocb_type)
  1045. {
  1046. const char func[] = "CT_IOCB";
  1047. const char *type;
  1048. srb_t *sp;
  1049. struct fc_bsg_job *bsg_job;
  1050. uint16_t comp_status;
  1051. int res;
  1052. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1053. if (!sp)
  1054. return;
  1055. bsg_job = sp->u.bsg_job;
  1056. type = "ct pass-through";
  1057. comp_status = le16_to_cpu(pkt->comp_status);
  1058. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1059. * fc payload to the caller
  1060. */
  1061. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1062. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1063. if (comp_status != CS_COMPLETE) {
  1064. if (comp_status == CS_DATA_UNDERRUN) {
  1065. res = DID_OK << 16;
  1066. bsg_job->reply->reply_payload_rcv_len =
  1067. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1068. ql_log(ql_log_warn, vha, 0x5048,
  1069. "CT pass-through-%s error "
  1070. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1071. type, comp_status,
  1072. bsg_job->reply->reply_payload_rcv_len);
  1073. } else {
  1074. ql_log(ql_log_warn, vha, 0x5049,
  1075. "CT pass-through-%s error "
  1076. "comp_status-status=0x%x.\n", type, comp_status);
  1077. res = DID_ERROR << 16;
  1078. bsg_job->reply->reply_payload_rcv_len = 0;
  1079. }
  1080. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1081. (uint8_t *)pkt, sizeof(*pkt));
  1082. } else {
  1083. res = DID_OK << 16;
  1084. bsg_job->reply->reply_payload_rcv_len =
  1085. bsg_job->reply_payload.payload_len;
  1086. bsg_job->reply_len = 0;
  1087. }
  1088. sp->done(vha, sp, res);
  1089. }
  1090. static void
  1091. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1092. struct sts_entry_24xx *pkt, int iocb_type)
  1093. {
  1094. const char func[] = "ELS_CT_IOCB";
  1095. const char *type;
  1096. srb_t *sp;
  1097. struct fc_bsg_job *bsg_job;
  1098. uint16_t comp_status;
  1099. uint32_t fw_status[3];
  1100. uint8_t* fw_sts_ptr;
  1101. int res;
  1102. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1103. if (!sp)
  1104. return;
  1105. bsg_job = sp->u.bsg_job;
  1106. type = NULL;
  1107. switch (sp->type) {
  1108. case SRB_ELS_CMD_RPT:
  1109. case SRB_ELS_CMD_HST:
  1110. type = "els";
  1111. break;
  1112. case SRB_CT_CMD:
  1113. type = "ct pass-through";
  1114. break;
  1115. default:
  1116. ql_dbg(ql_dbg_user, vha, 0x503e,
  1117. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1118. return;
  1119. }
  1120. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1121. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1122. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1123. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1124. * fc payload to the caller
  1125. */
  1126. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1127. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1128. if (comp_status != CS_COMPLETE) {
  1129. if (comp_status == CS_DATA_UNDERRUN) {
  1130. res = DID_OK << 16;
  1131. bsg_job->reply->reply_payload_rcv_len =
  1132. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1133. ql_dbg(ql_dbg_user, vha, 0x503f,
  1134. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1135. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1136. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1137. le16_to_cpu(((struct els_sts_entry_24xx *)
  1138. pkt)->total_byte_count));
  1139. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1140. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1141. }
  1142. else {
  1143. ql_dbg(ql_dbg_user, vha, 0x5040,
  1144. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1145. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1146. type, sp->handle, comp_status,
  1147. le16_to_cpu(((struct els_sts_entry_24xx *)
  1148. pkt)->error_subcode_1),
  1149. le16_to_cpu(((struct els_sts_entry_24xx *)
  1150. pkt)->error_subcode_2));
  1151. res = DID_ERROR << 16;
  1152. bsg_job->reply->reply_payload_rcv_len = 0;
  1153. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1154. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1155. }
  1156. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1157. (uint8_t *)pkt, sizeof(*pkt));
  1158. }
  1159. else {
  1160. res = DID_OK << 16;
  1161. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1162. bsg_job->reply_len = 0;
  1163. }
  1164. sp->done(vha, sp, res);
  1165. }
  1166. static void
  1167. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1168. struct logio_entry_24xx *logio)
  1169. {
  1170. const char func[] = "LOGIO-IOCB";
  1171. const char *type;
  1172. fc_port_t *fcport;
  1173. srb_t *sp;
  1174. struct srb_iocb *lio;
  1175. uint16_t *data;
  1176. uint32_t iop[2];
  1177. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1178. if (!sp)
  1179. return;
  1180. lio = &sp->u.iocb_cmd;
  1181. type = sp->name;
  1182. fcport = sp->fcport;
  1183. data = lio->u.logio.data;
  1184. data[0] = MBS_COMMAND_ERROR;
  1185. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1186. QLA_LOGIO_LOGIN_RETRIED : 0;
  1187. if (logio->entry_status) {
  1188. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1189. "Async-%s error entry - hdl=%x"
  1190. "portid=%02x%02x%02x entry-status=%x.\n",
  1191. type, sp->handle, fcport->d_id.b.domain,
  1192. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1193. logio->entry_status);
  1194. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1195. (uint8_t *)logio, sizeof(*logio));
  1196. goto logio_done;
  1197. }
  1198. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1199. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1200. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1201. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1202. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1203. le32_to_cpu(logio->io_parameter[0]));
  1204. data[0] = MBS_COMMAND_COMPLETE;
  1205. if (sp->type != SRB_LOGIN_CMD)
  1206. goto logio_done;
  1207. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1208. if (iop[0] & BIT_4) {
  1209. fcport->port_type = FCT_TARGET;
  1210. if (iop[0] & BIT_8)
  1211. fcport->flags |= FCF_FCP2_DEVICE;
  1212. } else if (iop[0] & BIT_5)
  1213. fcport->port_type = FCT_INITIATOR;
  1214. if (iop[0] & BIT_7)
  1215. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1216. if (logio->io_parameter[7] || logio->io_parameter[8])
  1217. fcport->supported_classes |= FC_COS_CLASS2;
  1218. if (logio->io_parameter[9] || logio->io_parameter[10])
  1219. fcport->supported_classes |= FC_COS_CLASS3;
  1220. goto logio_done;
  1221. }
  1222. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1223. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1224. switch (iop[0]) {
  1225. case LSC_SCODE_PORTID_USED:
  1226. data[0] = MBS_PORT_ID_USED;
  1227. data[1] = LSW(iop[1]);
  1228. break;
  1229. case LSC_SCODE_NPORT_USED:
  1230. data[0] = MBS_LOOP_ID_USED;
  1231. break;
  1232. default:
  1233. data[0] = MBS_COMMAND_ERROR;
  1234. break;
  1235. }
  1236. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1237. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1238. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1239. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1240. le16_to_cpu(logio->comp_status),
  1241. le32_to_cpu(logio->io_parameter[0]),
  1242. le32_to_cpu(logio->io_parameter[1]));
  1243. logio_done:
  1244. sp->done(vha, sp, 0);
  1245. }
  1246. static void
  1247. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1248. struct tsk_mgmt_entry *tsk)
  1249. {
  1250. const char func[] = "TMF-IOCB";
  1251. const char *type;
  1252. fc_port_t *fcport;
  1253. srb_t *sp;
  1254. struct srb_iocb *iocb;
  1255. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1256. int error = 1;
  1257. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1258. if (!sp)
  1259. return;
  1260. iocb = &sp->u.iocb_cmd;
  1261. type = sp->name;
  1262. fcport = sp->fcport;
  1263. if (sts->entry_status) {
  1264. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1265. "Async-%s error - hdl=%x entry-status(%x).\n",
  1266. type, sp->handle, sts->entry_status);
  1267. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1268. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1269. "Async-%s error - hdl=%x completion status(%x).\n",
  1270. type, sp->handle, sts->comp_status);
  1271. } else if (!(le16_to_cpu(sts->scsi_status) &
  1272. SS_RESPONSE_INFO_LEN_VALID)) {
  1273. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1274. "Async-%s error - hdl=%x no response info(%x).\n",
  1275. type, sp->handle, sts->scsi_status);
  1276. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1277. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1278. "Async-%s error - hdl=%x not enough response(%d).\n",
  1279. type, sp->handle, sts->rsp_data_len);
  1280. } else if (sts->data[3]) {
  1281. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1282. "Async-%s error - hdl=%x response(%x).\n",
  1283. type, sp->handle, sts->data[3]);
  1284. } else {
  1285. error = 0;
  1286. }
  1287. if (error) {
  1288. iocb->u.tmf.data = error;
  1289. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1290. (uint8_t *)sts, sizeof(*sts));
  1291. }
  1292. sp->done(vha, sp, 0);
  1293. }
  1294. /**
  1295. * qla2x00_process_response_queue() - Process response queue entries.
  1296. * @ha: SCSI driver HA context
  1297. */
  1298. void
  1299. qla2x00_process_response_queue(struct rsp_que *rsp)
  1300. {
  1301. struct scsi_qla_host *vha;
  1302. struct qla_hw_data *ha = rsp->hw;
  1303. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1304. sts_entry_t *pkt;
  1305. uint16_t handle_cnt;
  1306. uint16_t cnt;
  1307. vha = pci_get_drvdata(ha->pdev);
  1308. if (!vha->flags.online)
  1309. return;
  1310. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1311. pkt = (sts_entry_t *)rsp->ring_ptr;
  1312. rsp->ring_index++;
  1313. if (rsp->ring_index == rsp->length) {
  1314. rsp->ring_index = 0;
  1315. rsp->ring_ptr = rsp->ring;
  1316. } else {
  1317. rsp->ring_ptr++;
  1318. }
  1319. if (pkt->entry_status != 0) {
  1320. qla2x00_error_entry(vha, rsp, pkt);
  1321. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1322. wmb();
  1323. continue;
  1324. }
  1325. switch (pkt->entry_type) {
  1326. case STATUS_TYPE:
  1327. qla2x00_status_entry(vha, rsp, pkt);
  1328. break;
  1329. case STATUS_TYPE_21:
  1330. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1331. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1332. qla2x00_process_completed_request(vha, rsp->req,
  1333. ((sts21_entry_t *)pkt)->handle[cnt]);
  1334. }
  1335. break;
  1336. case STATUS_TYPE_22:
  1337. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1338. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1339. qla2x00_process_completed_request(vha, rsp->req,
  1340. ((sts22_entry_t *)pkt)->handle[cnt]);
  1341. }
  1342. break;
  1343. case STATUS_CONT_TYPE:
  1344. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1345. break;
  1346. case MBX_IOCB_TYPE:
  1347. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1348. (struct mbx_entry *)pkt);
  1349. break;
  1350. case CT_IOCB_TYPE:
  1351. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1352. break;
  1353. default:
  1354. /* Type Not Supported. */
  1355. ql_log(ql_log_warn, vha, 0x504a,
  1356. "Received unknown response pkt type %x "
  1357. "entry status=%x.\n",
  1358. pkt->entry_type, pkt->entry_status);
  1359. break;
  1360. }
  1361. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1362. wmb();
  1363. }
  1364. /* Adjust ring index */
  1365. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1366. }
  1367. static inline void
  1368. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1369. uint32_t sense_len, struct rsp_que *rsp, int res)
  1370. {
  1371. struct scsi_qla_host *vha = sp->fcport->vha;
  1372. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1373. uint32_t track_sense_len;
  1374. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1375. sense_len = SCSI_SENSE_BUFFERSIZE;
  1376. SET_CMD_SENSE_LEN(sp, sense_len);
  1377. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1378. track_sense_len = sense_len;
  1379. if (sense_len > par_sense_len)
  1380. sense_len = par_sense_len;
  1381. memcpy(cp->sense_buffer, sense_data, sense_len);
  1382. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1383. track_sense_len -= sense_len;
  1384. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1385. if (track_sense_len != 0) {
  1386. rsp->status_srb = sp;
  1387. cp->result = res;
  1388. }
  1389. if (sense_len) {
  1390. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1391. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1392. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1393. cp);
  1394. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1395. cp->sense_buffer, sense_len);
  1396. }
  1397. }
  1398. struct scsi_dif_tuple {
  1399. __be16 guard; /* Checksum */
  1400. __be16 app_tag; /* APPL identifier */
  1401. __be32 ref_tag; /* Target LBA or indirect LBA */
  1402. };
  1403. /*
  1404. * Checks the guard or meta-data for the type of error
  1405. * detected by the HBA. In case of errors, we set the
  1406. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1407. * to indicate to the kernel that the HBA detected error.
  1408. */
  1409. static inline int
  1410. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1411. {
  1412. struct scsi_qla_host *vha = sp->fcport->vha;
  1413. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1414. uint8_t *ap = &sts24->data[12];
  1415. uint8_t *ep = &sts24->data[20];
  1416. uint32_t e_ref_tag, a_ref_tag;
  1417. uint16_t e_app_tag, a_app_tag;
  1418. uint16_t e_guard, a_guard;
  1419. /*
  1420. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1421. * would make guard field appear at offset 2
  1422. */
  1423. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1424. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1425. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1426. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1427. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1428. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1429. ql_dbg(ql_dbg_io, vha, 0x3023,
  1430. "iocb(s) %p Returned STATUS.\n", sts24);
  1431. ql_dbg(ql_dbg_io, vha, 0x3024,
  1432. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1433. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1434. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1435. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1436. a_app_tag, e_app_tag, a_guard, e_guard);
  1437. /*
  1438. * Ignore sector if:
  1439. * For type 3: ref & app tag is all 'f's
  1440. * For type 0,1,2: app tag is all 'f's
  1441. */
  1442. if ((a_app_tag == 0xffff) &&
  1443. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1444. (a_ref_tag == 0xffffffff))) {
  1445. uint32_t blocks_done, resid;
  1446. sector_t lba_s = scsi_get_lba(cmd);
  1447. /* 2TB boundary case covered automatically with this */
  1448. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1449. resid = scsi_bufflen(cmd) - (blocks_done *
  1450. cmd->device->sector_size);
  1451. scsi_set_resid(cmd, resid);
  1452. cmd->result = DID_OK << 16;
  1453. /* Update protection tag */
  1454. if (scsi_prot_sg_count(cmd)) {
  1455. uint32_t i, j = 0, k = 0, num_ent;
  1456. struct scatterlist *sg;
  1457. struct sd_dif_tuple *spt;
  1458. /* Patch the corresponding protection tags */
  1459. scsi_for_each_prot_sg(cmd, sg,
  1460. scsi_prot_sg_count(cmd), i) {
  1461. num_ent = sg_dma_len(sg) / 8;
  1462. if (k + num_ent < blocks_done) {
  1463. k += num_ent;
  1464. continue;
  1465. }
  1466. j = blocks_done - k - 1;
  1467. k = blocks_done;
  1468. break;
  1469. }
  1470. if (k != blocks_done) {
  1471. ql_log(ql_log_warn, vha, 0x302f,
  1472. "unexpected tag values tag:lba=%x:%llx)\n",
  1473. e_ref_tag, (unsigned long long)lba_s);
  1474. return 1;
  1475. }
  1476. spt = page_address(sg_page(sg)) + sg->offset;
  1477. spt += j;
  1478. spt->app_tag = 0xffff;
  1479. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1480. spt->ref_tag = 0xffffffff;
  1481. }
  1482. return 0;
  1483. }
  1484. /* check guard */
  1485. if (e_guard != a_guard) {
  1486. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1487. 0x10, 0x1);
  1488. set_driver_byte(cmd, DRIVER_SENSE);
  1489. set_host_byte(cmd, DID_ABORT);
  1490. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1491. return 1;
  1492. }
  1493. /* check ref tag */
  1494. if (e_ref_tag != a_ref_tag) {
  1495. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1496. 0x10, 0x3);
  1497. set_driver_byte(cmd, DRIVER_SENSE);
  1498. set_host_byte(cmd, DID_ABORT);
  1499. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1500. return 1;
  1501. }
  1502. /* check appl tag */
  1503. if (e_app_tag != a_app_tag) {
  1504. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1505. 0x10, 0x2);
  1506. set_driver_byte(cmd, DRIVER_SENSE);
  1507. set_host_byte(cmd, DID_ABORT);
  1508. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1509. return 1;
  1510. }
  1511. return 1;
  1512. }
  1513. static void
  1514. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1515. struct req_que *req, uint32_t index)
  1516. {
  1517. struct qla_hw_data *ha = vha->hw;
  1518. srb_t *sp;
  1519. uint16_t comp_status;
  1520. uint16_t scsi_status;
  1521. uint16_t thread_id;
  1522. uint32_t rval = EXT_STATUS_OK;
  1523. struct fc_bsg_job *bsg_job = NULL;
  1524. sts_entry_t *sts;
  1525. struct sts_entry_24xx *sts24;
  1526. sts = (sts_entry_t *) pkt;
  1527. sts24 = (struct sts_entry_24xx *) pkt;
  1528. /* Validate handle. */
  1529. if (index >= MAX_OUTSTANDING_COMMANDS) {
  1530. ql_log(ql_log_warn, vha, 0x70af,
  1531. "Invalid SCSI completion handle 0x%x.\n", index);
  1532. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1533. return;
  1534. }
  1535. sp = req->outstanding_cmds[index];
  1536. if (sp) {
  1537. /* Free outstanding command slot. */
  1538. req->outstanding_cmds[index] = NULL;
  1539. bsg_job = sp->u.bsg_job;
  1540. } else {
  1541. ql_log(ql_log_warn, vha, 0x70b0,
  1542. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1543. req->id, index);
  1544. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1545. return;
  1546. }
  1547. if (IS_FWI2_CAPABLE(ha)) {
  1548. comp_status = le16_to_cpu(sts24->comp_status);
  1549. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1550. } else {
  1551. comp_status = le16_to_cpu(sts->comp_status);
  1552. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1553. }
  1554. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1555. switch (comp_status) {
  1556. case CS_COMPLETE:
  1557. if (scsi_status == 0) {
  1558. bsg_job->reply->reply_payload_rcv_len =
  1559. bsg_job->reply_payload.payload_len;
  1560. rval = EXT_STATUS_OK;
  1561. }
  1562. goto done;
  1563. case CS_DATA_OVERRUN:
  1564. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1565. "Command completed with date overrun thread_id=%d\n",
  1566. thread_id);
  1567. rval = EXT_STATUS_DATA_OVERRUN;
  1568. break;
  1569. case CS_DATA_UNDERRUN:
  1570. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1571. "Command completed with date underrun thread_id=%d\n",
  1572. thread_id);
  1573. rval = EXT_STATUS_DATA_UNDERRUN;
  1574. break;
  1575. case CS_BIDIR_RD_OVERRUN:
  1576. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1577. "Command completed with read data overrun thread_id=%d\n",
  1578. thread_id);
  1579. rval = EXT_STATUS_DATA_OVERRUN;
  1580. break;
  1581. case CS_BIDIR_RD_WR_OVERRUN:
  1582. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1583. "Command completed with read and write data overrun "
  1584. "thread_id=%d\n", thread_id);
  1585. rval = EXT_STATUS_DATA_OVERRUN;
  1586. break;
  1587. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1588. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1589. "Command completed with read data over and write data "
  1590. "underrun thread_id=%d\n", thread_id);
  1591. rval = EXT_STATUS_DATA_OVERRUN;
  1592. break;
  1593. case CS_BIDIR_RD_UNDERRUN:
  1594. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1595. "Command completed with read data data underrun "
  1596. "thread_id=%d\n", thread_id);
  1597. rval = EXT_STATUS_DATA_UNDERRUN;
  1598. break;
  1599. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1600. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1601. "Command completed with read data under and write data "
  1602. "overrun thread_id=%d\n", thread_id);
  1603. rval = EXT_STATUS_DATA_UNDERRUN;
  1604. break;
  1605. case CS_BIDIR_RD_WR_UNDERRUN:
  1606. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1607. "Command completed with read and write data underrun "
  1608. "thread_id=%d\n", thread_id);
  1609. rval = EXT_STATUS_DATA_UNDERRUN;
  1610. break;
  1611. case CS_BIDIR_DMA:
  1612. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1613. "Command completed with data DMA error thread_id=%d\n",
  1614. thread_id);
  1615. rval = EXT_STATUS_DMA_ERR;
  1616. break;
  1617. case CS_TIMEOUT:
  1618. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1619. "Command completed with timeout thread_id=%d\n",
  1620. thread_id);
  1621. rval = EXT_STATUS_TIMEOUT;
  1622. break;
  1623. default:
  1624. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1625. "Command completed with completion status=0x%x "
  1626. "thread_id=%d\n", comp_status, thread_id);
  1627. rval = EXT_STATUS_ERR;
  1628. break;
  1629. }
  1630. bsg_job->reply->reply_payload_rcv_len = 0;
  1631. done:
  1632. /* Return the vendor specific reply to API */
  1633. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1634. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1635. /* Always return DID_OK, bsg will send the vendor specific response
  1636. * in this case only */
  1637. sp->done(vha, sp, (DID_OK << 6));
  1638. }
  1639. /**
  1640. * qla2x00_status_entry() - Process a Status IOCB entry.
  1641. * @ha: SCSI driver HA context
  1642. * @pkt: Entry pointer
  1643. */
  1644. static void
  1645. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1646. {
  1647. srb_t *sp;
  1648. fc_port_t *fcport;
  1649. struct scsi_cmnd *cp;
  1650. sts_entry_t *sts;
  1651. struct sts_entry_24xx *sts24;
  1652. uint16_t comp_status;
  1653. uint16_t scsi_status;
  1654. uint16_t ox_id;
  1655. uint8_t lscsi_status;
  1656. int32_t resid;
  1657. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1658. fw_resid_len;
  1659. uint8_t *rsp_info, *sense_data;
  1660. struct qla_hw_data *ha = vha->hw;
  1661. uint32_t handle;
  1662. uint16_t que;
  1663. struct req_que *req;
  1664. int logit = 1;
  1665. int res = 0;
  1666. uint16_t state_flags = 0;
  1667. sts = (sts_entry_t *) pkt;
  1668. sts24 = (struct sts_entry_24xx *) pkt;
  1669. if (IS_FWI2_CAPABLE(ha)) {
  1670. comp_status = le16_to_cpu(sts24->comp_status);
  1671. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1672. state_flags = le16_to_cpu(sts24->state_flags);
  1673. } else {
  1674. comp_status = le16_to_cpu(sts->comp_status);
  1675. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1676. }
  1677. handle = (uint32_t) LSW(sts->handle);
  1678. que = MSW(sts->handle);
  1679. req = ha->req_q_map[que];
  1680. /* Validate handle. */
  1681. if (handle < MAX_OUTSTANDING_COMMANDS) {
  1682. sp = req->outstanding_cmds[handle];
  1683. } else
  1684. sp = NULL;
  1685. if (sp == NULL) {
  1686. ql_dbg(ql_dbg_io, vha, 0x3017,
  1687. "Invalid status handle (0x%x).\n", sts->handle);
  1688. if (IS_QLA82XX(ha))
  1689. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1690. else
  1691. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1692. qla2xxx_wake_dpc(vha);
  1693. return;
  1694. }
  1695. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1696. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1697. return;
  1698. }
  1699. /* Fast path completion. */
  1700. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1701. qla2x00_process_completed_request(vha, req, handle);
  1702. return;
  1703. }
  1704. req->outstanding_cmds[handle] = NULL;
  1705. cp = GET_CMD_SP(sp);
  1706. if (cp == NULL) {
  1707. ql_dbg(ql_dbg_io, vha, 0x3018,
  1708. "Command already returned (0x%x/%p).\n",
  1709. sts->handle, sp);
  1710. return;
  1711. }
  1712. lscsi_status = scsi_status & STATUS_MASK;
  1713. fcport = sp->fcport;
  1714. ox_id = 0;
  1715. sense_len = par_sense_len = rsp_info_len = resid_len =
  1716. fw_resid_len = 0;
  1717. if (IS_FWI2_CAPABLE(ha)) {
  1718. if (scsi_status & SS_SENSE_LEN_VALID)
  1719. sense_len = le32_to_cpu(sts24->sense_len);
  1720. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1721. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1722. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1723. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1724. if (comp_status == CS_DATA_UNDERRUN)
  1725. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1726. rsp_info = sts24->data;
  1727. sense_data = sts24->data;
  1728. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1729. ox_id = le16_to_cpu(sts24->ox_id);
  1730. par_sense_len = sizeof(sts24->data);
  1731. } else {
  1732. if (scsi_status & SS_SENSE_LEN_VALID)
  1733. sense_len = le16_to_cpu(sts->req_sense_length);
  1734. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1735. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1736. resid_len = le32_to_cpu(sts->residual_length);
  1737. rsp_info = sts->rsp_info;
  1738. sense_data = sts->req_sense_data;
  1739. par_sense_len = sizeof(sts->req_sense_data);
  1740. }
  1741. /* Check for any FCP transport errors. */
  1742. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1743. /* Sense data lies beyond any FCP RESPONSE data. */
  1744. if (IS_FWI2_CAPABLE(ha)) {
  1745. sense_data += rsp_info_len;
  1746. par_sense_len -= rsp_info_len;
  1747. }
  1748. if (rsp_info_len > 3 && rsp_info[3]) {
  1749. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1750. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1751. rsp_info_len, rsp_info[3]);
  1752. res = DID_BUS_BUSY << 16;
  1753. goto out;
  1754. }
  1755. }
  1756. /* Check for overrun. */
  1757. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1758. scsi_status & SS_RESIDUAL_OVER)
  1759. comp_status = CS_DATA_OVERRUN;
  1760. /*
  1761. * Based on Host and scsi status generate status code for Linux
  1762. */
  1763. switch (comp_status) {
  1764. case CS_COMPLETE:
  1765. case CS_QUEUE_FULL:
  1766. if (scsi_status == 0) {
  1767. res = DID_OK << 16;
  1768. break;
  1769. }
  1770. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1771. resid = resid_len;
  1772. scsi_set_resid(cp, resid);
  1773. if (!lscsi_status &&
  1774. ((unsigned)(scsi_bufflen(cp) - resid) <
  1775. cp->underflow)) {
  1776. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1777. "Mid-layer underflow "
  1778. "detected (0x%x of 0x%x bytes).\n",
  1779. resid, scsi_bufflen(cp));
  1780. res = DID_ERROR << 16;
  1781. break;
  1782. }
  1783. }
  1784. res = DID_OK << 16 | lscsi_status;
  1785. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1786. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1787. "QUEUE FULL detected.\n");
  1788. break;
  1789. }
  1790. logit = 0;
  1791. if (lscsi_status != SS_CHECK_CONDITION)
  1792. break;
  1793. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1794. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1795. break;
  1796. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1797. rsp, res);
  1798. break;
  1799. case CS_DATA_UNDERRUN:
  1800. /* Use F/W calculated residual length. */
  1801. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1802. scsi_set_resid(cp, resid);
  1803. if (scsi_status & SS_RESIDUAL_UNDER) {
  1804. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1805. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1806. "Dropped frame(s) detected "
  1807. "(0x%x of 0x%x bytes).\n",
  1808. resid, scsi_bufflen(cp));
  1809. res = DID_ERROR << 16 | lscsi_status;
  1810. goto check_scsi_status;
  1811. }
  1812. if (!lscsi_status &&
  1813. ((unsigned)(scsi_bufflen(cp) - resid) <
  1814. cp->underflow)) {
  1815. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1816. "Mid-layer underflow "
  1817. "detected (0x%x of 0x%x bytes).\n",
  1818. resid, scsi_bufflen(cp));
  1819. res = DID_ERROR << 16;
  1820. break;
  1821. }
  1822. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1823. lscsi_status != SAM_STAT_BUSY) {
  1824. /*
  1825. * scsi status of task set and busy are considered to be
  1826. * task not completed.
  1827. */
  1828. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1829. "Dropped frame(s) detected (0x%x "
  1830. "of 0x%x bytes).\n", resid,
  1831. scsi_bufflen(cp));
  1832. res = DID_ERROR << 16 | lscsi_status;
  1833. goto check_scsi_status;
  1834. } else {
  1835. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1836. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1837. scsi_status, lscsi_status);
  1838. }
  1839. res = DID_OK << 16 | lscsi_status;
  1840. logit = 0;
  1841. check_scsi_status:
  1842. /*
  1843. * Check to see if SCSI Status is non zero. If so report SCSI
  1844. * Status.
  1845. */
  1846. if (lscsi_status != 0) {
  1847. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1848. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1849. "QUEUE FULL detected.\n");
  1850. logit = 1;
  1851. break;
  1852. }
  1853. if (lscsi_status != SS_CHECK_CONDITION)
  1854. break;
  1855. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1856. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1857. break;
  1858. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1859. sense_len, rsp, res);
  1860. }
  1861. break;
  1862. case CS_PORT_LOGGED_OUT:
  1863. case CS_PORT_CONFIG_CHG:
  1864. case CS_PORT_BUSY:
  1865. case CS_INCOMPLETE:
  1866. case CS_PORT_UNAVAILABLE:
  1867. case CS_TIMEOUT:
  1868. case CS_RESET:
  1869. /*
  1870. * We are going to have the fc class block the rport
  1871. * while we try to recover so instruct the mid layer
  1872. * to requeue until the class decides how to handle this.
  1873. */
  1874. res = DID_TRANSPORT_DISRUPTED << 16;
  1875. if (comp_status == CS_TIMEOUT) {
  1876. if (IS_FWI2_CAPABLE(ha))
  1877. break;
  1878. else if ((le16_to_cpu(sts->status_flags) &
  1879. SF_LOGOUT_SENT) == 0)
  1880. break;
  1881. }
  1882. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1883. "Port down status: port-state=0x%x.\n",
  1884. atomic_read(&fcport->state));
  1885. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1886. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1887. break;
  1888. case CS_ABORTED:
  1889. res = DID_RESET << 16;
  1890. break;
  1891. case CS_DIF_ERROR:
  1892. logit = qla2x00_handle_dif_error(sp, sts24);
  1893. break;
  1894. default:
  1895. res = DID_ERROR << 16;
  1896. break;
  1897. }
  1898. out:
  1899. if (logit)
  1900. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1901. "FCP command status: 0x%x-0x%x (0x%x) "
  1902. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1903. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1904. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1905. comp_status, scsi_status, res, vha->host_no,
  1906. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1907. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1908. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1909. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1910. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1911. resid_len, fw_resid_len);
  1912. if (rsp->status_srb == NULL)
  1913. sp->done(ha, sp, res);
  1914. }
  1915. /**
  1916. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1917. * @ha: SCSI driver HA context
  1918. * @pkt: Entry pointer
  1919. *
  1920. * Extended sense data.
  1921. */
  1922. static void
  1923. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1924. {
  1925. uint8_t sense_sz = 0;
  1926. struct qla_hw_data *ha = rsp->hw;
  1927. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1928. srb_t *sp = rsp->status_srb;
  1929. struct scsi_cmnd *cp;
  1930. uint32_t sense_len;
  1931. uint8_t *sense_ptr;
  1932. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1933. return;
  1934. sense_len = GET_CMD_SENSE_LEN(sp);
  1935. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1936. cp = GET_CMD_SP(sp);
  1937. if (cp == NULL) {
  1938. ql_log(ql_log_warn, vha, 0x3025,
  1939. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1940. rsp->status_srb = NULL;
  1941. return;
  1942. }
  1943. if (sense_len > sizeof(pkt->data))
  1944. sense_sz = sizeof(pkt->data);
  1945. else
  1946. sense_sz = sense_len;
  1947. /* Move sense data. */
  1948. if (IS_FWI2_CAPABLE(ha))
  1949. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1950. memcpy(sense_ptr, pkt->data, sense_sz);
  1951. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1952. sense_ptr, sense_sz);
  1953. sense_len -= sense_sz;
  1954. sense_ptr += sense_sz;
  1955. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1956. SET_CMD_SENSE_LEN(sp, sense_len);
  1957. /* Place command on done queue. */
  1958. if (sense_len == 0) {
  1959. rsp->status_srb = NULL;
  1960. sp->done(ha, sp, cp->result);
  1961. }
  1962. }
  1963. /**
  1964. * qla2x00_error_entry() - Process an error entry.
  1965. * @ha: SCSI driver HA context
  1966. * @pkt: Entry pointer
  1967. */
  1968. static void
  1969. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  1970. {
  1971. srb_t *sp;
  1972. struct qla_hw_data *ha = vha->hw;
  1973. const char func[] = "ERROR-IOCB";
  1974. uint16_t que = MSW(pkt->handle);
  1975. struct req_que *req = NULL;
  1976. int res = DID_ERROR << 16;
  1977. ql_dbg(ql_dbg_async, vha, 0x502a,
  1978. "type of error status in response: 0x%x\n", pkt->entry_status);
  1979. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  1980. goto fatal;
  1981. req = ha->req_q_map[que];
  1982. if (pkt->entry_status & RF_BUSY)
  1983. res = DID_BUS_BUSY << 16;
  1984. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1985. if (sp) {
  1986. sp->done(ha, sp, res);
  1987. return;
  1988. }
  1989. fatal:
  1990. ql_log(ql_log_warn, vha, 0x5030,
  1991. "Error entry - invalid handle/queue.\n");
  1992. if (IS_QLA82XX(ha))
  1993. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1994. else
  1995. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1996. qla2xxx_wake_dpc(vha);
  1997. }
  1998. /**
  1999. * qla24xx_mbx_completion() - Process mailbox command completions.
  2000. * @ha: SCSI driver HA context
  2001. * @mb0: Mailbox0 register
  2002. */
  2003. static void
  2004. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2005. {
  2006. uint16_t cnt;
  2007. uint32_t mboxes;
  2008. uint16_t __iomem *wptr;
  2009. struct qla_hw_data *ha = vha->hw;
  2010. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2011. /* Read all mbox registers? */
  2012. mboxes = (1 << ha->mbx_count) - 1;
  2013. if (!ha->mcp)
  2014. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERRROR.\n");
  2015. else
  2016. mboxes = ha->mcp->in_mb;
  2017. /* Load return mailbox registers. */
  2018. ha->flags.mbox_int = 1;
  2019. ha->mailbox_out[0] = mb0;
  2020. mboxes >>= 1;
  2021. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2022. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2023. if (mboxes & BIT_0)
  2024. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2025. mboxes >>= 1;
  2026. wptr++;
  2027. }
  2028. }
  2029. /**
  2030. * qla24xx_process_response_queue() - Process response queue entries.
  2031. * @ha: SCSI driver HA context
  2032. */
  2033. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2034. struct rsp_que *rsp)
  2035. {
  2036. struct sts_entry_24xx *pkt;
  2037. struct qla_hw_data *ha = vha->hw;
  2038. if (!vha->flags.online)
  2039. return;
  2040. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2041. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2042. rsp->ring_index++;
  2043. if (rsp->ring_index == rsp->length) {
  2044. rsp->ring_index = 0;
  2045. rsp->ring_ptr = rsp->ring;
  2046. } else {
  2047. rsp->ring_ptr++;
  2048. }
  2049. if (pkt->entry_status != 0) {
  2050. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2051. (void)qlt_24xx_process_response_error(vha, pkt);
  2052. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2053. wmb();
  2054. continue;
  2055. }
  2056. switch (pkt->entry_type) {
  2057. case STATUS_TYPE:
  2058. qla2x00_status_entry(vha, rsp, pkt);
  2059. break;
  2060. case STATUS_CONT_TYPE:
  2061. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2062. break;
  2063. case VP_RPT_ID_IOCB_TYPE:
  2064. qla24xx_report_id_acquisition(vha,
  2065. (struct vp_rpt_id_entry_24xx *)pkt);
  2066. break;
  2067. case LOGINOUT_PORT_IOCB_TYPE:
  2068. qla24xx_logio_entry(vha, rsp->req,
  2069. (struct logio_entry_24xx *)pkt);
  2070. break;
  2071. case TSK_MGMT_IOCB_TYPE:
  2072. qla24xx_tm_iocb_entry(vha, rsp->req,
  2073. (struct tsk_mgmt_entry *)pkt);
  2074. break;
  2075. case CT_IOCB_TYPE:
  2076. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2077. break;
  2078. case ELS_IOCB_TYPE:
  2079. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2080. break;
  2081. case ABTS_RECV_24XX:
  2082. /* ensure that the ATIO queue is empty */
  2083. qlt_24xx_process_atio_queue(vha);
  2084. case ABTS_RESP_24XX:
  2085. case CTIO_TYPE7:
  2086. case NOTIFY_ACK_TYPE:
  2087. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2088. break;
  2089. case MARKER_TYPE:
  2090. /* Do nothing in this case, this check is to prevent it
  2091. * from falling into default case
  2092. */
  2093. break;
  2094. default:
  2095. /* Type Not Supported. */
  2096. ql_dbg(ql_dbg_async, vha, 0x5042,
  2097. "Received unknown response pkt type %x "
  2098. "entry status=%x.\n",
  2099. pkt->entry_type, pkt->entry_status);
  2100. break;
  2101. }
  2102. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2103. wmb();
  2104. }
  2105. /* Adjust ring index */
  2106. if (IS_QLA82XX(ha)) {
  2107. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2108. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2109. } else
  2110. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2111. }
  2112. static void
  2113. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2114. {
  2115. int rval;
  2116. uint32_t cnt;
  2117. struct qla_hw_data *ha = vha->hw;
  2118. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2119. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2120. return;
  2121. rval = QLA_SUCCESS;
  2122. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2123. RD_REG_DWORD(&reg->iobase_addr);
  2124. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2125. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2126. rval == QLA_SUCCESS; cnt--) {
  2127. if (cnt) {
  2128. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2129. udelay(10);
  2130. } else
  2131. rval = QLA_FUNCTION_TIMEOUT;
  2132. }
  2133. if (rval == QLA_SUCCESS)
  2134. goto next_test;
  2135. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2136. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2137. rval == QLA_SUCCESS; cnt--) {
  2138. if (cnt) {
  2139. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2140. udelay(10);
  2141. } else
  2142. rval = QLA_FUNCTION_TIMEOUT;
  2143. }
  2144. if (rval != QLA_SUCCESS)
  2145. goto done;
  2146. next_test:
  2147. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2148. ql_log(ql_log_info, vha, 0x504c,
  2149. "Additional code -- 0x55AA.\n");
  2150. done:
  2151. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2152. RD_REG_DWORD(&reg->iobase_window);
  2153. }
  2154. /**
  2155. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2156. * @irq:
  2157. * @dev_id: SCSI driver HA context
  2158. *
  2159. * Called by system whenever the host adapter generates an interrupt.
  2160. *
  2161. * Returns handled flag.
  2162. */
  2163. irqreturn_t
  2164. qla24xx_intr_handler(int irq, void *dev_id)
  2165. {
  2166. scsi_qla_host_t *vha;
  2167. struct qla_hw_data *ha;
  2168. struct device_reg_24xx __iomem *reg;
  2169. int status;
  2170. unsigned long iter;
  2171. uint32_t stat;
  2172. uint32_t hccr;
  2173. uint16_t mb[8];
  2174. struct rsp_que *rsp;
  2175. unsigned long flags;
  2176. rsp = (struct rsp_que *) dev_id;
  2177. if (!rsp) {
  2178. ql_log(ql_log_info, NULL, 0x5059,
  2179. "%s: NULL response queue pointer.\n", __func__);
  2180. return IRQ_NONE;
  2181. }
  2182. ha = rsp->hw;
  2183. reg = &ha->iobase->isp24;
  2184. status = 0;
  2185. if (unlikely(pci_channel_offline(ha->pdev)))
  2186. return IRQ_HANDLED;
  2187. spin_lock_irqsave(&ha->hardware_lock, flags);
  2188. vha = pci_get_drvdata(ha->pdev);
  2189. for (iter = 50; iter--; ) {
  2190. stat = RD_REG_DWORD(&reg->host_status);
  2191. if (stat & HSRX_RISC_PAUSED) {
  2192. if (unlikely(pci_channel_offline(ha->pdev)))
  2193. break;
  2194. hccr = RD_REG_DWORD(&reg->hccr);
  2195. ql_log(ql_log_warn, vha, 0x504b,
  2196. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2197. hccr);
  2198. qla2xxx_check_risc_status(vha);
  2199. ha->isp_ops->fw_dump(vha, 1);
  2200. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2201. break;
  2202. } else if ((stat & HSRX_RISC_INT) == 0)
  2203. break;
  2204. switch (stat & 0xff) {
  2205. case INTR_ROM_MB_SUCCESS:
  2206. case INTR_ROM_MB_FAILED:
  2207. case INTR_MB_SUCCESS:
  2208. case INTR_MB_FAILED:
  2209. qla24xx_mbx_completion(vha, MSW(stat));
  2210. status |= MBX_INTERRUPT;
  2211. break;
  2212. case INTR_ASYNC_EVENT:
  2213. mb[0] = MSW(stat);
  2214. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2215. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2216. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2217. qla2x00_async_event(vha, rsp, mb);
  2218. break;
  2219. case INTR_RSP_QUE_UPDATE:
  2220. case INTR_RSP_QUE_UPDATE_83XX:
  2221. qla24xx_process_response_queue(vha, rsp);
  2222. break;
  2223. case INTR_ATIO_QUE_UPDATE:
  2224. qlt_24xx_process_atio_queue(vha);
  2225. break;
  2226. case INTR_ATIO_RSP_QUE_UPDATE:
  2227. qlt_24xx_process_atio_queue(vha);
  2228. qla24xx_process_response_queue(vha, rsp);
  2229. break;
  2230. default:
  2231. ql_dbg(ql_dbg_async, vha, 0x504f,
  2232. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2233. break;
  2234. }
  2235. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2236. RD_REG_DWORD_RELAXED(&reg->hccr);
  2237. }
  2238. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2239. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2240. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2241. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2242. complete(&ha->mbx_intr_comp);
  2243. }
  2244. return IRQ_HANDLED;
  2245. }
  2246. static irqreturn_t
  2247. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2248. {
  2249. struct qla_hw_data *ha;
  2250. struct rsp_que *rsp;
  2251. struct device_reg_24xx __iomem *reg;
  2252. struct scsi_qla_host *vha;
  2253. unsigned long flags;
  2254. rsp = (struct rsp_que *) dev_id;
  2255. if (!rsp) {
  2256. ql_log(ql_log_info, NULL, 0x505a,
  2257. "%s: NULL response queue pointer.\n", __func__);
  2258. return IRQ_NONE;
  2259. }
  2260. ha = rsp->hw;
  2261. reg = &ha->iobase->isp24;
  2262. spin_lock_irqsave(&ha->hardware_lock, flags);
  2263. vha = pci_get_drvdata(ha->pdev);
  2264. qla24xx_process_response_queue(vha, rsp);
  2265. if (!ha->flags.disable_msix_handshake) {
  2266. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2267. RD_REG_DWORD_RELAXED(&reg->hccr);
  2268. }
  2269. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2270. return IRQ_HANDLED;
  2271. }
  2272. static irqreturn_t
  2273. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2274. {
  2275. struct qla_hw_data *ha;
  2276. struct rsp_que *rsp;
  2277. struct device_reg_24xx __iomem *reg;
  2278. unsigned long flags;
  2279. rsp = (struct rsp_que *) dev_id;
  2280. if (!rsp) {
  2281. ql_log(ql_log_info, NULL, 0x505b,
  2282. "%s: NULL response queue pointer.\n", __func__);
  2283. return IRQ_NONE;
  2284. }
  2285. ha = rsp->hw;
  2286. /* Clear the interrupt, if enabled, for this response queue */
  2287. if (!ha->flags.disable_msix_handshake) {
  2288. reg = &ha->iobase->isp24;
  2289. spin_lock_irqsave(&ha->hardware_lock, flags);
  2290. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2291. RD_REG_DWORD_RELAXED(&reg->hccr);
  2292. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2293. }
  2294. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2295. return IRQ_HANDLED;
  2296. }
  2297. static irqreturn_t
  2298. qla24xx_msix_default(int irq, void *dev_id)
  2299. {
  2300. scsi_qla_host_t *vha;
  2301. struct qla_hw_data *ha;
  2302. struct rsp_que *rsp;
  2303. struct device_reg_24xx __iomem *reg;
  2304. int status;
  2305. uint32_t stat;
  2306. uint32_t hccr;
  2307. uint16_t mb[8];
  2308. unsigned long flags;
  2309. rsp = (struct rsp_que *) dev_id;
  2310. if (!rsp) {
  2311. ql_log(ql_log_info, NULL, 0x505c,
  2312. "%s: NULL response queue pointer.\n", __func__);
  2313. return IRQ_NONE;
  2314. }
  2315. ha = rsp->hw;
  2316. reg = &ha->iobase->isp24;
  2317. status = 0;
  2318. spin_lock_irqsave(&ha->hardware_lock, flags);
  2319. vha = pci_get_drvdata(ha->pdev);
  2320. do {
  2321. stat = RD_REG_DWORD(&reg->host_status);
  2322. if (stat & HSRX_RISC_PAUSED) {
  2323. if (unlikely(pci_channel_offline(ha->pdev)))
  2324. break;
  2325. hccr = RD_REG_DWORD(&reg->hccr);
  2326. ql_log(ql_log_info, vha, 0x5050,
  2327. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2328. hccr);
  2329. qla2xxx_check_risc_status(vha);
  2330. ha->isp_ops->fw_dump(vha, 1);
  2331. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2332. break;
  2333. } else if ((stat & HSRX_RISC_INT) == 0)
  2334. break;
  2335. switch (stat & 0xff) {
  2336. case INTR_ROM_MB_SUCCESS:
  2337. case INTR_ROM_MB_FAILED:
  2338. case INTR_MB_SUCCESS:
  2339. case INTR_MB_FAILED:
  2340. qla24xx_mbx_completion(vha, MSW(stat));
  2341. status |= MBX_INTERRUPT;
  2342. break;
  2343. case INTR_ASYNC_EVENT:
  2344. mb[0] = MSW(stat);
  2345. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2346. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2347. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2348. qla2x00_async_event(vha, rsp, mb);
  2349. break;
  2350. case INTR_RSP_QUE_UPDATE:
  2351. case INTR_RSP_QUE_UPDATE_83XX:
  2352. qla24xx_process_response_queue(vha, rsp);
  2353. break;
  2354. case INTR_ATIO_QUE_UPDATE:
  2355. qlt_24xx_process_atio_queue(vha);
  2356. break;
  2357. case INTR_ATIO_RSP_QUE_UPDATE:
  2358. qlt_24xx_process_atio_queue(vha);
  2359. qla24xx_process_response_queue(vha, rsp);
  2360. break;
  2361. default:
  2362. ql_dbg(ql_dbg_async, vha, 0x5051,
  2363. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2364. break;
  2365. }
  2366. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2367. } while (0);
  2368. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2369. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2370. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2371. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2372. complete(&ha->mbx_intr_comp);
  2373. }
  2374. return IRQ_HANDLED;
  2375. }
  2376. /* Interrupt handling helpers. */
  2377. struct qla_init_msix_entry {
  2378. const char *name;
  2379. irq_handler_t handler;
  2380. };
  2381. static struct qla_init_msix_entry msix_entries[3] = {
  2382. { "qla2xxx (default)", qla24xx_msix_default },
  2383. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2384. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2385. };
  2386. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2387. { "qla2xxx (default)", qla82xx_msix_default },
  2388. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2389. };
  2390. static void
  2391. qla24xx_disable_msix(struct qla_hw_data *ha)
  2392. {
  2393. int i;
  2394. struct qla_msix_entry *qentry;
  2395. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2396. for (i = 0; i < ha->msix_count; i++) {
  2397. qentry = &ha->msix_entries[i];
  2398. if (qentry->have_irq)
  2399. free_irq(qentry->vector, qentry->rsp);
  2400. }
  2401. pci_disable_msix(ha->pdev);
  2402. kfree(ha->msix_entries);
  2403. ha->msix_entries = NULL;
  2404. ha->flags.msix_enabled = 0;
  2405. ql_dbg(ql_dbg_init, vha, 0x0042,
  2406. "Disabled the MSI.\n");
  2407. }
  2408. static int
  2409. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2410. {
  2411. #define MIN_MSIX_COUNT 2
  2412. int i, ret;
  2413. struct msix_entry *entries;
  2414. struct qla_msix_entry *qentry;
  2415. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2416. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2417. GFP_KERNEL);
  2418. if (!entries) {
  2419. ql_log(ql_log_warn, vha, 0x00bc,
  2420. "Failed to allocate memory for msix_entry.\n");
  2421. return -ENOMEM;
  2422. }
  2423. for (i = 0; i < ha->msix_count; i++)
  2424. entries[i].entry = i;
  2425. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2426. if (ret) {
  2427. if (ret < MIN_MSIX_COUNT)
  2428. goto msix_failed;
  2429. ql_log(ql_log_warn, vha, 0x00c6,
  2430. "MSI-X: Failed to enable support "
  2431. "-- %d/%d\n Retry with %d vectors.\n",
  2432. ha->msix_count, ret, ret);
  2433. ha->msix_count = ret;
  2434. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2435. if (ret) {
  2436. msix_failed:
  2437. ql_log(ql_log_fatal, vha, 0x00c7,
  2438. "MSI-X: Failed to enable support, "
  2439. "giving up -- %d/%d.\n",
  2440. ha->msix_count, ret);
  2441. goto msix_out;
  2442. }
  2443. ha->max_rsp_queues = ha->msix_count - 1;
  2444. }
  2445. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2446. ha->msix_count, GFP_KERNEL);
  2447. if (!ha->msix_entries) {
  2448. ql_log(ql_log_fatal, vha, 0x00c8,
  2449. "Failed to allocate memory for ha->msix_entries.\n");
  2450. ret = -ENOMEM;
  2451. goto msix_out;
  2452. }
  2453. ha->flags.msix_enabled = 1;
  2454. for (i = 0; i < ha->msix_count; i++) {
  2455. qentry = &ha->msix_entries[i];
  2456. qentry->vector = entries[i].vector;
  2457. qentry->entry = entries[i].entry;
  2458. qentry->have_irq = 0;
  2459. qentry->rsp = NULL;
  2460. }
  2461. /* Enable MSI-X vectors for the base queue */
  2462. for (i = 0; i < 2; i++) {
  2463. qentry = &ha->msix_entries[i];
  2464. if (IS_QLA82XX(ha)) {
  2465. ret = request_irq(qentry->vector,
  2466. qla82xx_msix_entries[i].handler,
  2467. 0, qla82xx_msix_entries[i].name, rsp);
  2468. } else {
  2469. ret = request_irq(qentry->vector,
  2470. msix_entries[i].handler,
  2471. 0, msix_entries[i].name, rsp);
  2472. }
  2473. if (ret) {
  2474. ql_log(ql_log_fatal, vha, 0x00cb,
  2475. "MSI-X: unable to register handler -- %x/%d.\n",
  2476. qentry->vector, ret);
  2477. qla24xx_disable_msix(ha);
  2478. ha->mqenable = 0;
  2479. goto msix_out;
  2480. }
  2481. qentry->have_irq = 1;
  2482. qentry->rsp = rsp;
  2483. rsp->msix = qentry;
  2484. }
  2485. /* Enable MSI-X vector for response queue update for queue 0 */
  2486. if (IS_QLA83XX(ha)) {
  2487. if (ha->msixbase && ha->mqiobase &&
  2488. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2489. ha->mqenable = 1;
  2490. } else
  2491. if (ha->mqiobase
  2492. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2493. ha->mqenable = 1;
  2494. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2495. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2496. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2497. ql_dbg(ql_dbg_init, vha, 0x0055,
  2498. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2499. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2500. msix_out:
  2501. kfree(entries);
  2502. return ret;
  2503. }
  2504. int
  2505. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2506. {
  2507. int ret;
  2508. device_reg_t __iomem *reg = ha->iobase;
  2509. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2510. /* If possible, enable MSI-X. */
  2511. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2512. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2513. goto skip_msi;
  2514. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2515. (ha->pdev->subsystem_device == 0x7040 ||
  2516. ha->pdev->subsystem_device == 0x7041 ||
  2517. ha->pdev->subsystem_device == 0x1705)) {
  2518. ql_log(ql_log_warn, vha, 0x0034,
  2519. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2520. ha->pdev->subsystem_vendor,
  2521. ha->pdev->subsystem_device);
  2522. goto skip_msi;
  2523. }
  2524. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2525. ql_log(ql_log_warn, vha, 0x0035,
  2526. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2527. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2528. goto skip_msix;
  2529. }
  2530. ret = qla24xx_enable_msix(ha, rsp);
  2531. if (!ret) {
  2532. ql_dbg(ql_dbg_init, vha, 0x0036,
  2533. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2534. ha->chip_revision, ha->fw_attributes);
  2535. goto clear_risc_ints;
  2536. }
  2537. ql_log(ql_log_info, vha, 0x0037,
  2538. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2539. skip_msix:
  2540. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2541. !IS_QLA8001(ha))
  2542. goto skip_msi;
  2543. ret = pci_enable_msi(ha->pdev);
  2544. if (!ret) {
  2545. ql_dbg(ql_dbg_init, vha, 0x0038,
  2546. "MSI: Enabled.\n");
  2547. ha->flags.msi_enabled = 1;
  2548. } else
  2549. ql_log(ql_log_warn, vha, 0x0039,
  2550. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2551. /* Skip INTx on ISP82xx. */
  2552. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2553. return QLA_FUNCTION_FAILED;
  2554. skip_msi:
  2555. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2556. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2557. QLA2XXX_DRIVER_NAME, rsp);
  2558. if (ret) {
  2559. ql_log(ql_log_warn, vha, 0x003a,
  2560. "Failed to reserve interrupt %d already in use.\n",
  2561. ha->pdev->irq);
  2562. goto fail;
  2563. }
  2564. clear_risc_ints:
  2565. /*
  2566. * FIXME: Noted that 8014s were being dropped during NK testing.
  2567. * Timing deltas during MSI-X/INTa transitions?
  2568. */
  2569. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA83XX(ha))
  2570. goto fail;
  2571. spin_lock_irq(&ha->hardware_lock);
  2572. if (IS_FWI2_CAPABLE(ha)) {
  2573. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_HOST_INT);
  2574. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_RISC_INT);
  2575. } else {
  2576. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2577. WRT_REG_WORD(&reg->isp.hccr, HCCR_CLR_RISC_INT);
  2578. WRT_REG_WORD(&reg->isp.hccr, HCCR_CLR_HOST_INT);
  2579. }
  2580. spin_unlock_irq(&ha->hardware_lock);
  2581. fail:
  2582. return ret;
  2583. }
  2584. void
  2585. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2586. {
  2587. struct qla_hw_data *ha = vha->hw;
  2588. struct rsp_que *rsp;
  2589. /*
  2590. * We need to check that ha->rsp_q_map is valid in case we are called
  2591. * from a probe failure context.
  2592. */
  2593. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2594. return;
  2595. rsp = ha->rsp_q_map[0];
  2596. if (ha->flags.msix_enabled)
  2597. qla24xx_disable_msix(ha);
  2598. else if (ha->flags.msi_enabled) {
  2599. free_irq(ha->pdev->irq, rsp);
  2600. pci_disable_msi(ha->pdev);
  2601. } else
  2602. free_irq(ha->pdev->irq, rsp);
  2603. }
  2604. int qla25xx_request_irq(struct rsp_que *rsp)
  2605. {
  2606. struct qla_hw_data *ha = rsp->hw;
  2607. struct qla_init_msix_entry *intr = &msix_entries[2];
  2608. struct qla_msix_entry *msix = rsp->msix;
  2609. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2610. int ret;
  2611. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2612. if (ret) {
  2613. ql_log(ql_log_fatal, vha, 0x00e6,
  2614. "MSI-X: Unable to register handler -- %x/%d.\n",
  2615. msix->vector, ret);
  2616. return ret;
  2617. }
  2618. msix->have_irq = 1;
  2619. msix->rsp = rsp;
  2620. return ret;
  2621. }