events.c 36 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is recieved, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. /* IRQ <-> VIRQ mapping. */
  55. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  56. /* IRQ <-> IPI mapping */
  57. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  58. /* Interrupt types. */
  59. enum xen_irq_type {
  60. IRQT_UNBOUND = 0,
  61. IRQT_PIRQ,
  62. IRQT_VIRQ,
  63. IRQT_IPI,
  64. IRQT_EVTCHN
  65. };
  66. /*
  67. * Packed IRQ information:
  68. * type - enum xen_irq_type
  69. * event channel - irq->event channel mapping
  70. * cpu - cpu this event channel is bound to
  71. * index - type-specific information:
  72. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  73. * guest, or GSI (real passthrough IRQ) of the device.
  74. * VIRQ - virq number
  75. * IPI - IPI vector
  76. * EVTCHN -
  77. */
  78. struct irq_info
  79. {
  80. enum xen_irq_type type; /* type */
  81. unsigned short evtchn; /* event channel */
  82. unsigned short cpu; /* cpu bound */
  83. union {
  84. unsigned short virq;
  85. enum ipi_vector ipi;
  86. struct {
  87. unsigned short pirq;
  88. unsigned short gsi;
  89. unsigned char vector;
  90. unsigned char flags;
  91. } pirq;
  92. } u;
  93. };
  94. #define PIRQ_NEEDS_EOI (1 << 0)
  95. #define PIRQ_SHAREABLE (1 << 1)
  96. static struct irq_info *irq_info;
  97. static int *pirq_to_irq;
  98. static int *evtchn_to_irq;
  99. struct cpu_evtchn_s {
  100. unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
  101. };
  102. static __initdata struct cpu_evtchn_s init_evtchn_mask = {
  103. .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
  104. };
  105. static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
  106. static inline unsigned long *cpu_evtchn_mask(int cpu)
  107. {
  108. return cpu_evtchn_mask_p[cpu].bits;
  109. }
  110. /* Xen will never allocate port zero for any purpose. */
  111. #define VALID_EVTCHN(chn) ((chn) != 0)
  112. static struct irq_chip xen_dynamic_chip;
  113. static struct irq_chip xen_percpu_chip;
  114. static struct irq_chip xen_pirq_chip;
  115. /* Constructor for packed IRQ information. */
  116. static struct irq_info mk_unbound_info(void)
  117. {
  118. return (struct irq_info) { .type = IRQT_UNBOUND };
  119. }
  120. static struct irq_info mk_evtchn_info(unsigned short evtchn)
  121. {
  122. return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
  123. .cpu = 0 };
  124. }
  125. static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
  126. {
  127. return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
  128. .cpu = 0, .u.ipi = ipi };
  129. }
  130. static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
  131. {
  132. return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
  133. .cpu = 0, .u.virq = virq };
  134. }
  135. static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
  136. unsigned short gsi, unsigned short vector)
  137. {
  138. return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
  139. .cpu = 0,
  140. .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
  141. }
  142. /*
  143. * Accessors for packed IRQ information.
  144. */
  145. static struct irq_info *info_for_irq(unsigned irq)
  146. {
  147. return &irq_info[irq];
  148. }
  149. static unsigned int evtchn_from_irq(unsigned irq)
  150. {
  151. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  152. return 0;
  153. return info_for_irq(irq)->evtchn;
  154. }
  155. unsigned irq_from_evtchn(unsigned int evtchn)
  156. {
  157. return evtchn_to_irq[evtchn];
  158. }
  159. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  160. static enum ipi_vector ipi_from_irq(unsigned irq)
  161. {
  162. struct irq_info *info = info_for_irq(irq);
  163. BUG_ON(info == NULL);
  164. BUG_ON(info->type != IRQT_IPI);
  165. return info->u.ipi;
  166. }
  167. static unsigned virq_from_irq(unsigned irq)
  168. {
  169. struct irq_info *info = info_for_irq(irq);
  170. BUG_ON(info == NULL);
  171. BUG_ON(info->type != IRQT_VIRQ);
  172. return info->u.virq;
  173. }
  174. static unsigned pirq_from_irq(unsigned irq)
  175. {
  176. struct irq_info *info = info_for_irq(irq);
  177. BUG_ON(info == NULL);
  178. BUG_ON(info->type != IRQT_PIRQ);
  179. return info->u.pirq.pirq;
  180. }
  181. static unsigned gsi_from_irq(unsigned irq)
  182. {
  183. struct irq_info *info = info_for_irq(irq);
  184. BUG_ON(info == NULL);
  185. BUG_ON(info->type != IRQT_PIRQ);
  186. return info->u.pirq.gsi;
  187. }
  188. static unsigned vector_from_irq(unsigned irq)
  189. {
  190. struct irq_info *info = info_for_irq(irq);
  191. BUG_ON(info == NULL);
  192. BUG_ON(info->type != IRQT_PIRQ);
  193. return info->u.pirq.vector;
  194. }
  195. static enum xen_irq_type type_from_irq(unsigned irq)
  196. {
  197. return info_for_irq(irq)->type;
  198. }
  199. static unsigned cpu_from_irq(unsigned irq)
  200. {
  201. return info_for_irq(irq)->cpu;
  202. }
  203. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  204. {
  205. int irq = evtchn_to_irq[evtchn];
  206. unsigned ret = 0;
  207. if (irq != -1)
  208. ret = cpu_from_irq(irq);
  209. return ret;
  210. }
  211. static bool pirq_needs_eoi(unsigned irq)
  212. {
  213. struct irq_info *info = info_for_irq(irq);
  214. BUG_ON(info->type != IRQT_PIRQ);
  215. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  216. }
  217. static inline unsigned long active_evtchns(unsigned int cpu,
  218. struct shared_info *sh,
  219. unsigned int idx)
  220. {
  221. return (sh->evtchn_pending[idx] &
  222. cpu_evtchn_mask(cpu)[idx] &
  223. ~sh->evtchn_mask[idx]);
  224. }
  225. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  226. {
  227. int irq = evtchn_to_irq[chn];
  228. BUG_ON(irq == -1);
  229. #ifdef CONFIG_SMP
  230. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  231. #endif
  232. clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
  233. set_bit(chn, cpu_evtchn_mask(cpu));
  234. irq_info[irq].cpu = cpu;
  235. }
  236. static void init_evtchn_cpu_bindings(void)
  237. {
  238. int i;
  239. #ifdef CONFIG_SMP
  240. struct irq_desc *desc;
  241. /* By default all event channels notify CPU#0. */
  242. for_each_irq_desc(i, desc) {
  243. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  244. }
  245. #endif
  246. for_each_possible_cpu(i)
  247. memset(cpu_evtchn_mask(i),
  248. (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
  249. }
  250. static inline void clear_evtchn(int port)
  251. {
  252. struct shared_info *s = HYPERVISOR_shared_info;
  253. sync_clear_bit(port, &s->evtchn_pending[0]);
  254. }
  255. static inline void set_evtchn(int port)
  256. {
  257. struct shared_info *s = HYPERVISOR_shared_info;
  258. sync_set_bit(port, &s->evtchn_pending[0]);
  259. }
  260. static inline int test_evtchn(int port)
  261. {
  262. struct shared_info *s = HYPERVISOR_shared_info;
  263. return sync_test_bit(port, &s->evtchn_pending[0]);
  264. }
  265. /**
  266. * notify_remote_via_irq - send event to remote end of event channel via irq
  267. * @irq: irq of event channel to send event to
  268. *
  269. * Unlike notify_remote_via_evtchn(), this is safe to use across
  270. * save/restore. Notifications on a broken connection are silently
  271. * dropped.
  272. */
  273. void notify_remote_via_irq(int irq)
  274. {
  275. int evtchn = evtchn_from_irq(irq);
  276. if (VALID_EVTCHN(evtchn))
  277. notify_remote_via_evtchn(evtchn);
  278. }
  279. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  280. static void mask_evtchn(int port)
  281. {
  282. struct shared_info *s = HYPERVISOR_shared_info;
  283. sync_set_bit(port, &s->evtchn_mask[0]);
  284. }
  285. static void unmask_evtchn(int port)
  286. {
  287. struct shared_info *s = HYPERVISOR_shared_info;
  288. unsigned int cpu = get_cpu();
  289. BUG_ON(!irqs_disabled());
  290. /* Slow path (hypercall) if this is a non-local port. */
  291. if (unlikely(cpu != cpu_from_evtchn(port))) {
  292. struct evtchn_unmask unmask = { .port = port };
  293. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  294. } else {
  295. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  296. sync_clear_bit(port, &s->evtchn_mask[0]);
  297. /*
  298. * The following is basically the equivalent of
  299. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  300. * the interrupt edge' if the channel is masked.
  301. */
  302. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  303. !sync_test_and_set_bit(port / BITS_PER_LONG,
  304. &vcpu_info->evtchn_pending_sel))
  305. vcpu_info->evtchn_upcall_pending = 1;
  306. }
  307. put_cpu();
  308. }
  309. static int xen_allocate_irq_dynamic(void)
  310. {
  311. int first = 0;
  312. int irq;
  313. #ifdef CONFIG_X86_IO_APIC
  314. /*
  315. * For an HVM guest or domain 0 which see "real" (emulated or
  316. * actual repectively) GSIs we allocate dynamic IRQs
  317. * e.g. those corresponding to event channels or MSIs
  318. * etc. from the range above those "real" GSIs to avoid
  319. * collisions.
  320. */
  321. if (xen_initial_domain() || xen_hvm_domain())
  322. first = get_nr_irqs_gsi();
  323. #endif
  324. retry:
  325. irq = irq_alloc_desc_from(first, -1);
  326. if (irq == -ENOMEM && first > NR_IRQS_LEGACY) {
  327. printk(KERN_ERR "Out of dynamic IRQ space and eating into GSI space. You should increase nr_irqs\n");
  328. first = max(NR_IRQS_LEGACY, first - NR_IRQS_LEGACY);
  329. goto retry;
  330. }
  331. if (irq < 0)
  332. panic("No available IRQ to bind to: increase nr_irqs!\n");
  333. return irq;
  334. }
  335. static int xen_allocate_irq_gsi(unsigned gsi)
  336. {
  337. int irq;
  338. /*
  339. * A PV guest has no concept of a GSI (since it has no ACPI
  340. * nor access to/knowledge of the physical APICs). Therefore
  341. * all IRQs are dynamically allocated from the entire IRQ
  342. * space.
  343. */
  344. if (xen_pv_domain() && !xen_initial_domain())
  345. return xen_allocate_irq_dynamic();
  346. /* Legacy IRQ descriptors are already allocated by the arch. */
  347. if (gsi < NR_IRQS_LEGACY)
  348. return gsi;
  349. irq = irq_alloc_desc_at(gsi, -1);
  350. if (irq < 0)
  351. panic("Unable to allocate to IRQ%d (%d)\n", gsi, irq);
  352. return irq;
  353. }
  354. static void xen_free_irq(unsigned irq)
  355. {
  356. /* Legacy IRQ descriptors are managed by the arch. */
  357. if (irq < NR_IRQS_LEGACY)
  358. return;
  359. irq_free_desc(irq);
  360. }
  361. static void pirq_unmask_notify(int irq)
  362. {
  363. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  364. if (unlikely(pirq_needs_eoi(irq))) {
  365. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  366. WARN_ON(rc);
  367. }
  368. }
  369. static void pirq_query_unmask(int irq)
  370. {
  371. struct physdev_irq_status_query irq_status;
  372. struct irq_info *info = info_for_irq(irq);
  373. BUG_ON(info->type != IRQT_PIRQ);
  374. irq_status.irq = pirq_from_irq(irq);
  375. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  376. irq_status.flags = 0;
  377. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  378. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  379. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  380. }
  381. static bool probing_irq(int irq)
  382. {
  383. struct irq_desc *desc = irq_to_desc(irq);
  384. return desc && desc->action == NULL;
  385. }
  386. static unsigned int __startup_pirq(unsigned int irq)
  387. {
  388. struct evtchn_bind_pirq bind_pirq;
  389. struct irq_info *info = info_for_irq(irq);
  390. int evtchn = evtchn_from_irq(irq);
  391. int rc;
  392. BUG_ON(info->type != IRQT_PIRQ);
  393. if (VALID_EVTCHN(evtchn))
  394. goto out;
  395. bind_pirq.pirq = pirq_from_irq(irq);
  396. /* NB. We are happy to share unless we are probing. */
  397. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  398. BIND_PIRQ__WILL_SHARE : 0;
  399. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  400. if (rc != 0) {
  401. if (!probing_irq(irq))
  402. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  403. irq);
  404. return 0;
  405. }
  406. evtchn = bind_pirq.port;
  407. pirq_query_unmask(irq);
  408. evtchn_to_irq[evtchn] = irq;
  409. bind_evtchn_to_cpu(evtchn, 0);
  410. info->evtchn = evtchn;
  411. out:
  412. unmask_evtchn(evtchn);
  413. pirq_unmask_notify(irq);
  414. return 0;
  415. }
  416. static unsigned int startup_pirq(struct irq_data *data)
  417. {
  418. return __startup_pirq(data->irq);
  419. }
  420. static void shutdown_pirq(struct irq_data *data)
  421. {
  422. struct evtchn_close close;
  423. unsigned int irq = data->irq;
  424. struct irq_info *info = info_for_irq(irq);
  425. int evtchn = evtchn_from_irq(irq);
  426. BUG_ON(info->type != IRQT_PIRQ);
  427. if (!VALID_EVTCHN(evtchn))
  428. return;
  429. mask_evtchn(evtchn);
  430. close.port = evtchn;
  431. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  432. BUG();
  433. bind_evtchn_to_cpu(evtchn, 0);
  434. evtchn_to_irq[evtchn] = -1;
  435. info->evtchn = 0;
  436. }
  437. static void enable_pirq(struct irq_data *data)
  438. {
  439. startup_pirq(data);
  440. }
  441. static void disable_pirq(struct irq_data *data)
  442. {
  443. }
  444. static void ack_pirq(struct irq_data *data)
  445. {
  446. int evtchn = evtchn_from_irq(data->irq);
  447. move_native_irq(data->irq);
  448. if (VALID_EVTCHN(evtchn)) {
  449. mask_evtchn(evtchn);
  450. clear_evtchn(evtchn);
  451. }
  452. }
  453. static int find_irq_by_gsi(unsigned gsi)
  454. {
  455. int irq;
  456. for (irq = 0; irq < nr_irqs; irq++) {
  457. struct irq_info *info = info_for_irq(irq);
  458. if (info == NULL || info->type != IRQT_PIRQ)
  459. continue;
  460. if (gsi_from_irq(irq) == gsi)
  461. return irq;
  462. }
  463. return -1;
  464. }
  465. int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
  466. {
  467. return xen_map_pirq_gsi(gsi, gsi, shareable, name);
  468. }
  469. /* xen_map_pirq_gsi might allocate irqs from the top down, as a
  470. * consequence don't assume that the irq number returned has a low value
  471. * or can be used as a pirq number unless you know otherwise.
  472. *
  473. * One notable exception is when xen_map_pirq_gsi is called passing an
  474. * hardware gsi as argument, in that case the irq number returned
  475. * matches the gsi number passed as second argument.
  476. *
  477. * Note: We don't assign an event channel until the irq actually started
  478. * up. Return an existing irq if we've already got one for the gsi.
  479. */
  480. int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
  481. {
  482. int irq = 0;
  483. struct physdev_irq irq_op;
  484. spin_lock(&irq_mapping_update_lock);
  485. if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
  486. printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
  487. pirq > nr_irqs ? "pirq" :"",
  488. gsi > nr_irqs ? "gsi" : "");
  489. goto out;
  490. }
  491. irq = find_irq_by_gsi(gsi);
  492. if (irq != -1) {
  493. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  494. irq, gsi);
  495. goto out; /* XXX need refcount? */
  496. }
  497. irq = xen_allocate_irq_gsi(gsi);
  498. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  499. handle_level_irq, name);
  500. irq_op.irq = irq;
  501. irq_op.vector = 0;
  502. /* Only the privileged domain can do this. For non-priv, the pcifront
  503. * driver provides a PCI bus that does the call to do exactly
  504. * this in the priv domain. */
  505. if (xen_initial_domain() &&
  506. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  507. xen_free_irq(irq);
  508. irq = -ENOSPC;
  509. goto out;
  510. }
  511. irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
  512. irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
  513. pirq_to_irq[pirq] = irq;
  514. out:
  515. spin_unlock(&irq_mapping_update_lock);
  516. return irq;
  517. }
  518. #ifdef CONFIG_PCI_MSI
  519. #include <linux/msi.h>
  520. #include "../pci/msi.h"
  521. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  522. {
  523. int rc;
  524. struct physdev_get_free_pirq op_get_free_pirq;
  525. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  526. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  527. WARN_ONCE(rc == -ENOSYS,
  528. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  529. return rc ? -1 : op_get_free_pirq.pirq;
  530. }
  531. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  532. int pirq, const char *name)
  533. {
  534. int irq, ret;
  535. spin_lock(&irq_mapping_update_lock);
  536. irq = xen_allocate_irq_dynamic();
  537. if (irq == -1)
  538. goto out;
  539. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  540. handle_level_irq, name);
  541. irq_info[irq] = mk_pirq_info(0, pirq, 0, 0);
  542. pirq_to_irq[pirq] = irq;
  543. ret = set_irq_msi(irq, msidesc);
  544. if (ret < 0)
  545. goto error_irq;
  546. out:
  547. spin_unlock(&irq_mapping_update_lock);
  548. return irq;
  549. error_irq:
  550. spin_unlock(&irq_mapping_update_lock);
  551. xen_free_irq(irq);
  552. return -1;
  553. }
  554. int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
  555. {
  556. int irq = -1;
  557. struct physdev_map_pirq map_irq;
  558. int rc;
  559. int pos;
  560. u32 table_offset, bir;
  561. memset(&map_irq, 0, sizeof(map_irq));
  562. map_irq.domid = DOMID_SELF;
  563. map_irq.type = MAP_PIRQ_TYPE_MSI;
  564. map_irq.index = -1;
  565. map_irq.pirq = -1;
  566. map_irq.bus = dev->bus->number;
  567. map_irq.devfn = dev->devfn;
  568. if (type == PCI_CAP_ID_MSIX) {
  569. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  570. pci_read_config_dword(dev, msix_table_offset_reg(pos),
  571. &table_offset);
  572. bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
  573. map_irq.table_base = pci_resource_start(dev, bir);
  574. map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
  575. }
  576. spin_lock(&irq_mapping_update_lock);
  577. irq = xen_allocate_irq_dynamic();
  578. if (irq == -1)
  579. goto out;
  580. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  581. if (rc) {
  582. printk(KERN_WARNING "xen map irq failed %d\n", rc);
  583. xen_free_irq(irq);
  584. irq = -1;
  585. goto out;
  586. }
  587. irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
  588. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  589. handle_level_irq,
  590. (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
  591. out:
  592. spin_unlock(&irq_mapping_update_lock);
  593. return irq;
  594. }
  595. #endif
  596. int xen_destroy_irq(int irq)
  597. {
  598. struct irq_desc *desc;
  599. struct physdev_unmap_pirq unmap_irq;
  600. struct irq_info *info = info_for_irq(irq);
  601. int rc = -ENOENT;
  602. spin_lock(&irq_mapping_update_lock);
  603. desc = irq_to_desc(irq);
  604. if (!desc)
  605. goto out;
  606. if (xen_initial_domain()) {
  607. unmap_irq.pirq = info->u.pirq.pirq;
  608. unmap_irq.domid = DOMID_SELF;
  609. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  610. if (rc) {
  611. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  612. goto out;
  613. }
  614. }
  615. pirq_to_irq[info->u.pirq.pirq] = -1;
  616. irq_info[irq] = mk_unbound_info();
  617. xen_free_irq(irq);
  618. out:
  619. spin_unlock(&irq_mapping_update_lock);
  620. return rc;
  621. }
  622. int xen_vector_from_irq(unsigned irq)
  623. {
  624. return vector_from_irq(irq);
  625. }
  626. int xen_gsi_from_irq(unsigned irq)
  627. {
  628. return gsi_from_irq(irq);
  629. }
  630. int xen_irq_from_pirq(unsigned pirq)
  631. {
  632. return pirq_to_irq[pirq];
  633. }
  634. int bind_evtchn_to_irq(unsigned int evtchn)
  635. {
  636. int irq;
  637. spin_lock(&irq_mapping_update_lock);
  638. irq = evtchn_to_irq[evtchn];
  639. if (irq == -1) {
  640. irq = xen_allocate_irq_dynamic();
  641. set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
  642. handle_fasteoi_irq, "event");
  643. evtchn_to_irq[evtchn] = irq;
  644. irq_info[irq] = mk_evtchn_info(evtchn);
  645. }
  646. spin_unlock(&irq_mapping_update_lock);
  647. return irq;
  648. }
  649. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  650. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  651. {
  652. struct evtchn_bind_ipi bind_ipi;
  653. int evtchn, irq;
  654. spin_lock(&irq_mapping_update_lock);
  655. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  656. if (irq == -1) {
  657. irq = xen_allocate_irq_dynamic();
  658. if (irq < 0)
  659. goto out;
  660. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  661. handle_percpu_irq, "ipi");
  662. bind_ipi.vcpu = cpu;
  663. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  664. &bind_ipi) != 0)
  665. BUG();
  666. evtchn = bind_ipi.port;
  667. evtchn_to_irq[evtchn] = irq;
  668. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  669. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  670. bind_evtchn_to_cpu(evtchn, cpu);
  671. }
  672. out:
  673. spin_unlock(&irq_mapping_update_lock);
  674. return irq;
  675. }
  676. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  677. {
  678. struct evtchn_bind_virq bind_virq;
  679. int evtchn, irq;
  680. spin_lock(&irq_mapping_update_lock);
  681. irq = per_cpu(virq_to_irq, cpu)[virq];
  682. if (irq == -1) {
  683. irq = xen_allocate_irq_dynamic();
  684. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  685. handle_percpu_irq, "virq");
  686. bind_virq.virq = virq;
  687. bind_virq.vcpu = cpu;
  688. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  689. &bind_virq) != 0)
  690. BUG();
  691. evtchn = bind_virq.port;
  692. evtchn_to_irq[evtchn] = irq;
  693. irq_info[irq] = mk_virq_info(evtchn, virq);
  694. per_cpu(virq_to_irq, cpu)[virq] = irq;
  695. bind_evtchn_to_cpu(evtchn, cpu);
  696. }
  697. spin_unlock(&irq_mapping_update_lock);
  698. return irq;
  699. }
  700. static void unbind_from_irq(unsigned int irq)
  701. {
  702. struct evtchn_close close;
  703. int evtchn = evtchn_from_irq(irq);
  704. spin_lock(&irq_mapping_update_lock);
  705. if (VALID_EVTCHN(evtchn)) {
  706. close.port = evtchn;
  707. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  708. BUG();
  709. switch (type_from_irq(irq)) {
  710. case IRQT_VIRQ:
  711. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  712. [virq_from_irq(irq)] = -1;
  713. break;
  714. case IRQT_IPI:
  715. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  716. [ipi_from_irq(irq)] = -1;
  717. break;
  718. default:
  719. break;
  720. }
  721. /* Closed ports are implicitly re-bound to VCPU0. */
  722. bind_evtchn_to_cpu(evtchn, 0);
  723. evtchn_to_irq[evtchn] = -1;
  724. }
  725. if (irq_info[irq].type != IRQT_UNBOUND) {
  726. irq_info[irq] = mk_unbound_info();
  727. xen_free_irq(irq);
  728. }
  729. spin_unlock(&irq_mapping_update_lock);
  730. }
  731. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  732. irq_handler_t handler,
  733. unsigned long irqflags,
  734. const char *devname, void *dev_id)
  735. {
  736. unsigned int irq;
  737. int retval;
  738. irq = bind_evtchn_to_irq(evtchn);
  739. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  740. if (retval != 0) {
  741. unbind_from_irq(irq);
  742. return retval;
  743. }
  744. return irq;
  745. }
  746. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  747. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  748. irq_handler_t handler,
  749. unsigned long irqflags, const char *devname, void *dev_id)
  750. {
  751. unsigned int irq;
  752. int retval;
  753. irq = bind_virq_to_irq(virq, cpu);
  754. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  755. if (retval != 0) {
  756. unbind_from_irq(irq);
  757. return retval;
  758. }
  759. return irq;
  760. }
  761. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  762. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  763. unsigned int cpu,
  764. irq_handler_t handler,
  765. unsigned long irqflags,
  766. const char *devname,
  767. void *dev_id)
  768. {
  769. int irq, retval;
  770. irq = bind_ipi_to_irq(ipi, cpu);
  771. if (irq < 0)
  772. return irq;
  773. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME;
  774. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  775. if (retval != 0) {
  776. unbind_from_irq(irq);
  777. return retval;
  778. }
  779. return irq;
  780. }
  781. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  782. {
  783. free_irq(irq, dev_id);
  784. unbind_from_irq(irq);
  785. }
  786. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  787. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  788. {
  789. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  790. BUG_ON(irq < 0);
  791. notify_remote_via_irq(irq);
  792. }
  793. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  794. {
  795. struct shared_info *sh = HYPERVISOR_shared_info;
  796. int cpu = smp_processor_id();
  797. unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
  798. int i;
  799. unsigned long flags;
  800. static DEFINE_SPINLOCK(debug_lock);
  801. struct vcpu_info *v;
  802. spin_lock_irqsave(&debug_lock, flags);
  803. printk("\nvcpu %d\n ", cpu);
  804. for_each_online_cpu(i) {
  805. int pending;
  806. v = per_cpu(xen_vcpu, i);
  807. pending = (get_irq_regs() && i == cpu)
  808. ? xen_irqs_disabled(get_irq_regs())
  809. : v->evtchn_upcall_mask;
  810. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  811. pending, v->evtchn_upcall_pending,
  812. (int)(sizeof(v->evtchn_pending_sel)*2),
  813. v->evtchn_pending_sel);
  814. }
  815. v = per_cpu(xen_vcpu, cpu);
  816. printk("\npending:\n ");
  817. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  818. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  819. sh->evtchn_pending[i],
  820. i % 8 == 0 ? "\n " : " ");
  821. printk("\nglobal mask:\n ");
  822. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  823. printk("%0*lx%s",
  824. (int)(sizeof(sh->evtchn_mask[0])*2),
  825. sh->evtchn_mask[i],
  826. i % 8 == 0 ? "\n " : " ");
  827. printk("\nglobally unmasked:\n ");
  828. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  829. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  830. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  831. i % 8 == 0 ? "\n " : " ");
  832. printk("\nlocal cpu%d mask:\n ", cpu);
  833. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  834. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  835. cpu_evtchn[i],
  836. i % 8 == 0 ? "\n " : " ");
  837. printk("\nlocally unmasked:\n ");
  838. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  839. unsigned long pending = sh->evtchn_pending[i]
  840. & ~sh->evtchn_mask[i]
  841. & cpu_evtchn[i];
  842. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  843. pending, i % 8 == 0 ? "\n " : " ");
  844. }
  845. printk("\npending list:\n");
  846. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  847. if (sync_test_bit(i, sh->evtchn_pending)) {
  848. int word_idx = i / BITS_PER_LONG;
  849. printk(" %d: event %d -> irq %d%s%s%s\n",
  850. cpu_from_evtchn(i), i,
  851. evtchn_to_irq[i],
  852. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  853. ? "" : " l2-clear",
  854. !sync_test_bit(i, sh->evtchn_mask)
  855. ? "" : " globally-masked",
  856. sync_test_bit(i, cpu_evtchn)
  857. ? "" : " locally-masked");
  858. }
  859. }
  860. spin_unlock_irqrestore(&debug_lock, flags);
  861. return IRQ_HANDLED;
  862. }
  863. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  864. /*
  865. * Search the CPUs pending events bitmasks. For each one found, map
  866. * the event number to an irq, and feed it into do_IRQ() for
  867. * handling.
  868. *
  869. * Xen uses a two-level bitmap to speed searching. The first level is
  870. * a bitset of words which contain pending event bits. The second
  871. * level is a bitset of pending events themselves.
  872. */
  873. static void __xen_evtchn_do_upcall(void)
  874. {
  875. int cpu = get_cpu();
  876. struct shared_info *s = HYPERVISOR_shared_info;
  877. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  878. unsigned count;
  879. do {
  880. unsigned long pending_words;
  881. vcpu_info->evtchn_upcall_pending = 0;
  882. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  883. goto out;
  884. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  885. /* Clear master flag /before/ clearing selector flag. */
  886. wmb();
  887. #endif
  888. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  889. while (pending_words != 0) {
  890. unsigned long pending_bits;
  891. int word_idx = __ffs(pending_words);
  892. pending_words &= ~(1UL << word_idx);
  893. while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
  894. int bit_idx = __ffs(pending_bits);
  895. int port = (word_idx * BITS_PER_LONG) + bit_idx;
  896. int irq = evtchn_to_irq[port];
  897. struct irq_desc *desc;
  898. mask_evtchn(port);
  899. clear_evtchn(port);
  900. if (irq != -1) {
  901. desc = irq_to_desc(irq);
  902. if (desc)
  903. generic_handle_irq_desc(irq, desc);
  904. }
  905. }
  906. }
  907. BUG_ON(!irqs_disabled());
  908. count = __this_cpu_read(xed_nesting_count);
  909. __this_cpu_write(xed_nesting_count, 0);
  910. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  911. out:
  912. put_cpu();
  913. }
  914. void xen_evtchn_do_upcall(struct pt_regs *regs)
  915. {
  916. struct pt_regs *old_regs = set_irq_regs(regs);
  917. exit_idle();
  918. irq_enter();
  919. __xen_evtchn_do_upcall();
  920. irq_exit();
  921. set_irq_regs(old_regs);
  922. }
  923. void xen_hvm_evtchn_do_upcall(void)
  924. {
  925. __xen_evtchn_do_upcall();
  926. }
  927. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  928. /* Rebind a new event channel to an existing irq. */
  929. void rebind_evtchn_irq(int evtchn, int irq)
  930. {
  931. struct irq_info *info = info_for_irq(irq);
  932. /* Make sure the irq is masked, since the new event channel
  933. will also be masked. */
  934. disable_irq(irq);
  935. spin_lock(&irq_mapping_update_lock);
  936. /* After resume the irq<->evtchn mappings are all cleared out */
  937. BUG_ON(evtchn_to_irq[evtchn] != -1);
  938. /* Expect irq to have been bound before,
  939. so there should be a proper type */
  940. BUG_ON(info->type == IRQT_UNBOUND);
  941. evtchn_to_irq[evtchn] = irq;
  942. irq_info[irq] = mk_evtchn_info(evtchn);
  943. spin_unlock(&irq_mapping_update_lock);
  944. /* new event channels are always bound to cpu 0 */
  945. irq_set_affinity(irq, cpumask_of(0));
  946. /* Unmask the event channel. */
  947. enable_irq(irq);
  948. }
  949. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  950. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  951. {
  952. struct evtchn_bind_vcpu bind_vcpu;
  953. int evtchn = evtchn_from_irq(irq);
  954. /* events delivered via platform PCI interrupts are always
  955. * routed to vcpu 0 */
  956. if (!VALID_EVTCHN(evtchn) ||
  957. (xen_hvm_domain() && !xen_have_vector_callback))
  958. return -1;
  959. /* Send future instances of this interrupt to other vcpu. */
  960. bind_vcpu.port = evtchn;
  961. bind_vcpu.vcpu = tcpu;
  962. /*
  963. * If this fails, it usually just indicates that we're dealing with a
  964. * virq or IPI channel, which don't actually need to be rebound. Ignore
  965. * it, but don't do the xenlinux-level rebind in that case.
  966. */
  967. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  968. bind_evtchn_to_cpu(evtchn, tcpu);
  969. return 0;
  970. }
  971. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  972. bool force)
  973. {
  974. unsigned tcpu = cpumask_first(dest);
  975. return rebind_irq_to_cpu(data->irq, tcpu);
  976. }
  977. int resend_irq_on_evtchn(unsigned int irq)
  978. {
  979. int masked, evtchn = evtchn_from_irq(irq);
  980. struct shared_info *s = HYPERVISOR_shared_info;
  981. if (!VALID_EVTCHN(evtchn))
  982. return 1;
  983. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  984. sync_set_bit(evtchn, s->evtchn_pending);
  985. if (!masked)
  986. unmask_evtchn(evtchn);
  987. return 1;
  988. }
  989. static void enable_dynirq(struct irq_data *data)
  990. {
  991. int evtchn = evtchn_from_irq(data->irq);
  992. if (VALID_EVTCHN(evtchn))
  993. unmask_evtchn(evtchn);
  994. }
  995. static void disable_dynirq(struct irq_data *data)
  996. {
  997. int evtchn = evtchn_from_irq(data->irq);
  998. if (VALID_EVTCHN(evtchn))
  999. mask_evtchn(evtchn);
  1000. }
  1001. static void ack_dynirq(struct irq_data *data)
  1002. {
  1003. int evtchn = evtchn_from_irq(data->irq);
  1004. move_masked_irq(data->irq);
  1005. if (VALID_EVTCHN(evtchn))
  1006. unmask_evtchn(evtchn);
  1007. }
  1008. static int retrigger_dynirq(struct irq_data *data)
  1009. {
  1010. int evtchn = evtchn_from_irq(data->irq);
  1011. struct shared_info *sh = HYPERVISOR_shared_info;
  1012. int ret = 0;
  1013. if (VALID_EVTCHN(evtchn)) {
  1014. int masked;
  1015. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1016. sync_set_bit(evtchn, sh->evtchn_pending);
  1017. if (!masked)
  1018. unmask_evtchn(evtchn);
  1019. ret = 1;
  1020. }
  1021. return ret;
  1022. }
  1023. static void restore_cpu_pirqs(void)
  1024. {
  1025. int pirq, rc, irq, gsi;
  1026. struct physdev_map_pirq map_irq;
  1027. for (pirq = 0; pirq < nr_irqs; pirq++) {
  1028. irq = pirq_to_irq[pirq];
  1029. if (irq == -1)
  1030. continue;
  1031. /* save/restore of PT devices doesn't work, so at this point the
  1032. * only devices present are GSI based emulated devices */
  1033. gsi = gsi_from_irq(irq);
  1034. if (!gsi)
  1035. continue;
  1036. map_irq.domid = DOMID_SELF;
  1037. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1038. map_irq.index = gsi;
  1039. map_irq.pirq = pirq;
  1040. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1041. if (rc) {
  1042. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1043. gsi, irq, pirq, rc);
  1044. irq_info[irq] = mk_unbound_info();
  1045. pirq_to_irq[pirq] = -1;
  1046. continue;
  1047. }
  1048. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1049. __startup_pirq(irq);
  1050. }
  1051. }
  1052. static void restore_cpu_virqs(unsigned int cpu)
  1053. {
  1054. struct evtchn_bind_virq bind_virq;
  1055. int virq, irq, evtchn;
  1056. for (virq = 0; virq < NR_VIRQS; virq++) {
  1057. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1058. continue;
  1059. BUG_ON(virq_from_irq(irq) != virq);
  1060. /* Get a new binding from Xen. */
  1061. bind_virq.virq = virq;
  1062. bind_virq.vcpu = cpu;
  1063. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1064. &bind_virq) != 0)
  1065. BUG();
  1066. evtchn = bind_virq.port;
  1067. /* Record the new mapping. */
  1068. evtchn_to_irq[evtchn] = irq;
  1069. irq_info[irq] = mk_virq_info(evtchn, virq);
  1070. bind_evtchn_to_cpu(evtchn, cpu);
  1071. }
  1072. }
  1073. static void restore_cpu_ipis(unsigned int cpu)
  1074. {
  1075. struct evtchn_bind_ipi bind_ipi;
  1076. int ipi, irq, evtchn;
  1077. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1078. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1079. continue;
  1080. BUG_ON(ipi_from_irq(irq) != ipi);
  1081. /* Get a new binding from Xen. */
  1082. bind_ipi.vcpu = cpu;
  1083. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1084. &bind_ipi) != 0)
  1085. BUG();
  1086. evtchn = bind_ipi.port;
  1087. /* Record the new mapping. */
  1088. evtchn_to_irq[evtchn] = irq;
  1089. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  1090. bind_evtchn_to_cpu(evtchn, cpu);
  1091. }
  1092. }
  1093. /* Clear an irq's pending state, in preparation for polling on it */
  1094. void xen_clear_irq_pending(int irq)
  1095. {
  1096. int evtchn = evtchn_from_irq(irq);
  1097. if (VALID_EVTCHN(evtchn))
  1098. clear_evtchn(evtchn);
  1099. }
  1100. EXPORT_SYMBOL(xen_clear_irq_pending);
  1101. void xen_set_irq_pending(int irq)
  1102. {
  1103. int evtchn = evtchn_from_irq(irq);
  1104. if (VALID_EVTCHN(evtchn))
  1105. set_evtchn(evtchn);
  1106. }
  1107. bool xen_test_irq_pending(int irq)
  1108. {
  1109. int evtchn = evtchn_from_irq(irq);
  1110. bool ret = false;
  1111. if (VALID_EVTCHN(evtchn))
  1112. ret = test_evtchn(evtchn);
  1113. return ret;
  1114. }
  1115. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1116. * the irq will be disabled so it won't deliver an interrupt. */
  1117. void xen_poll_irq_timeout(int irq, u64 timeout)
  1118. {
  1119. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1120. if (VALID_EVTCHN(evtchn)) {
  1121. struct sched_poll poll;
  1122. poll.nr_ports = 1;
  1123. poll.timeout = timeout;
  1124. set_xen_guest_handle(poll.ports, &evtchn);
  1125. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1126. BUG();
  1127. }
  1128. }
  1129. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1130. /* Poll waiting for an irq to become pending. In the usual case, the
  1131. * irq will be disabled so it won't deliver an interrupt. */
  1132. void xen_poll_irq(int irq)
  1133. {
  1134. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1135. }
  1136. void xen_irq_resume(void)
  1137. {
  1138. unsigned int cpu, irq, evtchn;
  1139. init_evtchn_cpu_bindings();
  1140. /* New event-channel space is not 'live' yet. */
  1141. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1142. mask_evtchn(evtchn);
  1143. /* No IRQ <-> event-channel mappings. */
  1144. for (irq = 0; irq < nr_irqs; irq++)
  1145. irq_info[irq].evtchn = 0; /* zap event-channel binding */
  1146. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1147. evtchn_to_irq[evtchn] = -1;
  1148. for_each_possible_cpu(cpu) {
  1149. restore_cpu_virqs(cpu);
  1150. restore_cpu_ipis(cpu);
  1151. }
  1152. restore_cpu_pirqs();
  1153. }
  1154. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1155. .name = "xen-dyn",
  1156. .irq_disable = disable_dynirq,
  1157. .irq_mask = disable_dynirq,
  1158. .irq_unmask = enable_dynirq,
  1159. .irq_eoi = ack_dynirq,
  1160. .irq_set_affinity = set_affinity_irq,
  1161. .irq_retrigger = retrigger_dynirq,
  1162. };
  1163. static struct irq_chip xen_pirq_chip __read_mostly = {
  1164. .name = "xen-pirq",
  1165. .irq_startup = startup_pirq,
  1166. .irq_shutdown = shutdown_pirq,
  1167. .irq_enable = enable_pirq,
  1168. .irq_unmask = enable_pirq,
  1169. .irq_disable = disable_pirq,
  1170. .irq_mask = disable_pirq,
  1171. .irq_ack = ack_pirq,
  1172. .irq_set_affinity = set_affinity_irq,
  1173. .irq_retrigger = retrigger_dynirq,
  1174. };
  1175. static struct irq_chip xen_percpu_chip __read_mostly = {
  1176. .name = "xen-percpu",
  1177. .irq_disable = disable_dynirq,
  1178. .irq_mask = disable_dynirq,
  1179. .irq_unmask = enable_dynirq,
  1180. .irq_ack = ack_dynirq,
  1181. };
  1182. int xen_set_callback_via(uint64_t via)
  1183. {
  1184. struct xen_hvm_param a;
  1185. a.domid = DOMID_SELF;
  1186. a.index = HVM_PARAM_CALLBACK_IRQ;
  1187. a.value = via;
  1188. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1189. }
  1190. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1191. #ifdef CONFIG_XEN_PVHVM
  1192. /* Vector callbacks are better than PCI interrupts to receive event
  1193. * channel notifications because we can receive vector callbacks on any
  1194. * vcpu and we don't need PCI support or APIC interactions. */
  1195. void xen_callback_vector(void)
  1196. {
  1197. int rc;
  1198. uint64_t callback_via;
  1199. if (xen_have_vector_callback) {
  1200. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1201. rc = xen_set_callback_via(callback_via);
  1202. if (rc) {
  1203. printk(KERN_ERR "Request for Xen HVM callback vector"
  1204. " failed.\n");
  1205. xen_have_vector_callback = 0;
  1206. return;
  1207. }
  1208. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1209. "enabled\n");
  1210. /* in the restore case the vector has already been allocated */
  1211. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1212. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1213. }
  1214. }
  1215. #else
  1216. void xen_callback_vector(void) {}
  1217. #endif
  1218. void __init xen_init_IRQ(void)
  1219. {
  1220. int i;
  1221. cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
  1222. GFP_KERNEL);
  1223. irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
  1224. /* We are using nr_irqs as the maximum number of pirq available but
  1225. * that number is actually chosen by Xen and we don't know exactly
  1226. * what it is. Be careful choosing high pirq numbers. */
  1227. pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
  1228. for (i = 0; i < nr_irqs; i++)
  1229. pirq_to_irq[i] = -1;
  1230. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1231. GFP_KERNEL);
  1232. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1233. evtchn_to_irq[i] = -1;
  1234. init_evtchn_cpu_bindings();
  1235. /* No event channels are 'live' right now. */
  1236. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1237. mask_evtchn(i);
  1238. if (xen_hvm_domain()) {
  1239. xen_callback_vector();
  1240. native_init_IRQ();
  1241. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1242. * __acpi_register_gsi can point at the right function */
  1243. pci_xen_hvm_init();
  1244. } else {
  1245. irq_ctx_init(smp_processor_id());
  1246. if (xen_initial_domain())
  1247. xen_setup_pirqs();
  1248. }
  1249. }