mscan.c 18 KB

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  1. /*
  2. * CAN bus driver for the alone generic (as possible as) MSCAN controller.
  3. *
  4. * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
  5. * Varma Electronics Oy
  6. * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
  7. * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the version 2 of the GNU General Public License
  11. * as published by the Free Software Foundation
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/netdevice.h>
  27. #include <linux/if_arp.h>
  28. #include <linux/if_ether.h>
  29. #include <linux/list.h>
  30. #include <linux/can.h>
  31. #include <linux/can/dev.h>
  32. #include <linux/can/error.h>
  33. #include <linux/io.h>
  34. #include "mscan.h"
  35. static struct can_bittiming_const mscan_bittiming_const = {
  36. .name = "mscan",
  37. .tseg1_min = 4,
  38. .tseg1_max = 16,
  39. .tseg2_min = 2,
  40. .tseg2_max = 8,
  41. .sjw_max = 4,
  42. .brp_min = 1,
  43. .brp_max = 64,
  44. .brp_inc = 1,
  45. };
  46. struct mscan_state {
  47. u8 mode;
  48. u8 canrier;
  49. u8 cantier;
  50. };
  51. static enum can_state state_map[] = {
  52. CAN_STATE_ERROR_ACTIVE,
  53. CAN_STATE_ERROR_WARNING,
  54. CAN_STATE_ERROR_PASSIVE,
  55. CAN_STATE_BUS_OFF
  56. };
  57. static int mscan_set_mode(struct net_device *dev, u8 mode)
  58. {
  59. struct mscan_priv *priv = netdev_priv(dev);
  60. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  61. int ret = 0;
  62. int i;
  63. u8 canctl1;
  64. if (mode != MSCAN_NORMAL_MODE) {
  65. if (priv->tx_active) {
  66. /* Abort transfers before going to sleep */#
  67. out_8(&regs->cantarq, priv->tx_active);
  68. /* Suppress TX done interrupts */
  69. out_8(&regs->cantier, 0);
  70. }
  71. canctl1 = in_8(&regs->canctl1);
  72. if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
  73. setbits8(&regs->canctl0, MSCAN_SLPRQ);
  74. for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
  75. if (in_8(&regs->canctl1) & MSCAN_SLPAK)
  76. break;
  77. udelay(100);
  78. }
  79. /*
  80. * The mscan controller will fail to enter sleep mode,
  81. * while there are irregular activities on bus, like
  82. * somebody keeps retransmitting. This behavior is
  83. * undocumented and seems to differ between mscan built
  84. * in mpc5200b and mpc5200. We proceed in that case,
  85. * since otherwise the slprq will be kept set and the
  86. * controller will get stuck. NOTE: INITRQ or CSWAI
  87. * will abort all active transmit actions, if still
  88. * any, at once.
  89. */
  90. if (i >= MSCAN_SET_MODE_RETRIES)
  91. dev_dbg(dev->dev.parent,
  92. "device failed to enter sleep mode. "
  93. "We proceed anyhow.\n");
  94. else
  95. priv->can.state = CAN_STATE_SLEEPING;
  96. }
  97. if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
  98. setbits8(&regs->canctl0, MSCAN_INITRQ);
  99. for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
  100. if (in_8(&regs->canctl1) & MSCAN_INITAK)
  101. break;
  102. }
  103. if (i >= MSCAN_SET_MODE_RETRIES)
  104. ret = -ENODEV;
  105. }
  106. if (!ret)
  107. priv->can.state = CAN_STATE_STOPPED;
  108. if (mode & MSCAN_CSWAI)
  109. setbits8(&regs->canctl0, MSCAN_CSWAI);
  110. } else {
  111. canctl1 = in_8(&regs->canctl1);
  112. if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
  113. clrbits8(&regs->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
  114. for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
  115. canctl1 = in_8(&regs->canctl1);
  116. if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
  117. break;
  118. }
  119. if (i >= MSCAN_SET_MODE_RETRIES)
  120. ret = -ENODEV;
  121. else
  122. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  123. }
  124. }
  125. return ret;
  126. }
  127. static int mscan_start(struct net_device *dev)
  128. {
  129. struct mscan_priv *priv = netdev_priv(dev);
  130. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  131. u8 canrflg;
  132. int err;
  133. out_8(&regs->canrier, 0);
  134. INIT_LIST_HEAD(&priv->tx_head);
  135. priv->prev_buf_id = 0;
  136. priv->cur_pri = 0;
  137. priv->tx_active = 0;
  138. priv->shadow_canrier = 0;
  139. priv->flags = 0;
  140. if (priv->type == MSCAN_TYPE_MPC5121) {
  141. /* Clear pending bus-off condition */
  142. if (in_8(&regs->canmisc) & MSCAN_BOHOLD)
  143. out_8(&regs->canmisc, MSCAN_BOHOLD);
  144. }
  145. err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
  146. if (err)
  147. return err;
  148. canrflg = in_8(&regs->canrflg);
  149. priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
  150. priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
  151. MSCAN_STATE_TX(canrflg))];
  152. out_8(&regs->cantier, 0);
  153. /* Enable receive interrupts. */
  154. out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
  155. return 0;
  156. }
  157. static int mscan_restart(struct net_device *dev)
  158. {
  159. struct mscan_priv *priv = netdev_priv(dev);
  160. if (priv->type == MSCAN_TYPE_MPC5121) {
  161. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  162. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  163. WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
  164. "bus-off state expected");
  165. out_8(&regs->canmisc, MSCAN_BOHOLD);
  166. /* Re-enable receive interrupts. */
  167. out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
  168. } else {
  169. if (priv->can.state <= CAN_STATE_BUS_OFF)
  170. mscan_set_mode(dev, MSCAN_INIT_MODE);
  171. return mscan_start(dev);
  172. }
  173. return 0;
  174. }
  175. static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
  176. {
  177. struct can_frame *frame = (struct can_frame *)skb->data;
  178. struct mscan_priv *priv = netdev_priv(dev);
  179. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  180. int i, rtr, buf_id;
  181. u32 can_id;
  182. if (skb->len != sizeof(*frame) || frame->can_dlc > 8) {
  183. kfree_skb(skb);
  184. dev->stats.tx_dropped++;
  185. return NETDEV_TX_OK;
  186. }
  187. out_8(&regs->cantier, 0);
  188. i = ~priv->tx_active & MSCAN_TXE;
  189. buf_id = ffs(i) - 1;
  190. switch (hweight8(i)) {
  191. case 0:
  192. netif_stop_queue(dev);
  193. dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n");
  194. return NETDEV_TX_BUSY;
  195. case 1:
  196. /*
  197. * if buf_id < 3, then current frame will be send out of order,
  198. * since buffer with lower id have higher priority (hell..)
  199. */
  200. netif_stop_queue(dev);
  201. case 2:
  202. if (buf_id < priv->prev_buf_id) {
  203. priv->cur_pri++;
  204. if (priv->cur_pri == 0xff) {
  205. set_bit(F_TX_WAIT_ALL, &priv->flags);
  206. netif_stop_queue(dev);
  207. }
  208. }
  209. set_bit(F_TX_PROGRESS, &priv->flags);
  210. break;
  211. }
  212. priv->prev_buf_id = buf_id;
  213. out_8(&regs->cantbsel, i);
  214. rtr = frame->can_id & CAN_RTR_FLAG;
  215. /* RTR is always the lowest bit of interest, then IDs follow */
  216. if (frame->can_id & CAN_EFF_FLAG) {
  217. can_id = (frame->can_id & CAN_EFF_MASK)
  218. << (MSCAN_EFF_RTR_SHIFT + 1);
  219. if (rtr)
  220. can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
  221. out_be16(&regs->tx.idr3_2, can_id);
  222. can_id >>= 16;
  223. /* EFF_FLAGS are inbetween the IDs :( */
  224. can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
  225. | MSCAN_EFF_FLAGS;
  226. } else {
  227. can_id = (frame->can_id & CAN_SFF_MASK)
  228. << (MSCAN_SFF_RTR_SHIFT + 1);
  229. if (rtr)
  230. can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
  231. }
  232. out_be16(&regs->tx.idr1_0, can_id);
  233. if (!rtr) {
  234. void __iomem *data = &regs->tx.dsr1_0;
  235. u16 *payload = (u16 *)frame->data;
  236. /* It is safe to write into dsr[dlc+1] */
  237. for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
  238. out_be16(data, *payload++);
  239. data += 2 + _MSCAN_RESERVED_DSR_SIZE;
  240. }
  241. }
  242. out_8(&regs->tx.dlr, frame->can_dlc);
  243. out_8(&regs->tx.tbpr, priv->cur_pri);
  244. /* Start transmission. */
  245. out_8(&regs->cantflg, 1 << buf_id);
  246. if (!test_bit(F_TX_PROGRESS, &priv->flags))
  247. dev->trans_start = jiffies;
  248. list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
  249. can_put_echo_skb(skb, dev, buf_id);
  250. /* Enable interrupt. */
  251. priv->tx_active |= 1 << buf_id;
  252. out_8(&regs->cantier, priv->tx_active);
  253. return NETDEV_TX_OK;
  254. }
  255. /* This function returns the old state to see where we came from */
  256. static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
  257. {
  258. struct mscan_priv *priv = netdev_priv(dev);
  259. enum can_state state, old_state = priv->can.state;
  260. if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
  261. state = state_map[max(MSCAN_STATE_RX(canrflg),
  262. MSCAN_STATE_TX(canrflg))];
  263. priv->can.state = state;
  264. }
  265. return old_state;
  266. }
  267. static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
  268. {
  269. struct mscan_priv *priv = netdev_priv(dev);
  270. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  271. u32 can_id;
  272. int i;
  273. can_id = in_be16(&regs->rx.idr1_0);
  274. if (can_id & (1 << 3)) {
  275. frame->can_id = CAN_EFF_FLAG;
  276. can_id = ((can_id << 16) | in_be16(&regs->rx.idr3_2));
  277. can_id = ((can_id & 0xffe00000) |
  278. ((can_id & 0x7ffff) << 2)) >> 2;
  279. } else {
  280. can_id >>= 4;
  281. frame->can_id = 0;
  282. }
  283. frame->can_id |= can_id >> 1;
  284. if (can_id & 1)
  285. frame->can_id |= CAN_RTR_FLAG;
  286. frame->can_dlc = get_can_dlc(in_8(&regs->rx.dlr) & 0xf);
  287. if (!(frame->can_id & CAN_RTR_FLAG)) {
  288. void __iomem *data = &regs->rx.dsr1_0;
  289. u16 *payload = (u16 *)frame->data;
  290. for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
  291. *payload++ = in_be16(data);
  292. data += 2 + _MSCAN_RESERVED_DSR_SIZE;
  293. }
  294. }
  295. out_8(&regs->canrflg, MSCAN_RXF);
  296. }
  297. static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
  298. u8 canrflg)
  299. {
  300. struct mscan_priv *priv = netdev_priv(dev);
  301. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  302. struct net_device_stats *stats = &dev->stats;
  303. enum can_state old_state;
  304. dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg);
  305. frame->can_id = CAN_ERR_FLAG;
  306. if (canrflg & MSCAN_OVRIF) {
  307. frame->can_id |= CAN_ERR_CRTL;
  308. frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  309. stats->rx_over_errors++;
  310. stats->rx_errors++;
  311. } else {
  312. frame->data[1] = 0;
  313. }
  314. old_state = check_set_state(dev, canrflg);
  315. /* State changed */
  316. if (old_state != priv->can.state) {
  317. switch (priv->can.state) {
  318. case CAN_STATE_ERROR_WARNING:
  319. frame->can_id |= CAN_ERR_CRTL;
  320. priv->can.can_stats.error_warning++;
  321. if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
  322. (canrflg & MSCAN_RSTAT_MSK))
  323. frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
  324. if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
  325. (canrflg & MSCAN_TSTAT_MSK))
  326. frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
  327. break;
  328. case CAN_STATE_ERROR_PASSIVE:
  329. frame->can_id |= CAN_ERR_CRTL;
  330. priv->can.can_stats.error_passive++;
  331. frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
  332. break;
  333. case CAN_STATE_BUS_OFF:
  334. frame->can_id |= CAN_ERR_BUSOFF;
  335. /*
  336. * The MSCAN on the MPC5200 does recover from bus-off
  337. * automatically. To avoid that we stop the chip doing
  338. * a light-weight stop (we are in irq-context).
  339. */
  340. if (priv->type != MSCAN_TYPE_MPC5121) {
  341. out_8(&regs->cantier, 0);
  342. out_8(&regs->canrier, 0);
  343. setbits8(&regs->canctl0,
  344. MSCAN_SLPRQ | MSCAN_INITRQ);
  345. }
  346. can_bus_off(dev);
  347. break;
  348. default:
  349. break;
  350. }
  351. }
  352. priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
  353. frame->can_dlc = CAN_ERR_DLC;
  354. out_8(&regs->canrflg, MSCAN_ERR_IF);
  355. }
  356. static int mscan_rx_poll(struct napi_struct *napi, int quota)
  357. {
  358. struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
  359. struct net_device *dev = napi->dev;
  360. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  361. struct net_device_stats *stats = &dev->stats;
  362. int npackets = 0;
  363. int ret = 1;
  364. struct sk_buff *skb;
  365. struct can_frame *frame;
  366. u8 canrflg;
  367. while (npackets < quota) {
  368. canrflg = in_8(&regs->canrflg);
  369. if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
  370. break;
  371. skb = alloc_can_skb(dev, &frame);
  372. if (!skb) {
  373. if (printk_ratelimit())
  374. dev_notice(dev->dev.parent, "packet dropped\n");
  375. stats->rx_dropped++;
  376. out_8(&regs->canrflg, canrflg);
  377. continue;
  378. }
  379. if (canrflg & MSCAN_RXF)
  380. mscan_get_rx_frame(dev, frame);
  381. else if (canrflg & MSCAN_ERR_IF)
  382. mscan_get_err_frame(dev, frame, canrflg);
  383. stats->rx_packets++;
  384. stats->rx_bytes += frame->can_dlc;
  385. npackets++;
  386. netif_receive_skb(skb);
  387. }
  388. if (!(in_8(&regs->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
  389. napi_complete(&priv->napi);
  390. clear_bit(F_RX_PROGRESS, &priv->flags);
  391. if (priv->can.state < CAN_STATE_BUS_OFF)
  392. out_8(&regs->canrier, priv->shadow_canrier);
  393. ret = 0;
  394. }
  395. return ret;
  396. }
  397. static irqreturn_t mscan_isr(int irq, void *dev_id)
  398. {
  399. struct net_device *dev = (struct net_device *)dev_id;
  400. struct mscan_priv *priv = netdev_priv(dev);
  401. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  402. struct net_device_stats *stats = &dev->stats;
  403. u8 cantier, cantflg, canrflg;
  404. irqreturn_t ret = IRQ_NONE;
  405. cantier = in_8(&regs->cantier) & MSCAN_TXE;
  406. cantflg = in_8(&regs->cantflg) & cantier;
  407. if (cantier && cantflg) {
  408. struct list_head *tmp, *pos;
  409. list_for_each_safe(pos, tmp, &priv->tx_head) {
  410. struct tx_queue_entry *entry =
  411. list_entry(pos, struct tx_queue_entry, list);
  412. u8 mask = entry->mask;
  413. if (!(cantflg & mask))
  414. continue;
  415. out_8(&regs->cantbsel, mask);
  416. stats->tx_bytes += in_8(&regs->tx.dlr);
  417. stats->tx_packets++;
  418. can_get_echo_skb(dev, entry->id);
  419. priv->tx_active &= ~mask;
  420. list_del(pos);
  421. }
  422. if (list_empty(&priv->tx_head)) {
  423. clear_bit(F_TX_WAIT_ALL, &priv->flags);
  424. clear_bit(F_TX_PROGRESS, &priv->flags);
  425. priv->cur_pri = 0;
  426. } else {
  427. dev->trans_start = jiffies;
  428. }
  429. if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
  430. netif_wake_queue(dev);
  431. out_8(&regs->cantier, priv->tx_active);
  432. ret = IRQ_HANDLED;
  433. }
  434. canrflg = in_8(&regs->canrflg);
  435. if ((canrflg & ~MSCAN_STAT_MSK) &&
  436. !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
  437. if (canrflg & ~MSCAN_STAT_MSK) {
  438. priv->shadow_canrier = in_8(&regs->canrier);
  439. out_8(&regs->canrier, 0);
  440. napi_schedule(&priv->napi);
  441. ret = IRQ_HANDLED;
  442. } else {
  443. clear_bit(F_RX_PROGRESS, &priv->flags);
  444. }
  445. }
  446. return ret;
  447. }
  448. static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
  449. {
  450. struct mscan_priv *priv = netdev_priv(dev);
  451. int ret = 0;
  452. if (!priv->open_time)
  453. return -EINVAL;
  454. switch (mode) {
  455. case CAN_MODE_START:
  456. ret = mscan_restart(dev);
  457. if (ret)
  458. break;
  459. if (netif_queue_stopped(dev))
  460. netif_wake_queue(dev);
  461. break;
  462. default:
  463. ret = -EOPNOTSUPP;
  464. break;
  465. }
  466. return ret;
  467. }
  468. static int mscan_do_set_bittiming(struct net_device *dev)
  469. {
  470. struct mscan_priv *priv = netdev_priv(dev);
  471. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  472. struct can_bittiming *bt = &priv->can.bittiming;
  473. u8 btr0, btr1;
  474. btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
  475. btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
  476. BTR1_SET_TSEG2(bt->phase_seg2) |
  477. BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
  478. dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n",
  479. btr0, btr1);
  480. out_8(&regs->canbtr0, btr0);
  481. out_8(&regs->canbtr1, btr1);
  482. return 0;
  483. }
  484. static int mscan_open(struct net_device *dev)
  485. {
  486. int ret;
  487. struct mscan_priv *priv = netdev_priv(dev);
  488. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  489. /* common open */
  490. ret = open_candev(dev);
  491. if (ret)
  492. return ret;
  493. napi_enable(&priv->napi);
  494. ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
  495. if (ret < 0) {
  496. dev_err(dev->dev.parent, "failed to attach interrupt\n");
  497. goto exit_napi_disable;
  498. }
  499. priv->open_time = jiffies;
  500. clrbits8(&regs->canctl1, MSCAN_LISTEN);
  501. ret = mscan_start(dev);
  502. if (ret)
  503. goto exit_free_irq;
  504. netif_start_queue(dev);
  505. return 0;
  506. exit_free_irq:
  507. priv->open_time = 0;
  508. free_irq(dev->irq, dev);
  509. exit_napi_disable:
  510. napi_disable(&priv->napi);
  511. close_candev(dev);
  512. return ret;
  513. }
  514. static int mscan_close(struct net_device *dev)
  515. {
  516. struct mscan_priv *priv = netdev_priv(dev);
  517. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  518. netif_stop_queue(dev);
  519. napi_disable(&priv->napi);
  520. out_8(&regs->cantier, 0);
  521. out_8(&regs->canrier, 0);
  522. mscan_set_mode(dev, MSCAN_INIT_MODE);
  523. close_candev(dev);
  524. free_irq(dev->irq, dev);
  525. priv->open_time = 0;
  526. return 0;
  527. }
  528. static const struct net_device_ops mscan_netdev_ops = {
  529. .ndo_open = mscan_open,
  530. .ndo_stop = mscan_close,
  531. .ndo_start_xmit = mscan_start_xmit,
  532. };
  533. int register_mscandev(struct net_device *dev, int mscan_clksrc)
  534. {
  535. struct mscan_priv *priv = netdev_priv(dev);
  536. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  537. u8 ctl1;
  538. ctl1 = in_8(&regs->canctl1);
  539. if (mscan_clksrc)
  540. ctl1 |= MSCAN_CLKSRC;
  541. else
  542. ctl1 &= ~MSCAN_CLKSRC;
  543. if (priv->type == MSCAN_TYPE_MPC5121)
  544. ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
  545. ctl1 |= MSCAN_CANE;
  546. out_8(&regs->canctl1, ctl1);
  547. udelay(100);
  548. /* acceptance mask/acceptance code (accept everything) */
  549. out_be16(&regs->canidar1_0, 0);
  550. out_be16(&regs->canidar3_2, 0);
  551. out_be16(&regs->canidar5_4, 0);
  552. out_be16(&regs->canidar7_6, 0);
  553. out_be16(&regs->canidmr1_0, 0xffff);
  554. out_be16(&regs->canidmr3_2, 0xffff);
  555. out_be16(&regs->canidmr5_4, 0xffff);
  556. out_be16(&regs->canidmr7_6, 0xffff);
  557. /* Two 32 bit Acceptance Filters */
  558. out_8(&regs->canidac, MSCAN_AF_32BIT);
  559. mscan_set_mode(dev, MSCAN_INIT_MODE);
  560. return register_candev(dev);
  561. }
  562. void unregister_mscandev(struct net_device *dev)
  563. {
  564. struct mscan_priv *priv = netdev_priv(dev);
  565. struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
  566. mscan_set_mode(dev, MSCAN_INIT_MODE);
  567. clrbits8(&regs->canctl1, MSCAN_CANE);
  568. unregister_candev(dev);
  569. }
  570. struct net_device *alloc_mscandev(void)
  571. {
  572. struct net_device *dev;
  573. struct mscan_priv *priv;
  574. int i;
  575. dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
  576. if (!dev)
  577. return NULL;
  578. priv = netdev_priv(dev);
  579. dev->netdev_ops = &mscan_netdev_ops;
  580. dev->flags |= IFF_ECHO; /* we support local echo */
  581. netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
  582. priv->can.bittiming_const = &mscan_bittiming_const;
  583. priv->can.do_set_bittiming = mscan_do_set_bittiming;
  584. priv->can.do_set_mode = mscan_do_set_mode;
  585. for (i = 0; i < TX_QUEUE_SIZE; i++) {
  586. priv->tx_queue[i].id = i;
  587. priv->tx_queue[i].mask = 1 << i;
  588. }
  589. return dev;
  590. }
  591. MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
  592. MODULE_LICENSE("GPL v2");
  593. MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");