ati_pcigart.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196
  1. /**
  2. * \file ati_pcigart.c
  3. * ATI PCI GART support
  4. *
  5. * \author Gareth Hughes <gareth@valinux.com>
  6. */
  7. /*
  8. * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
  9. *
  10. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  11. * All Rights Reserved.
  12. *
  13. * Permission is hereby granted, free of charge, to any person obtaining a
  14. * copy of this software and associated documentation files (the "Software"),
  15. * to deal in the Software without restriction, including without limitation
  16. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  17. * and/or sell copies of the Software, and to permit persons to whom the
  18. * Software is furnished to do so, subject to the following conditions:
  19. *
  20. * The above copyright notice and this permission notice (including the next
  21. * paragraph) shall be included in all copies or substantial portions of the
  22. * Software.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  25. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  26. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  27. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  28. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  29. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  30. * DEALINGS IN THE SOFTWARE.
  31. */
  32. #include "drmP.h"
  33. # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
  34. static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
  35. struct drm_ati_pcigart_info *gart_info)
  36. {
  37. gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
  38. PAGE_SIZE,
  39. gart_info->table_mask);
  40. if (gart_info->table_handle == NULL)
  41. return -ENOMEM;
  42. return 0;
  43. }
  44. static void drm_ati_free_pcigart_table(struct drm_device *dev,
  45. struct drm_ati_pcigart_info *gart_info)
  46. {
  47. drm_pci_free(dev, gart_info->table_handle);
  48. gart_info->table_handle = NULL;
  49. }
  50. int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
  51. {
  52. struct drm_sg_mem *entry = dev->sg;
  53. unsigned long pages;
  54. int i;
  55. int max_pages;
  56. /* we need to support large memory configurations */
  57. if (!entry) {
  58. DRM_ERROR("no scatter/gather memory!\n");
  59. return 0;
  60. }
  61. if (gart_info->bus_addr) {
  62. max_pages = (gart_info->table_size / sizeof(u32));
  63. pages = (entry->pages <= max_pages)
  64. ? entry->pages : max_pages;
  65. for (i = 0; i < pages; i++) {
  66. if (!entry->busaddr[i])
  67. break;
  68. pci_unmap_page(dev->pdev, entry->busaddr[i],
  69. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  70. }
  71. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
  72. gart_info->bus_addr = 0;
  73. }
  74. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
  75. gart_info->table_handle) {
  76. drm_ati_free_pcigart_table(dev, gart_info);
  77. }
  78. return 1;
  79. }
  80. EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
  81. int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
  82. {
  83. struct drm_local_map *map = &gart_info->mapping;
  84. struct drm_sg_mem *entry = dev->sg;
  85. void *address = NULL;
  86. unsigned long pages;
  87. u32 *pci_gart, page_base, gart_idx;
  88. dma_addr_t bus_address = 0;
  89. int i, j, ret = 0;
  90. int max_ati_pages, max_real_pages;
  91. if (!entry) {
  92. DRM_ERROR("no scatter/gather memory!\n");
  93. goto done;
  94. }
  95. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
  96. DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
  97. ret = drm_ati_alloc_pcigart_table(dev, gart_info);
  98. if (ret) {
  99. DRM_ERROR("cannot allocate PCI GART page!\n");
  100. goto done;
  101. }
  102. address = gart_info->table_handle->vaddr;
  103. bus_address = gart_info->table_handle->busaddr;
  104. } else {
  105. address = gart_info->addr;
  106. bus_address = gart_info->bus_addr;
  107. DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
  108. (unsigned long long)bus_address,
  109. (unsigned long)address);
  110. }
  111. pci_gart = (u32 *) address;
  112. max_ati_pages = (gart_info->table_size / sizeof(u32));
  113. max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
  114. pages = (entry->pages <= max_real_pages)
  115. ? entry->pages : max_real_pages;
  116. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
  117. memset(pci_gart, 0, max_ati_pages * sizeof(u32));
  118. } else {
  119. for (gart_idx = 0; gart_idx < max_ati_pages; gart_idx++)
  120. DRM_WRITE32(map, gart_idx * sizeof(u32), 0);
  121. }
  122. gart_idx = 0;
  123. for (i = 0; i < pages; i++) {
  124. /* we need to support large memory configurations */
  125. entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
  126. 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  127. if (entry->busaddr[i] == 0) {
  128. DRM_ERROR("unable to map PCIGART pages!\n");
  129. drm_ati_pcigart_cleanup(dev, gart_info);
  130. address = NULL;
  131. bus_address = 0;
  132. goto done;
  133. }
  134. page_base = (u32) entry->busaddr[i];
  135. for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
  136. u32 val;
  137. switch(gart_info->gart_reg_if) {
  138. case DRM_ATI_GART_IGP:
  139. val = page_base | 0xc;
  140. break;
  141. case DRM_ATI_GART_PCIE:
  142. val = (page_base >> 8) | 0xc;
  143. break;
  144. default:
  145. case DRM_ATI_GART_PCI:
  146. val = page_base;
  147. break;
  148. }
  149. if (gart_info->gart_table_location ==
  150. DRM_ATI_GART_MAIN)
  151. pci_gart[gart_idx] = cpu_to_le32(val);
  152. else
  153. DRM_WRITE32(map, gart_idx * sizeof(u32), val);
  154. gart_idx++;
  155. page_base += ATI_PCIGART_PAGE_SIZE;
  156. }
  157. }
  158. ret = 1;
  159. #if defined(__i386__) || defined(__x86_64__)
  160. wbinvd();
  161. #else
  162. mb();
  163. #endif
  164. done:
  165. gart_info->addr = address;
  166. gart_info->bus_addr = bus_address;
  167. return ret;
  168. }
  169. EXPORT_SYMBOL(drm_ati_pcigart_init);